Display substrate and display apparatus

Abstract

The present disclosure relates to the technical field of display. Provided are a display panel and a display apparatus. The display substrate comprises a base, and a plurality of first voltage-stabilizing signal lines (VH), a plurality of second voltage-stabilizing signal lines and a plurality of data signal lines (Data), which are disposed on one side of the base, wherein at least some of the first voltage-stabilizing signal lines (VH) are provided with a plurality of shielding structures (ZD), and the plurality of shielding structures (ZD) are arranged at intervals in a row direction (X); each data signal line (Data) and at least one second voltage-stabilizing signal line (VL) located on either side of the data signal line (Data) correspond to at least one shielding structure (ZD); and the orthographic projections of at least some of the shielding structures (ZD) on the base are located between the orthographic projections of the corresponding data signal lines (Data) on the base and the orthographic projections of the corresponding second voltage-stabilizing signal lines (VL) on the base.

Description

Display substrate and display device Technical Field

[0001] This disclosure relates to the field of display technology, and more specifically, to a display substrate and a display device. Background Technology

[0002] OLED (Organic Light Emitting Diode) display panels have advantages such as self-illumination, wide color gamut, high contrast, flexibility, and high response, making them promising for a wide range of applications. However, the uniformity of light emission in current display panels still needs improvement, which can easily lead to abnormal display images.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] This disclosure provides a display substrate and a display device. The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] According to one aspect of this disclosure, a display substrate is provided, including a substrate and a plurality of sub-pixels, a plurality of first voltage-regulating signal lines, a plurality of second voltage-regulating signal lines, and a plurality of data signal lines disposed on one side of the substrate; at least some of the sub-pixels include pixel driving circuits, the pixel driving circuits of the at least some sub-pixels forming multiple columns, and the data signal lines are electrically connected to at least some of the pixel driving circuits in at least one column of pixel driving circuits; the plurality of first voltage-regulating signal lines extend along a row direction and are spaced apart along a column direction, the row direction intersecting the column direction; the plurality of second voltage-regulating signal lines and the plurality of data signal lines extend along the column direction and are spaced apart along the row direction;

[0006] At least a portion of the first voltage-regulated signal line is provided with multiple shielding structures. In the row direction, the multiple shielding structures are arranged at intervals. The data signal line is located between two adjacent second voltage-regulated signal lines. The data signal line and at least one second voltage-regulated signal line located on both sides of the data signal line correspond to at least one shielding structure. The orthographic projection of at least a portion of the shielding structure on the substrate is located between the orthographic projection of the corresponding data signal line on the substrate and the orthographic projection of the corresponding second voltage-regulated signal line on the substrate.

[0007] In a direction perpendicular to the plane of the substrate, the data signal line and the second voltage-regulated signal line are located on the side of the first voltage-regulated signal line away from the substrate, and the first voltage-regulated signal line is located on the side of at least some components in the pixel driving circuit away from the substrate.

[0008] In one exemplary embodiment of this disclosure, the first regulated signal line is located in a first source-drain metal layer, and the second regulated signal line and the data signal line are located in a second source-drain metal layer; or, the first regulated signal line is located in the second source-drain metal layer, and the second regulated signal line and the data signal line are located in the third source-drain metal layer.

[0009] In a direction perpendicular to the plane of the substrate, the second source / drain metal layer is located on the side of the first source / drain metal layer away from the substrate, and the third source / drain metal layer is located on the side of the second source / drain metal layer away from the substrate.

[0010] In one exemplary embodiment of this disclosure, the elements in the pixel driving circuit include at least one capacitor and a plurality of transistors, the plurality of transistors including at least a driving transistor, at least one plate of the at least one capacitor is connected to the control electrode of the driving transistor, and in a direction perpendicular to the plane of the substrate, the first regulated signal line is located on the side of the capacitor away from the substrate.

[0011] In one exemplary embodiment of this disclosure, the at least one capacitor located in the same pixel driving circuit corresponds to at least one occlusion structure. In the row direction, the orthographic projection of at least a portion of the occlusion structure onto the substrate is located between the orthographic projection of the corresponding data signal line onto the substrate and the orthographic projection of the corresponding at least one capacitor onto the substrate.

[0012] In one exemplary embodiment of this disclosure, the at least one capacitor in the pixel driving circuit includes a first capacitor and a second capacitor, the control electrode of the driving transistor is connected to the second plate of the second capacitor, and the second electrode of the driving transistor is connected to the second plate of the first capacitor.

[0013] The first node corresponds to at least one shielding structure. In the row direction, at least a portion of the shielding structure has its orthographic projection on the substrate located between the orthographic projection of the corresponding data signal line on the substrate and the orthographic projection of the corresponding first node on the substrate. The first node is the node where the control electrode of the driving transistor is connected to the second plate of the second capacitor.

[0014] In one exemplary embodiment of this disclosure, the plurality of transistors further includes a second transistor as a reset transistor, the second terminal of the second transistor being connected to the first plate of the first capacitor and the first plate of the second capacitor;

[0015] The fourth node corresponds to at least one shielding structure. In the row direction, at least a portion of the shielding structure has its orthographic projection on the substrate located between the orthographic projection of the corresponding data signal line on the substrate and the orthographic projection of the corresponding fourth node on the substrate. The fourth node is the node where the second electrode of the second transistor is connected to the first plate of the first capacitor and the first plate of the second capacitor.

[0016] In one exemplary embodiment of this disclosure, the plurality of blocking structures form a plurality of blocking units, each blocking unit including a first blocking structure and a second blocking structure, and each blocking unit corresponds to one of the data signal lines;

[0017] In the row direction, the blocking unit corresponds to the first node and the fourth node on both sides of the corresponding data signal line, the first blocking structure corresponds to the first node, and the second blocking structure corresponds to the fourth node; the plurality of blocking units are arranged at intervals, and in the same blocking unit, the second blocking structure and the first blocking structure are arranged at intervals in sequence, the first blocking structure and the second blocking structure are located on both sides of the corresponding data signal line, the first blocking structure and the corresponding first node are located on one side of the corresponding data signal line, and the second blocking structure and the corresponding fourth node are located on the other side of the corresponding data signal line.

[0018] In one exemplary embodiment of this disclosure, in the row direction, the orthographic projection of at least a portion of the structure in the first blocking structure onto the substrate is located between the orthographic projection of the corresponding data signal line onto the substrate and the orthographic projection of the corresponding first node onto the substrate; the orthographic projection of at least a portion of the structure in the second blocking structure onto the substrate is located between the orthographic projection of the corresponding data signal line onto the substrate and the orthographic projection of the corresponding fourth node onto the substrate.

[0019] In one exemplary embodiment of this disclosure, the blocking structure corresponds to one of the data signal lines. In the row direction, the blocking structure corresponds to a first node and a fourth node located on both sides of the corresponding data signal line. The orthographic projection of at least a portion of the blocking structure on the substrate is located between the orthographic projection of the corresponding first node on the substrate and the orthographic projection of the corresponding fourth node on the substrate, and at least partially overlaps with the orthographic projection of the corresponding at least a portion of the data signal line on the substrate.

[0020] In one exemplary embodiment of this disclosure, in the row direction, the first node is located in a pixel driving circuit on one side of the corresponding data signal line, and the fourth node is located in a pixel driving circuit on the other side of the corresponding data signal line.

[0021] In the same pixel driving circuit, in the row direction, the first node and the fourth node are located on both sides of the first center line, which is the center line extending from the first capacitor and the second capacitor along the column direction.

[0022] In one exemplary embodiment of this disclosure, the orthogonal projection of the at least one capacitor on the substrate does not overlap with the orthogonal projection of the data signal line on the substrate, but at least partially overlaps with the orthogonal projections of at least a portion of the second voltage-regulating signal line and at least a portion of the first voltage-regulating signal line on the substrate.

[0023] In one exemplary embodiment of this disclosure, in a direction perpendicular to the plane of the substrate, the capacitor includes a first electrode plate located on one side of the substrate and a second electrode plate located on the side of the first electrode plate away from the substrate; the transistor includes: an active layer located on the side of the second electrode plate away from the substrate, a control electrode located on the side of the active layer away from the substrate, and a first electrode and a second electrode located on the side of the control electrode away from the substrate;

[0024] The first voltage regulator signal line is disposed on the same layer as the first electrode and the second electrode. In a direction perpendicular to the plane of the substrate, the second voltage regulator signal line is located on the side of the first electrode and the second electrode away from the substrate.

[0025] In one exemplary embodiment of this disclosure, the plurality of second voltage-regulating signal lines include a first type of second voltage-regulating signal line and a second type of second voltage-regulating signal line, and the at least one capacitor located in the same pixel driving circuit corresponds to one of the first type of second voltage-regulating signal lines and one of the second type of voltage-regulating signal lines;

[0026] The data signal line corresponds to one of the first type second voltage-regulated signal lines and one of the second type second voltage-regulated signal lines. In the row direction, the data signal line is located between the corresponding first type second voltage-regulated signal line and the corresponding second type second voltage-regulated signal line. The at least one capacitor in the same pixel driving circuit, as well as the corresponding first type second voltage-regulated signal line and the corresponding second type second voltage-regulated signal line, are located between two adjacent data signal lines.

[0027] In one exemplary embodiment of this disclosure, the first voltage regulator signal line includes a first power connection line, the second type of second voltage regulator signal line includes a first power line, and at least a portion of the first power line and at least a portion of the first power connection line are connected by vias to form a mesh structure.

[0028] In one exemplary embodiment of this disclosure, the first type of second voltage regulation signal line includes a first initialization power connection line, a second initialization power connection line, and a second power line. The plurality of sub-pixels form a plurality of pixel units. Each pixel unit includes three sub-pixels. The pixel driving circuits of the three sub-pixels in the same pixel unit are arranged sequentially along the row direction.

[0029] The first initialization power connection line, the second initialization power connection line, and the second power line, which are corresponding to the same pixel unit, are respectively located in the pixel driving circuits of the three sub-pixels in the pixel unit.

[0030] In one exemplary embodiment of this disclosure, the plurality of transistors includes a first transistor as an initialization transistor and a second transistor as an initialization transistor, the first terminal of the first transistor and the first terminal of the second transistor are connected to the first initialization connection line, and the orthogonal projections of the first initialization transistor and the second initialization transistor on the substrate do not overlap with the orthogonal projections of the at least one capacitor on the substrate.

[0031] In one exemplary embodiment of this disclosure, the display substrate further includes a plurality of first reset signal lines and a plurality of second reset signal lines, wherein the plurality of first reset signal lines and the plurality of second reset signal lines extend along the row direction and are spaced apart along the column direction;

[0032] The pixel driving circuits of at least some sub-pixels are formed in multiple rows. The first reset signal line is electrically connected to the control electrode of at least some of the first transistors in at least one row of pixel driving circuits. The second reset signal line is electrically connected to the control electrode of at least some of the second transistors in at least one row of pixel driving circuits. The first reset signal line and the second reset signal line are disposed on the same layer as the first electrode and the second electrode, and their orthogonal projections on the substrate do not overlap with the orthogonal projections of the at least one capacitor on the substrate.

[0033] In one exemplary embodiment of this disclosure, the plurality of transistors further includes a fourth transistor as a data writing transistor and a sixth transistor as a light-emitting control transistor. The first terminal of the fourth transistor is connected to the data signal line, and the first terminal of the sixth transistor is connected to the second terminal of the driving transistor. The orthographic projections of the fourth transistor and the sixth transistor on the substrate do not overlap with the orthographic projections of the at least one capacitor on the substrate.

[0034] In the same pixel driving circuit, in the row direction, the first transistor and the second transistor are located on opposite sides of the driving transistor; in the column direction, the first transistor and the second transistor are located on one side of the driving transistor, the fourth transistor is located on the other side of the driving transistor, and the sixth transistor is located between the third transistor and the first transistor and the second transistor.

[0035] In one exemplary embodiment of this disclosure, the display substrate further includes a plurality of scan signal lines and a plurality of second light emission control signal lines, wherein the plurality of scan signal lines and the plurality of second light emission control signal lines are disposed on the same layer as the first electrode and the second electrode, and extend along the row direction and are spaced apart along the column direction;

[0036] The pixel driving circuits of at least some sub-pixels form multiple rows, the scanning signal line is electrically connected to the control electrode of at least some fourth transistors in at least one row of pixel driving circuits, and the second light emission control signal line is electrically connected to the control electrode of at least some sixth transistors in at least one row of pixel driving circuits.

[0037] In the same row of pixel driving circuits, in the column direction, the first regulated signal line with the blocking structure is located between the scan signal line and the second light emission control signal line.

[0038] In one exemplary embodiment of this disclosure, the orthographic projection of the second light-emitting control signal line on the substrate and the orthographic projection of the capacitor on the substrate do not overlap.

[0039] In one exemplary embodiment of this disclosure, in the same row of pixel driving circuits, in the column direction, the occlusion structure is located between the scan signal line and the second light emission control signal line.

[0040] In one exemplary embodiment of this disclosure, the shape of the shielding structure is a block structure, or the shape of the shielding structure is a strip or a broken line extending along the column direction.

[0041] In one exemplary embodiment of this disclosure, the pixel driving circuit includes a seventh transistor as a reset transistor and a fifth transistor as a light-emitting control transistor; the first terminal of the seventh transistor is connected to the second initialization power supply connection line, the first terminal of the fifth transistor is connected to the second power supply line, and the second terminal of the fifth transistor is connected to the first terminal of the driving transistor.

[0042] In the column direction, the fifth transistor is located on the side of the fourth transistor away from the driving transistor, and the seventh transistor is located on the side of the first transistor and the second transistor away from the driving transistor.

[0043] In one exemplary embodiment of this disclosure, the same pixel driving circuit corresponds to one of the first type of second voltage regulator signal lines and one of the second type of second voltage regulator signal lines;

[0044] In the same pixel driving circuit: the orthographic projections of the channels of the first transistor and the fourth transistor on the substrate at least partially overlap with the orthographic projections of the corresponding first type second voltage-regulating signal lines on the substrate; the orthographic projections of the channels of the driving transistor, the second transistor, the fifth transistor, and the sixth transistor on the substrate at least partially overlap with the orthographic projections of the corresponding second type second voltage-regulating signal lines on the substrate.

[0045] In one exemplary embodiment of this disclosure, at least some sub-pixels further include a plurality of anodes, which are located on the side of the plurality of second voltage-regulating signal lines away from the substrate in a direction perpendicular to the plane of the substrate; the orthogonal projection of the channel of the seventh transistor on the substrate is located within the range of the orthogonal projection of at least one anode on the substrate.

[0046] In one exemplary embodiment of this disclosure, the pixel unit includes at least a first sub-pixel, a second sub-pixel, and a third sub-pixel; in the same sub-pixel, the second electrode of the sixth transistor and the second electrode of the seventh transistor are electrically connected to the anode of the sub-pixel;

[0047] In the same pixel unit, the orthographic projection of the anode of the first sub-pixel onto the substrate covers the orthographic projection of the channel of the seventh transistor in the first sub-pixel onto the substrate; the orthographic projection of the anode of the second sub-pixel onto the substrate covers the orthographic projection of the channel of the seventh transistor in the second and third sub-pixels onto the substrate; the orthographic projection of the anode of the third sub-pixel and the corresponding second type second voltage regulation signal line onto the substrate covers the orthographic projection of the channel of the second transistor in the pixel unit onto the substrate.

[0048] According to one aspect of this disclosure, a display substrate is provided, comprising: a substrate and a plurality of sub-pixels disposed on one side of the substrate, and a plurality of control signal lines, wherein at least one sub-pixel includes a pixel driving circuit, the at least one pixel driving circuit includes a plurality of transistors and at least one capacitor, the plurality of transistors including at least a driving transistor; the pixel driving circuits of the plurality of sub-pixels are arranged in multiple rows, the plurality of control signal lines extend along a row direction and are spaced apart along a column direction, the row direction intersecting the column direction; the control signal lines are electrically connected to the control electrode of at least one transistor in at least one row of pixel driving circuits, and in a direction perpendicular to the plane of the substrate, the control signal lines are located on the side of the capacitor away from the substrate;

[0049] In the same pixel driving circuit, the control electrode of the driving transistor is electrically connected to at least one plate of the at least one capacitor; the orthographic projection of at least one control signal line on the substrate and the orthographic projection of the at least one capacitor on the substrate do not overlap.

[0050] In one exemplary embodiment of this disclosure, the plurality of transistors includes at least a first transistor as an initialization transistor, a second transistor as an initialization transistor, and a seventh transistor as an initial transistor, and the control signal lines include at least a first reset signal line, a second reset signal line, and a third reset signal line;

[0051] The first reset signal line is electrically connected to the control electrode of at least a portion of the first transistor in at least one row of pixel driving circuits; the second reset signal line is electrically connected to the control electrode of at least a portion of the second transistor in at least one row of pixel driving circuits; and the third reset signal line is electrically connected to the control electrode of at least a portion of the seventh transistor in at least one row of pixel driving circuits. The orthographic projections of the first reset signal line, the second reset signal line, and the third reset signal line on the substrate do not overlap with the orthographic projections of the at least one capacitor on the substrate.

[0052] In one exemplary embodiment of this disclosure, the display substrate further includes a plurality of first initialization power lines and a plurality of second initialization power lines, wherein the plurality of first initialization power lines and the plurality of second initialization power lines extend along the row direction and are spaced apart along the column direction;

[0053] The first initialization power line is connected to the first terminal of the first transistor and the first terminal of the second transistor in at least one row of pixel driving circuits; the second initialization power line is connected to the first terminal of the seventh transistor in at least one row of pixel driving circuits.

[0054] In the same pixel driving circuit, in the column direction, the first reset signal line, the second reset signal line, the first initialization power line, the third reset signal line, and the second initial power line are arranged at intervals and located on the same side of the driving transistor and the at least one capacitor.

[0055] In one exemplary embodiment of this disclosure, the variety of transistors further includes a sixth transistor as a light-emitting control transistor. In the same pixel driving circuit, in the column direction, the driving transistor is located on one side of the sixth transistor, the first transistor and the second transistor are located on the other side of the sixth transistor, and the seventh transistor is located on the side of the first transistor and the second transistor away from the sixth transistor.

[0056] In one exemplary embodiment of this disclosure, the control signal line further includes a plurality of second light-emitting control signal lines, which extend along the row direction and are spaced apart along the column direction; the second light-emitting control signal lines are electrically connected to the control electrode of at least a portion of the sixth transistor in at least one row of pixel driving circuits.

[0057] In the same row of pixel driving circuits, in the column direction, the second light emission control signal line is located between the at least one capacitor and the first reset signal line, and there is no overlap between the orthogonal projection of the second light emission control signal line and the at least one capacitor on the substrate.

[0058] In one exemplary embodiment of this disclosure, in a direction perpendicular to the plane of the substrate, the third reset signal line is located on the side of the at least one capacitor away from the substrate, and the first reset signal line, the second reset signal line, the second light emission control signal line, the first initialization power line, and the second initial power line are located on the side of the third reset signal line away from the substrate.

[0059] In one exemplary embodiment of this disclosure, in the row direction, the first transistor is located on one side of the driving transistor, and the second transistor is located on the other side of the driving transistor;

[0060] In the same pixel driving circuit, the orthogonal projection of the driving transistor on the substrate at least partially overlaps with the orthogonal projection of the at least one capacitor on the substrate.

[0061] According to one aspect of this disclosure, a display device is provided, comprising the display substrate described in any one of the foregoing claims.

[0062] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0063] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0064] Figure 1 is a schematic diagram of a display device;

[0065] Figure 2 is a schematic diagram of the structure of a display substrate;

[0066] Figure 3 is a schematic cross-sectional view of a display substrate;

[0067] Figure 4 is a schematic diagram of the equivalent circuit of a pixel driving circuit;

[0068] Figure 5a shows a schematic diagram of the structure of the display substrate provided in an embodiment of this disclosure;

[0069] Figure 5b shows a schematic diagram of the structure of the display substrate provided in an embodiment of this disclosure;

[0070] Figure 6 is a schematic diagram of a display substrate after the formation of the first conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0071] Figure 7a is a schematic diagram of a display substrate after the formation of the second conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0072] Figure 7b is a schematic diagram of the second conductive layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0073] Figure 8a is a schematic diagram of a display substrate after a semiconductor layer pattern has been formed, according to an exemplary embodiment of the present disclosure.

[0074] Figure 8b is a schematic diagram of the second semiconductor layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0075] Figure 9a is a schematic diagram of a display substrate after the formation of a third conductive layer pattern according to an exemplary embodiment of the present disclosure.

[0076] Figure 9b is a schematic diagram of the third conductive layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0077] Figure 10 is a schematic diagram of a display substrate after the formation of a fourth insulating layer pattern according to an exemplary embodiment of the present disclosure;

[0078] Figure 11a is a schematic diagram of a display substrate after the fourth conductive layer pattern is formed, according to an exemplary embodiment of the present disclosure.

[0079] Figure 11b is a schematic diagram of the fourth conductive layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0080] Figure 12 is a schematic diagram showing the formation of a first planarization layer pattern according to an exemplary embodiment of the present disclosure;

[0081] Figure 13a is a schematic diagram of a display substrate after the fifth conductive layer pattern is formed, according to an exemplary embodiment of the present disclosure.

[0082] Figure 13b is a schematic diagram of the fifth conductive layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0083] Figure 14 is a schematic diagram of a display substrate after a second planarization layer pattern has been formed, according to an exemplary embodiment of the present disclosure.

[0084] Figure 15a is a schematic diagram of a display substrate after an anode conductive layer pattern has been formed, according to an exemplary embodiment of the present disclosure.

[0085] Figure 15b is a schematic diagram of the anode conductive layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0086] Figure 16a is a schematic diagram of a display substrate after forming a pixel definition layer pattern according to an exemplary embodiment of the present disclosure;

[0087] Figure 16b is a schematic diagram of a pixel definition layer pattern of a display substrate provided in an exemplary embodiment of the present disclosure;

[0088] Figure 17a is a schematic diagram of a display substrate after the fourth conductive layer pattern is formed, according to an exemplary embodiment of the present disclosure.

[0089] Figure 17b is a schematic diagram of the fourth conductive layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0090] Figure 18 is a schematic diagram showing the formation of a first planarization layer pattern according to an exemplary embodiment of the present disclosure;

[0091] Figure 19 is a schematic diagram of a display substrate after the fifth conductive layer pattern is formed, according to an exemplary embodiment of the present disclosure.

[0092] Figure 20 is a schematic diagram of a display substrate after forming a second planarization layer pattern according to an exemplary embodiment of the present disclosure;

[0093] Figure 21 is a schematic diagram of a display substrate after an anode conductive layer pattern has been formed, according to an exemplary embodiment of the present disclosure.

[0094] Figure 22 is a schematic diagram of a display substrate after forming a pixel definition layer pattern according to an exemplary embodiment of the present disclosure. Detailed Implementation

[0095] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in many ways without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as being limited only to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to with reference to general designs.

[0096] The scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the thickness and spacing of each film layer, and the width and spacing of each signal line, can be adjusted according to actual conditions. The drawings described in this disclosure are merely structural schematic diagrams, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0097] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0098] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0099] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0100] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0101] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged. In embodiments of this disclosure, the gate electrode can be referred to as the control electrode.

[0102] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0103] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0104] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0105] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0106] In the embodiments of this disclosure, "about" means a value that is not strictly limited and is within the range of process and measurement errors.

[0107] Figure 1 shows a schematic diagram of a display device. The display substrate may include a timing controller, a data signal driving circuit, a scan signal driving circuit, a light emission signal driving circuit, and a pixel array. The timing controller is connected to the data signal driving circuit, the scan signal driving circuit, and the light emission signal driving circuit. The data signal driving circuit is connected to multiple data signal lines (D1 to Dn), the scan signal driving circuit is connected to multiple scan signal lines (G1 to Gm), and the light emission signal driving circuit is connected to multiple light emission signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light emission device connected to the circuit unit. The circuit unit may include a pixel driving circuit, which may be connected to the scan signal lines, the light emission signal lines, and the data signal lines (which may be referred to as data lines). In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data signal driving circuit to the data signal driving circuit, clock signals, scan start signals, etc. of specifications suitable for the scan signal driving circuit to the scan signal driving circuit, and clock signals, transmit stop signals, etc. of specifications suitable for the light emission signal driving circuit to the light emission signal driving circuit. The data signal driving circuit can use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data signal driving circuit can sample the grayscale values ​​using a clock signal and apply the data voltage corresponding to the grayscale value to data signal lines D1 to Dn on a pixel-by-pixel basis, where n can be a natural number. The scan signal driving circuit can generate scan signals to be provided to scan signal lines G1, G2, G3, ..., Gm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan signal driving circuit can sequentially provide scan signals with conduction level pulses to scan signal lines G1 to Gm. For example, a scan signal driving circuit can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal, where m can be a natural number. A light-emitting signal driving circuit can generate transmit signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from a timing controller. For example, a light-emitting signal driving circuit can sequentially provide transmit signals with cutoff level pulses to light-emitting signal lines E1 to Eo. For example, a light-emitting driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals, provided in the form of cutoff level pulses, to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0108] Figure 2 is a schematic diagram of a planar structure of a display substrate. As shown in Figure 2, the display substrate may include multiple pixel units P arranged in a matrix. At least one pixel unit P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each of the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 includes a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 are respectively connected to the pixel driving circuit of their respective sub-pixels. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of their respective sub-pixels.

[0109] In an exemplary embodiment, a pixel unit P may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. In an exemplary embodiment, the shape of the sub-pixels in the pixel unit may be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels may be arranged horizontally side by side, vertically side by side, or in a triangular arrangement; this disclosure does not limit the specific arrangement.

[0110] Figure 3 is a cross-sectional schematic diagram of a display substrate, illustrating the structure of three sub-pixels of an OLED display substrate. As shown in Figure 3, on a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 101, and an encapsulation layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as spacers, etc., which are not limited herein.

[0111] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 for each sub-pixel may include multiple transistors and storage capacitors constituting the pixel driving circuit. The light-emitting structure layer 103 may include an anode 301, an organic light-emitting layer 302, and a cathode 303. The anode 301 is connected to the drain electrode of the driving transistor 210 through a via. The organic light-emitting layer 302 is connected to the anode 301, and the cathode 303 is connected to the organic light-emitting layer 302. The organic light-emitting layer 302 emits light of a corresponding color under the driving force of the anode 301 and the cathode 303. The encapsulation layer 104 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked together. The first and third encapsulation layers 401 and 403 may be made of inorganic materials, while the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is disposed between the first and third encapsulation layers 401 and 403, ensuring that external moisture cannot enter the light-emitting structure layer 103.

[0112] In an exemplary embodiment, the organic light-emitting layer 302 may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In this exemplary embodiment, the hole injection layer of all sub-pixels may be a common layer connected together, the electron injection layer of all sub-pixels may be a common layer connected together, the hole transport layer of all sub-pixels may be a common layer connected together, the electron transport layer of all sub-pixels may be a common layer connected together, and the hole block layer of all sub-pixels may be a common layer connected together. The emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0113] In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, 8T1C, or 7T2C structure. Figure 4 is an equivalent circuit diagram of a pixel driving circuit. As shown in Figure 4, the pixel driving circuit can include 7 transistors (first transistor T1 to seventh transistor T7) and 2 capacitors C (first capacitor C1 and second capacitor C2). The pixel driving circuit can be connected to 11 signal lines (data signal line D, scan signal line Gate, first reset control line Reset1, second reset control line Reset2, third reset control line Reset3, first light emission control line EM1, second light emission control line EM2, first initial signal line Vinit1, second initial signal line Vinit2, first power supply line VDD, and second power supply line VSS).

[0114] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, a fourth node N4, and a fifth node N5. The first node N1 is connected to the control electrode of the third transistor T3, the second electrode of the fourth transistor T4, the second terminal of the second capacitor C2, and the second electrode of the first transistor T1. The second node N2 is connected to the first electrode of the third transistor T3 and the second electrode of the fifth transistor T5. The third node N3 is connected to the second terminal of the first capacitor C1, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6. The fourth node N4 is connected to the first terminal of the first capacitor C1, the first terminal of the second capacitor C2, and the second electrode of the second transistor T2. The fifth node N5 is connected to the second electrode of the sixth transistor T6, the second electrode of the seventh transistor T7, and the anode of the light-emitting device EL.

[0115] In an exemplary embodiment, the first terminal of the first capacitor C1 is connected to the fourth node N4, and the second terminal of the first capacitor C1 is connected to the third node N3; the first terminal of the second capacitor C2 is connected to the fourth node N4, and the second terminal of the second capacitor C2 is connected to the first node N1.

[0116] The control electrode of the first transistor T1 is connected to the first reset control line Reset1, the first terminal of the first transistor T1 is connected to the first initial signal line Vinit1, and the second terminal of the first transistor is connected to the first node N1. When a conduction-level reset signal is applied to the first reset control line Reset1, the first transistor T1 transmits an initialization voltage to the control electrode of the third transistor T3 to initialize the charge on the control electrode of the third transistor T3.

[0117] The control electrode of the second transistor T2 is connected to the second reset control line Reset2, the first electrode of the second transistor T2 is connected to the first initial signal line Vinit1, and the second electrode of the second transistor T2 is connected to the fourth node N4.

[0118] The control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called the driving transistor. The third transistor T3 determines the amount of driving current flowing between the first power line VDD and the second power line VSS based on the potential difference between its control electrode and its first electrode.

[0119] The control electrode of the fourth transistor T4 is connected to the scan signal line Gate, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor. When a conduction-level scan signal is applied to the scan signal line Gate, the fourth transistor T4 causes the data voltage of the data signal line D to be input to the pixel driving circuit.

[0120] The control electrode of the fifth transistor T5 is connected to the first light-emitting control line EM1, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2. The control electrode of the sixth transistor T6 is connected to the second light-emitting control line M2E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device (also the fifth node N5). The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors. When a conduction-level light-emitting signal is applied to the first light-emitting control line EM1 and the second light-emitting control line EM2, the fifth transistor T5 and the sixth transistor T6 conduct, forming a driving current path between the first power supply line VDD and the second power supply line VSS, causing the light-emitting device to emit light.

[0121] The control electrode of the seventh transistor T7 is connected to the third reset control line Reset3, the first electrode of the seventh transistor T7 is connected to the second initial signal line Vinit2, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device (also the fifth node N5). When a conduction-level reset signal is applied to the third reset control line Reset3, the seventh transistor T7 transmits an initialization voltage to the first electrode of the light-emitting device to initialize or release the accumulated charge in the first electrode of the light-emitting device.

[0122] In an exemplary embodiment, the second electrode of the light-emitting device is connected to the second power line VSS, where the signal on the second power line VSS is a low-level signal, and the signal on the first power line VDD is a continuously high-level signal. In this exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit simplifies the process flow, reduces the manufacturing difficulty of the display panel, and improves product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors.

[0123] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be a low-temperature polycrystalline silicon thin-film transistor (LTPS), or an oxide thin-film transistor (N-type transistor), or a combination of both. Using the same type of transistor in the pixel driving circuit simplifies the process flow, reduces the manufacturing difficulty of the display panel, and improves product yield. The active layer of the LTPS is made of low-temperature polycrystalline silicon, while the active layer of the oxide thin-film transistor is made of oxide. LTPS transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current, low-frequency driving capability, and low power consumption. Integrating LTPS and oxide thin-film transistors onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0124] In an exemplary embodiment, the light-emitting device EL can be an organic light-emitting diode (OLED), including a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together.

[0125] Due to limitations in pixel architecture and layout space, such as in display substrates requiring high PPI, the signal traces in the pixel driving circuit are relatively dense. In actual structures, the distance between signal traces in the pixel driving circuit is usually close, or the signal traces in two conductive layers overlap, which can easily cause crosstalk problems and affect display quality. In addition, the characteristics of the transistors (TFTs) in the pixel driving circuit will shift under illumination, which will also affect display quality.

[0126] An exemplary embodiment of this disclosure provides a display substrate, which may include: a substrate and a plurality of sub-pixels, a plurality of first voltage-regulating signal lines, a plurality of second voltage-regulating signal lines, and a plurality of data signal lines disposed on one side of the substrate; at least some of the sub-pixels include pixel driving circuits, the pixel driving circuits of the at least some of the sub-pixels forming multiple columns, and the data signal lines being electrically connected to at least some of the pixel driving circuits in at least one column of pixel driving circuits; the plurality of first voltage-regulating signal lines extending along a row direction and spaced apart along a column direction, the row direction intersecting the column direction; the plurality of second voltage-regulating signal lines and the plurality of data signal lines extending along the column direction and spaced apart along the row direction;

[0127] At least a portion of the first voltage-regulated signal line is provided with multiple shielding structures. In the row direction, the multiple shielding structures are arranged at intervals. The data signal line is located between two adjacent second voltage-regulated signal lines. The data signal line and at least one second voltage-regulated signal line located on both sides of the data signal line correspond to at least one shielding structure. The orthographic projection of at least a portion of the shielding structure on the substrate is located between the orthographic projection of the corresponding data signal line on the substrate and the orthographic projection of the corresponding second voltage-regulated signal line on the substrate.

[0128] In a direction perpendicular to the plane of the substrate, the data signal line and the second voltage-regulated signal line are located on the side of the first voltage-regulated signal line away from the substrate, and the first voltage-regulated signal line is located on the side of at least some components in the pixel driving circuit away from the substrate.

[0129] The display substrate provided in this embodiment includes a plurality of first regulated signal lines, a plurality of second regulated signal lines, a plurality of data signal lines, and a plurality of shielding structures. At least a portion of the first regulated signal lines are provided with a plurality of shielding structures. In the row direction, the plurality of shielding structures are arranged at intervals. The data signal lines are located between two adjacent second regulated signal lines. A data signal line and at least one second regulated signal line located on both sides of the data signal line correspond to at least one shielding structure. The orthographic projection of at least a portion of the shielding structure on the substrate is located between the orthographic projection of the corresponding data signal line on the substrate and the orthographic projection of the corresponding second regulated signal line on the substrate. In the direction perpendicular to the plane of the substrate, the data signal line and the second regulated signal line are located on the side of the first regulated signal line away from the substrate. The first regulated signal line is located on the side of at least a portion of the components in the pixel driving circuit away from the substrate. The shielding structures on the first regulated signal lines can shield the signals on the data signal lines, reduce the interference of the data signal lines to the at least a portion of the components, and reduce signal crosstalk between the data signal lines and the at least a portion of the components, thereby improving the display effect.

[0130] As shown in Figures 5a and 5b, these are schematic diagrams of a planar structure of a display substrate provided in an embodiment of this disclosure. The display substrate provided in this embodiment may include: a substrate and a plurality of sub-pixels Pxij, a plurality of first voltage-regulating signal lines VH, a plurality of second voltage-regulating signal lines VL, and a plurality of data signal lines Data disposed on one side of the substrate; at least a portion of the sub-pixels Pxij include pixel driving circuits, and the pixel driving circuits of at least a portion of the sub-pixels Pxij form multiple columns; the data signal lines Data are electrically connected to at least a portion of the pixel driving circuits in at least one column of pixel driving circuits; the plurality of first voltage-regulating signal lines VH extend along the row direction X and are spaced apart along the column direction Y, and the row direction X intersects the column direction Y; the plurality of second voltage-regulating signal lines VL and the plurality of data signal lines Data extend along the column direction Y and are spaced apart along the row direction X;

[0131] At least a portion of the first regulated signal line VH is provided with multiple blocking structures ZD. In the row direction X, the multiple blocking structures ZD are arranged at intervals. The data signal line Data is located between two adjacent second regulated signal lines VL. The data signal line Data and at least one second regulated signal line VL located on both sides of the data signal line Data correspond to at least one blocking structure ZD. The orthographic projection of at least a portion of the structure in the blocking structure ZD on the substrate is located between the orthographic projection of the corresponding data signal line Data on the substrate and the orthographic projection of the corresponding second regulated signal line VL on the substrate.

[0132] In a direction perpendicular to the plane of the substrate, the data signal line Data and the second voltage regulator signal line VL are located on the side of the first voltage regulator signal line VH away from the substrate, and the first voltage regulator signal line VL is located on the side of the pixel driving circuit where at least some components are away from the substrate.

[0133] The shielding structure ZD is set between the second regulated signal line VL and the data signal line Data. The signal in the shielding structure ZD can, to a certain extent, act as a constant voltage signal to shield the data signal from the circuit nodes, reduce the parasitic capacitance between the data signal and the circuit nodes, thereby effectively reducing crosstalk and improving image quality.

[0134] In an exemplary embodiment, the first regulated signal line VH is located in the first source-drain metal layer, and the second regulated signal line VL and the data signal line Data are located in the second source-drain metal layer; or, the first regulated signal line VH is located in the second source-drain metal layer, and the second regulated signal line VL and the data signal line Data are located in the third source-drain metal layer.

[0135] In a direction perpendicular to the plane of the substrate, the second source / drain metal layer is located on the side of the first source / drain metal layer away from the substrate, and the third source / drain metal layer is located on the side of the second source / drain metal layer away from the substrate.

[0136] In an exemplary embodiment, as shown in Figures 5a and 5b, at least some sub-pixels may include a pixel driving circuit. The components in the at least some pixel driving circuit may include at least one capacitor and multiple transistors. The multiple transistors include at least one driving transistor T3. At least one plate of the at least one capacitor is connected to the control electrode of the driving transistor T3. In a direction perpendicular to the plane of the substrate, the first regulated signal line VH is located on the side of the capacitor away from the substrate.

[0137] In an exemplary embodiment, as shown in Figures 5a and 5b, at least one capacitor located in the same pixel driving circuit corresponds to at least one occlusion structure ZD. In the row direction X, at least a portion of the occlusion structure ZD is projected onto the substrate, with its orthographic projection located between the orthographic projection of the corresponding data signal line Data onto the substrate and the orthographic projection of the corresponding at least one capacitor onto the substrate.

[0138] In an exemplary embodiment, the orthographic projection of at least a portion of the structure in the shielding structure ZD onto the substrate is located between the orthographic projection of the corresponding data signal line Data onto the substrate and the orthographic projection of the corresponding at least one capacitor onto the substrate. On the one hand, this can shield the data signal line Data from interference to adjacent capacitor elements, thereby reducing signal interference between the data signal line Data and adjacent capacitors. The aforementioned at least a portion of the elements may include at least one capacitor adjacent to the data signal line Data. On the other hand, the signal in the shielding structure ZD can act as a constant voltage signal to shield the data signal from the circuit nodes, reducing the parasitic capacitance between the data signal and the circuit nodes, thereby effectively reducing crosstalk and improving image quality.

[0139] In an exemplary embodiment, as shown in Figures 5a and 5b, the at least one capacitor in the pixel driving circuit may include a first capacitor C1 and a second capacitor C2. The control electrode of the driving transistor T3 is connected to the second plate C22 of the second capacitor C2, and the second electrode of the driving transistor T3 is connected to the second plate C12 of the first capacitor.

[0140] In an exemplary embodiment, as shown in Figures 5a and 5b, the first node N1 corresponds to at least one shielding structure ZD. In the row direction, the orthographic projection of at least a portion of the shielding structure ZD onto the substrate is located between the orthographic projection of the corresponding data signal line Data onto the substrate and the orthographic projection of the corresponding first node N1 onto the substrate. The first node N1 is the node where the control electrode of the driving transistor T3 is connected to the second plate C22 of the second capacitor C2. The signal in the shielding structure ZD can be used as a constant voltage signal to shield the data signal from the first node N1, thereby reducing the parasitic capacitance between the data signal and the first node N1 and effectively reducing crosstalk.

[0141] In an exemplary embodiment, as shown in Figures 5a and 5b, the plurality of transistors may further include a second transistor T2 as a reset transistor, the second terminal of the second transistor T2 being connected to the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2.

[0142] The fourth node N4 corresponds to at least one blocking structure ZD. In the row direction X, the orthographic projection of at least a portion of the blocking structure ZD onto the substrate is located between the orthographic projection of the corresponding data signal line Data onto the substrate and the orthographic projection of the corresponding fourth node N4 onto the substrate. The fourth node N4 is the node where the second electrode of the second transistor T2 is connected to the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2.

[0143] In an exemplary embodiment, as shown in Figures 5a and 5b, in the row direction X, the occlusion structure ZD corresponds to the first node N1 and the fourth node N4 located on both sides of the corresponding data signal line Data. The orthographic projection of at least a portion of the structure in the occlusion structure ZD onto the substrate lies between the orthographic projections of the corresponding first node N1 and the corresponding fourth node N4 onto the substrate, and at least partially overlaps with the orthographic projections of the corresponding at least a portion of the data signal line Data onto the substrate. The signal in the occlusion structure ZD can act as a constant voltage signal to shield the data signal from the circuit nodes, reducing the parasitic capacitance between the data signal and the circuit nodes, thereby effectively reducing crosstalk and improving image quality.

[0144] In an exemplary embodiment, as shown in FIG5a, multiple occlusion structures ZD form multiple occlusion units ZD0. The occlusion unit ZD0 includes a first occlusion structure ZD1 and a second occlusion structure ZD2. The occlusion unit ZD0 corresponds to one of the data signal lines Data.

[0145] In an exemplary embodiment, in the row direction X, the blocking unit ZD0 corresponds to the first node N1 and the fourth node N4 on both sides of the corresponding data signal line Data. The first blocking structure ZD1 corresponds to the first node N1, and the second blocking structure ZD2 corresponds to the fourth node N4. Multiple blocking units ZD0 are arranged at intervals. In the same blocking unit ZD0, the second blocking structure ZD2 and the first blocking structure ZD1 are arranged at intervals in sequence. The first blocking structure ZD1 and the second blocking structure ZD2 are located on both sides of the corresponding data signal line Data. The first blocking structure ZD1 and the corresponding first node N1 are located on one side of the corresponding data signal line Data, and the second blocking structure ZD2 and the corresponding fourth node N4 are located on the other side of the corresponding data signal line Data. The first blocking structure ZD1 can reduce the signal crosstalk between the data signal line Data and the corresponding first node N1, and the second blocking structure ZD2 can reduce the signal crosstalk between the data signal line Data and the corresponding fourth node N4.

[0146] In an exemplary embodiment, as shown in FIG5a, in the row direction X, the orthographic projection of at least a portion of the structure in the first occlusion structure ZD1 onto the substrate is located between the orthographic projection of the corresponding data signal line Data onto the substrate and the orthographic projection of the corresponding first node N1 onto the substrate; the orthographic projection of at least a portion of the structure in the second occlusion structure ZD2 onto the substrate is located between the orthographic projection of the corresponding data signal line Data onto the substrate and the orthographic projection of the corresponding fourth node N4 onto the substrate.

[0147] By placing the first blocking structure ZD1 and the second blocking structure ZD2 between the circuit node and the data signal line Data, the signal in the blocking structure ZD can, to a certain extent, act as a constant voltage signal to shield the data signal from the circuit node, reducing the parasitic capacitance between the data signal and the circuit node, thereby effectively reducing crosstalk and improving image quality.

[0148] In an exemplary embodiment, as shown in FIG5b, the occlusion structure ZD corresponds to one of the data signal lines Data. In the row direction X, the occlusion structure ZD corresponds to the first node N1 and the fourth node N4 located on both sides of the corresponding data signal line Data. The orthographic projection of at least a portion of the structure in the occlusion structure ZD on the substrate is located between the orthographic projection of the corresponding first node N1 on the substrate and the orthographic projection of the corresponding fourth node N4 on the substrate, and at least partially overlaps with the orthographic projection of the corresponding at least a portion of the data signal line Data on the substrate.

[0149] In an exemplary embodiment, as shown in FIG5b, in the row direction X, the occlusion structure ZD corresponds to the first node N1 and the fourth node N4 located on both sides of the corresponding data signal line Data. The orthographic projection of at least a portion of the structure in the occlusion structure ZD onto the substrate is located between the orthographic projections of the corresponding first node N1 and the corresponding fourth node N4 onto the substrate, and at least partially overlaps with the orthographic projections of the corresponding at least a portion of the data signal line Data onto the substrate. The signal in the occlusion structure ZD can act as a constant voltage signal to shield the data signal from the nodes of the circuit (e.g., the first node N1 and the fourth node N4), reducing the parasitic capacitance between the data signal and the circuit nodes, thereby effectively reducing crosstalk and improving image quality.

[0150] In an exemplary embodiment, the shielding structure ZD can shield the signal of the data signal line Data, reducing the parasitic capacitance between the data signal line Data and the circuit nodes (e.g., the first node N1 and the fourth node N4), and reducing the signal crosstalk between the data signal line Data and the circuit nodes. Even if the distance between the data signal line Data and the circuit nodes (e.g., the first node N1 and the fourth node N4) is very close, the signal crosstalk and parasitic capacitance between the data signal line Data and the circuit nodes (e.g., the first node N1 and the fourth node N4) are still relatively small (the shielding effect of the shielding structure ZD increases the signal transmission path between the data signal line Data and the circuit nodes, thereby reducing crosstalk and parasitic capacitance). Therefore, with the shielding structure ZD set, the distance between the data signal line Data and the circuit nodes N1 and N4 can be reduced, thereby increasing the PPI of the display substrate, while the display effect will not be affected by the large parasitic capacitance and crosstalk between the data signal line Data and the circuit nodes N1 and N4.

[0151] In an exemplary embodiment, as shown in Figures 5a and 5b, in the row direction X, the first node N1 is located in the pixel driving circuit on one side of the corresponding data signal line Data, and the fourth node N4 is located in the pixel driving circuit on the other side of the corresponding data signal line Data.

[0152] In the same pixel driving circuit, in the row direction X, the first node N1 and the fourth node N4 are located on both sides of the first center line, which is the center line of the first capacitor C1 and the second capacitor C2 extending along the column direction Y.

[0153] In an exemplary embodiment, as shown in Figures 5a and 5b, the orthogonal projection of at least one capacitor on the substrate does not overlap with the orthogonal projection of the data signal line Data on the substrate, but at least partially overlaps with the orthogonal projections of at least a portion of the second regulated signal line VL and at least a portion of the first regulated signal line VH on the substrate, which can reduce signal crosstalk between the data signal line Data and the capacitor.

[0154] In an exemplary embodiment, in a direction perpendicular to the plane of the substrate, the capacitor includes a first electrode plate located on one side of the substrate and a second electrode plate located on the side of the first electrode plate away from the substrate; the transistor includes: an active layer located on the side of the second electrode plate away from the substrate, a control electrode located on the side of the active layer away from the substrate, and a first electrode and a second electrode located on the side of the control electrode away from the substrate.

[0155] The first voltage regulator signal line VH is disposed on the same layer as the first and second electrodes. In the direction perpendicular to the plane of the substrate, the second voltage regulator signal line VL is located on the side of the first and second electrodes away from the substrate.

[0156] In an exemplary embodiment, as shown in Figures 5a and 5b, the plurality of second voltage-stabilized signal lines VL may include a first type of second voltage-stabilized signal line VL-1 and a second type of second voltage-stabilized signal line VL-2, at least one capacitor located in the same pixel driving circuit, corresponding to one of the first type of second voltage-stabilized signal lines VL-1 and one of the second type of second voltage-stabilized signal lines VL-2.

[0157] The data signal line Data corresponds to one of the first type second voltage-regulated signal lines VL-1 and one of the second type second voltage-regulated signal lines VL-2. In the row direction X, the data signal line Data is located between the corresponding first type second voltage-regulated signal line VL-1 and the corresponding second type second voltage-regulated signal line VL-2. The at least one capacitor in the same pixel driving circuit and the corresponding first type second voltage-regulated signal line VL-1 and the corresponding second type second voltage-regulated signal line VL-2 are located between two adjacent data signal lines Data.

[0158] In an exemplary embodiment, as shown in Figures 5a and 5b, the first regulated signal line VH includes a first power connection line VSSL, and the second type of second regulated signal line VL-2 includes a first power line VSS. At least a portion of the first power line VSS and at least a portion of the first power connection line VSSL are connected through vias to form a mesh structure. In this exemplary embodiment, the mesh structure formed by connecting at least a portion of the first power lines and at least a portion of the first power connection lines through vias helps to reduce resistance, lower the loading of the regulated signal lines, and reduce power consumption.

[0159] In an exemplary embodiment, as shown in Figures 5a and 5b, the first type of second voltage regulation signal line VL-1 includes a first initialization power connection line Vinit1L, a second initialization power connection line Vinit2L, and a second power line VDD. The plurality of sub-pixels Pxij form a plurality of pixel units P. Each pixel unit P includes three sub-pixels. The pixel driving circuits of the three sub-pixels in the same pixel unit P are arranged sequentially along the row direction X.

[0160] The first initialization power connection line Vinit1L, the second initialization power connection line Vinit2L, and the second power line VDD, which are corresponding to the same pixel unit, are respectively located in the pixel driving circuits of the three sub-pixels in the pixel unit P.

[0161] In an exemplary embodiment, as shown in Figures 5a and 5b, a plurality of transistors include a first transistor T1 as an initialization transistor and a second transistor T2 as an initialization transistor. The first terminal of the first transistor T1 and the first terminal of the second transistor T2 are connected to a first initialization connection line Vinit1L. The orthographic projections of the first initialization transistor T1 and the second initialization transistor T2 on the substrate do not overlap with the orthographic projections of at least one capacitor on the substrate.

[0162] In an exemplary embodiment, as shown in Figures 5a and 5b, the display substrate further includes a plurality of first reset signal lines Reset1 and a plurality of second reset signal lines Reset2, wherein the plurality of first reset signal lines Reset1 and the plurality of second reset signal lines Reset2 extend along the row direction X and are spaced apart along the column direction Y;

[0163] The pixel driving circuits of at least some sub-pixels are formed in multiple rows. The first reset signal line Reset1 is electrically connected to the control electrode of at least some of the first transistors T1 in at least one row of pixel driving circuits, and the second reset signal line Reset2 is electrically connected to the control electrode of at least some of the second transistors T2 in at least one row of pixel driving circuits. The first reset signal line Reset1 and the second reset signal line Reset2 are disposed on the same layer as the first electrode and the second electrode, and their orthogonal projections on the substrate do not overlap with the orthogonal projections of at least one capacitor on the substrate, which can reduce the parasitic capacitance between the first reset signal line Reset1 and the second reset signal line Reset2 and the capacitor.

[0164] In an exemplary embodiment, as shown in Figures 5a and 5b, the plurality of transistors may further include a fourth transistor T4 as a data writing transistor and a sixth transistor T6 as a light-emitting control transistor. The first terminal of the fourth transistor T4 is connected to the data signal line Data, and the first terminal of the sixth transistor T6 is connected to the second terminal of the driving transistor T3. The orthographic projections of the fourth transistor T4 and the sixth transistor T6 on the substrate do not overlap with the orthographic projections of at least one capacitor on the substrate.

[0165] In the same pixel driving circuit, in the row direction X, the first transistor T1 and the second transistor T2 are located on both sides of the driving transistor T3; in the column direction Y, the first transistor T1 and the second transistor T2 are located on one side of the driving transistor T3, the fourth transistor T4 is located on the other side of the driving transistor T3, and the sixth transistor T6 is located between the third transistor T3 and the first transistor T1 and the second transistor T2.

[0166] In an exemplary embodiment, as shown in Figures 5a and 5b, the display substrate includes a plurality of scan signal lines Gate and a plurality of second light emission control signal lines EM2. The plurality of scan signal lines Gate and the plurality of second light emission control signal lines EM2 are disposed on the same layer as the first electrode and the second electrode, and extend along the row direction X and are spaced apart along the column direction Y.

[0167] At least some of the sub-pixels' pixel driving circuits form multiple rows, the scan signal line Gate is electrically connected to the control electrode of at least some of the fourth transistor T4 in at least one row of pixel driving circuits, and the second light emission control signal line EM2 is electrically connected to the control electrode of at least some of the sixth transistor T6 in at least one row of pixel driving circuits.

[0168] In the same row of pixel driving circuits, in the column direction Y, the first regulated signal line VH with a blocking structure ZD is located between the scan signal line Gate and the second light emission control signal line EM2.

[0169] In an exemplary embodiment, as shown in Figures 5a and 5b, the orthographic projection of the second light-emitting control signal line EM2 on the substrate and the orthographic projection of the capacitor on the substrate do not overlap, which can reduce the parasitic capacitance between the second light-emitting control signal line EM2 and the capacitor.

[0170] In an exemplary embodiment, in the same row pixel driving circuit, in the column direction Y, the occlusion structure ZD is located between the scan signal line Gate and the second light emission control signal line EM2.

[0171] In an exemplary embodiment, as shown in FIG5b, the shape of the occlusion structure ZD is a block structure, or as shown in FIG5a, the shape of the occlusion structure ZD is a strip or a broken line extending along the column direction Y.

[0172] In an exemplary embodiment, as shown in Figures 5a and 5b, the pixel driving circuit includes a seventh transistor T7 as a reset transistor and a fifth transistor T5 as a light-emitting control transistor; the first terminal of the seventh transistor T7 is connected to the second initialization power connection line Vinit2L, the first terminal of the fifth transistor T5 is connected to the second power line VDD, and the second terminal of the fifth transistor T5 is connected to the first terminal of the driving transistor T3.

[0173] In the listed direction Y, the fifth transistor T5 is located on the side of the fourth transistor T4 away from the driving transistor T3, and the seventh transistor T7 is located on the side of the first transistor T1 and the second transistor T2 away from the driving transistor T3.

[0174] In an exemplary embodiment, as shown in Figures 5a and 5b, the same pixel driving circuit corresponds to one of the first type second voltage regulator signal lines VL-1 and one of the second type second voltage regulator signal lines VL-2.

[0175] In the same pixel driving circuit: the orthographic projections of the channels of the first transistor T1 and the fourth transistor T4 onto the substrate at least partially overlap with the orthographic projections of the corresponding first-type second voltage-regulating signal line VL-1 onto the substrate; the orthographic projections of the channels of the driving transistor T3, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 onto the substrate at least partially overlap with the orthographic projections of the corresponding second-type second voltage-regulating signal line VL-2 onto the substrate, which can reduce the influence of illumination on the driving transistor T3, the second transistor T2, and the fifth transistor T5, and improve the stability of the driving transistor T3, the second transistor T2, and the fifth transistor T5.

[0176] In an exemplary embodiment, as shown in Figures 15a and 15b, at least some sub-pixels also include a plurality of anodes AN, which are located on the side of the plurality of second voltage regulation signal lines VL away from the substrate in a direction perpendicular to the plane of the substrate; the orthogonal projection of the channel of the seventh transistor T7 onto the substrate is located within the range of the orthogonal projection of at least one anode AN onto the substrate.

[0177] In an exemplary embodiment, a pixel unit includes at least a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3; in the same sub-pixel, the second electrode of the sixth transistor T6 and the second electrode of the seventh crystal T7 are electrically connected to the anode AN of the sub-pixel.

[0178] In the same pixel unit, the orthographic projection of the anode AN1 of the first sub-pixel P1 onto the substrate covers the orthographic projection of the channel of the seventh transistor T7 in the first sub-pixel P1 onto the substrate, which can reduce the influence of illumination on the seventh transistor T7 in the first sub-pixel P1 and improve the stability of the seventh transistor T7 in the first sub-pixel P1; the orthographic projection of the anode AN2 of the second sub-pixel P2 onto the substrate covers the orthographic projection of the channel of the seventh transistor T7 in the second sub-pixel P2 and the third sub-pixel P3 onto the substrate, which can reduce the influence of illumination on the seventh transistor T7 in the second sub-pixel P2 and the third sub-pixel P3 and improve the stability of the seventh transistor T7 in the second sub-pixel P2 and the third sub-pixel P3; the orthographic projection of the anode AN3 of the third sub-pixel P3 and the corresponding second type second voltage regulation signal line VL-2 onto the substrate covers the orthographic projection of the channel of the second crystal T2 transistor in this pixel unit onto the substrate, which can reduce the influence of illumination on the second transistor T2 and improve the stability of the second transistor T2.

[0179] This disclosure also provides a display substrate, as shown in Figures 5a and 5b. The display substrate may include a substrate and a plurality of sub-pixels Pxij disposed on one side of the substrate, and a plurality of control signal lines CL. At least one sub-pixel includes a pixel driving circuit, and the at least one pixel driving circuit includes a plurality of transistors and at least one capacitor. The plurality of transistors include at least a driving transistor. The pixel driving circuits of the plurality of sub-pixels Pxij form multiple rows. The plurality of control signal lines CL extend along the row direction X and are arranged at intervals along the column direction Y. The row direction X intersects the column direction Y. The control signal lines CL are electrically connected to the control electrode of at least one transistor in at least one row of pixel driving circuits. In the direction perpendicular to the plane of the substrate, the control signal lines CL are located on the side of the capacitor away from the substrate.

[0180] In the same pixel driving circuit, the control electrode of the driving transistor T3 is electrically connected to at least one plate of at least one capacitor; the orthographic projection of at least one control signal line CL on the substrate and the orthographic projection of at least one capacitor on the substrate do not overlap.

[0181] In an exemplary embodiment, the orthographic projection of at least one control signal line CL on the substrate and the orthographic projection of at least one capacitor on the substrate do not overlap, which can reduce the parasitic capacitance between the control signal line CL and the capacitor.

[0182] In an exemplary embodiment, as shown in Figures 5a and 5b, the types of multiple transistors include at least a first transistor T1 as an initialization transistor, a second transistor T2 as an initialization transistor, and a seventh transistor T7 as an initialization transistor, and the control signal line CL includes at least a first reset signal line Reset1, a second reset signal line Reset2, and a third reset signal line Reset3.

[0183] The first reset signal line Reset1 is electrically connected to the control electrode of at least a portion of the first transistor T1 in at least one row of pixel driving circuits; the second reset signal line Reset2 is electrically connected to the control electrode of at least a portion of the second transistor T2 in at least one row of pixel driving circuits; and the third reset signal line Reset3 is electrically connected to the control electrode of at least a portion of the seventh transistor T7 in at least one row of pixel driving circuits. The orthographic projections of the first reset signal line Reset1, the second reset signal line Reset2, and the third reset signal line Reset3 on the substrate do not overlap with the orthographic projection of at least one capacitor on the substrate, which can reduce the parasitic capacitance between the first reset signal line Reset1, the second reset signal line Reset2, the third reset signal line Reset3 and the capacitor.

[0184] In an exemplary embodiment, as shown in Figures 5a and 5b, there are multiple first initialization power lines Vinit1 and multiple second initialization power lines Vinit2, which extend along the row direction X and are arranged at intervals along the column direction Y.

[0185] The first initialization power line Vinit1 is connected to the first terminal of the first transistor T1 and the first terminal of the second transistor T2 in at least one row of pixel driving circuits; the second initialization power line Vinit2 is connected to the first terminal of the seventh transistor T7 in at least one row of pixel driving circuits.

[0186] In the same pixel driving circuit, in the column direction Y, the first reset signal line Reset1, the second reset signal line Reset2, the first initial power supply line Vinit1, the third reset signal line Reset3, and the second initial power supply line Vinit2 are arranged in sequence at intervals and are located on the same side of the driving transistor T3 and at least one capacitor.

[0187] In an exemplary embodiment, as shown in Figures 5a and 5b, the variety of transistors also includes a sixth transistor T6 as a light-emitting control transistor. In the same pixel driving circuit, in the column direction Y, the driving transistor T3 is located on one side of the sixth transistor T6, the first transistor T1 and the second transistor T2 are located on the other side of the sixth transistor T6, and the seventh transistor T7 is located on the side of the first transistor T1 and the second transistor T2 away from the sixth transistor T6.

[0188] In an exemplary embodiment, as shown in Figures 5a and 5b, the control signal line CL further includes a plurality of second light emission control signal lines EM2, which extend along the row direction X and are spaced apart along the column direction Y; the second light emission control signal lines EM2 are electrically connected to the control electrode of at least a portion of the sixth transistor T6 in at least one row pixel driving circuit.

[0189] In the same row of pixel driving circuits, in the column direction Y, the second light emission control signal line EM2 is located between at least one capacitor and the first reset signal line Reset1. The orthogonal projections of the second light emission control signal line EM2 and at least one capacitor on the substrate do not overlap, which can reduce the parasitic capacitance between the second light emission control signal line EM2 and the capacitor.

[0190] In an exemplary embodiment, in a direction perpendicular to the plane of the substrate, the third reset signal line Reset3 is located on the side of at least one capacitor away from the substrate, and the first reset signal line Reset1, the second reset signal line Reset2, the second light emission control signal line EM2, the first initialization power line Vinit1, and the second initial power line Vinit2 are located on the side of the third reset signal line Reset3 away from the substrate.

[0191] In an exemplary embodiment, as shown in Figures 5a and 5b, in the row direction X, the first transistor T1 is located on one side of the driving transistor T3, and the second transistor T2 is located on the other side of the driving transistor T3.

[0192] In the same pixel driving circuit, the orthographic projection of the driving transistor T3 on the substrate at least partially overlaps with the orthographic projection of at least one capacitor on the substrate.

[0193] In an exemplary embodiment, the row direction X can be referred to as the first direction X, and the column direction Y can be referred to as the second direction Y.

[0194] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film of a certain material fabricated on a substrate (or substrate plate) using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0195] In an exemplary embodiment, taking three sub-pixels (a row of pixel driving circuits for one sub-pixel and a column of pixel driving circuits for three sub-pixels) in the display area (AA) as an example, the fabrication process of a display substrate may include the following operations.

[0196] (101) A substrate is prepared on a glass substrate. In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may include, but is not limited to, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, an adhesive layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer soft films, etc. The materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also called barrier layers, and the material of the adhesive layer may be amorphous silicon (a-Si). In an exemplary embodiment, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, its preparation process may include: firstly, coating a layer of polyimide on a glass substrate, curing it into a film to form a first flexible material (PI1) layer; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible material layer; then depositing an amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating another layer of polyimide on the amorphous silicon layer, curing it into a film to form a second flexible material (PI2) layer; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thus completing the substrate preparation.

[0197] (102) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: depositing a first conductive film on a substrate, patterning the first conductive film using a patterning process, and forming a first conductive layer pattern on the substrate. As shown in FIG6, which is a schematic diagram of the planar structure of three sub-pixels after the formation of the first conductive layer, the first conductive layer may be referred to as the first gate metal (GATE1) layer.

[0198] In an exemplary embodiment, the first conductive layer pattern may include at least: a first electrode C11 of a first capacitor C1 and a first electrode C21 of a second capacitor C2; in the same sub-pixel, the first electrode C11 of the first capacitor C1 and the first electrode C21 of the second capacitor C2 are interconnected, for example, the first electrode C11 of the first capacitor C1 and the first electrode C21 of the second capacitor C2 may be an integrally formed structure.

[0199] (103) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a first insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second conductive film using a patterning process to form a first insulating layer covering the first conductive layer; and a second conductive layer pattern disposed on the first insulating layer, as shown in Figures 7a and 7b. Figure 7a is a planar structural diagram of three sub-pixels after the formation of the second conductive layer, and Figure 7b is a planar schematic diagram of the second conductive layer in Figure 7a. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0200] In an exemplary embodiment, the second conductive layer pattern includes at least: a second electrode C12 of the first capacitor C1 and a second electrode C22 of the second capacitor C2. In the second direction Y, within the same sub-pixel, the second electrode C12 of the first capacitor C1 can be located on one side of the second electrode C22 of the second capacitor C2. For example, within the same sub-pixel, the second electrodes C12 of the first capacitor C1 and C22 of the second capacitor C2 can be arranged sequentially along the second direction Y.

[0201] In an exemplary embodiment, the outlines of the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 can be approximately rectangular, with at least one edge of the rectangle having a broken line structure. The orthographic projections of the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 on the substrate overlap with the orthographic projections of the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 on the substrate. For example, the orthographic projections of the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 on the substrate can be located within the range of the orthographic projections of the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 on the substrate. In an exemplary embodiment, the first plate C11 and the second plate C12 of the first capacitor C1 constitute the first capacitor C1, and the first plate C21 and the second plate C22 of the second capacitor C2 constitute the second capacitor C2.

[0202] In an exemplary embodiment, a protrusion K11 may be provided on the first plate C11 of the first capacitor C1. The protrusion K11 may be located at the edge of the first plate C11 of the first capacitor C1 (e.g., the protrusion K11 may be located at a corner of the first plate C11 of the first capacitor C1). The outline of the protrusion K11 may be generally rectangular. In an exemplary embodiment, the protrusion K11 is configured to accommodate a subsequently formed ninth via and a twelfth via, which are located on the protrusion K11, so that the second electrode of the subsequently formed second transistor T2 is connected to the first plate C21 of the second capacitor C2 (which is also the first plate C11 of the first capacitor C1).

[0203] In an exemplary embodiment, the second conductive layer in two adjacent columns of pixel driving circuits can be the same, and the second conductive layer in two adjacent rows of pixel driving circuits can be the same.

[0204] (104) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: depositing a second insulating film and a semiconductor film sequentially on a substrate on which the aforementioned pattern is formed, patterning the semiconductor film using a patterning process to form a second insulating layer covering the substrate, and a semiconductor layer pattern disposed on the second insulating layer, as shown in Figures 8a to 8b. Figure 8a is a planar structural diagram of three sub-pixels after the semiconductor layer is formed, and Figure 8b is a planar schematic diagram of the semiconductor layer in Figure 8a.

[0205] In an exemplary embodiment, the semiconductor layer pattern in at least some of the sub-pixels includes at least: the active layer AT1 of the first transistor T1 to the active layer AT7 of the seventh transistor T7.

[0206] In an exemplary embodiment, within the same sub-pixel, the active layer AT1 of the first transistor T1 and the active layer AT4 of the fourth transistor T4 can be interconnected, the active layer AT3 of the third transistor T3, the active layer AT5 of the fifth transistor T5 to the active layer AT7 of the seventh transistor T7 can be interconnected, and the active layer AT2 of the second transistor T2 can be independently configured. For example, the active layer AT1 of the first transistor T1 and the active layer AT4 of the fourth transistor T4 can be an interconnected integral structure, and the active layer AT3 of the third transistor T3, the active layer AT5 of the fifth transistor T5 to the active layer AT7 of the seventh transistor T7 can be an interconnected integral structure.

[0207] In an exemplary embodiment, within the same sub-pixel, in the first direction X, the active layer of the first transistor T1 and the active layer AT4 of the fourth transistor T4 may be located on the same side of the active layers AT5 of the fifth transistor T5 to the active layers AT7 of the seventh transistor T7, and the active layer AT2 of the second transistor T2 may be located on the other side of the active layers AT5 of the fifth transistor T5 to the active layers AT7 of the seventh transistor T7; in the second direction Y, the active layers AT5 of the fifth transistor T5 and the active layers AT6 of the sixth transistor T6 are located on both sides of the active layer AT3 of the third transistor T3, and the active layer AT7 of the seventh transistor T7 is located on the side of the active layer AT6 of the sixth transistor T6 away from the active layer AT3 of the third transistor T3.

[0208] In an exemplary embodiment, taking the sub-pixel in the Mth row and Nth column as an example: In the first direction X, the active layer AT1 of the first transistor T1 and the active layer AT4 of the fourth transistor T4 are located on the side away from the active layers AT3 of the third transistor T3, AT5 of the fifth transistor T5, and AT6 of the sixth transistor T6, respectively. The active layer AT2 of the second transistor T2 is located near the active layers AT3 of the third transistor T3, AT5 of the fifth transistor T5, and AT6 of the sixth transistor T6, respectively. On one side of the sub-pixel; in the second direction Y, the active layer AT4 of the fourth transistor T4 is located on the side of the active layer AT1 of the first transistor T1 away from the sub-pixel of the M+1 row, the active layer AT2 of the second transistor T2 is located on the side of the active layer AT3 of the third transistor T3 away from the sub-pixel of the M-1 row, the active layer AT7 of the seventh transistor T7 is located on the side of the active layer AT6 of the sixth transistor T6 close to the sub-pixel of the M+1 row, and the active layer AT5 of the fifth transistor T5 is located on the side of the active layer AT3 of the third transistor T3 away from the sub-pixel of the M+1 row.

[0209] In an exemplary embodiment, the active layer AT1 of the first transistor T1, the active layer AT2 of the second transistor T2, the active layer AT3 of the third transistor T3, the active layer AT4 of the fourth transistor T4, the active layer AT5 of the fifth transistor T5, and the active layer AT6 of the sixth transistor T6 can be in the shape of an "I" and the active layer 27 of the seventh transistor T7 can be in the shape of an "L".

[0210] In an exemplary embodiment, the active layer of at least some transistors may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the second region AT12 of the active layer AT1 of the first transistor T1 can serve as the second region AT42 of the active layer AT4 of the fourth transistor T4, the first region AT31 of the active layer AT3 of the third transistor T3 can serve as the second region AT52 of the active layer AT5 of the fifth transistor T5, the second region AT32 of the active layer AT3 of the third transistor T3 can serve as the first region AT61 of the active layer AT6 of the sixth transistor T6, and the second region AT62 of the active layer AT6 of the sixth transistor T6 can serve as the second region AT72 of the active layer AT7 of the seventh transistor T7. The first region AT11 of the active layer AT1 of the first transistor T1, the first region AT41 of the active layer AT4 of the fourth transistor T4, the first region AT51 of the active layer AT5 of the fifth transistor T5, and the first region AT71 of the active layer AT7 of the seventh transistor T7 can be individually configured.

[0211] In an exemplary embodiment, the active layers in two adjacent columns of pixel driving circuits are substantially the same, and the active layers in two adjacent rows of pixel driving circuits are substantially the same.

[0212] In an exemplary embodiment, the conductor layer may be an oxide, i.e., the first transistor T1 to the seventh transistor T7 are oxide thin-film transistors. In an exemplary embodiment, the oxide may be any one or more of the following: indium gallium zinc oxide (InGaZnO), indium gallium zinc nitride (InGaZnON), zinc oxide (ZnO), zinc oxynitride (ZnON), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), lanthanum copper sulfide oxide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium gallium aluminum nitride (InGaAlN). In some possible implementations, the semiconductor thin film may be indium gallium zinc oxide (IGZO), which has a higher electron mobility than amorphous silicon. Since the leakage current of IGZO TFT is relatively small, using N-type transistors can avoid leakage at the first node N1 during the light-emitting stage.

[0213] (105) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: sequentially depositing a third insulating film and a third conductive film on a substrate on which the aforementioned pattern is formed; patterning the third conductive film using a patterning process to form a third insulating layer covering the semiconductor layer; and a third conductive layer pattern disposed on the third insulating layer, as shown in Figures 9a and 9b. Figure 9a is a planar structural diagram of three sub-pixels after the formation of the third conductive layer, and Figure 9b is a planar schematic diagram of the third conductive layer in Figure 9a. In an exemplary embodiment, the third conductive layer may be referred to as a third gate metal (GATE3) layer.

[0214] In an exemplary embodiment, the third conductive layer pattern includes at least: a first light-emitting control line EM1, a third reset control line Reset3, a control electrode T1g of a first transistor T1, a control electrode T2g of a second transistor T2, a control electrode T3g of a third transistor T3, a control electrode T4g of a fourth transistor T4, and a control electrode T6g of a sixth transistor T6. The first light-emitting control line EM1 and the third reset control line Reset3 can be zigzag or strip-shaped extending along the first direction X of the main body. In the same column of sub-pixels, the third reset control line Reset3 and the first light-emitting control line EM1 can be arranged at intervals along the second direction Y. In the second direction Y, in the same sub-pixel, the control electrodes T1g of the first transistor T1 to T4g of the fourth transistor T4 and T6g of the sixth transistor T6 can be located between the first light-emitting control line EM1 and the third reset control line Reset3.

[0215] In an exemplary embodiment, the region where the first light-emitting control line EM1 overlaps with the active layer AT5 of the fifth transistor T5 can be used as the control electrode of the fifth transistor T5, and the region where the third reset control line Reset3 overlaps with the active layer AT7 of the seventh transistor T7 can be used as the control electrode of the seventh transistor T7.

[0216] In an exemplary embodiment, the orthographic projection of the control electrode T1g of the first transistor T1 onto the substrate at least partially overlaps with the orthographic projection of the active layer AT1 of the first transistor T1 onto the substrate; the orthographic projection of the control electrode T2g of the second transistor T2 onto the substrate at least partially overlaps with the orthographic projection of the active layer AT2 of the second transistor T2 onto the substrate; the orthographic projection of the control electrode T3g of the third transistor T3 onto the substrate at least partially overlaps with the orthographic projection of the active layer AT3 of the third transistor T3 onto the substrate; the orthographic projection of the control electrode T4g of the fourth transistor T4 onto the substrate at least partially overlaps with the orthographic projection of the active layer AT4 of the fourth transistor T4 onto the substrate; and the orthographic projection of the control electrode T6g of the sixth transistor T6 onto the substrate at least partially overlaps with the orthographic projection of the active layer AT6 of the sixth transistor T6 onto the substrate.

[0217] In an exemplary embodiment, the control electrode T1g of the first transistor T1, the control electrode T2g of the second transistor T2, the control electrode T4g of the fourth transistor T4, and the control electrode T6g of the sixth transistor T6 are generally strip-shaped or zigzag-shaped structures extending along the first direction X, and the control electrode T3g of the third transistor T3 is generally rectangular. In the same sub-pixel, in the second direction Y, the control electrodes T1g of the first transistor T1, T2g of the second transistor T2, T3g of the third transistor T3, T4g of the fourth transistor T4, and T6g of the sixth transistor T6 are located between the first light-emitting control line EM1 and the third reset control line Reset3. The control electrode T1g of the first transistor T1 is located between the control electrode T2g of the second transistor T2 and the control electrode T6g of the sixth transistor T6. The control electrode T3g of the third transistor T3 can be located between the control electrode T4g of the fourth transistor T4 and the control electrode T6g of the sixth transistor T6. The control electrode T4g of the fourth transistor T4 can be located between the control electrode T3g of the third transistor T3 and the first light-emitting control line EM1. The control electrode T2g of the second transistor T2 can be located between the control electrode T1g of the first transistor T1 and the third reset control line Reset3. In the first direction X, in the same sub-pixel, the control electrodes T1g of the first transistor T1 and T4g of the fourth transistor T4 can be located on the same side of the control electrode T3g of the third transistor T3.

[0218] In an exemplary embodiment, the third conductive layer in adjacent row pixel driving circuits is substantially the same.

[0219] In an exemplary embodiment, after the third conductive layer pattern is formed, the third conductive layer can be used as a shield to conduct the semiconductor layer. The semiconductor layer in the region shielded by the third conductive layer forms the channel region of the first transistor T1 to the seventh transistor T7. The semiconductor layer in the region not shielded by the third conductive layer is conducted, that is, the first region and the second region of the active layer AT1 of the first transistor T1 to the active layer AT7 of the seventh transistor T7 are both conducted.

[0220] (106) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming a fourth insulating layer pattern may include: depositing a fourth insulating film on a substrate on which the aforementioned pattern is formed, and patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the third conductive layer. The fourth insulating layer has a plurality of vias, as shown in FIG10, FIG10 being a planar structural diagram of three sub-pixels after the fourth insulating layer is formed.

[0221] In an exemplary embodiment, at least some of the vias in the sub-pixels include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17, and an eighteenth via V18.

[0222] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate lies within the orthographic projection of the active layer AT1 of the first transistor T1 onto the substrate. The fourth and third insulating layers within the first via V1 are etched away, exposing the surface of the first region AT11 of the active layer AT1 of the first transistor T1. The first via V1 is configured to allow the first electrode of the subsequently formed first transistor T1 to be connected to the active layer AT1 of the first transistor T1 through the via.

[0223] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate lies within the orthographic projection of the active layer AT1 of the first transistor T1 onto the substrate. The fourth insulating layer and the third insulating layer within the second via V2 are etched away, exposing the surface of the second region AT12 of the active layer AT1 of the first transistor T1 (which is also the second region AT42 of the active layer AT4 of the fourth transistor T4). The second via V2 is configured to connect the second electrode of the subsequently formed first transistor T1 to the active layer AT1 of the first transistor T1 through the via, and to connect the second electrode of the subsequently formed fourth transistor T4 to the active layer AT4 of the fourth transistor T4 through the via.

[0224] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate lies within the orthographic projection of the active layer AT2 of the second transistor T2 onto the substrate. The fourth insulating layer and the third insulating layer within the third via V3 are etched away, exposing the surface of the first region AT21 of the active layer AT2 of the second transistor T2. The third via V3 is configured to allow the first electrode of the subsequently formed second transistor T2 to be connected to the active layer AT2 of the second transistor T2 through the via.

[0225] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate lies within the orthographic projection of the active layer AT3 of the third transistor T3 onto the substrate. The fourth and third insulating layers within the fourth via V4 are etched away, exposing the surface of the second region AT32 of the active layer AT3 of the third transistor T3 (which is also the first region AT61 of the active layer AT6 of the sixth transistor T6). The fourth via V4 is configured to connect the second electrode of the subsequently formed third transistor T3 to the active layer AT3 of the third transistor T3 through the via, and to connect the first electrode of the subsequently formed sixth transistor T6 to the active layer AT6 of the sixth transistor T6 through the via.

[0226] In an exemplary embodiment, the orthogonal projection of the fifth via V5 onto the substrate lies within the orthogonal projection of the active layer AT4 of the fourth transistor T4 onto the substrate. The fourth and third insulating layers within the fifth via V5 are etched away, exposing the first region AT41 of the active layer AT4 of the fourth transistor T4. The fifth via V5 is configured to allow the first electrode of the subsequently formed fourth transistor T4 to be connected to the active layer AT4 of the fourth transistor T4 through the via.

[0227] In an exemplary embodiment, the orthogonal projection of the sixth via V6 onto the substrate lies within the orthogonal projection of the active layer AT5 of the fifth transistor T5 onto the substrate. The fourth and third insulating layers within the sixth via V6 are etched away, exposing the surface of the first region AT51 of the active layer AT5 of the fifth transistor T5. The sixth via V6 is configured to allow the first electrode of the subsequently formed fifth transistor T5 to be connected to the active layer AT5 of the fifth transistor T5 through this via.

[0228] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate lies within the orthographic projection of the active layer AT6 of the sixth transistor T6 onto the substrate. The fourth and third insulating layers within the seventh via V7 are etched away, exposing the surface of the second region AT62 of the active layer AT6 of the sixth transistor T6 (which is also the second region AT72 of the active layer AT7 of the seventh transistor T7). The seventh via V7 is configured to connect the second electrode of the subsequently formed sixth transistor T6 to the active layer AT6 of the sixth transistor T6 through the via, and to connect the second electrode of the subsequently formed seventh transistor T7 to the active layer AT7 of the seventh transistor T7 through the via.

[0229] In an exemplary embodiment, the orthographic projection of the eighth via V8 onto the substrate lies within the orthographic projection of the active layer AT7 of the seventh transistor T7 onto the substrate. The fourth and third insulating layers within the eighth via V8 are etched away, exposing the surface of the first region AT71 of the active layer AT7 of the seventh transistor T7. The eighth via V8 is configured to allow the first electrode of the subsequently formed seventh transistor T7 to be connected to the active layer AT7 of the seventh transistor T7 through the via.

[0230] In an exemplary embodiment, the orthographic projection of the ninth via V9 onto the substrate lies within the range of the orthographic projection of the first electrode C11 of the first capacitor C1 onto the substrate (the orthographic projection of the ninth via V9 onto the substrate may lie within the range of the orthographic projection of the protrusion K11 onto the substrate). The fourth, third, second, and first insulating layers within the ninth via V9 are etched away, exposing the surface of the first electrode C11 of the first capacitor C1 (which is also the first electrode C21 of the second capacitor C2). The ninth via V9 is configured to allow the second electrode of the subsequently formed second transistor T2 to be connected to the first electrode C11 of the first capacitor C1 (which is also the first electrode C21 of the second capacitor C2) through this via.

[0231] In an exemplary embodiment, the orthographic projection of the tenth via V10 onto the substrate lies within the orthographic projection of the second electrode C12 of the first capacitor C1 onto the substrate. The fourth, third, and second insulating layers within the tenth via V10 are etched away, exposing the surface of the second electrode C12 of the first capacitor C1. The tenth via V10 is configured to allow the second electrode of the subsequently formed third transistor T3 (which is also the first electrode of the sixth transistor T6) to be connected to the second electrode C12 of the first capacitor C1 through this via.

[0232] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate lies within the range of the orthographic projection of the second electrode C22 of the second capacitor C2 onto the substrate. The fourth, third, and second insulating layers within the eleventh via V11 are etched away, exposing the surface of the second electrode C22 of the second capacitor C2. The eleventh via V11 is configured to allow a subsequently formed fourth connection electrode to be connected to the second electrode C22 of the second capacitor C2 through this via.

[0233] In an exemplary embodiment, the orthographic projection of the twelfth via V12 onto the substrate lies within the orthographic projection of the active layer AT2 of the second transistor T2 onto the substrate. The fourth and third insulating layers within the twelfth via V12 are etched away, exposing the surface of the second region AT22 of the active layer AT2 of the second transistor T2. The twelfth via V12 is configured to allow the second electrode of the subsequently formed second transistor T2 to be connected through the via to the first electrode C11 of the first capacitor C1 (which is also the first electrode C21 of the second capacitor C2).

[0234] In an exemplary embodiment, the orthogonal projection of the thirteenth via V13 onto the substrate lies within the orthogonal projection of the control electrode T1g of the first transistor T1 onto the substrate. The fourth insulating layer within the thirteenth via V13 is etched away, exposing the surface of the control electrode T1g of the first transistor T1. The thirteenth via V13 is configured to allow the subsequently formed first reset control line Reset1 to be connected to the control electrode T1g of the first transistor T1 through this via.

[0235] In an exemplary embodiment, the orthogonal projection of the fourteenth via V14 onto the substrate lies within the orthogonal projection of the control electrode T2g of the second transistor T2 onto the substrate. The fourth insulating layer within the fourteenth via V14 is etched away, exposing the surface of the control electrode T2g of the second transistor T2. The fourteenth via V14 is configured to allow the subsequently formed second reset control line Reset2 to connect to the control electrode T2g of the second transistor T2 through this via.

[0236] In an exemplary embodiment, the orthogonal projection of the fifteenth via V15 onto the substrate lies within the orthogonal projection of the control electrode T3g of the third transistor T3 onto the substrate. The fourth insulating layer within the fifteenth via V15 is etched away, exposing the surface of the control electrode T3g of the third transistor T3. The fifteenth via V15 is configured to allow the second electrode of the subsequently formed first transistor T1 (which is also the second electrode of the fourth transistor T4) to be connected to the control electrode T3g of the third transistor T3 through this via.

[0237] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 onto the substrate lies within the orthographic projection of the active layer AT4 of the fourth transistor T4 onto the substrate. The fourth and third insulating layers within the sixteenth via V16 are etched away, exposing the surface of the second region AT42 of the active layer AT4 of the fourth transistor T4 (which is also the second region AT12 of the active layer AT1 of the first transistor T1). The sixteenth via V16 is configured to allow a subsequently formed fourth connection electrode to be connected to the second region AT42 of the active layer AT4 of the fourth transistor T4 (which is also the second region AT12 of the active layer AT1 of the first transistor T1) through this via.

[0238] In an exemplary embodiment, the orthogonal projection of the seventeenth via V17 onto the substrate lies within the orthogonal projection of the control electrode T4g of the fourth transistor T4 onto the substrate. The fourth insulating layer within the seventeenth via V17 is etched away, exposing the surface of the control electrode T4g of the fourth transistor T4. The seventeenth via V17 is configured to allow the subsequently formed scan signal line Gate to be connected to the control electrode T4g of the fourth transistor T4 through this via.

[0239] In an exemplary embodiment, the orthogonal projection of the eighteenth via V18 onto the substrate lies within the orthogonal projection of the control electrode T6g of the sixth transistor T6 onto the substrate. The fourth insulating layer within the eighteenth via V18 is etched away, exposing the surface of the control electrode T6g of the sixth transistor T6. The eighteenth via V18 is configured to allow the subsequently formed second light-emitting control line EM2 to connect to the control electrode T6g of the sixth transistor T6 through this via.

[0240] (107) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on a substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer disposed on a fourth insulating layer, as shown in Figures 11a and 11b. Figure 11a is a planar structural diagram of three sub-pixels after the formation of the fourth conductive layer, and Figure 11b is a planar schematic diagram of the fourth conductive layer in Figure 11a. In an exemplary embodiment, the fourth conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0241] In an exemplary embodiment, the fourth conductive layer includes at least: a second power connection line VDDL, a first power connection line VSSL, a scan signal line Gate, a second light emission control line EM2, a first reset control line Reset1, a first initial signal line Vinit1, a second reset control line Reset2, a second initial signal line Vinit2, a first connection electrode L1, a second connection electrode L2, a third connection electrode L3, a fourth connection electrode L4, a fifth connection electrode L5, and a sixth connection electrode L6.

[0242] In an exemplary embodiment, the main body of the second power connection line VDDL, the first power connection line VSSL, the scan signal line Gate, the second light emission control line EM2, the first reset control line Reset1, the first initial signal line Vinit1, the second reset control line Reset2, and the second initial signal line Vinit2 can be a strip-shaped structure or a zigzag structure extending along the first direction X. The second power connection line VDDL, the scan signal line Gate, the first power connection line VSSL, the second light emission control line EM2, the first reset control line Reset1, the second reset control line Reset2, the first initial signal line Vinit1, and the second initial signal line Vinit2 can be arranged sequentially at intervals along the opposite direction of the second direction Y.

[0243] In an exemplary embodiment, within the same sub-pixel, in the second direction Y, the first connecting electrode L1 may be located between the second power connection line VDDL and the scan signal line Gate; the second connecting electrode L2 and the third connecting electrode L3 may be located between the body of the first power connection line VSSL and the second light emission control line EM2; the third connecting electrode L3 and the second connecting electrode L2 may be arranged at intervals along the second direction Y; the fourth connecting electrode L4 may be located between the scan signal line Gate and the body of the first power connection line VSSL; the fifth connecting electrode L5 may be located between the first power connection line VSSL and the second light emission control line EM2; and the sixth connecting electrode L6 may be located between the body of the first initial signal line Vinit1 and the body of the second initial signal line Vinit2.

[0244] In an exemplary embodiment, the second power connection line VDDL can be connected to the first region AT51 of the active layer AT5 of the fifth transistor T5 in that row of sub-pixels via the sixth via V6 in that row of sub-pixels. In an exemplary embodiment, the first power connection line VDDL can serve as the first electrode of the fifth transistor T5, configured to provide a first power supply voltage to the plurality of fifth transistors T5 in that sub-pixel.

[0245] In an exemplary embodiment, the scan signal line Gate can be connected to the control electrode T4g of the fourth transistor T4 in a row of sub-pixels through the seventeenth via V17 in that row of sub-pixels, and is configured to provide scan signals to a plurality of fourth transistors T4 in that row of sub-pixels.

[0246] In an exemplary embodiment, the first power connection line VSSL can be connected to a plurality of subsequently formed first power lines. At least a portion of the first power connection line VSSL is electrically connected to the plurality of first power lines, and at least a portion of the first power lines are electrically connected to the plurality of first power connection lines VSSL located in the multi-row pixel driving circuit. At least a portion of the first power connection line VSSL and at least a portion of the first power lines are interconnected to form a grid structure, which can reduce the voltage drop of the first power lines and improve the display uniformity of the display substrate. In an exemplary embodiment, a plurality of blocking structures ZD may be provided on the first power connection line VSSL, and the plurality of blocking structures ZD form a plurality of blocking units ZD0. The plurality of blocking units ZD0 are arranged along the first direction X. In the same blocking unit ZD, there may be a first blocking structure ZD1 and a second blocking structure ZD2, and the first blocking structure ZD1 and the second blocking structure ZD2 in the same blocking unit ZD0 are arranged at intervals along the first direction X. The first blocking structure ZD1 and the second blocking structure ZD2 may extend along the second direction Y. In the same sub-pixel, in the first direction X, the second connecting electrode L2 to the fourth connecting electrode L4 may be located between two adjacent blocking units ZD0, and the main body of the first capacitor C1 and the second capacitor C2 is located between two adjacent blocking units ZD0.

[0247] In an exemplary embodiment, the second light-emitting control line EM2 can be connected via the eighteenth via V18 in a row of sub-pixels to the control electrode T6g of the sixth transistor T6 in that row of sub-pixels, and is configured to provide light-emitting control signals to the plurality of sixth transistors T6 in that row of sub-pixels.

[0248] In an exemplary embodiment, the first reset control line Reset1 can be connected to the control electrode T1g of the first transistor T1 in the row of sub-pixels through the thirteenth via V13 in the row of sub-pixels, and is configured to provide a first reset control signal to the plurality of first transistors T1 in the row of sub-pixels.

[0249] In an exemplary embodiment, the first initial signal line Vinit1 can be connected to the first region AT11 of the active layer AT1 of the first transistor T1 in the row of sub-pixels via a first via V1 in the row of sub-pixels, and to the first region AT21 of the active layer AT2 of the second transistor T2 in the row of sub-pixels via a third via V3 in the row of sub-pixels, thus providing a first initial signal to the first transistor T1 and the second transistor T2 in the row of sub-pixels. In an exemplary embodiment, the first initial signal line Vinit1 can serve as the first electrode of the first transistor T1 and the first electrode of the second transistor T2.

[0250] In an exemplary embodiment, the second reset control line Reset2 can be connected to the control electrode T2g of the second transistor T2 in the row of sub-pixels through the fourteenth via V14 in the row of sub-pixels, and is configured to provide a second reset control signal to the plurality of second transistors T2 in the row of sub-pixels.

[0251] In an exemplary embodiment, the second initial signal line Vinit2 can be connected to the first region AT71 of the active layer AT7 of the seventh transistor T7 located in that row of sub-pixels via the eighth via V8 in that row of sub-pixels, thus providing a second initial signal to the seventh transistor T7 of that row of sub-pixels. In an exemplary embodiment, the second initial signal line Vinit2 can serve as the first electrode of the seventh transistor T7.

[0252] In an exemplary embodiment, the first connection electrode L1 is a strip-shaped structure or a zigzag structure extending along the first direction X. The first connection electrode L1 is connected to the first region AT41 of the active layer AT4 of the fourth transistor T4 through a fifth via V5. In an exemplary embodiment, the first connection electrode L1 can serve as the first electrode of the fourth transistor T4 and is configured to be connected to a subsequently formed data signal line.

[0253] In an exemplary embodiment, the main body of the second connection electrode L2 is along the first direction X. Its first end is connected to the second region AT12 of the active layer AT1 of the first transistor T1 (which is also the second region AT42 of the active layer AT4 of the fourth transistor T4) via a second via V2. Its second end is connected to the control electrode T3g of the third transistor T3 via a fifteenth via V15. The second region AT12 of the active layer AT1 of the first transistor T1 (which is also the second region AT42 of the active layer AT4 of the fourth transistor T4) and the control electrode T3g of the third transistor T3 are electrically connected via the second connection electrode L2, so that the second electrode of the first transistor T1, the second electrode of the fourth transistor T4, and the control electrode T4g of the third transistor T3 have the same potential. In an exemplary embodiment, the second connection electrode L2 can serve as the second electrode of both the first transistor T1 and the fourth transistor T4.

[0254] In an exemplary embodiment, the main body of the third connection electrode L3 extends along the first direction X. One end is connected to the second region AT32 of the active layer AT3 of the third transistor T3 (which is also the first region AT61 of the active layer AT6 of the sixth transistor T6) through the fourth via V4, and the other end is connected to the second plate C12 of the first capacitor C1 through the tenth via V10. The second region AT32 of the active layer AT3 of the third transistor T3 (which is also the first region AT61 of the active layer AT6 of the sixth transistor T6) and the second plate C12 of the first capacitor C1 are connected through the third connection electrode L3. In an exemplary embodiment, the third connection electrode L3 can serve as the second electrode of the third transistor T3 and the first electrode of the sixth transistor T6.

[0255] In an exemplary embodiment, the main body of the fourth connecting electrode L4 extends along the first direction X. One end is connected to the second plate C22 of the second capacitor C2 through the eleventh via V11, and the other end is connected to the second region AT12 of the active layer AT1 of the first transistor T1 (which is also the second region AT42 of the active layer AT4 of the fourth transistor T4) through the sixteenth via V16. The second plate C22 of the second capacitor C2 and the second region AT12 of the active layer AT1 of the first transistor T1 (which is also the second region AT42 of the active layer AT4 of the fourth transistor T4) can be electrically connected through the fourth connecting electrode L4, so that the fourth connecting electrode L4 and the second plate C22 of the second capacitor C2 have the same potential.

[0256] In an exemplary embodiment, the main body of the fifth connection electrode L5 extends along the second direction Y. One end is connected to the second region AT22 of the active layer AT2 of the second transistor T2 through the twelfth via V12, and the other end is connected to the first electrode C21 of the second capacitor C2 (which is also the first electrode C11 of the first capacitor C1) through the ninth via V9. The second region AT22 of the active layer AT2 of the second transistor T2 and the first electrode C21 of the second capacitor C2 (which is also the first electrode C11 of the first capacitor C1) are connected through the fifth connection electrode L5. In an exemplary embodiment, the fifth connection electrode L5 can serve as the second electrode of the second transistor T2.

[0257] In an exemplary embodiment, the sixth connection electrode L6 is connected to the second region AT62 of the active layer AT6 of the sixth transistor T6 (which is also the second region AT72 of the active layer AT7 of the seventh transistor T7) via the seventh via V7. In an exemplary embodiment, the sixth connection electrode L6 can serve as the second electrode of both the sixth transistor T6 and the seventh transistor T7, and the sixth connection electrode L6 is configured to be connected to the anode connection electrode of a subsequently formed light-emitting element.

[0258] (108) Forming a fifth insulating layer and a first planarization layer pattern. In an exemplary embodiment, forming a fifth insulating layer and a first planarization layer pattern may include: depositing a fifth insulating film on a substrate on which the aforementioned pattern is formed, then coating a first planarization film, and patterning the first planarization film and the fifth insulating film using a patterning process to form a fifth insulating layer covering the fourth conductive layer pattern and a first planarization layer disposed on the fifth insulating layer. A plurality of vias are provided on the fifth insulating layer and the first planarization layer, as shown in FIG12, FIG12 being a planar structural diagram of three sub-pixels after the first planarization layer is formed.

[0259] In an exemplary embodiment, the plurality of vias in each sub-pixel may include at least: a nineteenth via V19, a twentieth via V20, a twenty-first via V21, a twenty-second via V22, a twenty-third via V23, and a fourteenth via V24.

[0260] In an exemplary embodiment, the orthographic projection of the nineteenth via V19 onto the substrate lies within the range of the orthographic projection of the first initial signal line Vinit1 onto the substrate. The first planarization layer and the fifth insulating layer within the nineteenth via V19 are etched away, exposing the surface of the first initial signal line Vinit1. The nineteenth via V19 is configured to allow a subsequently formed first initial signal connection line to be connected to the first initial signal line Vinit1 through the via.

[0261] In an exemplary embodiment, the orthographic projection of the twentieth via V20 onto the substrate lies within the range of the orthographic projection of the sixth connecting electrode L6 onto the substrate. The first planarization layer and the fifth insulating layer within the twentieth via V20 are etched away, exposing the surface of the sixth connecting electrode L6. The twentieth via V20 is configured to allow the anode connecting electrode of a subsequently formed light-emitting element to be electrically connected to the sixth connecting electrode L6 through this via.

[0262] In an exemplary embodiment, the orthographic projection of the twenty-first via V21 onto the substrate lies within the range of the orthographic projection of the first connection electrode L1 onto the substrate. The first planarization layer and the fifth insulating layer within the twenty-first via V21 are etched away, exposing the surface of the first connection electrode L1. The twenty-first via V21 is configured to allow subsequently formed data signal lines to be electrically connected to the first connection electrode L1 through the via.

[0263] In an exemplary embodiment, the orthographic projection of the twenty-second via V22 onto the substrate lies within the range of the orthographic projection of the first power connection line VSSL onto the substrate. The first planarization layer and the fifth insulating layer within the twenty-second via V22 are etched away, exposing the surface of the first power connection line VSSL. The twenty-second via V22 is configured to allow a subsequently formed first power line to be connected to the first power connection line VSSL through this via.

[0264] In an exemplary embodiment, the orthographic projection of the 23rd via V23 onto the substrate lies within the range of the orthographic projection of the second power connection line VDDL onto the substrate. The first planarization layer and the fifth insulating layer within the 23rd via V23 are etched away, exposing the surface of the second power connection line VDDL. The 23rd via V23 is configured to allow a subsequently formed second power line to be connected to the second power connection line VDDL through this via.

[0265] In an exemplary embodiment, the orthographic projection of the 24th via V24 onto the substrate lies within the range of the orthographic projection of the second initial signal line Vinit2 onto the substrate. The first planarization layer and the fifth insulating layer within the 24th via V24 are etched away, exposing the surface of the second initial signal line Vinit2. The 24th via V24 is configured to allow subsequently formed second initial signal connection lines to be connected to the second initial signal line Vinit2 through this via.

[0266] (109) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the fifth conductive film using a patterning process to form a fifth conductive layer disposed on a first planarization layer, as shown in Figures 13a and 13b. Figure 13a is a planar structural diagram of three sub-pixels after the formation of the fifth conductive layer, and Figure 13b is a planar schematic diagram of the fifth conductive layer in Figure 13a. In an exemplary embodiment, the fifth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0267] In an exemplary embodiment, the fifth conductive layer includes at least: a data signal line Data, a first power line VSS, a second power line VDD, a first initial signal connection line Vinit1L, a second initial signal connection line Vinit2L, and an anode connection electrode ZL.

[0268] In an exemplary embodiment, the data signal line Data is a polygonal line extending along the second direction Y. The data signal line Data can be connected to the first connection electrode L1 through the twenty-first via V21. Since the first connection electrode L1 is connected to the first region AT41 of the active layer AT4 of the fourth transistor T4 through the via, the connection between the data signal line Data and the first electrode of the fourth transistor T4 is achieved, thus writing the data signal into the fourth transistor T4. In an exemplary embodiment, the data signal line Data can correspond to a blocking unit ZD0. In the first direction X, the first blocking structure ZD1 and the second blocking structure ZD2 in the same blocking unit ZD0 can be located on opposite sides of the corresponding main body structure of the data signal line Data.

[0269] In an exemplary embodiment, the anode connection electrode ZL in the sub-pixel is shaped like an "I", or is a strip or a broken line extending along the second direction Y. The anode connection electrode ZL can be connected to the sixth connection electrode L6 through the twentieth via V20. Since the sixth connection electrode L6 is connected to the second region AT62 of the active layer AT6 of the sixth transistor T6 (which is also the second region AT72 of the active layer AT7 of the seventh transistor T7) through the via, the connection between the anode connection electrode ZL and the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 is realized.

[0270] In an exemplary embodiment, the first initial signal connection line Vinit1L is a zigzag shape extending along the second direction Y in the main body. The first initial signal connection line Vinit1L can be connected to the first initial signal connection line Vinit1 through the nineteenth via V19. Multiple first initial signal connection lines Vinit1L and multiple first initial signal connection lines Vinit1 form a grid structure, so that the first initial signals received by the first transistor T1 and the second transistor T2 in adjacent sub-pixels are basically consistent. This is beneficial to improving the uniformity of the panel display, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0271] In an exemplary embodiment, the second initial signal connection line Vinit2L is a zigzag shape extending along the second direction Y in the main body. The second initial signal connection line Vinit2L can be connected to the second initial signal connection line Vinit2 through the twenty-fourth via V24. Multiple second initial signal connection lines Vinit2L and multiple second initial signal connection lines Vinit2 form a grid structure, so that the second initial signal received by the seventh transistor T7 in adjacent sub-pixels is basically consistent, which is beneficial to improving the uniformity of the panel display, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0272] In an exemplary embodiment, the first power line VSS is a zigzag shape extending along the second direction Y of the main body. The first power line VSS can be connected to the first power connection line VSSL through the twenty-second via V22. At least a portion of the first power connection line VSSL is electrically connected to a plurality of first power lines VSS. At least a portion of the first power lines VSS is electrically connected to a plurality of first power connection lines VSSL located in the multi-row pixel driving circuit. At least a portion of the first power connection lines VSSL and at least a portion of the first power lines VSS are interconnected to form a grid structure, which can reduce the voltage drop of the first power line VSS and improve the display uniformity of the display substrate. For example, each first power connection line VSSL is electrically connected to a plurality of first power lines VSS, each first power line VSS is electrically connected to a plurality of first power connection lines VSSL located in the multi-row pixel driving circuit, and the plurality of first power connection lines VSSL and the plurality of first power lines VSS are interconnected to form a grid structure. In an exemplary embodiment, the display substrate may include a display area and a border area surrounding the display area. The display area may have multiple sub-pixels Pxij, and the border area may have a first power signal line. In the first direction X, the first power connection line VSSL may be electrically connected to the first power signal line of the border area located on both sides of the display area; in the second direction Y, the first power line VSS may be electrically connected to the first power signal line of the border area located on both sides of the display area.

[0273] In an exemplary embodiment, the second power line VDD is a zigzag shape extending along the second direction Y in the main body. The second power line VDD can be connected to the second power connection line VDDL through the twenty-third via V23. Multiple second power connection lines VDDL and multiple second power lines VDD are interconnected to form a grid structure, so that the second power signal received by the fifth transistor T5 in adjacent sub-pixels is basically consistent. This is beneficial to improving the uniformity of the panel display, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0274] In an exemplary embodiment, multiple sub-pixels Pxij form multiple pixel units P. Each pixel unit may include three sub-pixels arranged along a first direction X. Each sub-pixel has a data signal line Data and a first power line VSS. Within the same pixel unit, the data signal line Data and the first power line VSS can be arranged alternately along the first direction X. A first initial signal connection line Vinit1L, a second initial signal connection line Vinit2L, and a second power line VDD can be located between adjacent data signal lines Data and first power lines VSS. For example, within the same pixel unit, the first initial signal connection line Vinit1L can be located between the data signal line Data and the first power line VSS of the first sub-pixel, the second initial signal connection line Vinit2L can be located between the data signal line Data and the first power line VSS of the second sub-pixel, and the second power line VDD can be located between the data signal line Data and the first power line VSS of the third sub-pixel.

[0275] Thus, the driving circuit layer is fabricated on the substrate. The driving circuit layer has pixel driving circuits for multiple sub-pixels. Figures 6 to 13b show schematic diagrams of the planar structure of the pixel driving circuits for sub-pixels in the display substrate. In an exemplary embodiment, in the direction perpendicular to the plane of the display substrate, the driving circuit layer may include a first conductive layer, a second conductive layer, a semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially disposed on the substrate.

[0276] In an exemplary embodiment, in a direction perpendicular to the plane of the display substrate, the driving circuit layer may include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, and a first planarization layer. The first insulating layer is disposed between the first conductive layer and the second conductive layer, the second insulating layer is disposed between the second conductive layer and the semiconductor layer, the third insulating layer is disposed between the semiconductor layer and the third conductive layer, the fourth insulating layer is disposed between the third conductive layer and the fourth conductive layer, and the fifth insulating layer and the first planarization layer are disposed between the fourth conductive layer and the fifth conductive layer.

[0277] In an exemplary embodiment, after the driving circuit layer is fabricated, a light-emitting structure layer is fabricated on the driving circuit layer. The fabrication process of the light-emitting structure layer may include the following operations: Forming a second planarization layer pattern, wherein at least an anode via is provided on the second planarization layer. Forming an anode pattern (i.e., an anode conductive layer), wherein the anode is connected to the anode connection electrode through the anode via. Forming an anode pixel definition layer, wherein pixel openings are provided on the pixel definition layer, and the pixel openings expose the anode. Forming an organic light-emitting layer using vapor deposition or inkjet printing, wherein a cathode is formed on the organic light-emitting layer. Forming an encapsulation layer, wherein the encapsulation layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers may be made of inorganic materials, and the second encapsulation layer may be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer. The steps for forming the anode conductive layer are as follows:

[0278] (110) Forming a second planarization layer pattern. In an exemplary embodiment, forming a second planarization layer pattern may include: coating a second planarization film on a substrate on which the aforementioned pattern is formed, and patterning the second planarization film using a patterning process to form a second planarization layer covering the pattern of the fifth conductive layer. A plurality of vias are provided on the second planarization layer, as shown in FIG14, FIG14 being a planar structural diagram of three sub-pixels after the formation of the second planarization layer.

[0279] In an exemplary embodiment, the plurality of vias may include at least: a twenty-fifth via V25.

[0280] In an exemplary embodiment, each sub-pixel's via includes at least a 25th via V25. The orthographic projection of the 25th via V25 onto the substrate lies within the orthographic projection of the anode connection electrode ZL onto the substrate. The second planarization layer within the 25th via V25 is removed, exposing the surface of the anode connection electrode ZL. The 25th via V25 is configured to allow a subsequently formed anode to be electrically connected to the anode connection electrode ZL through the via.

[0281] (111) Forming an anode conductive layer pattern. In an exemplary embodiment, forming an anode conductive layer pattern may include: depositing an anode conductive film on a substrate on which the aforementioned pattern is formed, and patterning the anode conductive film using a patterning process to form an anode conductive layer pattern disposed on a second planarization layer, as shown in Figures 15a to 15b. Figure 15a is a planar structural schematic diagram of three sub-pixels after the anode conductive layer is formed, and Figure 15b is a planar schematic diagram of the anode conductive layer in Figure 15a.

[0282] In an exemplary embodiment, the anode conductive layer pattern may include at least a plurality of anodes AN, which may include: a first anode AN1, a second anode AN2 and a third anode AN3. The area where the first anode AN1 is located may form a red light-emitting unit that emits red light, the area where the second anode AN2 is located may form a green light-emitting unit that emits green light, and the area where the third anode AN3 is located may form a blue light-emitting unit that emits blue light.

[0283] In an exemplary embodiment, the first anode AN1, the second anode AN2, and the third anode AN3 can be connected to the anode connection electrode ZL in the corresponding sub-pixel through the twenty-third via V23. Since the anode connection electrode ZL in the sub-pixel is electrically connected to the second electrode of the sixth transistor T6 (which is also the second electrode of the seventh transistor T7) through the via, the first anode AN1, the second anode AN2, and the third anode AN3 can be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 through the anode connection electrode ZL, respectively, thereby enabling the pixel driving circuit to drive the light-emitting device to emit light.

[0284] In an exemplary embodiment, the anode AN may include an anode body portion AN01 and an anode connecting portion AN02. The anode body portion AN01 may be a rectangular structure. One end of the anode connecting portion AN02 is connected to the anode body portion AN01, and the other end is electrically connected to the anode connecting electrode ZL through a twenty-third via V23. The anode connecting portion AN02 may be a strip-shaped structure or a block-shaped structure extending along a first direction X or a second direction Y. The anode connecting portion AN02 may be configured to compensate for the differences in parasitic capacitance between multiple sub-pixels caused by signal traces. By setting the anode connecting portion AN02, the parasitic capacitance of multiple sub-pixels can be kept basically consistent, thereby improving the display uniformity of the display substrate. In an exemplary embodiment, the same pixel unit may include a first sub-pixel, a second sub-pixel, and a third sub-pixel. The first anode is electrically connected to the pixel driving circuit in the first sub-pixel, the second anode is electrically connected to the pixel driving circuit in the second sub-pixel, and the third anode is electrically connected to the pixel driving circuit in the third sub-pixel. In the same pixel unit, the orthographic projection of the third anode AN3 onto the substrate can cover the orthographic projection of the channel of the second transistor T2 in that pixel unit onto the substrate; the orthographic projection of the first anode AN1 onto the substrate can cover the orthographic projection of the channel of the seventh transistor T7 in the first sub-pixel onto the substrate; the orthographic projection of the second anode AN2 onto the substrate can cover the orthographic projection of the channel of the seventh transistor T7 in the second and third sub-pixels onto the substrate. In the third anode AN3, the anode body portion AN01 may have a protrusion AN03 on the side near the first anode AN1 and the second anode AN2. The protrusion AN03 can block the channel of the second transistor T2 located in the first sub-pixel, and the anode connection portion AN02 can block the channel of the second transistor T2 located in the second and third sub-pixels.

[0285] (112) Forming a pixel definition layer pattern. In an exemplary embodiment, forming a pixel definition layer pattern may include: depositing a pixel definition layer film on a substrate on which the aforementioned pattern is formed, and patterning the pixel definition layer using a patterning process to form a pixel definition layer pattern disposed on the anode conductive layer, as shown in Figures 16a and 16b. Figure 16a is a schematic diagram of the planar structure of three sub-pixels after the pixel definition layer is formed, and Figure 16b is a schematic diagram of the planar structure of the pixel definition layer in Figure 16a.

[0286] In an exemplary embodiment, the pixel definition layer pattern may include multiple pixel openings K0, which expose the anode AN. In an exemplary embodiment, the orthographic projection of the pixel opening K0 onto the substrate lies within the range of the orthographic projection of the anode AN onto the substrate. In an exemplary embodiment, the pixel opening K0 may include a pixel opening K01 of a first sub-pixel, a pixel opening K02 of a second sub-pixel, and a pixel opening K03 of a third sub-pixel. The orthographic projection of the pixel opening K01 of the first sub-pixel onto the substrate overlaps with the orthographic projection of the first anode AN1 onto the substrate; the orthographic projection of the pixel opening K02 of the second sub-pixel onto the substrate overlaps with the orthographic projection of the second anode AN2 onto the substrate; and the orthographic projection of the pixel opening K03 of the third sub-pixel onto the substrate overlaps with the orthographic projection of the third anode AN3 onto the substrate.

[0287] In an exemplary embodiment, the first conductive layer, second conductive layer, third conductive layer, fourth conductive layer, and fifth conductive layer can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo, Ti / Al / Ti, etc. The first insulating layer, second insulating layer, third insulating layer, fourth insulating layer, and fifth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). They can be single-layer, multi-layer, or composite layers.

[0288] In an exemplary embodiment, taking three sub-pixels (a row of pixel driving circuits for one sub-pixel and a column of pixel driving circuits for three sub-pixels) in the display area (AA) as an example, the fabrication process of another display substrate may include steps (101) to (112) as described above, wherein the difference from steps (101) to (112) is as follows:

[0289] The fourth conductive layer formed in step (107) above can be shown in Figures 17a and 17b. Figure 17a is a planar structural diagram of the three sub-pixels after the formation of the fourth conductive layer, and Figure 17b is a planar schematic diagram of the fourth conductive layer in Figure 17a. The difference between the fourth conductive layer pattern shown in Figure 17b and the fourth conductive layer pattern shown in Figure 11b is that in the fourth conductive layer pattern shown in Figure 17b, among the multiple shielding structures ZD set on the first power connection line VSSL, each shielding structure ZD is roughly a block structure, and each shielding structure ZD can be a shielding unit ZD0 (i.e., a shielding unit ZD0 includes a block-shaped shielding structure ZD). The shielding structure ZD corresponds to one of the data signal lines Data, and the shielding structure ZD and the corresponding at least part of the data signal line Data at least partially overlap the orthogonal projection on the substrate. In the same sub-pixel, in the first direction X, the second connecting electrode L2 to the fourth connecting electrode L4 can be located between two adjacent shielding structures ZD, and the main body of the first capacitor C1 and the second capacitor C2 is located between two adjacent shielding structures ZD. In an exemplary embodiment, the structure after forming the fifth insulating layer and the first planarization layer based on FIG17a can be as shown in FIG18, the structure after forming the fifth conductive layer based on FIG18 can be as shown in FIG19, the structure after forming the second planarization layer based on FIG19 can be as shown in FIG20, the structure after forming the anode conductive layer based on FIG20 can be as shown in FIG21, and the structure after forming the pixel definition layer based on FIG21 can be as shown in FIG22.

[0290] In exemplary embodiments, the sub-pixel rows and sub-pixel columns described in this disclosure can be understood as the rows and columns of pixel driving circuits in a sub-pixel. The anode in a sub-pixel is connected to the pixel driving circuit in the corresponding sub-pixel, but the position of the anode of a sub-pixel does not necessarily correspond completely to the row and column of the pixel driving circuit it is connected to. For example, the orthographic projection of the anode AN3 of the third sub-pixel on the substrate may overlap with the orthographic projection of the pixel driving circuit of the first sub-pixel and the pixel driving circuit of the second sub-pixel on the substrate.

[0291] The structures and fabrication processes described above in this disclosure are merely illustrative examples. In the exemplary embodiments, the corresponding structures and patterning processes can be modified and added or reduced as needed. The display substrates in this disclosure can be applied to other display devices with pixel driving circuits, such as quantum dot displays, etc. This disclosure does not limit them.

[0292] This disclosure also provides a display device, which may include the display substrate of any of the foregoing embodiments. The display device may be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0293] The display substrate and display device provided in this disclosure include a plurality of first regulated signal lines, a plurality of second regulated signal lines, a plurality of data signal lines, and a plurality of shielding structures. At least a portion of the first regulated signal lines are provided with a plurality of shielding structures. In the row direction X, the plurality of shielding structures are arranged at intervals. The data signal lines are located between two adjacent second regulated signal lines. A data signal line and at least one second regulated signal line located on both sides of the data signal line correspond to at least one shielding structure. The orthographic projection of at least a portion of the shielding structure on the substrate is located between the orthographic projection of the corresponding data signal line on the substrate and the orthographic projection of the corresponding second regulated signal line on the substrate. In a direction perpendicular to the plane of the substrate, the data signal line and the second regulated signal line are located on the side of the first regulated signal line away from the substrate. The first regulated signal line is located on the side of at least a portion of the components in the pixel driving circuit away from the substrate. The shielding structures on the first regulated signal lines can shield the signals on the data signal lines, reduce the interference of the data signal lines to the at least a portion of the components, and reduce signal crosstalk between the data signal lines and the at least a portion of the components, thereby improving the display effect.

[0294] The accompanying drawings of the embodiments disclosed herein only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in a general design.

[0295] Where there is no conflict, the features of the embodiments disclosed herein can be combined with each other to obtain new embodiments.

[0296] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of these embodiments and is not intended to limit the scope of these embodiments. Any person skilled in the art to which these embodiments pertain may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the patent protection scope of these embodiments shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising: The system comprises a substrate and a plurality of sub-pixels, a plurality of first voltage-regulating signal lines, a plurality of second voltage-regulating signal lines, and a plurality of data signal lines disposed on one side of the substrate. At least some of the sub-pixels include pixel driving circuits, which are arranged in multiple columns. The data signal lines are electrically connected to at least some of the pixel driving circuits in at least one column of pixel driving circuits. The plurality of first voltage-regulating signal lines extend along the row direction and are spaced apart along the column direction, with the row direction intersecting the column direction. The plurality of second voltage-regulating signal lines and the plurality of data signal lines extend along the column direction and are spaced apart along the row direction. At least a portion of the first voltage-regulated signal line is provided with multiple shielding structures. In the row direction, the multiple shielding structures are arranged at intervals. The data signal line is located between two adjacent second voltage-regulated signal lines. The data signal line and at least one second voltage-regulated signal line located on both sides of the data signal line correspond to at least one shielding structure. The orthographic projection of at least a portion of the shielding structure on the substrate is located between the orthographic projection of the corresponding data signal line on the substrate and the orthographic projection of the corresponding second voltage-regulated signal line on the substrate. In a direction perpendicular to the plane of the substrate, the data signal line and the second voltage-regulated signal line are located on the side of the first voltage-regulated signal line away from the substrate, and the first voltage-regulated signal line is located on the side of at least some components in the pixel driving circuit away from the substrate.

2. The display substrate according to claim 1, wherein, The first regulated signal line is located in the first source-drain metal layer, and the second regulated signal line and the data signal line are located in the second source-drain metal layer; or, the first regulated signal line is located in the second source-drain metal layer, and the second regulated signal line and the data signal line are located in the third source-drain metal layer. In a direction perpendicular to the plane of the substrate, the second source / drain metal layer is located on the side of the first source / drain metal layer away from the substrate, and the third source / drain metal layer is located on the side of the second source / drain metal layer away from the substrate.

3. The display substrate according to claim 1, wherein, The pixel driving circuit includes at least one capacitor and multiple transistors, the multiple transistors including at least one driving transistor, at least one plate of the at least one capacitor is connected to the control electrode of the driving transistor, and the first regulated signal line is located on the side of the capacitor away from the substrate in a direction perpendicular to the plane of the substrate.

4. The display substrate according to claim 3, wherein, The at least one capacitor located in the same pixel driving circuit corresponds to at least one occlusion structure. In the row direction, the orthographic projection of at least a portion of the occlusion structure onto the substrate is located between the orthographic projection of the corresponding data signal line onto the substrate and the orthographic projection of the corresponding at least one capacitor onto the substrate.

5. The display substrate according to claim 4, wherein, The at least one capacitor in the pixel driving circuit includes a first capacitor and a second capacitor. The control electrode of the driving transistor is connected to the second plate of the second capacitor, and the second electrode of the driving transistor is connected to the second plate of the first capacitor. The first node corresponds to at least one shielding structure. In the row direction, at least a portion of the shielding structure has its orthographic projection on the substrate located between the orthographic projection of the corresponding data signal line on the substrate and the orthographic projection of the corresponding first node on the substrate. The first node is the node where the control electrode of the driving transistor is connected to the second plate of the second capacitor.

6. The display substrate according to claim 5, wherein, The plurality of transistors also includes a second transistor as a reset transistor, the second terminal of the second transistor being connected to the first plate of the first capacitor and the first plate of the second capacitor; The fourth node corresponds to at least one shielding structure. In the row direction, at least a portion of the shielding structure has its orthographic projection on the substrate located between the orthographic projection of the corresponding data signal line on the substrate and the orthographic projection of the corresponding fourth node on the substrate. The fourth node is the node where the second electrode of the second transistor is connected to the first plate of the first capacitor and the first plate of the second capacitor.

7. The display substrate according to claim 6, wherein, The plurality of blocking structures form a plurality of blocking units, each blocking unit including a first blocking structure and a second blocking structure, and each blocking unit corresponds to one of the data signal lines; In the row direction, the blocking unit corresponds to the first node and the fourth node on both sides of the corresponding data signal line, the first blocking structure corresponds to the first node, and the second blocking structure corresponds to the fourth node; the plurality of blocking units are arranged at intervals, and in the same blocking unit, the second blocking structure and the first blocking structure are arranged at intervals in sequence, the first blocking structure and the second blocking structure are located on both sides of the corresponding data signal line, the first blocking structure and the corresponding first node are located on one side of the corresponding data signal line, and the second blocking structure and the corresponding fourth node are located on the other side of the corresponding data signal line.

8. The display substrate according to claim 7, wherein, In the row direction, at least a portion of the structure in the first blocking structure has its orthographic projection on the substrate located between the orthographic projection of the corresponding data signal line on the substrate and the orthographic projection of the corresponding first node on the substrate; At least a portion of the structure in the second shielding structure has its orthographic projection on the substrate located between the orthographic projection of the corresponding data signal line on the substrate and the orthographic projection of the corresponding fourth node on the substrate.

9. The display substrate according to claim 6, wherein, The blocking structure corresponds to one of the data signal lines. In the row direction, the blocking structure corresponds to the first node and the fourth node located on both sides of the corresponding data signal line. The orthographic projection of at least a portion of the blocking structure on the substrate is located between the orthographic projection of the corresponding first node on the substrate and the orthographic projection of the corresponding fourth node on the substrate, and at least partially overlaps with the orthographic projection of the corresponding at least a portion of the data signal line on the substrate.

10. The display substrate according to any one of claims 7 to 9, wherein, In the row direction, the first node is located in the pixel driving circuit on one side of the corresponding data signal line, and the fourth node is located in the pixel driving circuit on the other side of the corresponding data signal line. In the same pixel driving circuit, in the row direction, the first node and the fourth node are located on both sides of the first center line, which is the center line extending from the first capacitor and the second capacitor along the column direction.

11. The display substrate according to any one of claims 3 to 9, wherein, The orthogonal projection of the at least one capacitor onto the substrate has no overlapping area with the orthogonal projection of the data signal line onto the substrate, but at least partially overlaps with the orthogonal projections of at least a portion of the second voltage-regulating signal line and at least a portion of the first voltage-regulating signal line onto the substrate.

12. The display substrate according to any one of claims 3 to 9, wherein, In a direction perpendicular to the plane of the substrate, the capacitor includes a first electrode plate located on one side of the substrate and a second electrode plate located on the side of the first electrode plate away from the substrate; the transistor includes: an active layer located on the side of the second electrode plate away from the substrate, a control electrode located on the side of the active layer away from the substrate, and a first electrode and a second electrode located on the side of the control electrode away from the substrate; The first voltage regulator signal line is disposed on the same layer as the first electrode and the second electrode. In a direction perpendicular to the plane of the substrate, the second voltage regulator signal line is located on the side of the first electrode and the second electrode away from the substrate.

13. The display substrate according to claim 12, wherein, The plurality of second voltage-stabilized signal lines include first-type second voltage-stabilized signal lines and second-type second voltage-stabilized signal lines. The at least one capacitor located in the same pixel driving circuit corresponds to one of the first-type second voltage-stabilized signal lines and one of the second-type second voltage-stabilized signal lines. The data signal line corresponds to one of the first type second voltage-regulated signal lines and one of the second type second voltage-regulated signal lines. In the row direction, the data signal line is located between the corresponding first type second voltage-regulated signal line and the corresponding second type second voltage-regulated signal line. The at least one capacitor in the same pixel driving circuit, as well as the corresponding first type second voltage-regulated signal line and the corresponding second type second voltage-regulated signal line, are located between two adjacent data signal lines.

14. The display substrate according to claim 13, wherein, The first voltage regulator signal line includes a first power connection line, and the second type of second voltage regulator signal line includes a first power line. At least a portion of the first power line and at least a portion of the first power connection line are connected through vias to form a mesh structure.

15. The display substrate according to claim 13, wherein, The first type of second voltage regulation signal line includes a first initialization power connection line, a second initialization power connection line, and a second power line. The multiple sub-pixels form multiple pixel units. Each pixel unit includes three sub-pixels. The pixel driving circuits of the three sub-pixels in the same pixel unit are arranged sequentially along the row direction. The first initialization power connection line, the second initialization power connection line, and the second power line, which are corresponding to the same pixel unit, are respectively located in the pixel driving circuits of the three sub-pixels in the pixel unit.

16. The display substrate according to claim 15, wherein, The plurality of transistors includes a first transistor and a second transistor as initialization transistors, the first terminal of the first transistor and the first terminal of the second transistor are connected to the first initialization power line, and the orthogonal projections of the first transistor and the second transistor on the substrate do not overlap with the orthogonal projections of the at least one capacitor on the substrate.

17. The display substrate according to claim 16, further comprising a plurality of first reset signal lines and a plurality of second reset signal lines, wherein the plurality of first reset signal lines and the plurality of second reset signal lines extend along the row direction and are spaced apart along the column direction; The pixel driving circuits of at least some sub-pixels are formed in multiple rows. The first reset signal line is electrically connected to the control electrode of at least some of the first transistors in at least one row of pixel driving circuits. The second reset signal line is electrically connected to the control electrode of at least some of the second transistors in at least one row of pixel driving circuits. The first reset signal line and the second reset signal line are disposed on the same layer as the first electrode and the second electrode, and their orthogonal projections on the substrate do not overlap with the orthogonal projections of the at least one capacitor on the substrate.

18. The display substrate according to claim 16, wherein, The plurality of transistors also includes a fourth transistor as a data writing transistor and a sixth transistor as a light-emitting control transistor. The first terminal of the fourth transistor is connected to the data signal line, and the first terminal of the sixth transistor is connected to the second terminal of the driving transistor. The orthographic projections of the fourth transistor and the sixth transistor on the substrate do not overlap with the orthographic projections of the at least one capacitor on the substrate. In the same pixel driving circuit, in the row direction, the first transistor and the second transistor are located on opposite sides of the driving transistor; in the column direction, the first transistor and the second transistor are located on one side of the driving transistor, the fourth transistor is located on the other side of the driving transistor, and the sixth transistor is located between the driving transistor and the first transistor and the second transistor.

19. The display substrate according to claim 18, further comprising a plurality of scan signal lines and a plurality of second light emission control signal lines, wherein the plurality of scan signal lines and the plurality of second light emission control signal lines are disposed in the same layer as the first electrode and the second electrode, and extend along the row direction and are spaced apart along the column direction; The pixel driving circuits of at least some sub-pixels form multiple rows, the scanning signal line is electrically connected to the control electrode of at least some fourth transistors in at least one row of pixel driving circuits, and the second light emission control signal line is electrically connected to the control electrode of at least some sixth transistors in at least one row of pixel driving circuits. In the same row of pixel driving circuits, in the column direction, the first voltage regulation signal line with the blocking structure is located between the scan signal line and the second light emission control signal line.

20. The display substrate according to claim 19, wherein, The orthographic projection of the second light-emitting control signal line on the substrate and the orthographic projection of the capacitor on the substrate do not overlap.

21. The display substrate according to claim 19, wherein, In the same row of pixel driving circuits, in the column direction, the occlusion structure is located between the scan signal line and the second light emission control signal line.

22. The display substrate according to claim 21, wherein, The shape of the shielding structure is a block structure, or the shape of the shielding structure is a strip or a broken line extending along the column direction.

23. The display substrate according to claim 18, wherein, The pixel driving circuit includes a seventh transistor as a reset transistor and a fifth transistor as a light-emitting control transistor; the first terminal of the seventh transistor is connected to the second initialization power supply connection line, the first terminal of the fifth transistor is connected to the second power supply line connection line, and the second terminal of the fifth transistor is connected to the first terminal of the driving transistor. In the column direction, the fifth transistor is located on the side of the fourth transistor away from the driving transistor, and the seventh transistor is located on the side of the first transistor and the second transistor away from the driving transistor.

24. The display substrate according to claim 23, wherein, The pixel driving circuit corresponds to one of the first type second voltage regulation signal lines and one of the second type second voltage regulation signal lines; In the same pixel driving circuit: the orthographic projection of the channel of the first transistor and the channel of the fourth transistor on the substrate at least partially overlaps with the orthographic projection of the corresponding first type second voltage regulation signal line on the substrate; The orthographic projections of the channels of the driving transistor, the second transistor, the fifth transistor, and the sixth transistor onto the substrate at least partially overlap with the orthographic projections of the corresponding second type second voltage regulation signal lines onto the substrate.

25. The display substrate according to claim 24, wherein, At least some sub-pixels also include multiple anodes, which are located on the side of the multiple second voltage regulation signal lines away from the substrate in a direction perpendicular to the plane of the substrate; the orthogonal projection of the channel of the seventh transistor on the substrate is located within the range of the orthogonal projection of at least one anode on the substrate.

26. The display substrate according to claim 25, wherein, The pixel unit includes at least a first sub-pixel, a second sub-pixel, and a third sub-pixel; in the same sub-pixel, the second electrode of the sixth transistor and the second electrode of the seventh transistor are electrically connected to the anode of the sub-pixel; In the same pixel unit, the orthographic projection of the anode of the first sub-pixel onto the substrate covers the orthographic projection of the channel of the seventh transistor in the first sub-pixel onto the substrate; the orthographic projection of the anode of the second sub-pixel onto the substrate covers the orthographic projection of the channel of the seventh transistor in the second and third sub-pixels onto the substrate; the orthographic projection of the anode of the third sub-pixel and the corresponding second type second voltage regulation signal line onto the substrate covers the orthographic projection of the second transistor in the pixel unit onto the substrate.

27. A display substrate, comprising: The substrate and a plurality of sub-pixels and a plurality of control signal lines disposed on one side of the substrate, wherein at least one sub-pixel includes a pixel driving circuit, the at least one pixel driving circuit includes a plurality of transistors and at least one capacitor, the plurality of transistors including at least a driving transistor; the pixel driving circuits of the plurality of sub-pixels form multiple rows, the plurality of control signal lines extend along the row direction and are spaced apart along the column direction, the row direction intersecting the column direction; The control signal line is electrically connected to the control electrode of at least one transistor in at least one row of pixel driving circuits, and in a direction perpendicular to the plane of the substrate, the control signal line is located on the side of the capacitor away from the substrate; In the same pixel driving circuit, the control electrode of the driving transistor is electrically connected to at least one plate of the at least one capacitor; There is no overlap between the orthographic projection of at least one control signal line on the substrate and the orthographic projection of at least one capacitor on the substrate.

28. The display substrate according to claim 27, wherein, The plurality of transistors include at least a first transistor as an initialization transistor, a second transistor as an initialization transistor, and a seventh transistor as an initial transistor; the control signal lines include at least a first reset signal line, a second reset signal line, and a third reset signal line. The first reset signal line is electrically connected to the control electrode of at least a portion of the first transistor in at least one row of pixel driving circuits; the second reset signal line is electrically connected to the control electrode of at least a portion of the second transistor in at least one row of pixel driving circuits; and the third reset signal line is electrically connected to the control electrode of at least a portion of the seventh transistor in at least one row of pixel driving circuits. The orthographic projections of the first reset signal line, the second reset signal line, and the third reset signal line on the substrate do not overlap with the orthographic projections of the at least one capacitor on the substrate.

29. The display substrate according to claim 28, further comprising a plurality of first initialization power lines and a plurality of second initialization power lines, wherein the plurality of first initialization power lines and the plurality of second initialization power lines extend along the row direction and are spaced apart along the column direction; The first initialization power line is connected to the first terminal of the first transistor and the first terminal of the second transistor in at least one row of pixel driving circuits; the second initialization power line is connected to the first terminal of the seventh transistor in at least one row of pixel driving circuits. In the same pixel driving circuit, in the column direction, the first reset signal line, the second reset signal line, the first initialization power line, the third reset signal line, and the second initial power line are arranged at intervals and located on the same side of the driving transistor and the at least one capacitor.

30. The display substrate according to claim 29, wherein, The variety of transistors also includes a sixth transistor as a light-emitting control transistor. In the same pixel driving circuit, in the column direction, the driving transistor is located on one side of the sixth transistor, the first transistor and the second transistor are located on the other side of the sixth transistor, and the seventh transistor is located on the side of the first transistor and the second transistor away from the sixth transistor.

31. The display substrate according to claim 30, wherein, The control signal line also includes a plurality of second light-emitting control signal lines, which extend along the row direction and are spaced apart along the column direction; The second light emission control signal line is electrically connected to the control electrode of at least a portion of the sixth transistor in at least one row of pixel driving circuits; In the same row of pixel driving circuits, in the column direction, the second light emission control signal line is located between the at least one capacitor and the first reset signal line, and there is no overlap between the orthogonal projection of the second light emission control signal line and the at least one capacitor on the substrate.

32. The display substrate according to claim 31, wherein, In a direction perpendicular to the plane of the substrate, the third reset signal line is located on the side of the at least one capacitor away from the substrate, and the first reset signal line, the second reset signal line, the second light emission control signal line, the first initialization power line, and the second initial power line are located on the side of the third reset signal line away from the substrate.

33. The display substrate according to any one of claims 28 to 32, wherein, In the row direction, the first transistor is located on one side of the driving transistor, and the second transistor is located on the other side of the driving transistor; In the same pixel driving circuit, the orthogonal projection of the driving transistor on the substrate at least partially overlaps with the orthogonal projection of the at least one capacitor on the substrate.

34. A display device, wherein, The display device includes a display substrate according to any one of claims 1-26 or 27-33.

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