High-speed pipeline analog-to-digital converter and electronic device

Abstract

A high-speed pipeline analog-to-digital converter and an electronic device. The high-speed pipeline analog-to-digital converter comprises multiple stages of pipeline processing units which are cascaded, wherein a first stage of pipeline processing unit (10) is used for receiving a differential analog input signal and outputting a differential signal and a corresponding quantized signal; the remaining stages of pipeline processing units (20) are configured to execute a differential sampling operation and a residue transfer operation; the execution of the differential sampling operation comprises: the N-th stage of pipeline processing unit (20) performs differential sampling to obtain a sampled signal, and receives a quantization result outputted through a quantization operation of the (N-1)-th stage of pipeline processing unit (20); and execution of the residue transfer operation comprises: the N-th stage of pipeline processing unit (20) determines a residue signal, quantizes the residue signal of the N-th stage of pipeline processing unit (20) to obtain a quantization result, and transfers the quantization result and the residue signal to the (N+1)-th stage of pipeline processing unit (20). The high-speed pipeline analog-to-digital converter has the characteristics of high energy efficiency, low complexity, and high-speed conversion.

Description

High-speed pipelined analog-to-digital converters and electronic equipment Technical Field

[0001] This disclosure relates to the field of analog-to-digital conversion technology, and in particular to a high-speed pipelined analog-to-digital converter and electronic device. Background Technology

[0002] An analog-to-digital converter (ADC) is an electronic system that converts analog signals into digital signals, typically implemented using integrated circuits (chips). The main specifications of an ADC are fourfold: speed (sampling rate), accuracy (effective bits or signal-to-noise ratio), power consumption, and cost (chip area).

[0003] Commonly used high-speed ADC structures mainly include voltage-domain ADCs and time-domain ADCs. Time-domain ADCs can achieve sampling rates higher than 3 GS / s; however, their quantization accuracy depends on the matching degree of gate delays, making their performance unstable when environmental factors such as process technology, voltage, and temperature (PVT) change. In contrast, voltage-domain ADCs (flash ADCs, pipelined ADCs, successive approximation ADCs (SAR ADCs)) have better PVT robustness. Among them, flash ADCs can achieve the highest sampling rate (above 5 GS / s) in low-precision applications with 4-5 significant bits; however, their power consumption and area cost increase exponentially with increasing accuracy, making them unsuitable for higher-precision applications. SAR ADCs have high energy efficiency, but their speed is slow (below 1.5 GS / s), requiring large-scale time-interleaving structures to achieve high sampling rates, increasing the cost and complexity of the ADC input front-end.

[0004] Pipeline ADCs offer faster speeds than SAR ADCs, but the traditional architecture of a pipelined ADC involves three sequential operation steps—sampling, quantization, and amplification, as shown in Figures 1a and 1b. Therefore, its sampling rate typically does not exceed 3 GS / s. The specific workflow is as follows: Taking the Nth stage as an example, in phase Φ1, the residual signal amplified by the (N-1)th stage is sampled; in phase Φ2, the sampled signal is quantized to obtain the quantization result D[N] of this stage; in phase Φ3, the difference between the sampled signal and the quantization result is calculated to obtain the residual signal, which is then amplified by a residual amplifier (RA) and sent to the (N+1)th stage. The (N+1)th stage samples the residual signal amplified by the Nth stage in phase Φ3, and then continues with the quantization and amplification steps of this stage, thus forming a pipeline structure.

[0005] In related technologies, there are two main methods to improve the speed of pipelined ADCs:

[0006] 1. The "forward quantization" method performs parallel sampling and quantization operations;

[0007] 2. The "Amplification with Residual Difference" method involves parallel quantization and amplification operations.

[0008] Figures 2a and 2b illustrate the operating mode of a pipelined ADC using the "forward quantization" method. This method performs sampling and quantization operations simultaneously at each stage, reducing the required operation steps from three to two (sampling & quantization, amplification), thus improving the speed of the pipelined ADC. The main difference between this architecture and the traditional pipelined ADC architecture lies in the input signal of each quantizer stage.

[0009] As shown in Figures 2a and 2b, in phase Φ1, the Nth stage samples the residual signal amplified by the (N-1)th stage. In this traditional architecture, the input signal to the Nth stage quantizer is the signal sampled by the Nth stage (the black dashed line in Figure 2a). In this architecture, the input signal to the Nth stage quantizer is the residual signal of the (N-1)th stage, thus quantization can be performed without waiting for the current stage's sampling to finish. Therefore, in phase Φ1, the Nth stage can perform sampling and quantization operations simultaneously.

[0010] As shown in Figures 2a and 2b, in phase Φ2, the Nth stage subtracts the sampled signal from the quantization result to obtain the residual signal, and then amplifies the residual signal through the residual amplifier before sending it to the N+1th stage.

[0011] In this architecture, since the input signal of each quantizer is the residual signal before amplification by the previous stage, adjacent quantizers need to form a master quantizer and a sub-quantizer structure to ensure that the residual signal is properly quantized. That is, the quantizer of the (N+1)th stage is a sub-quantizer of the Nth stage quantizer. Therefore, the reference voltage of the (N+1)th stage quantizer needs to be generated by a reference voltage multiplexer (V in Figure 2a). th The multiplexer (MUX) is controlled by the quantization result of the Nth stage.

[0012] This pipeline architecture improves overall speed by parallelizing the sampling and quantization processes through quantization of the residual signal from the previous stage. However, this architecture requires generating multiple reference voltages to form a reference voltage multiplexer, increasing the complexity and power consumption of the reference voltage generation module and reducing energy efficiency.

[0013] Figures 3a and 3b illustrate the working mode of the pipelined ADC using the "amplification followed by residual error" method, which performs the quantization and amplification operations of each stage simultaneously. This also reduces the required operation steps from three to two (sampling, quantization & amplification), thus improving the speed of the pipelined ADC.

[0014] The main difference between this architecture and the traditional pipelined ADC architecture lies in the location where the difference between the quantization results is calculated at each stage.

[0015] As shown in Figures 3a and 3b, in phase Φ1, the Nth stage samples the output signal of the (N-1)th stage residual amplifier.

[0016] As shown in Figures 3a and 3b, in phase Φ2, when the Nth stage quantizer quantizes the sampled signal, the residual amplifier in the traditional architecture needs to wait for the sampled signal and the quantization result to be subtracted before amplification (phase Φ3 in Figures 1a and 1b). In the architecture shown in Figures 3a and 3b, the residual amplifier directly performs both quantization and amplification operations on the sampled signal simultaneously in phase Φ2. At the same time, the (N+1)th stage samples the amplified signal and receives the quantization result from the Nth stage, subtracting the result from the Nth stage's output to generate the residual signal.

[0017] The pipeline architecture shown in Figures 3a and 3b parallelizes the quantization and amplification processes by generating the residual difference signal through a method of amplification followed by subtraction, thereby improving the overall speed.

[0018] However, compared to the traditional architecture shown in Figures 1a and 1b, and the architecture using the "forward quantization" method shown in Figures 2a and 2b, the input signal of the residual amplifier in the architecture shown in Figures 3a and 3b is a large-swing signal that is not subtracted from the quantization result, as shown in Figure 4. The traditional architecture and the architecture using the "forward quantization" method perform subtraction before amplification, resulting in a smaller input signal swing for the residual amplifier, better linearity, and no output saturation. The architecture shown in Figures 3a and 3b amplifies first and then performs subtraction, resulting in a larger input signal swing for the residual amplifier, poorer linearity, and potential output saturation, which will severely affect the ADC performance. Therefore, the residual amplifier in this architecture requires higher power consumption or complex linearity enhancement techniques to ensure its linearity, and it is necessary to avoid output saturation, increasing additional design complexity and power consumption.

[0019] It is evident that the pipelined ADC of the relevant technology has disadvantages such as slow speed, low energy efficiency, high requirements for the linearity of the residual amplifier, saturation problem at the amplifier output, and high complexity of the reference voltage generation module. Summary of the Invention

[0020] According to one aspect of this disclosure, a high-speed pipelined analog-to-digital converter is provided, including cascaded multi-stage pipelined processing units. A first-stage pipelined processing unit is used to receive differential analog input signals and output differential signals and corresponding quantized signals. Except for the first-stage pipelined processing unit, the remaining pipelined processing units are configured to perform differential sampling operations and residual propagation operations.

[0021] The differential sampling operation includes: the Nth stage pipeline processing unit differentially samples the residual signal or the differential signal received from the previous stage to obtain a sampled signal, and receives the quantization result output by the N-1th stage pipeline processing unit, where N is a positive integer greater than 1.

[0022] The residual propagation operation includes: the Nth stage pipeline processing unit determining the residual signal between the sampled signal and the quantization result of the previous stage pipeline processing unit, performing a quantization operation on the residual signal of the Nth stage pipeline processing unit to obtain a quantization result, and propagating the quantization result and residual signal of the Nth stage pipeline processing unit to the (N+1)th stage pipeline processing unit, wherein the quantization result output by each stage pipeline processing unit is used as the analog-to-digital conversion result of the analog input signal.

[0023] In one possible implementation, each stage of the pipeline processing unit is configured to perform differential sampling and residual transfer operations based on a target clock signal, wherein the target clock signal is set to a form in which a first phase and a second phase alternate periodically, wherein, in the first phase, the Nth stage pipeline processing unit differentially samples the residual signal or the differential signal received from the previous stage to obtain a sampled signal, and receives the quantization result output by the (N-1)th stage pipeline processing unit; in the second phase, the Nth stage pipeline processing unit determines the residual signal between the sampled signal and the quantization result of the previous stage pipeline processing unit, performs a quantization operation on the residual signal of the Nth stage pipeline processing unit to obtain a quantization result, and transfers the quantization result and residual signal of the Nth stage pipeline processing unit to the (N+1)th stage pipeline processing unit.

[0024] In one possible implementation, the analog-to-digital converter includes a first input buffer and a second input buffer, the input terminals of the first input buffer and the second input buffer being used to input the analog input signal, and the output terminals of the first input buffer and the second input buffer being connected to the first-stage pipeline processing unit.

[0025] In one possible implementation, each pipeline processing unit further includes a unity-gain voltage buffer, which is used to transmit the residual signal or the differential signal to the sampling circuit of the next pipeline processing unit. The unity-gain voltage buffer includes a first MOS transistor and a second MOS transistor. The gate of the first MOS transistor is used to receive the residual signal or the differential signal, the drain of the first MOS transistor is used to receive a power supply voltage, the source of the first MOS transistor is connected to the drain of the second MOS transistor, the gate of the second MOS transistor is used to receive a bias voltage, and the source of the second MOS transistor is grounded. The first MOS transistor is configured to be biased in the saturation region. The source of the first MOS transistor and the drain of the second MOS transistor serve as the output terminals of the unity-gain voltage buffer, used to output the buffered residual signal or differential signal.

[0026] In one possible implementation, the unity-gain voltage buffer satisfies the following first condition: V DD ≤V GS +V th , where V DD The voltage V represents the power supply voltage. GS V represents the gate-source voltage of the first MOS transistor. th This represents the turn-on threshold voltage of the first MOS transistor. Each pipeline processing unit is configured to periodically perform pipelined operations under a target clock signal, which is set to a form where a first phase and a second phase alternate periodically. When the unity-gain voltage buffer in each pipeline processing unit satisfies the first condition, each pipeline processing unit is configured as follows: in each first phase, the 2nth pipeline processing unit performs a differential sampling operation, and the (2n-1)th pipeline processing unit performs a residual propagation operation, where n is a positive integer; in each second phase, the 2nth pipeline processing unit performs a residual propagation operation, and the (2n-1)th pipeline processing unit performs a differential sampling operation.

[0027] In one possible implementation, the first-stage pipelined processing unit includes a first access switch, a second access switch, a first ground switch, a second ground switch, a first common-mode switch, a second common-mode switch, a first capacitor, a second capacitor, a first unity-gain voltage buffer, a second unity-gain voltage buffer, and a quantizer. The first terminal of the first access switch and the first terminal of the second access switch are respectively used to receive the positive and negative signals of the differential analog input signal. The second terminal of the first access switch is connected to the first terminal of the first capacitor, the input terminal of the first unity-gain voltage buffer, and the first input terminal of the quantizer in the first-stage pipelined processing unit. The second terminal of the second access switch is connected to the first terminal of the second capacitor, the input terminal of the second unity-gain voltage buffer, and the second input terminal of the quantizer in the first-stage pipelined processing unit. The second terminal of the first capacitor is grounded through the first ground switch and connected to the common-mode reference voltage through the first common-mode switch. The second terminal of the second capacitor is grounded through the second ground switch and connected to the common-mode reference voltage through the second common-mode switch. In one possible implementation, the first access switch, the second access switch, the first ground switch, and the second ground switch are turned on in the first phase of the clock cycle, the first common-mode switch and the second common-mode switch are turned on in the second phase of the clock cycle, and the quantizer of the first pipeline processing unit is enabled in the second phase of the clock cycle.

[0028] In one possible implementation, each pipelined processing unit, except for the first-stage pipelined processing unit, includes: a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a first sampling capacitor, a second sampling capacitor, a third unity-gain voltage buffer, a fourth unity-gain voltage buffer, and a quantizer. The first terminal of the first switch and the first terminal of the second switch are respectively used to receive the positive and negative signals of the differential or residual signals output by the previous-stage pipelined processing unit. The second terminal of the first switch is connected to the first terminal of the first sampling capacitor, the input terminal of the third unity-gain voltage buffer, and the first input terminal of the quantizer of the pipelined processing unit. The second terminal of the second switch is connected to the first terminal of the second sampling capacitor, the input terminal of the fourth unity-gain voltage buffer, and the second input terminal of the quantizer of the pipelined processing unit. The second terminal of a sampling capacitor receives the negative signal of the differential signal or residual signal output by the previous stage pipeline processing unit through the third switch and is connected to a positive or negative reference voltage through the fifth switch. The second terminal of the second sampling capacitor receives the positive signal of the differential signal or residual signal output by the previous stage pipeline processing unit through the fourth switch and is connected to a negative or positive reference voltage through the sixth switch. If the quantization result output by the previous stage is a high-level signal, the second terminal of the first sampling capacitor is connected to the negative reference voltage, and the second terminal of the second sampling capacitor is connected to the positive reference voltage. Conversely, if the quantization result output by the previous stage is a low-level signal, the second terminal of the first sampling capacitor is connected to the positive reference voltage, and the second terminal of the second sampling capacitor is connected to the negative reference voltage. The difference between the positive reference voltage and the negative reference voltage is a preset reference voltage.

[0029] In one possible implementation, the first switch, the second switch, the third switch, and the fourth switch are turned on in the second phase of the clock cycle of the preceding pipeline unit, the fifth switch and the sixth switch are turned on in the first phase of the clock cycle of the next pipeline unit, and the quantizer of the pipeline unit is enabled in the first phase of the clock cycle of the next pipeline unit.

[0030] According to one aspect of this disclosure, an electronic device is provided, the electronic device including a high-speed pipelined analog-to-digital converter as described.

[0031] Each stage of the pipeline processing unit in this disclosure adopts differential sampling technology to achieve double gain, which can achieve high-efficiency signal amplification without the need for a dedicated amplifier. Compared with related technologies, it saves circuit area and cost. Furthermore, since there is no need to set up a corresponding amplification process, the sampling and amplification of analog signals can be achieved in the differential sampling operation, which can improve the speed of analog-to-digital conversion. Therefore, the high-speed pipeline analog-to-digital converter in this disclosure has the characteristics of high energy efficiency, low complexity, and high-speed conversion.

[0032] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Other features and aspects of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0033] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the specification, serve to illustrate the technical solutions of this disclosure.

[0034] Figure 1a shows a schematic diagram of a traditional pipelined ADC architecture, and Figure 1b shows a schematic diagram of the operating modes of a traditional pipelined ADC architecture.

[0035] Figure 2a shows a schematic diagram of a pipelined ADC using the "forward quantization" method, and Figure 2b shows a schematic diagram of the operating mode of a pipelined ADC using the "forward quantization" method.

[0036] Figure 3a shows a schematic diagram of a pipelined ADC using the "scale-up and residual error generation" method, and Figure 3b shows a schematic diagram of the operating mode of the pipelined ADC using the "scale-up and residual error generation" method.

[0037] Figure 4 shows a schematic diagram comparing the input and output signal swings of the residual amplifier in the three pipeline architectures shown in Figures 1a, 2a, and 3a.

[0038] Figure 5 shows a schematic diagram of a high-speed pipelined analog-to-digital converter according to an embodiment of the present disclosure.

[0039] Figure 6a shows a schematic diagram comparing differential sampling and single-ended sampling circuits.

[0040] Figure 6b shows a schematic diagram of an adjacent pipeline processing unit according to an embodiment of the present disclosure.

[0041] Figure 6c shows a timing diagram of adjacent pipeline processing units according to an embodiment of the present disclosure.

[0042] Figure 7 shows a schematic diagram of a unity-gain voltage buffer according to an embodiment of the present disclosure.

[0043] Figure 8 shows a schematic diagram of operation without power gating technology and with existing switch-based power gating technology.

[0044] Figure 9a shows a schematic diagram of automatic power gating based on the unity-gain voltage buffer.

[0045] Figure 9b shows a schematic diagram comparing the total power consumption of the automatic power gating technology shown in Figure 9a with the two methods in Figure 8.

[0046] Figure 10a shows a schematic diagram of a high-speed pipelined analog-to-digital converter according to an embodiment of the present disclosure.

[0047] Figure 10b shows a schematic diagram of the execution timing of the high-speed pipelined analog-to-digital converter shown in Figure 10a. Detailed Implementation

[0048] Various exemplary embodiments, features, and aspects of this disclosure will now be described in detail with reference to the accompanying drawings. The same reference numerals in the drawings denote elements that have the same or similar functions. Although various aspects of the embodiments are shown in the drawings, they are not necessarily drawn to scale unless specifically indicated otherwise.

[0049] In the description of this disclosure, it should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this disclosure and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this disclosure.

[0050] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this disclosure, "a plurality of" means two or more, unless otherwise expressly specified.

[0051] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.

[0052] The term “exemplary” as used herein means “serving as an example, embodiment, or illustration.” Any embodiment illustrated herein as “exemplary” is not necessarily to be construed as superior to or better than other embodiments.

[0053] In this document, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent three cases: A alone, A and B simultaneously, and B alone. Furthermore, the term "at least one" in this document means any combination of at least two of any one or more elements. For example, including at least one of A, B, and C can mean including any one or more elements selected from the set consisting of A, B, and C.

[0054] Furthermore, to better illustrate this disclosure, numerous specific details are set forth in the following detailed description. Those skilled in the art will understand that this disclosure can be practiced without certain specific details. In some instances, methods, means, components, and circuits well known to those skilled in the art have not been described in detail in order to highlight the main points of this disclosure.

[0055] The background technology has already introduced the shortcomings of pipelined ADCs. As can be seen from Figure 4, the two architectures shown in Figures 2a and 3a retain the residual amplifier module in the traditional architecture. The residual amplifier is usually the bottleneck limiting the performance of pipelined ADCs and is also the module with the largest power consumption. Therefore, the two architectures shown in Figures 2a and 3a have the disadvantage of low energy efficiency.

[0056] The advantages and disadvantages of the existing high-speed pipeline architectures mentioned above are summarized in Table 1.

[0057] Table 1: Comparison of the advantages and disadvantages of existing high-speed pipeline architectures

[0058] Please refer to Figure 5, which shows a schematic diagram of a high-speed pipelined analog-to-digital converter according to an embodiment of the present disclosure.

[0059] As shown in Figure 5, the high-speed pipelined analog-to-digital converter includes cascaded multi-stage pipelined processing units. The first-stage pipelined processing unit 10 is used to receive differential analog input signals and output differential signals and corresponding quantized signals. Except for the first-stage pipelined processing unit 10, the other pipelined processing units 20 are configured to perform differential sampling operations and residual propagation operations.

[0060] The differential sampling operation includes: the Nth stage pipeline processing unit differentially samples the residual signal or the differential signal received from the previous stage to obtain a sampled signal, and receives the quantization result output by the N-1th stage pipeline processing unit, where N is a positive integer greater than 1.

[0061] The residual propagation operation includes: the Nth stage pipeline processing unit determining the residual signal between the sampled signal and the quantization result of the previous stage pipeline processing unit; performing a quantization operation on the residual signal of the Nth stage pipeline processing unit to obtain a quantization result; and propagating the quantization result and residual signal of the Nth stage pipeline processing unit to the (N+1)th stage pipeline processing unit.

[0062] The quantization results of the quantization outputs of each stage of the pipeline processing unit are used as the analog-to-digital conversion results of the analog input signal.

[0063] The pipeline processing units at each stage of this disclosure use differential sampling technology to achieve double gain, enabling high-efficiency signal amplification without the need for a dedicated amplifier. Compared to related technologies that require a residual amplifier, this saves circuit area and cost. Furthermore, since no dedicated amplification process is needed, analog signal sampling and amplification are achieved during differential sampling, which improves the speed of analog-to-digital conversion. Therefore, the high-speed pipelined analog-to-digital converter of this disclosure features high energy efficiency, low complexity, and high-speed conversion.

[0064] The embodiments disclosed herein do not limit the specific implementation of each stage of the pipeline processing unit. Those skilled in the art can set it according to actual conditions and needs. As long as the first stage pipeline processing unit can receive differential analog input signals and output differential signals and corresponding quantization signals, the other stages of the pipeline processing unit can perform differential sampling operations and residual difference propagation operations.

[0065] For example, the analog input signal can be any analog signal that requires analog-to-digital conversion, and this embodiment of the present disclosure does not limit this.

[0066] The following section introduces the single-ended sampling method in differential sampling and correlation techniques.

[0067] Please refer to Figure 6a, which shows a comparative schematic diagram of differential sampling and single-ended sampling circuits.

[0068] For example, as shown in Figure 6a, the sampling capacitor C in the single-ended sampling circuit S One end is connected to the input voltage signal V IN The other end is connected to a fixed voltage (usually ground), so after sampling, capacitor C... S The voltage on is the input voltage signal V. IN .

[0069] For example, as shown in Figure 6a, the sampling capacitor C in the differential sampling circuit S The two ends are respectively connected to the positive input signal V IN and negative input signal -V INTherefore, after sampling, capacitor C S The voltage on the circuit is twice the input voltage (2V). IN ).

[0070] This demonstrates that the differential sampling circuit can achieve double gain without the need for an additional amplifier, making it a highly energy-efficient amplification method. In this embodiment, the ADC chip is a fully differential circuit, and the input signal is a differential signal. Therefore, there is no need to generate an additional negative input signal in the ADC; simply connect the two ends of the differential input signal to the sampling capacitor C. S Differential sampling can be achieved at both ends.

[0071] In one possible implementation, each stage of the pipeline processing unit is configured to perform differential sampling and residual propagation operations based on a target clock signal, wherein the target clock signal is set to a form in which a first phase and a second phase alternate periodically, wherein...

[0072] In the first phase, the Nth stage pipeline processing unit performs differential sampling on the residual signal or the differential signal received from the previous stage to obtain a sampled signal, and receives the quantization result output by the N-1th stage pipeline processing unit.

[0073] In the second phase, the Nth stage pipelined processing unit determines the residual signal between the sampled signal and the quantization result of the previous stage pipelined processing unit, performs a quantization operation on the residual signal of the Nth stage pipelined processing unit to obtain a quantization result, and transmits the quantization result and residual signal of the Nth stage pipelined processing unit to the (N+1)th stage pipelined processing unit.

[0074] Please refer to Figure 6b, which shows a schematic diagram of an adjacent pipeline processing unit according to an embodiment of the present disclosure.

[0075] Please refer to Figure 6c, which shows a timing diagram of adjacent pipeline processing units according to an embodiment of the present disclosure.

[0076] For example, as shown in FIG6b, embodiments of this disclosure can be configured with corresponding switches between pipeline stages to conduct the switches at different phases and achieve corresponding operations. It should be noted that FIG6b is not intended to limit the circuit structure of the pipeline processing unit, but rather to provide an exemplary description of the signal processing process. In FIG6b, the "×1" and "×2" inside the buffer represent the corresponding gains; "×2" indicates that differential sampling can achieve 2x amplification, and "×1" indicates that the amplification factor of the unity-gain voltage buffer is 1.

[0077] This disclosure does not limit the quantization processing method in each stage of the pipeline processing unit. Those skilled in the art can use relevant technologies to implement it according to actual conditions and needs. For example, a quantizer (such as a flash quantizer) in related technologies can be used to quantize the analog signal (residual difference signal), and then the quantization result can be converted from digital to analog by a digital-to-analog converter (DAC) to obtain the corresponding analog signal. In this way, this disclosure can use a subtractor or other devices to "determine the residual difference signal between the sampled signal and the quantization result of the previous pipeline processing unit". Of course, "determining the residual difference signal between the sampled signal and the quantization result of the previous pipeline processing unit" can be achieved by a subtractor or other methods. Those skilled in the art can use appropriate technical solutions to implement it according to actual conditions and needs. This disclosure does not limit it.

[0078] For example, as shown in Figure 6c, the target clock signal is set to a periodic alternation of a first phase (Φ1 phase) and a second phase (Φ2 phase), with each period T... S It includes the first phase (Φ1 phase) and the second phase (Φ2 phase), with the Φ1 phase and Φ2 phase alternating periodically.

[0079] For example, as shown in Figures 6b and 6c, in phase Φ1 (the first phase), the switch between stage N and stage N-1 can be turned on. Stage N performs differential sampling on the residual signal from stage N-1 (buffer BUF), and sends the sampled signal obtained by differential sampling to one end of the subtractor. Unlike the aforementioned architectures (Figures 1a, 2a, and 3a), this embodiment of the disclosure uses a differential sampling method, achieving a double gain while sampling. Simultaneously, as shown in Figures 6b and 6c, in phase Φ1, the quantizer of stage N-1 is enabled to perform quantization. Thus, stage N receives the quantization result from stage N-1, and the digital-to-analog converter in stage N performs a digital-to-analog conversion operation on the quantization result to obtain the corresponding analog signal, which is then sent to the subtractor.

[0080] For example, as shown in Figures 6b and 6c, in phase Φ2 (the second phase), the Nth stage uses a subtractor to subtract the differentially sampled and amplified signal from the analog signal corresponding to the quantization result, generating a residual signal. This residual signal is then passed to the (N+1)th stage through a unity-gain voltage buffer (BUF). Simultaneously, in phase Φ2, the quantizer of the Nth stage is enabled to perform quantization. Thus, the quantizer of the Nth stage quantizes the residual signal, and the quantization result D[N] is also sent to the (N+1)th stage.

[0081] The pipeline architecture of this disclosure parallelizes the sampling and amplification processes through differential sampling, reducing the required operation steps from three to two (sampling & amplification, quantization & residual propagation), thus improving the speed of the pipelined ADC. Furthermore, with the same gain-bandwidth product, the unity-gain voltage buffer has a gain of 1, providing a higher bandwidth compared to the residual amplifier, resulting in faster residual propagation and further improving the speed of the pipelined ADC.

[0082] The high-speed pipelined ADC architecture of this disclosure eliminates the residual amplifier module, which accounts for the largest power consumption in traditional architectures, and achieves gain using differential sampling, resulting in high energy efficiency. Compared with the pipeline architecture using the "forward quantization" method shown in Figure 2a, this disclosure embodiment does not require the generation of an additional reference voltage, reducing the design complexity and power consumption of the reference voltage module. Compared with the pipeline architecture using the "abbreviated residual signal generation" method shown in Figure 3a, this disclosure embodiment uses a unity-gain voltage buffer to transmit the amplified residual signal, improving linearity compared to the residual amplifier while avoiding output saturation.

[0083] The advantages of the embodiments disclosed herein compared to existing high-speed pipelined ADC architectures are summarized in Table 2.

[0084] Table 2: Summary of the advantages of the embodiments of this disclosure compared to existing high-speed pipelined ADC architectures

[0085] In one possible implementation, the analog-to-digital converter may include a first input buffer and a second input buffer. The input terminals of the first and second input buffers are used to input the analog input signal, and the output terminals of the first and second input buffers are connected to the first-stage pipeline processing unit. Thus, embodiments of this disclosure can receive differential input signals through the first and second input buffers.

[0086] The embodiments disclosed herein do not limit the specific implementation of the first input buffer and the second input buffer. Those skilled in the art can implement them using buffer circuits from related technologies according to actual conditions and needs.

[0087] In one possible implementation, as shown in FIG6b, each pipeline processing unit may further include a unity-gain voltage buffer (BUF) for transmitting the residual signal or the differential signal to the sampling circuit of the next pipeline processing unit.

[0088] This disclosure does not limit the specific implementation of the unity-gain voltage buffer, and those skilled in the art can implement it using relevant technologies according to actual conditions and needs. Of course, the aforementioned first input buffer and second input buffer can also be the unity-gain voltage buffer described in this disclosure.

[0089] Please refer to Figure 7, which shows a schematic diagram of a unity-gain voltage buffer according to an embodiment of the present disclosure.

[0090] In one possible implementation, as shown in FIG7, the unity-gain voltage buffer may include a first MOS transistor M1 and a second MOS transistor M2.

[0091] The gate of the first MOS transistor M1 is used to receive the residual signal or the differential signal (denoted as V here). IN1 The drain of the first MOS transistor M1 is used to receive the power supply voltage V. DD The source of the first MOS transistor M1 is connected to the drain of the second MOS transistor M2.

[0092] The gate of the second MOS transistor M2 is used to receive the bias voltage, and the source of the second MOS transistor M2 is grounded.

[0093] In this configuration, the first MOS transistor M1 is configured to be biased in the saturation region. The source of the first MOS transistor M1 and the drain of the second MOS transistor M2 serve as the output terminals of the unity-gain voltage buffer, used to output the buffered residual signal or differential signal (V). OUT1 ).

[0094] For example, the first MOS transistor M1 and the second MOS transistor M2 are NMOS transistors.

[0095] The embodiments of this disclosure do not limit the method of generating the bias voltage. For example, as shown in FIG7, a bias circuit can be set to generate a corresponding bias voltage and output it to the gate of the second MOS transistor M2. Of course, it can also receive an externally input bias voltage. The embodiments of this disclosure do not limit this. In addition, the embodiments of this disclosure do not limit the specific implementation of the bias circuit. Those skilled in the art can use relevant technologies to implement it according to the actual situation and needs.

[0096] In the high-speed pipelined ADC architecture of this disclosure embodiment, the unity-gain voltage buffer can be implemented using a source follower (SF) circuit as shown in Figure 7, with the input signal V IN1The residual signal or differential signal is transmitted to the output terminal through the first MOS transistor M1. It is worth noting that during this process, the first MOS transistor M1 needs to be biased in the saturation region, i.e., the gate-source voltage V of the first MOS transistor M1... GS It needs to be higher than its threshold voltage V th At the same time, the output signal V OUT1 Relative to the input signal V IN1 There is a level shift, i.e., V OUT1 =V IN1 -V GS .

[0097] Please refer to Figure 8, which shows a schematic diagram of operation without power gating technology and with existing switch-based power gating technology.

[0098] As shown in Figure 8, without power gating technology, in phase Φ2, the voltage buffer of the current pipeline processing unit transmits the residual signal or differential signal to the next stage, consuming the corresponding static power consumption; however, in phase Φ1, the current pipeline samples the residual signal or differential signal of the previous stage, and the voltage buffer still consumes the same amount of static power consumption, thus wasting approximately 50% of the static power consumption.

[0099] As shown in Figure 8, switch-based power gating technology achieves current shutdown by connecting a switch in series in the source follower. In phase Φ2, the switch is closed, allowing the voltage buffer to operate normally; in phase Φ1, the switch is open, thus saving approximately 50% of static power consumption. However, in advanced processes, the power supply voltage V... DD Typically low, therefore a larger switch size is required to reduce the switch's on-resistance R. ON This reduces the voltage space occupied by the switching resistor, while a larger switch size increases the additional dynamic power consumption used to drive the switch. Therefore, this switch-based power gating technology has very limited improvement in energy efficiency.

[0100] In view of this, the present disclosure proposes a new automatic power gating mechanism based on the unity-gain voltage buffer, which can realize automatic power gating at each level without the need to set an additional switch in the unity-gain voltage buffer.

[0101] In one possible implementation, the unity-gain voltage buffer can be configured to satisfy the following first condition to achieve automatic power gating: the first condition is: V DD ≤V GS +V th , where V DD The voltage V represents the power supply voltage. GS V represents the gate-source voltage of the first MOS transistor M1. th This represents the turn-on threshold voltage of the first MOS transistor M1.

[0102] The pipeline processing units at each stage are configured to periodically perform pipelined operations under a target clock signal, wherein the target clock signal is set to a form in which a first phase and a second phase alternate periodically. When the unity-gain voltage buffers in each pipeline processing unit satisfy the first condition, each pipeline processing unit is configured as follows:

[0103] In each first phase, the 2nth pipeline processing unit performs a differential sampling operation, and the 2n-1th pipeline processing unit performs a residual propagation operation, where n is a positive integer;

[0104] In each second phase, the 2nth pipeline processing unit performs a residual propagation operation, and the 2n-1th pipeline processing unit performs a differential sampling operation.

[0105] The 2nth pipeline unit is the even-numbered pipeline unit in the cascaded pipeline units, and the 2n-1th pipeline unit is the pipeline unit preceding the even-numbered pipeline unit (i.e., the odd-numbered pipeline unit).

[0106] It should be noted that in this embodiment, "n" is the number of each level of pipeline processing unit after excluding the aforementioned first-level pipeline processing unit. That is, except for the first-level pipeline processing unit, the numbers of the other levels of pipeline processing units start from 1. Alternatively, the number of the first-level pipeline processing unit can be recorded as "0", and the second-level pipeline processing unit corresponds to the first odd-numbered level pipeline processing unit (2n-1) with n=1.

[0107] Please refer to Figure 9a, which shows a schematic diagram of automatic power gating based on the unity-gain voltage buffer.

[0108] In the high-speed pipelined ADC architecture of this disclosure embodiment, the interstage residual signal transmission is preferably implemented using a voltage buffer with a source follower structure.

[0109] For example, as shown in Figure 9a, in phase Φ1, the even-numbered stage (2n-th stage) pipeline processing unit performs differential sampling, and the odd-numbered stage (2n-1-th stage) pipeline processing unit performs residual propagation. At this time, the input signal of the voltage buffer of the even-numbered stage pipeline processing unit (i.e., the output signal of the odd-numbered stage voltage buffer) is V. R [2n]=V R [2n-1]-V GS V R [2n-1] is the input signal of the voltage buffer of the odd-numbered pipeline processing unit (i.e., the residual signal of the odd-numbered stage at this time), V GSThis represents the gate-source voltage of the first MOS transistor M1 in the unity-gain voltage buffer of the odd-level pipelined processing unit. As mentioned earlier, the gate-source voltage V... GS The voltage V above the threshold voltage of the first MOS transistor M1 th Furthermore, to ensure the reliability of the transistor, the gate voltage V R [2n-1] needs to be lower than the power supply voltage V. DD From this, we can derive V R [2n] <V DD -V GS If condition V is satisfied DD ≤V GS +V th Then V R [2n] <V DD -V GS ≤V th At this time, the gate voltage V of the first MOS transistor M1 in the even-numbered stage voltage buffer is... R [2n] is below its threshold voltage V th Therefore, the first MOS transistor M1 is in the cutoff region, resulting in zero current in the voltage buffer in the even-numbered stages, thus achieving power supply gating.

[0110] For example, as shown in Figure 9a, in the Φ2 phase, the even-numbered stage (2nth stage) pipeline processing unit performs residual propagation, and the odd-numbered stage (2n-1th stage) pipeline processing unit performs differential sampling. Similarly, the voltage buffer in the odd-numbered stage implements power gating at this time.

[0111] It can be seen that in the high-speed pipelined ADC architecture of this disclosure embodiment, the cascaded structure of interstage source followers can realize an automatic power gating technology, which reuses the first MOS transistor M1 in the pipelined processing unit as a switch to cut off the current, without the need for additional switches and switch drive power consumption.

[0112] Please refer to Figure 9b, which shows a comparison of the total power consumption of the automatic power gating technology shown in Figure 9a with the two methods in Figure 8.

[0113] As shown in Figure 9b, compared to Figure 8 which does not use gating technology, the embodiments of this disclosure reduce static power consumption by 50%. Compared to the switch-based power gating technology in Figure 8, the embodiments of this disclosure eliminate the additional power consumption of the switch drive. It is worth noting that the implementation condition of the automatic power gating technology in the embodiments of this disclosure is V. DD ≤V GS +V th Simply set the power supply voltage V DD Less than or equal to the transistor gate-source voltage V GS and threshold voltage V thThe sum of these values ​​is sufficient to meet the requirements, which can be easily achieved in advanced processes, such as the nominal power supply voltage V in 28nm CMOS processes. DD The voltage is 0.9V, which can be achieved by selecting a transistor with a threshold voltage higher than 0.45V.

[0114] The following provides a possible implementation of a high-speed pipelined analog-to-digital converter according to an embodiment of this disclosure.

[0115] Please refer to Figure 10a, which shows a schematic diagram of a high-speed pipelined analog-to-digital converter according to an embodiment of the present disclosure.

[0116] Please refer to Figure 10b, which shows a timing diagram of the execution of the high-speed pipelined analog-to-digital converter shown in Figure 10a.

[0117] In one possible implementation, as shown in FIG10a, the first-stage pipeline processing unit may include a first access switch S11, a second access switch S12, a first grounding switch S13, a second grounding switch S14, a first common-mode switch S15, a second common-mode switch S16, and a first capacitor C. S01 Second capacitor C S02 First unity-gain voltage buffer SF 01 and the second unity-gain voltage buffer SF 02 Quantizer Qua1, where,

[0118] The first terminal of the first access switch S11 and the first terminal of the second access switch S12 are respectively used to receive the positive signal (V) of the differential analog input signal. INP ), negative signal (V) INN ),

[0119] The second terminal of the first access switch S11 is connected to the first capacitor C. S01 The first terminal, the first unity-gain voltage buffer SF 01 The input terminal of the quantizer Qua1 in the first-stage pipeline processing unit.

[0120] The second terminal of the second access switch S12 is connected to the second capacitor C. S02 The first terminal and the second unity-gain voltage buffer SF 02 The input terminal of the first-stage pipeline processing unit and the second input terminal of the quantizer Qua1.

[0121] The first capacitor C S01 The second terminal is grounded through the first grounding switch S13 and connected to the common-mode reference voltage V through the first common-mode switch S15. REFCM ,

[0122] The second capacitor C S02 The second terminal is grounded through the second grounding switch S14 and connected to the common-mode reference voltage V through the second common-mode switch S16. REFCM .

[0123] In one possible implementation, as shown in FIG10a, the first access switch S11, the second access switch S12, the first ground switch S13, and the second ground switch S14 are turned on in the first phase Φ1 of the clock cycle, the first common-mode switch S15 and the second common-mode switch S16 are turned on in the second phase Φ2 of the clock cycle, and the quantizer Qua1 of the first-stage pipeline processing unit is enabled in the second phase Φ2 of the clock cycle.

[0124] In one possible implementation, as shown in FIG10a, each stage of the pipeline processing unit, in addition to the first stage pipeline processing unit, may include:

[0125] First switch S21, second switch S22, third switch S23, fourth switch S24, fifth switch S25, sixth switch S26, first sampling capacitor C S11 Second sampling capacitor C S12 Third unity gain voltage buffer SF 11 and the fourth unit gain voltage buffer SF 12 Quantizer Qua2, where,

[0126] The first terminal of the first switch S21 and the first terminal of the second switch S22 are respectively used to receive the positive and negative signals of the differential signal or residual signal output by the previous stage pipeline processing unit.

[0127] The second terminal of the first switch S21 is connected to the first sampling capacitor C. S11 The first terminal, the third unity-gain voltage buffer SF 11 The input terminal of the quantizer Qua2 in this pipeline processing unit.

[0128] The second terminal of the second switch S22 is connected to the second sampling capacitor C. S12 The first terminal, the fourth unity-gain voltage buffer SF 12 The input terminal of the pipeline processing unit, the second input terminal of the quantizer Qua2,

[0129] The first sampling capacitor C S11 The second terminal receives the negative signal of the differential signal or residual signal output from the previous stage pipeline processing unit through the third switch S23, and is connected to a positive reference voltage (V) through the fifth switch S25. REFP) or negative reference voltage (V REFN ),

[0130] The second sampling capacitor C S12 The second terminal receives the positive signal of the differential signal or residual signal output by the previous stage pipeline processing unit through the fourth switch S24, and is connected to the negative reference voltage or positive reference voltage through the sixth switch S26.

[0131] Wherein, if the quantization result output from the previous stage is a high-level signal, then the first sampling capacitor C S11 The second terminal is connected to the negative reference voltage, and the second sampling capacitor C S12 The second terminal is connected to the positive reference voltage; conversely, if the quantization result output by the previous stage is a low-level signal, then the first sampling capacitor C S11 The second terminal is connected to the positive reference voltage, and the second sampling capacitor C S12 The second terminal is connected to the negative reference voltage.

[0132] Wherein, the difference between the positive reference voltage and the negative reference voltage is a preset reference voltage (V). REF =V REFP -V REFN The preset reference voltage can also be called the differential reference voltage.

[0133] This disclosure does not limit the specific magnitude and generation method of the common-mode reference voltage and the preset reference voltage; those skilled in the art can set them according to actual conditions and needs. For example, V REFCM This is the common-mode voltage of the reference voltage, the input common-mode voltage that enables the unity-gain voltage buffer (source follower) to function properly. For example, V... REFCM =0.5*(V REFP +V REFN As an example, since the first-stage pipelined processing unit does not have the quantization result from the previous stage, there is no difference step. Therefore, both the P terminal (positive terminal) and the N terminal (negative terminal) are connected to the common-mode reference voltage V. REFCM Subsequent pipeline processing units need to generate residual voltage through differential calculations; therefore, the P and N terminals must be connected to positive reference voltages (V). REFP ) or negative reference voltage (V REFN The common-mode voltage of both is also V. REFCM .

[0134] In this embodiment, the first sampling capacitor C is selected based on the quantization result of the previous stage output. S11 Second sampling capacitor C S12The specific implementation method of the connected positive and negative reference voltages is not limited. Those skilled in the art can use relevant technologies to implement it according to the actual situation and needs. For example, a multiplexer can be set to select the first sampling capacitor C according to the quantization result. S11 Second sampling capacitor C S12 The positive and negative reference voltages are connected; of course, other implementation methods can be used.

[0135] It should be noted that the pipeline processing unit shown in Figure 10a selects the first sampling capacitor C based on the quantization result of the previous stage output. S11 Second sampling capacitor C S12 The positive and negative reference voltages are connected, and the first sampling capacitor C is set. S11 Second sampling capacitor C S12 This is to achieve "determining the residual difference signal between the sampled signal and the quantization result of the previous pipeline processing unit". However, this embodiment of the present disclosure does not limit this. As mentioned above, those skilled in the art can also use a subtractor to obtain the residual difference signal between the two.

[0136] In one possible implementation, as shown in FIG10a, the first switch S21, the second switch S22, the third switch S23, and the fourth switch S24 are turned on in the second phase Φ2 of the clock cycle of the previous pipeline unit, the fifth switch S25 and the sixth switch S26 are turned on in the first phase Φ1 of the clock cycle of the next pipeline unit, and the quantizer Qua2 of the pipeline unit is enabled in the first phase Φ1 of the clock cycle of the next pipeline unit.

[0137] In one possible implementation, as shown in Figure 10a, the positive signal (V) of the differential analog input signal INP ), negative signal (V) INN After passing through the input buffer (SF) IN1 / SF IN2 It is sent to the first-level production line processing unit.

[0138] In one possible implementation, Figure 10b shows the timing signal diagram of the first two stages of the pipelined ADC, which illustrates the portion of the signal from the input to the second stage in one pipeline pass.

[0139] As shown in Figures 10a and 10b, in phase Φ1, the first access switch S11, the second access switch S12, the first grounding switch S13, and the second grounding switch S14 are turned on. The first-stage pipeline processing unit samples the input signal to obtain the differential signal V. RP [0]-V RN [0] = ΔV, without loss of generality, assume ΔV > 0.

[0140] As shown in Figures 10a and 10b, in phase Φ2, the first common-mode switch S15 and the second common-mode switch S16 are turned on, and the first unity-gain voltage buffer SF of the first-stage pipeline processing unit is activated. 01 and the second unity-gain voltage buffer SF 02 The input terminal is raised to a suitable input common-mode level, i.e., the common-mode reference voltage V. REFCM This allows the differential signal ΔV to be transmitted to the second stage.

[0141] As can be seen from the operating mode of the pipelined ADC in the embodiments of this disclosure described above, the second-stage pipelined processing unit performs differential sampling on this signal (differential signal ΔV) (including the two dashed box portions of the second stage in Figure 10a), that is, the sampling capacitor at the P terminal (positive terminal) (the first sampling capacitor C) S11 The sampling voltage is ΔV, and the sampling capacitor (second sampling capacitor C) is located at the N-terminal (negative terminal). S12 The sampling voltage is -ΔV.

[0142] Meanwhile, as shown in Figures 10a and 10b, in phase Φ2, the quantizer Qua1 of the first-stage pipeline processing unit quantizes the differential signal ΔV to obtain the quantization result D[0] (since ΔV>0, D[0]=1). At the beginning of the next phase Φ1, the second stage subtracts the differentially sampled signal from the quantization result D[0] to generate a residual signal. Specifically, the sampling capacitor (first sampling capacitor C) at the P terminal (positive terminal) of the sampling voltage ΔV is sampled. S11 The base plate is connected to the negative reference voltage V. REFN V RP [1] = V REFN +ΔV, sampling voltage is -ΔV, the sampling capacitor (second sampling capacitor C) is located at the N-terminal (negative terminal). S12 The base plate is connected to a positive reference voltage V. REFP V RN [1] = V REFP -ΔV. Therefore, the residual signal of the second-stage pipeline processing unit is V. RP [1]-V RN [1]=2ΔV-V REF V REF =V REFP -V REFN This shows that differential sampling achieves a twofold gain, as shown in Figures 10a and 10b, which correspond to ΔV = 0.7V. REF In this situation, after the residual signal is generated, the second-stage pipeline processing unit processes the residual signal V. RP [1]-V RN [1] Through the third unity-gain voltage buffer SF 11 and the fourth unit gain voltage buffer SF12 The signal is transmitted to the third-level pipeline processing unit, and the residual signal is quantized to obtain the quantization result D[1], which is also sent to the third-level pipeline processing unit.

[0143] The structure and operating mode of the remaining stages (such as stages 3 to 10) of the pipelined processing unit are the same as those of stage 2 (the last stage, stage 10, does not need to perform residual propagation, so the corresponding unity-gain voltage buffer can be removed to reduce costs), thus realizing a high-speed single-channel 10-stage pipelined ADC.

[0144] In summary, the high-speed pipelined analog-to-digital converter of this disclosure has the following advantages over existing methods:

[0145] Compared with the traditional pipelined ADC shown in Figure 1a, it reduces the number of operation steps and improves the sampling rate (speed);

[0146] Compared with the two existing methods for increasing the speed of pipelined ADCs shown in Figures 2a and 3a, this method eliminates the need for a complex reference voltage generation module, thus avoiding the problems of poor linearity of the residual amplifier and output saturation.

[0147] By employing differential sampling technology to achieve double gain, the redundant amplifier module, which accounts for the largest proportion of power consumption in traditional pipelined ADCs, is eliminated, thereby improving overall energy efficiency.

[0148] Using a unity-gain voltage buffer for residual transfer provides a larger bandwidth compared to using a residual amplifier in related technologies, further improving the overall speed.

[0149] An automatic power gating mechanism is implemented through a unity-gain voltage buffer, which saves 50% of static power consumption without the need for additional switches and switch drive power consumption.

[0150] At the application level, the embodiments of this disclosure can be used as a single-channel ADC in all high-speed (1-5GS / s sampling rate), medium-low precision (6-8 bit quantization accuracy) ADC products, and can also be used as a sub-channel of a time-interleaved ADC in ultra-high-speed (above 5GS / s sampling rate), medium-low precision (6-8 bit quantization accuracy) ADC products. The embodiments of this disclosure do not limit their application areas. The advantages of the embodiments of this disclosure are that they solve the problems of slow speed and low energy efficiency of single-channel or sub-channel ADCs in these products, and reduce the number of interleaved channels, design complexity, and calibration difficulty of ultra-high-speed time-interleaved ADCs.

[0151] The embodiments disclosed herein employ differential sampling technology to perform two parallel sampling and amplification processes, and use a unity-gain voltage buffer for residual error propagation, thereby reducing the operation steps of the pipelined ADC to two (sampling & amplification, quantization & residual error propagation), thus improving the overall speed.

[0152] The embodiments disclosed herein employ a specific unity-gain voltage buffer and utilize an automatic power gating technique implemented through an interstage source follower cascade structure. This reduces static power consumption by 50% without requiring additional switches or switch drive power consumption.

[0153] According to one aspect of this disclosure, an electronic device is provided, the electronic device including a high-speed pipelined analog-to-digital converter as described.

[0154] This disclosure does not limit the specific type of electronic device. Electronic devices may include terminal devices, such as user equipment (UE), mobile devices, user terminals, terminals, handheld devices, computing devices, or in-vehicle devices. Examples of terminals include: mobile phones, tablets, laptops, PDAs, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, wireless terminals in industrial control, self-driving, remote medical surgery, smart grids, transportation safety, smart cities, smart homes, and vehicle-to-everything (V2X) networks. For example, a server can be a local server or a cloud server.

[0155] Of course, high-speed pipelined analog-to-digital converters can also be integrated into the processing component to perform the corresponding analog-to-digital conversion operations. In one example, the processing component includes, but is not limited to, a separate processor, discrete components, or a combination of processors and discrete components. The processor may include a controller in an electronic device with instruction execution capabilities. The processor can be implemented in any suitable manner, for example, by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components. Within the processor, the executable instructions can be executed through hardware circuits such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0156] The various embodiments of this disclosure have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or improvement of the technology in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A high-speed pipelined analog-to-digital converter, comprising: The analog-to-digital converter comprises a plurality of cascade pipeline processing units, a first pipeline processing unit is configured to receive a differential analog input signal and output a differential signal and a corresponding quantization signal, and each pipeline processing unit other than the first pipeline processing unit is configured to perform a differential sampling operation and a residual difference transmission operation, wherein the differential sampling operation comprises: an Nth pipeline processing unit performing differential sampling on a residual difference signal received from a previous stage or the differential signal to obtain a sampling signal, and receiving a quantization result output by an (N-1)th pipeline processing unit, N being a positive integer greater than 1; the residual difference transmission operation comprises: the Nth pipeline processing unit determining a residual difference signal between the sampling signal and the quantization result of the previous stage, performing a quantization operation on the residual difference signal of the Nth pipeline processing unit to obtain a quantization result, and transmitting the quantization result and the residual difference signal of the Nth pipeline processing unit to an (N+1)th pipeline processing unit, wherein the quantization result output by each pipeline processing unit is an analog-to-digital conversion result of the analog input signal.

2. The high-speed pipeline analog-to-digital converter of claim 1, wherein, Each pipeline processing unit is configured to perform the differential sampling operation and the residual difference transmission operation based on a target clock signal, the target clock signal being set in a form of periodically alternating between a first phase and a second phase, wherein in the first phase, the Nth pipeline processing unit performs differential sampling on a residual difference signal received from a previous stage or the differential signal to obtain a sampling signal, and receives a quantization result output by an (N-1)th pipeline processing unit; in the second phase, the Nth pipeline processing unit determines a residual difference signal between the sampling signal and the quantization result of the previous stage, performs a quantization operation on the residual difference signal of the Nth pipeline processing unit to obtain a quantization result, and transmits the quantization result and the residual difference signal of the Nth pipeline processing unit to an ( N+1)th pipeline processing unit.

3. The high-speed pipeline analog-to-digital converter of claim 1, wherein, The analog-to-digital converter comprises a first input buffer and a second input buffer, input ends of the first input buffer and the second input buffer are configured to input the analog input signal, and output ends of the first input buffer and the second input buffer are connected to the first pipeline processing unit.

4. The high-speed pipeline analog-to-digital converter of claim 1, wherein, Each pipeline processing unit further comprises a unit-gain voltage buffer configured to transmit the residual difference signal or the differential signal to a sampling circuit of a next stage pipeline processing unit, wherein the unit-gain voltage buffer comprises a first MOS transistor and a second MOS transistor, a gate of the first MOS transistor is configured to receive the residual difference signal or the differential signal, a drain of the first MOS transistor is configured to receive a power supply voltage, and a source of the first MOS transistor is connected to a drain of the second MOS transistor, a gate of the second MOS transistor is configured to receive a bias voltage, and a source of the second MOS transistor is grounded, The first MOS transistor is configured to be biased in a saturation region, and a source of the first MOS transistor and a drain of the second MOS transistor are configured as an output terminal of the unit-gain voltage buffer for outputting a residual error signal or a differential signal after buffering.

5. The high-speed pipeline analog-to-digital converter of claim 4, wherein, The unit gain voltage buffer satisfies a first condition: V DD ≤ V GS + V th , where V DD represents the power supply voltage, V GS represents the gate-source voltage of the first MOS transistor, and V th represents the on threshold voltage of the first MOS transistor. The pipeline processing units are configured to periodically perform pipeline operations under a target clock signal, the target clock signal being set in a form of periodically alternating between a first phase and a second phase, and in a case that the unit-gain voltage buffers in the pipeline processing units all satisfy the first condition, the pipeline processing units are configured to: In each first phase, the 2nth pipeline processing unit performs a differential sampling operation, and the 2n-1th pipeline processing unit performs a residual error transfer operation, where n is a positive integer. In each second phase, the 2nth pipeline processing unit performs a residual error transfer operation, and the 2n-1th pipeline processing unit performs a differential sampling operation.

6. The high-speed pipeline analog-to-digital converter of claim 1, wherein, The first-stage pipeline processing unit comprises a first access switch, a second access switch, a first ground switch, a second ground switch, a first common-mode switch, a second common-mode switch, a first capacitor, a second capacitor, a first unit-gain voltage buffer and a second unit-gain voltage buffer, and a quantizer. The first end of the first access switch and the first end of the second access switch are configured to receive a positive signal and a negative signal of the differential analog input signal, respectively. The second end of the first access switch is connected to the first end of the first capacitor, the input terminal of the first unit-gain voltage buffer, and the first input terminal of the quantizer of the first-stage pipeline processing unit. The second end of the second access switch is connected to the first end of the second capacitor, the input terminal of the second unit-gain voltage buffer, and the second input terminal of the quantizer of the first-stage pipeline processing unit. The second end of the first capacitor is grounded through the first ground switch and accesses the common-mode reference voltage through the first common-mode switch. The second end of the second capacitor is grounded through the second ground switch and accesses the common-mode reference voltage through the second common-mode switch.

7. The high-speed pipeline analog-to-digital converter of claim 6, wherein, The first access switch, the second access switch, the first ground switch, and the second ground switch are turned on in a first phase of a clock cycle, the first common-mode switch and the second common-mode switch are turned on in a second phase of the clock cycle, and the quantizer of the first-stage pipeline processing unit is enabled in the second phase of the clock cycle.

8. The high-speed pipeline analog-to-digital converter of any of claims 1-6, wherein, Each pipeline processing unit other than the first-stage pipeline processing unit comprises: a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a first sampling capacitor, a second sampling capacitor, a third unit-gain voltage buffer and a fourth unit-gain voltage buffer, and a quantizer. The first end of the first switch and the first end of the second switch are configured to receive a positive signal and a negative signal of a differential signal or a residual error signal output by a previous-stage pipeline processing unit, respectively. The second end of the first switch is connected to the first end of the first sampling capacitor, the input terminal of the third unit-gain voltage buffer, and the first input terminal of the quantizer of the pipeline processing unit. a second end of the first switch is connected to a first end of the first sampling capacitor, an input end of the third unit gain voltage buffer, a first input end of a quantizer of the pipeline processing unit, a second end of the second switch is connected to a first end of the second sampling capacitor, an input end of the fourth unit gain voltage buffer, a second input end of the quantizer of the pipeline processing unit, a second end of the first sampling capacitor receives a negative signal of a differential signal or a residual signal output by a previous stage pipeline processing unit through the third switch and accesses a positive reference voltage or a negative reference voltage through the fifth switch, a second end of the second sampling capacitor receives a positive signal of the differential signal or the residual signal output by the previous stage pipeline processing unit through the fourth switch and accesses the negative reference voltage or the positive reference voltage through the sixth switch, wherein, if a quantization result output by the previous stage is a high level signal, the second end of the first sampling capacitor accesses the negative reference voltage and the second end of the second sampling capacitor accesses the positive reference voltage; otherwise, if the quantization result output by the previous stage is a low level signal, the second end of the first sampling capacitor accesses the positive reference voltage and the second end of the second sampling capacitor accesses the negative reference voltage, wherein, a difference between the positive reference voltage and the negative reference voltage is a preset reference voltage.

9. The high-speed pipeline analog-to-digital converter of claim 8, wherein, the first switch, the second switch, the third switch and the fourth switch are turned on in a second phase of a clock cycle of the previous stage pipeline processing unit, the fifth switch and the sixth switch are turned on in a first phase of a clock cycle of a next stage pipeline processing unit, and the quantizer of the pipeline processing unit is enabled in the first phase of the clock cycle of the next stage pipeline processing unit.

10. An electronic device, comprising: The electronic device comprises the high speed pipeline analog-to-digital converter as claimed in any one of claims 1-9.

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