Semiconductor structure and preparation method therefor, and processor and electronic device

Abstract

The embodiments of the present application relate to the technical field of semiconductors. Provided are a semiconductor structure and a preparation method therefor, and a processor and an electronic device. The semiconductor structure comprises a memory die and a logic die, which are stacked and bonded. The memory die comprises static random access memories. Each static random access memory comprises a memory structure layer and a memory interconnection layer, wherein the memory interconnection layer is stacked on one side of the memory structure layer, the memory structure layer comprises a memory device, the memory interconnection layer comprises a first interconnection metal, and the memory device is coupled to the first interconnection metal. The memory die further comprises lead-out traces, wherein one end of each lead-out trace is coupled to the corresponding first interconnection metal, and the other end thereof is arranged on the surface of the memory die that is close to the logic die. In this way, there is no need to reserve channels so as to accommodate lead-out traces. In addition, static random access memories have relatively strong driving capability and electrostatic discharge protection capability, such that there is no need to reserve channels to accommodate a buffer and an electrostatic discharge protection device, thereby realizing a channel-free design.

Description

Semiconductor structures and their fabrication methods, processors and electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202411989857.0, filed on December 27, 2024, entitled "Semiconductor Structure and Preparation Method Thereof, Processor and Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] Embodiments of this application provide a semiconductor structure and its fabrication method, a processor, and an electronic device, relating to the field of semiconductor technology. Background Technology

[0003] Semiconductor structures can include memory chips and logic chips. Memory chips include multiple static random access memories (SARMs), which can be set at intervals.

[0004] Typically, the area utilization rate of memory chips is low, which is not conducive to the high integration of semiconductor structures. Summary of the Invention

[0005] The embodiments of this application provide a semiconductor structure and its fabrication method, a processor, and an electronic device, which can improve the area utilization of storage particles and increase the integration of semiconductor structures.

[0006] On one hand, embodiments of this application provide a semiconductor structure. The semiconductor structure includes memory chips and logic chips. The memory chips and logic chips are stacked and bonded. The memory chip includes a static random access memory (SRAM), which includes a memory structure layer and a memory interconnect layer, with the memory interconnect layer stacked on one side of the memory structure layer. The memory structure layer includes a memory device, and the memory interconnect layer includes a first interconnect metal, with the memory device coupled to the first interconnect metal. The memory chip also includes a lead-out trace, one end of which is coupled to the first interconnect metal, and the other end of which is disposed on the surface of the memory chip near the logic chip.

[0007] In embodiments of this application, the lead-out trace is coupled to a first interconnect metal, enabling the lead-out trace to be coupled to the memory device via the first interconnect metal. One end of the lead-out trace away from the first interconnect metal is disposed on the surface of the memory chip near the logic chip (the first surface), allowing this end of the lead-out trace to be coupled to the logic chip.

[0008] Understandably, positioning the end of the lead-out trace furthest from the first interconnect metal on the surface of the memory chip closest to the logic chip allows the lead-out trace to couple with the logic chip without needing to be wound. This reduces the space occupied by the lead-out trace in the XY plane (the plane intersecting the stacking direction Z of the memory and logic chips). Therefore, during the physical design (PD) stage, there is no need to reserve a channel between two adjacent static random access memories (SRAMs) to accommodate the lead-out trace, achieving a channelless design. This reduces the distance between two adjacent SRAMs, improves the area utilization of the memory chips, and thus increases the integration density of the semiconductor structure. Furthermore, it allows for a larger number of SRAMs to be placed on the memory chips, which is beneficial for improving processor performance.

[0009] Furthermore, by adopting the above configuration method, while reducing the distance between two adjacent static random access memories (SRAMs), the distance between the lead-out traces coupled to the two adjacent SRAMs will not be too small, thus meeting the routing design requirements (design rule).

[0010] In some possible implementations, the lead-out traces extend parallel to the stack-up direction of the memory and logic chips. This arrangement reduces the space occupied by the lead-out traces in the XY plane, which helps to reduce the distance between two adjacent static random access memories (SRAMs), improves the area utilization of the memory chips, and thus increases the integration density of the semiconductor structure.

[0011] In some possible implementations, the first interconnect metal comprises multiple metal layers. These multiple metal layers include a first metal layer and a second metal layer, with the first metal layer closer to the logic chip than the second metal layer. Lead-out traces are coupled to the first metal layer. This configuration shortens the length of the lead-out traces and improves the ease with which the lead-out traces couple the first metal layer to the logic chip.

[0012] In some possible implementations, the first interconnect metal includes a first output port. The static random access memory (SRAM) includes a first output device coupled between the first output port and the memory device. The first output device includes a first fin field-effect transistor (FET). The number of fins of the first fin field-effect transistor is greater than or equal to 10 and less than or equal to 40. Understandably, the more fins the fin field-effect transistor has, the stronger its driving capability. Setting the number of fins of the first fin field-effect transistor to be greater than or equal to 10 can improve its driving capability, meet driving capability requirements, improve the output signal strength of the SRAM, improve signal integrity, and enable the SRAM to drive logic particles. Compared to adding buffers (such as repeaters or inverters) during the automatic place and route (APR) stage to enhance signal strength, increasing the number of fins in the first fin field-effect transistor (FFET) to increase signal strength eliminates the need for pre-reserved channels to accommodate the buffers during the physical design phase. This achieves a channelless design, which helps reduce the distance between two adjacent static random access memories (SRAMs), improves the area utilization of the memory chips, and thus increases the integration density of the semiconductor structure. Setting the number of fins in the first fin field-effect transistor to less than or equal to 40 reduces its size, facilitating its miniaturization.

[0013] In some possible implementations, the first interconnect metal includes a first input port. The static random access memory (SRAM) also includes a bypass cell coupled to the first input port. The bypass cell is turned on when its input voltage exceeds a set voltage threshold; and / or, when its input current exceeds a set current threshold. Understandably, the bypass cell can be connected in parallel with the memory device. The bypass cell being turned on when its input voltage exceeds a set voltage threshold; and / or when its input current exceeds a set current threshold, reduces the risk of damage to the memory device, enabling the SRAM to have electrostatic discharge (ESD) protection capabilities, meeting ESD requirements without requiring additional protection during the physical design phase. In other words, by including a bypass module in the SRAM, no channel needs to be reserved during the physical design phase to accommodate other bypass devices, achieving a channelless design. This facilitates reducing the distance between two adjacent SRAMs, improving the area utilization of the memory chips, and thus increasing the integration density of the semiconductor structure.

[0014] In some possible implementations, the bypass unit includes a bypass device and a bypass trace. The bypass device is disposed in the memory structure layer, and the bypass trace is disposed in the memory interconnect layer. The bypass device and the bypass trace are coupled together. This configuration allows the bypass device to be coupled to the first input port via the bypass trace, improving the ease of coupling the bypass unit to the first input port.

[0015] In some possible implementations, the traces include input traces and output traces. The input traces are coupled to the first input port, and the output traces are coupled to the first output port. This configuration allows the first input port and the first output port to be coupled to the logic chip via traces, and reduces the space occupied by the input and output traces in the XY plane. This helps to reduce the distance between two adjacent static random access memories, improves the area utilization of the memory chip, and thus improves the integration density of the semiconductor structure.

[0016] In some possible implementations, the logic granules include standard cells, and lead-out traces are coupled to the standard cells. The orthographic projection of the lead-out traces onto the logic granules falls within the area of ​​the standard cells. This arrangement allows the placement of the lead-out traces to correspond to the placement of the standard cells, reducing the space occupied by the lead-out traces in the XY plane, thereby reducing the distance between two adjacent static random access memories (SRAMs), improving the area utilization of the memory granules, and thus increasing the integration density of the semiconductor structure.

[0017] In some possible implementations, multiple static random access memories (SRAMs) are used, spaced apart. The distance between any two adjacent SRAMs is less than 2 micrometers. This arrangement improves the area utilization of the memory chips, thereby increasing the integration density of the semiconductor structure. Furthermore, it allows for a greater number of SRAMs to be placed on the memory chips, which is beneficial for improving processor performance.

[0018] In some possible implementations, the semiconductor structure also includes a bonding layer. This bonding layer is stacked between the memory chips and the logic chips, with the memory and logic chips being co-bonded through the bonding layer. Understandably, enabling co-bonding of the memory and logic chips allows for three-dimensional integration, improving the integration density of the semiconductor structure and facilitating miniaturization. Furthermore, it improves the efficiency of data transmission between the memory and logic chips, meaning higher performance can be achieved in a smaller space, meeting the needs of high-performance computing, smartphones, and other fields.

[0019] On the other hand, embodiments of this application provide a method for fabricating a semiconductor structure. The method includes: forming lead traces. One end of the lead trace is coupled to a first interconnect metal of a memory chip, and the first interconnect metal is coupled to a memory device of the memory chip. The other end of the lead trace is disposed on a first surface of the memory chip. The memory chip is then bonded to a logic chip. The first surface is the surface of the memory chip adjacent to the logic chip.

[0020] Understandably, the lead-out trace is coupled to the first interconnect metal, enabling the lead-out trace to be coupled to the memory device through the first interconnect metal. The end of the lead-out trace away from the first interconnect metal is disposed on a first surface, which is the surface of the memory chip close to the logic chip, so that the end of the lead-out trace away from the first interconnect metal can be coupled to the logic chip.

[0021] By positioning the lead-out trace away from the first interconnect metal at the surface of the memory chip closest to the logic chip (the first surface), the lead-out trace can be coupled to the logic chip without winding, reducing the space occupied by the lead-out trace in the XY plane (the plane intersecting the stacking direction of the memory chip and the logic chip). Therefore, during the physical design phase, there is no need to reserve a channel between two adjacent static random access memories (SRAMs) to accommodate the lead-out trace, achieving a channelless design. This reduces the distance between two adjacent SRAMs, improves the area utilization of the memory chip, and thus increases the integration density of the semiconductor structure. Furthermore, it allows for the placement of a larger number of SRAMs on the memory chip, which is beneficial for improving processor performance.

[0022] Furthermore, by adopting the above configuration method, while reducing the distance between two adjacent static random access memories (SRAMs), the distance between the lead-out traces coupled to the two adjacent SRAMs will not be too small, thus meeting the trace design requirements.

[0023] In some possible implementations, forming a lead-out trace includes: creating a via on a first surface, the via exposing other interconnect metals of the storage chip, the other interconnect metals being located on the side of the first interconnect metal closer to the logic chip and coupled to the interconnect metal. A lead-out trace is formed within the via. This configuration allows one end of the lead-out trace to be coupled to the first interconnect metal via the other interconnect metals, while the other end can be located on the first surface.

[0024] In another aspect, embodiments of this application provide a processor. The processor includes a package structure and a semiconductor structure as described above, wherein the package structure packages the semiconductor structure.

[0025] The processor provided in the embodiments of this application includes the semiconductor structure described above, and therefore has all the aforementioned beneficial effects, which will not be repeated here.

[0026] In another aspect, embodiments of this application provide an electronic device. The electronic device includes a circuit board and a processor as described above, the processor being disposed on one side of the circuit board and coupled to the circuit board.

[0027] The electronic device provided in the embodiments of this application includes the processor as described above, and therefore has all the beneficial effects described above, which will not be repeated here. Attached Figure Description

[0028] Figure 1 is a schematic diagram of the structure of an electronic device provided in some embodiments of this application;

[0029] Figure 2 is a cross-sectional view of Figure 1 along the A1-A1 direction in some embodiments;

[0030] Figure 3 is a schematic diagram showing the positional relationship between the processor and the circuit board provided in some embodiments of this application;

[0031] Figure 4 is a top view of the storage particles provided in some embodiments of this application;

[0032] Figure 5 is a cross-sectional view along the A2-A2 direction in some embodiments of Figure 4;

[0033] Figure 6 shows a schematic diagram of the positional relationship between two static random access memories in some possible scenarios;

[0034] Figure 7 is a cross-sectional view along the A2-A2 direction in some embodiments of Figure 4;

[0035] Figure 8 is a cross-sectional view along the A3-A3 direction in some embodiments of Figure 4;

[0036] Figure 9 is a schematic diagram showing the positional relationship of two static random access memories provided in some embodiments of this application;

[0037] Figure 10 is a schematic diagram of the semiconductor structure provided in some embodiments of this application;

[0038] Figure 11 is a flowchart of the steps of a method for fabricating a semiconductor structure provided in some embodiments of this application;

[0039] Figure 12 is a flowchart of the steps of a method for fabricating a semiconductor structure provided in some other embodiments of this application;

[0040] Figure 13 is a schematic diagram of the structure of the connecting hole provided in some embodiments of this application. Detailed Implementation

[0041] The technical solutions in some embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application are within the scope of protection of this application.

[0042] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiment," "example," "specific example," or "some examples" are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this application. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific feature, structure, material, or characteristic may be included in any suitable manner in any one or more embodiments or examples.

[0043] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, "a plurality of" means two or more.

[0044] In describing some embodiments, the term "coupled" and its derivative expressions may be used. The term "coupled" refers to direct or indirect electrical contact between two or more components.

[0045] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0046] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0047] As used herein, “vertical” includes the situation described and situations similar to the situation described, within an acceptable range of deviation, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “vertical” includes absolute verticality and approximate verticality, where an acceptable range of deviation for approximate verticality could be, for example, within 5°.

[0048] Figure 1 is a structural schematic diagram of an electronic device provided in some embodiments of this application. Figure 2 is a cross-sectional schematic diagram along the A1-A1 direction in some embodiments of Figure 1. As shown in Figures 1 and 2, embodiments of this application provide an electronic device 300. The electronic device 300 can be a mobile phone, tablet computer, personal computer (PC), in-vehicle device (e.g., vehicle computer), smart wearable device (e.g., smartwatch, smart bracelet), virtual reality (VR) device, augmented reality (AR) device, network base station, high-performance server, etc. Embodiments of this application do not further limit the type of electronic device 300.

[0049] The electronic device 300 may include a housing 301, which encloses a receiving space. The electronic device 300 may also include a processor 200, a circuit board 303, and a battery (not shown). The processor 200, circuit board 303, and battery may be located within the receiving space enclosed by the housing 301, and the housing 301 provides protection for the processor 200, circuit board 303, and battery.

[0050] Taking an electronic device 300 as a mobile phone or tablet computer as an example, as shown in Figure 2, the housing 301 may include a middle frame 3011 and a back cover 3012. The middle frame 3011 may include a middle plate 3013 and a frame 3014, with the frame 3014 surrounding and connected to the middle plate 3013. The frame 3014 and the middle plate 3013 can enclose one or more cavities, where the processor 200, circuit board 303, and battery can be disposed. The back cover 3012 is located on one side of the frame 3014 and connected to the frame 3014.

[0051] Referring again to Figures 1 and 2, the electronic device 300 may further include a display screen 302. For example, the display screen 302 may be a liquid crystal display (LCD), an organic light-emitting diode (OLED) display, an active matrix organic light-emitting diode (AMOLED) display, a flexible light-emitting diode (FLED) display, a sub-millimeter light-emitting diode (Mini LED) display, a micro light-emitting diode (Micro LED) display, a quantum dot light-emitting diode (QLED) display, etc. The embodiments of this application do not further limit the specific form of the display screen 302. The display screen 302 may be disposed on the side of the frame 3014 away from the rear housing 3012 and connected to the frame 3014.

[0052] Understandably, the opening of the cavity enclosed by the bezel 3014 and the middle plate 3013 can face either the rear shell 3012 or the display screen 302. When the opening of the cavity enclosed by the bezel 3014 and the middle plate 3013 faces the rear shell 3012, as shown in Figure 2, the rear shell 3012 can close the opening of the cavity enclosed by the bezel 3014 and the middle plate 3013. When the opening of the cavity enclosed by the bezel 3014 and the middle plate 3013 faces the display screen 302, the display screen 302 can close the opening of the cavity enclosed by the bezel 3014 and the middle plate 3013.

[0053] When multiple receiving cavities are enclosed by the frame 3014 and the middle plate 3013, the opening orientations of the multiple receiving cavities may be the same or different, and the embodiments of this application do not further limit this.

[0054] Referring to Figure 2, in some examples, the processor 200 is disposed on one side of the circuit board 303 and coupled to the circuit board 303.

[0055] For example, processor 200 can be at least one of a central processing unit (CPU), a graphics processing unit (GPU), a system-on-chip (SOC), a charge integrated circuit (charge IC), and a radio frequency (RF) chip. The embodiments of this application do not further limit the specific form of processor 200.

[0056] Circuit board 303 can be at least one of a printed circuit board (PCB), a flexible printed circuit board (FPC), and a flexible printed circuit board (FPCB). Circuit board 303 can be a motherboard, or it can be another type of circuit board besides a motherboard, such as a sub-board or a power management board.

[0057] Figure 3 is a schematic diagram showing the positional relationship between the processor and the circuit board provided in some embodiments of this application. It is understood that in some of the accompanying drawings of the embodiments of this application, taking Figure 3 as an example, the thickness of some components (or films) in the semiconductor structure 100 is enlarged to clearly show the semiconductor structure 100. This does not represent a relationship between the actual thickness of these components (or films) and the thickness of other components (e.g., circuit board 303), nor does it represent a relationship between the actual thicknesses of different components (or films).

[0058] In some examples, as shown in Figure 3, processor 200 may include package structure 201 and semiconductor structure 100, with package structure 201 encapsulating semiconductor structure 100.

[0059] As shown in Figure 3, for example, package structure 201 may include package substrate 2011 and second pin 2012. Package substrate 2011 may be a printed circuit board or a silicon bridge. Semiconductor structure 100 may include a first pin 102, which is coupled to package substrate 2011. For example, first pin 102 may be a metal ball.

[0060] The second pin 2012 is located on the side of the package substrate 2011 away from the semiconductor structure 100, and the package substrate 2011 is coupled to the circuit board 303 through the second pin 2012. For example, the second pin 2012 can be a metal ball. Understandably, the shape and number of the first pin 102 can be the same as or different from the shape and number of the second pin 2012.

[0061] Referring again to Figure 3, the packaging structure 201 may further include a shielding cover 2013. The shielding cover 2013 covers the semiconductor structure 100 and is connected to the packaging substrate 2011. The shielding cover 2013 may be made of metal and serves as electromagnetic shielding.

[0062] Understandably, the package structure 201 may also include other components. The embodiments of this application do not further limit the package structure 201; the semiconductor structure 100 is illustrated below.

[0063] Referring again to Figure 3, in some examples, the semiconductor structure 100 may include a memory die (SRAM die) 110 and a logic die 120. The memory die 110 and the logic die 120 are stacked and bonded together.

[0064] Understandably, the storage chip 110 and the logic chip 120 are stacked, that is, the storage chip 110 and the logic chip 120 can be stacked vertically (stacked along the thickness direction) to achieve three-dimensional integration, improve the integration of the semiconductor structure 100, and facilitate the miniaturization of the semiconductor structure 100.

[0065] Furthermore, the bonding of storage chip 110 and logic chip 120 enables high-density interconnection between dies, improving the efficiency of storage chip 110 driving logic chip 120 and the efficiency of logic chip 120 accessing storage chip 110, achieving higher performance in a smaller space, and meeting the needs of high-performance computing, smartphones and other fields.

[0066] For example, logic particle 120 may include standard cell 1201 (see Figure 10). The storage particle 110 and logic particle 120 are stacked, so that no storage structure needs to be set on logic particle 120, which can increase the area ratio of standard cell 1201 on logic particle 120.

[0067] In some examples, as shown in FIG3, the semiconductor structure 100 may further include a bonding layer 101, which is stacked between the memory chip 110 and the logic chip 120, and the memory chip 110 and the logic chip 120 are hybrid bonded (HB) through the bonding layer 101.

[0068] The bonding layer 101 may include a bonding medium and a bonding metal, with the bonding metal embedded within the bonding medium. The bonding metal may be made of materials such as copper, silver, aluminum, or gold. The bonding medium may include an insulating material, such as silicon oxide, silicon nitride, or one or more combinations of other high-dielectric-constant insulating materials, serving as electrical isolation. The memory chip 110 and the logic chip 120 are respectively coupled to the bonding metal, enabling the memory chip 110 and the logic chip 120 to be co-bonded through the bonding layer 101.

[0069] In other examples, the memory chip 110 and the logic chip 120 may also be bonded by other means, such as adhesive bonding, anodic bonding, direct wafer bonding and metal bonding. The embodiments of this application do not further limit the bonding method between the memory chip 110 and the logic chip 120.

[0070] In some examples, as shown in Figure 3, the memory chip 110 is closer to the package substrate 2011 relative to the logic chip 120. In this case, the first pin 102 is located on the side of the memory chip 110 away from the logic chip 120. In other examples, the memory chip 110 may also be further away from the package substrate 2011 relative to the logic chip 120. In this case, the first pin 102 is located on the side of the logic chip 120 away from the memory chip 110.

[0071] Figure 4 is a top view of a storage particle provided in some embodiments of this application. In some examples, as shown in Figure 4, the storage particle 110 may include a static random access memory (SRAM) 130. Understandably, the static random access memory 130 is capable of storing data and has advantages such as fast access speed, low latency, and high stability.

[0072] In some examples, as shown in Figure 4, the number of static random access memories 130 can be multiple to increase the storage capacity of the memory chip 110. The multiple static random access memories 130 can be spaced apart; for example, the multiple static random access memories 130 can be arranged in an array. In some examples, the memory chip 110 can be referred to as an SRAM die, and the semiconductor structure 100 can be referred to as Logic on SRAM.

[0073] Figure 5 is a cross-sectional view along the A2-A2 direction in some embodiments of Figure 4. It is understood that, in the accompanying drawings of the embodiments of this application, Figure 5 is used as an example; to simplify the structure of the drawings, Figure 5 only shows a static random access memory 130 and other structural layers 140 disposed on one side of the static random access memory 130.

[0074] In some examples, as shown in FIG5, the static random access memory 130 may include a memory structure layer 131 and a memory interconnect layer 132, with the memory interconnect layer 132 stacked on one side of the memory structure layer 131.

[0075] Understandably, the memory interconnect layer 132 may be closer to the logic particle 120 than the memory structure layer 131, and the memory interconnect layer 132 is used to couple the memory structure layer 131 and the logic particle 120.

[0076] Referring again to Figure 5, in some examples, the storage structure layer 131 may include a storage device 1311 and a storage medium 1312, with the storage device 1311 embedded within the storage medium 1312.

[0077] Understandably, the storage device 1311 is capable of storing data. The storage device 1311 can be a transistor, or it can be a capacitor. There can be multiple storage devices 1311, which can be spaced apart within the storage medium 1312. The embodiments of this application do not further limit the number, specific form, or placement of the storage devices 1311 within the storage medium 1312.

[0078] It is understood that in the accompanying drawings of the embodiments of this application, taking FIG5 as an example, only one storage device 1311 is shown in order to simplify the structure of the drawings, and the number of storage devices 1311 is not limited.

[0079] The storage medium 1312 may include an insulating material, such as silicon oxide, silicon nitride, and one or more combinations of high dielectric constant insulating materials, to provide electrical isolation.

[0080] Referring again to Figure 5, in some examples, the storage interconnect layer 132 may include a first interconnect metal 1321 and a first interconnect medium 1322, with the first interconnect metal 1321 embedded within the first interconnect medium 1322.

[0081] The first interconnect medium 1322 and the storage medium 1312 can be stacked. The first interconnect metal 1321 may include a metal layer 13211 and metal traces 13212. There can be multiple metal layers 13211, and multiple metal layers 13211 can be stacked. The metal traces 13212 are coupled to different metal layers 13211.

[0082] For example, the number of metal layers 13211 can be two, three, four, or more. The embodiments of this application do not further limit the number of metal layers 13211. In the accompanying drawings of the embodiments of this application, Figure 5 is used as an example to illustrate only one possible coupling method between metal layers 13211 and metal traces 13212, and does not further limit the coupling method between metal layers 13211 and metal traces 13212.

[0083] The material of the first interconnect metal 1321 may include copper, silver, aluminum, or gold. The materials of the metal layer 13211 and the metal trace 13212 may be the same or different. The first interconnect dielectric 1322 may include an insulating material, such as silicon oxide, silicon nitride, and one or more combinations of high dielectric constant insulating materials, serving as electrical isolation. The materials of the first interconnect dielectric 1322 and the storage dielectric 1312 may be the same or different.

[0084] The storage device 1311 is coupled to the first interconnect metal 1321, so that multiple storage devices 1311 can be interconnected through the first interconnect metal 1321, thereby enabling the static random access memory 130 to perform storage functions.

[0085] Figure 6 is a schematic diagram of the positional relationship between two static random access memories (SRAMs) under some possible conditions. In some possible cases, as shown in Figure 6, a via Q can be formed on the sidewall P2 of the SRAM 130 (the sidewall P2 intersects with the surface of the memory chip 110 near the logic chip 120), and the via Q exposes the first interconnect metal 1321.

[0086] A trace M is formed within the via Q, enabling the trace M to be coupled to the metal layer 13211. The trace M extends beyond the via Q, bypassing the static random access memory 130 and coupling to the logic chip 120. A channel is reserved between two adjacent static random access memories 130 to accommodate the trace M.

[0087] The above configuration increases the distance between two adjacent static random access memories 130, affecting the area utilization of the storage chip 110, reducing the integration density of the semiconductor structure 100, and hindering the miniaturization of the semiconductor structure 100.

[0088] Figure 7 is a cross-sectional view along the A2-A2 direction in some embodiments of Figure 4. Figure 8 is a cross-sectional view along the A3-A3 direction in some embodiments of Figure 4. Based on this, in the embodiments of this application, as shown in Figures 7 and 8, the storage chip 110 further includes a lead-out trace 1101, one end of which is coupled to the first interconnect metal 1321, and the other end of which is disposed on the surface of the storage chip 110 near the logic chip 120 (first surface P1).

[0089] For example, lead-out trace 1101 can be referred to as an SRAM pin. One end of lead-out trace 1101 may be coupled to at least one of metal layer 13211 and metal trace 13212. The end of lead-out trace 1101 away from the first interconnect metal 1321 may be exposed on the surface of memory chip 110 near logic chip 120 (first surface P1).

[0090] For example, the end of the lead-out trace 1101 away from the first interconnect metal 1321 can be flush with the surface of the memory chip 110 near the logic chip 120, or the end of the lead-out trace 1101 away from the first interconnect metal 1321 can protrude from the surface of the memory chip 110 near the logic chip 120. Understandably, the material of the lead-out trace 1101 can include copper, silver, aluminum, or gold, etc. The material of the lead-out trace 1101 can be the same as or different from the material of the first interconnect metal 1321.

[0091] The surface of the memory chip 110 near the logic chip 120 can be the surface of the memory interconnect layer 132 away from the memory structure layer 131. Alternatively, as shown in Figures 7 and 8, the memory chip 110 may also include other structural layers 140, which are stacked on the side of the memory interconnect layer 132 away from the memory structure layer 131. For example, the other structural layer 140 can be a power network structure layer or a signal line structure layer. The embodiments of this application do not further limit the type of the other structural layer 140.

[0092] Other structural layers 140 may include other interconnect metals 1401 and a second interconnect dielectric 1402, with the other interconnect metals 1401 embedded within the second interconnect dielectric 1402. The material of the other interconnect metals 1401 may include copper, silver, aluminum, or gold, etc. The second interconnect dielectric 1402 may include an insulating material, such as one or more combinations of silicon oxide, silicon nitride, and high dielectric constant insulating materials, serving as electrical isolation.

[0093] For example, other interconnect metals 1401 can be coupled to the first interconnect metal 1321, and the lead trace 1101 can be coupled to the first interconnect metal 1321 through other interconnect metals 1401.

[0094] When the storage particle 110 includes other structural layers 140, as shown in Figures 7 and 8, the surface of the storage particle 110 near the logic particle 120 can be the surface of the other structural layers 140 away from the storage interconnect layer 132. The embodiments of this application use the storage particle 110 including other structural layers 140 as an example for further illustration.

[0095] Understandably, the lead-out trace 1101 is coupled to the first interconnect metal 1321, enabling the lead-out trace 1101 to be coupled to the memory device 1311 via the first interconnect metal 1321. For example, one memory device 1311 may be coupled to one lead-out trace 1101, or one memory device 1311 may be coupled to two, three, or more lead-out traces 1101. One end of the lead-out trace 1101, away from the first interconnect metal 1321, is disposed on the surface of the memory chip 110 near the logic chip 120, allowing this end to be coupled to the bonding layer 101, thereby enabling coupling to the logic chip 120 via the bonding layer 101.

[0096] In some examples, as shown in Figures 7 and 8, the lead-out trace 1101 is embedded in the second interconnect medium 1402, and one end of the lead-out trace 1101 is coupled to the first interconnect metal 1321, while the other end is flush with the surface of the memory chip 110 near the logic chip 120 (first surface P1).

[0097] Figure 9 is a schematic diagram showing the positional relationship of two static random access memories provided in some embodiments of this application. It is understood that Figure 9 shows the connecting hole Q and the connecting hole 1101 respectively in order to clearly show the extension direction of the lead-out trace 1101, and does not mean that the lead-out trace 1101 is disposed outside the connecting hole Q.

[0098] For example, as shown in Figure 9, a via Q can be formed on the surface of the storage chip 110 near the logic chip 120 (first surface P1). The via Q penetrates a portion of the second interconnect medium 1402 to expose other interconnect metals 1401 (refer to Figure 13). A lead-out trace 1101 is formed within the via Q, such that one end of the lead-out trace 1101 can be coupled to the first interconnect metal 1321 through other interconnect metals 1401, and the other end can be disposed on the surface of the storage chip 110 near the logic chip 120.

[0099] Compared to placing the via Q on the sidewall P2 of the static random access memory 130, the embodiment of this application allows the end of the lead-out trace 1101 away from the first interconnect metal 1321 to be disposed on the surface of the memory chip 110 near the logic chip 120, eliminating the need for winding and reducing the space occupied by the lead-out trace 1101 in the XY plane (the XY plane is the plane intersecting the stacking direction Z of the memory chip 110 and the logic chip 120). For example, the XY plane can be perpendicular or approximately perpendicular to the stacking direction Z of the memory chip 110 and the logic chip 120.

[0100] In this way, during the physical design (PD) stage, there is no need to reserve a channel between two adjacent static random access memories (SRAMs) 130 to accommodate the lead-out traces 1101, enabling a channelless design. This reduces the distance between two adjacent SRAMs 130, improves the area utilization of the memory chips 110, and thus increases the integration density of the semiconductor structure 100. Furthermore, a greater number of SRAMs 130 can be placed on the memory chips 110, which is beneficial for improving the performance of the processor 200.

[0101] Furthermore, by adopting the above configuration, while reducing the distance between two adjacent static random access memories 130, the distance between the lead-out traces 1101 coupled to the two adjacent static random access memories 130 will not be too small, thus meeting the routing design requirements (design rule).

[0102] In some examples, as shown in Figures 7 and 8, the extension direction of the lead-out trace 1101 is parallel to the stack-up direction Z of the memory chip 110 and the logic chip 120. Understandably, the extension direction of the lead-out trace 1101 can be parallel or approximately parallel to the stack-up direction Z of the memory chip 110 and the logic chip 120.

[0103] The XY plane intersects the stacking direction Z of memory chips 110 and logic chips 120. The extension direction of the lead-out trace 1101 can be parallel or approximately parallel to the stacking direction Z of memory chips 110 and logic chips 120, so that the extension direction of the lead-out trace 1101 can intersect the XY plane. For example, the extension direction of the lead-out trace 1101 can be perpendicular or approximately perpendicular to the XY plane.

[0104] Setting the extension direction of the lead-out trace 1101 to be parallel to the stacking direction Z of the memory chip 110 and the logic chip 120 can reduce the space occupied by the lead-out trace 1101 in the XY plane, which is beneficial to reduce the distance between two adjacent static random access memories 130, improve the area utilization of the memory chip 110, and thus improve the integration density of the semiconductor structure 100.

[0105] In some examples, as shown in Figures 7 and 8, multiple metal layers 13211 include a first metal layer 13211a and a second metal layer 13211b, with the first metal layer 13211a closer to the logic chip 120 relative to the second metal layer 13211b. A lead-out trace 1101 is coupled to the first metal layer 13211a.

[0106] Understandably, there can be one or more second metal layers 13211b, and the first metal layer 13211a is closer to the logic chip 120 relative to any one of the second metal layers 13211b. For example, the first metal layer 13211a can be the metal layer 13211 closest to the logic chip 120 among multiple metal layers 13211. Connecting the lead-out trace 1101 to the first metal layer 13211a can shorten the length of the lead-out trace 1101 and improve the ease with which the lead-out trace couples the first metal layer 13211a and the logic chip 120.

[0107] Figure 10 is a schematic diagram of a semiconductor structure provided in some embodiments of this application. As shown in Figure 10, in some examples, the first interconnect metal 1321 includes a first input port 130a and a first output port 130b. For example, the first input port 130a may be a portion of the first interconnect metal 1321 coupled to the input terminal of the memory device 1311. The first output port 130b may be a portion of the first interconnect metal 1321 coupled to the output terminal of the memory device 1311.

[0108] The lead-out trace 1101 includes an input lead-out trace 1101a and an output lead-out trace 1101b. The input lead-out trace 1101a is coupled to the first input port 130a, and the output lead-out trace 1101b is coupled to the first output port 130b, so that the first input port 130a and the first output port 130b can be coupled to the logic chip 120 through the lead-out trace 1101, respectively. Furthermore, this reduces the space occupied by the input lead-out trace 1101a and the output lead-out trace 1101b in the XY plane, which helps to reduce the distance between two adjacent static random access memories 130, improves the area utilization of the memory chip 110, and thus improves the integration density of the semiconductor structure 100.

[0109] In some examples, as shown in Figure 10, the logic granule 120 includes a standard cell 1201, with a lead-out trace 1101 coupled to the standard cell 1201.

[0110] As shown in Figure 10, for example, logic particle 120 may include a stacked logic structure layer 121 and a logic interconnect layer 122. Logic structure layer 121 may include standard cells 1201 and logic media 1212, with standard cells 1201 embedded within logic media 1212. Standard cells 1201 may be the core region of logic particle 120, and may include one or more logic gates. Logic media 1212 may include an insulating material, such as silicon oxide, silicon nitride, and one or more combinations of high dielectric constant insulating materials, serving as electrical isolation.

[0111] The logic interconnect layer 122 may be located close to the memory chip 110 relative to the logic structure layer 121. The logic interconnect layer 122 may include a logic interconnect metal 1221 and a third interconnect medium 1222. The logic interconnect metal 1221 is embedded within the third interconnect medium 1222. The material of the logic interconnect metal 1221 may include copper, silver, aluminum, or gold, etc. The third interconnect medium 1222 may include an insulating material, such as silicon oxide, silicon nitride, and one or more combinations of high dielectric constant insulating materials, serving as electrical isolation.

[0112] Understandably, the logical interconnect layer 122 and the storage interconnect layer 132 are coupled to the bonding layer 101, respectively.

[0113] Referring again to Figure 10, in some examples, the orthographic projection of the lead-out trace 1101 onto the logic chip 120 falls within the range of the standard cell 1201.

[0114] Understandably, the lead-out trace 1101 is coupled to the standard cell 1201, enabling the standard cell 1201 to write data into the static random access memory 130 and to read data from the static random access memory 130.

[0115] The orthographic projection of the lead-out trace 1101 onto the logic chip 120 falls within the range of the standard cell 1201, so that the setting position of the lead-out trace 1101 corresponds to the setting position of the standard cell 1201, reducing the space occupied by the lead-out trace 1101 in the XY plane, thereby reducing the distance between two adjacent static random access memories 130, improving the area utilization of the memory chip 110, and thus improving the integration density of the semiconductor structure 100.

[0116] In some examples, as shown in FIG10, the static random access memory 130 further includes a first output device 1313 coupled between the first output port 130b and the memory device 1311.

[0117] For example, the first output device 1313 can be embedded within the storage medium 1312, and the first output device 1313 can be coupled to the output terminal of the storage device 1311 via the first interconnect metal 1321. Furthermore, the first output device 1313 is coupled to the first output port 130b. There can be multiple first output devices 1313, and these multiple first output devices 1313 can be interconnected via the first interconnect metal 1321.

[0118] Understandably, the first output device 1313 is used to output the data stored in the storage device 1311. The stronger the driving capability of the first output device 1313, the greater the signal strength and the higher the signal integrity of the static random access memory 130. Conversely, the weaker the driving capability of the first output device 1313, the weaker the signal strength and the lower the signal integrity of the static random access memory 130.

[0119] The first output device 1313 includes a first fin field-effect transistor (Fin Fet, not shown in the figure). The number of fins of the first fin field-effect transistor is greater than or equal to 10 and less than or equal to 40.

[0120] Understandably, the more fins a finned transistor has, the stronger its driving capability. Setting the number of fins of the first finned transistor to be greater than or equal to 10 can improve its driving capability, meet the driving capability requirements, increase the output signal strength of the static random access memory 130, improve signal integrity, and enable the static random access memory 130 to drive the logic chip 120.

[0121] Compared to adding buffers (such as repeaters or inverters) during the automatic place and route (APR) stage to enhance signal strength, increasing the number of fins of the first fin field-effect transistor to increase signal strength eliminates the need to reserve channels to accommodate the buffers during the physical design (PD) stage, achieving a channelless design. This helps reduce the distance between two adjacent static random access memories 130, improves the area utilization of the memory chips 110, and thus increases the integration density of the semiconductor structure 100.

[0122] Setting the number of fins of the first fin field-effect transistor to less than or equal to 40 can reduce the size of the first fin field-effect transistor and facilitate its miniaturization.

[0123] In other examples, the driving capability of the first fin field-effect transistor can also be increased by increasing the fin area of ​​the first fin field-effect transistor.

[0124] Referring again to Figure 10, in some examples, the static random access memory 130 further includes a bypass unit 133 coupled to the first input port 130a. The bypass unit 133 is turned on when the input voltage of the bypass unit 133 is greater than a set voltage threshold; and / or, the bypass unit 133 is turned on when the input current of the bypass unit 133 is greater than a set current threshold.

[0125] Understandably, the bypass unit 133 can be connected in parallel with the storage device 1311. The bypass unit 133 is turned on when the input voltage of the bypass unit 133 exceeds a set voltage threshold; and / or, the bypass unit 133 is turned on when the input current of the bypass unit 133 exceeds a set current threshold, reducing the risk of damage to the storage device 1311 and enabling the static random access memory 130 to have electrostatic discharge (ESD) protection capabilities, meeting ESD requirements without requiring additional protection during the physical design phase.

[0126] In other words, by including bypass units 133 in the static random access memory 130, there is no need to reserve channels to accommodate other bypass devices during the physical design stage, thus achieving a channelless design. This helps to reduce the distance between two adjacent static random access memories 130, improves the area utilization of the storage particles 110, and thereby improves the integration of the semiconductor structure 100.

[0127] For example, when the bypass unit 133 is turned on, the input terminal of the bypass unit 133 can be coupled to the ground terminal, or when the bypass unit 133 is turned on, the input terminal of the bypass unit 133 can also be coupled to the power supply terminal.

[0128] Understandably, the embodiments of this application do not further limit the values ​​of the set voltage threshold and the set current threshold. In some examples, the bypass unit 133 may be referred to as a CDM cell (charged device model cell).

[0129] In some examples, bypass unit 133 includes bypass device 1331 and bypass trace 1332, with bypass device 1331 disposed in memory structure layer 131 and bypass trace 1332 disposed in memory interconnect layer 132. For example, bypass device 1331 may be embedded in memory medium 1312 and bypass trace 1332 may be embedded in first interconnect medium 1322.

[0130] Bypass trace 1332 and first interconnect metal 1321 can be on the same layer and made of the same material. Understandably, "on the same layer" refers to a layer structure formed using the same film deposition process to create a specific pattern, and then using the same photomask through a single patterning process. Depending on the specific pattern, the same patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the formed layer structure can be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses.

[0131] Bypass device 1331 and bypass trace 1332 are coupled together. This configuration allows bypass device 1331 to be coupled to the first input port 130a via bypass trace 1332, improving the ease of coupling bypass unit 133 to the first input port 130a.

[0132] For example, the bypass device 1331 may include a switching transistor, such as a bipolar transistor or a metal-oxide-semiconductor field-effect transistor (MOSFET). The bypass unit 133 is turned on when the input voltage of the bypass unit 133 is greater than a set voltage threshold; and / or, the bypass device 1331 is turned on when the input current of the bypass unit 133 is greater than a set current threshold, enabling the static random access memory 130 to have electrostatic discharge protection capability.

[0133] In the embodiments of this application, the end of the lead-out trace 1101 away from the first interconnect metal 1321 is disposed on the surface of the storage particle 110 away from the logic particle 120 (first surface P1), so that the lead-out trace 1101 can be coupled to the logic particle 120 without winding, reducing the space occupied by the lead-out trace 1101 in the XY plane (the XY plane is the plane that intersects with the stacking direction Z of the storage particle 110 and the logic particle 120), thereby eliminating the need to reserve a channel between two adjacent static random access memories 130 to accommodate the lead-out trace.

[0134] Furthermore, the first output device 1313 has a strong driving capability, meeting the driving capability requirements, thus eliminating the need to reserve a channel between two adjacent static random access memories 130 to accommodate a buffer device. In addition, the static random access memories 130 are capable of electrostatic discharge protection, meeting ESD requirements, thus eliminating the need to reserve a channel between two adjacent static random access memories 130 to accommodate a bypass device.

[0135] In other words, the embodiments of this application can realize a channelless design, and multiple static random access memories 130 can be arranged closely. The distance between two adjacent static random access memories 130 only needs to meet the design requirements. There is no need to reserve channel space for the lead-out traces 1101, buffer devices and protection devices, which improves the integration of the semiconductor structure 100.

[0136] In some examples, the distance between any two adjacent static random access memories 130 is less than 2 micrometers (μm).

[0137] This configuration improves the area utilization of the storage chip 110, thereby increasing the integration density of the semiconductor structure 100. Furthermore, it allows for the placement of a larger number of static random access memories (SRAMs) 130 on the storage chip 110, which helps improve the performance of the processor 200.

[0138] For example, the distance between any two adjacent static random access memories 130 can be 0.5 μm, 1 μm, or 1.5 μm, etc. The embodiments of this application do not further limit the value of the distance between any two adjacent static random access memories 130.

[0139] Referring again to FIG10, in some examples, logic 120 includes a second output device 1202 and a second output port (not shown in the figure), the second output device 1202 being coupled between the second output port and the standard cell 1201.

[0140] Understandably, standard cell 1201 can access memory chip 110 through second output device 1202. The stronger the driving capability of second output device 1202, the stronger the signal strength and the higher the signal integrity of static random access memory 130. Conversely, the weaker the driving capability of second output device 1202, the weaker the signal strength and the lower the signal integrity of static random access memory 130.

[0141] The second output device 1202 includes a second fin field-effect transistor (not shown in the figure), and the number of fins of the second fin field-effect transistor is greater than or equal to 10 and less than or equal to 40.

[0142] Understandably, the more fins a finned transistor has, the stronger its driving capability. Setting the number of fins of the second finned transistor to be greater than or equal to 10 can improve its driving capability, meet the driving capability requirements, increase the output signal strength of the logic chip 120, improve signal integrity, and enable the logic chip 120 to access the memory chip 110.

[0143] Setting the number of fins of the second fin field-effect transistor to less than or equal to 40 can reduce the size of the second fin field-effect transistor and facilitate its miniaturization.

[0144] In other examples, the driving capability of the second fin field-effect transistor can also be increased by increasing the fin area of ​​the second fin field-effect transistor.

[0145] On the other hand, embodiments of this application provide a method for fabricating a semiconductor structure. This method can be used to fabricate the aforementioned semiconductor structure, and therefore possesses all the aforementioned beneficial effects, which will not be elaborated further here.

[0146] Figure 11 is a flowchart of the steps of a method for fabricating a semiconductor structure provided in some embodiments of this application.

[0147] For example, as shown in Figure 11, the method for fabricating a semiconductor structure includes:

[0148] Step S101: Forming a lead-out trace. One end of the lead-out trace is coupled to the first interconnect metal of the memory chip, and the first interconnect metal is coupled to the memory device of the memory chip. The other end of the lead-out trace is disposed on the first surface of the memory chip.

[0149] Step S102: Bond the memory chip to the logic chip. The first surface is the surface of the memory chip adjacent to the logic chip.

[0150] Understandably, the lead-out trace 1101 is coupled to the first interconnect metal 1321, enabling the lead-out trace 1101 to be coupled to the memory device 1311 via the first interconnect metal 1321. One end of the lead-out trace 1101 away from the first interconnect metal 1321 is disposed on a first surface P1, which is the surface of the memory chip 110 near the logic chip 120. This allows the end of the lead-out trace 1101 away from the first interconnect metal 1321 to be coupled to the bonding layer 101, thereby enabling coupling to the logic chip 120 via the bonding layer 101.

[0151] The lead-out trace 1101 is positioned at one end away from the first interconnect metal 1321 on the surface of the memory chip 110 near the logic chip 120 (first surface P1). This allows the lead-out trace 1101 to be coupled to the logic chip 120 without winding, reducing the space occupied by the lead-out trace 1101 in the XY plane (the XY plane is the plane intersecting the stacking direction Z of the memory chip 110 and the logic chip 120). Therefore, during the physical design (PD) stage, there is no need to reserve a channel between two adjacent static random access memories (SRAMs) 130 to accommodate the lead-out trace 1101, achieving a channelless design. This reduces the distance between two adjacent SRAMs 130, improves the area utilization of the memory chip 110, and thus increases the integration density of the semiconductor structure 100. Furthermore, a larger number of SRAMs 130 can be placed on the memory chip 110, which is beneficial for improving the performance of the processor 200.

[0152] Furthermore, by adopting the above configuration, while reducing the distance between two adjacent static random access memories 130, the distance between the lead-out traces 1101 coupled to the two adjacent static random access memories 130 will not be too small, thus meeting the routing design requirements (design rule).

[0153] Figure 12 is a flowchart illustrating the steps of a method for fabricating a semiconductor structure according to other embodiments of this application. In some examples, as shown in Figure 12, forming lead traces includes:

[0154] Step S1011: A connecting hole is opened on the first surface, exposing other interconnect metals of the storage particle. The other interconnect metals are located on the side of the first interconnect metal close to the logic particle and are coupled to the interconnect metal.

[0155] Step S1012: Form an outgoing trace inside the connecting hole.

[0156] This configuration allows one end of the lead-out trace 1101 to be coupled to the first interconnect metal 1321 via other interconnect metals 1401, while the other end can be disposed on the first surface P1.

[0157] Figure 13 is a schematic diagram of the structure of a connecting hole provided in some embodiments of this application. For example, as shown in Figure 13, a first connecting hole Q1 and a second connecting hole Q2 can be formed on the first surface P1, with the first connecting hole Q1 exposing other interconnecting metals 1401.

[0158] An input lead-out trace 1101a is formed within the first connecting hole Q1, enabling the first lead-out trace 1101a to be coupled to the first input port 130a via other interconnect metal 1401. An output lead-out trace 1101b is formed within the second connecting hole Q2, enabling the second lead-out trace 1101b to be coupled to the first output port 130b via other interconnect metal 1401.

[0159] In summary, the embodiments of this application have at least the following beneficial effects:

[0160] In the embodiments of this application, the lead-out trace 1101 is coupled to the first interconnect metal 1321, so that the lead-out trace 1101 can be coupled to the memory device 1311 through the first interconnect metal 1321. One end of the lead-out trace 1101 away from the first interconnect metal 1321 is disposed on the surface of the memory chip 110 near the logic chip 120 (first surface P1), so that the end of the lead-out trace 1101 away from the first interconnect metal 1321 can be coupled to the bonding layer 101, thereby enabling coupling to the logic chip 120 through the bonding layer 101.

[0161] Understandably, by positioning the end of the lead-out trace 1101 furthest from the first interconnect metal 1321 on the surface of the memory chip 110 near the logic chip 120, the lead-out trace 1101 can be coupled to the logic chip 120 without winding, reducing the space occupied by the lead-out trace 1101 in the XY plane (the XY plane is the plane intersecting the stacking direction Z of the memory chip 110 and the logic chip 120). Therefore, during the physical design (PD) stage, it is unnecessary to reserve a channel between two adjacent static random access memories (SRAMs) 130 to accommodate the lead-out trace 1101, achieving a channelless design. This reduces the distance between two adjacent SRAMs 130, improves the area utilization of the memory chip 110, and thus increases the integration density of the semiconductor structure 100. Furthermore, it allows for the placement of a larger number of SRAMs 130 on the memory chip 110, which is beneficial for improving the performance of the processor 200.

[0162] Furthermore, by adopting the above configuration, while reducing the distance between two adjacent static random access memories 130, the distance between the lead-out traces 1101 coupled to the two adjacent static random access memories 130 will not be too small, thus meeting the routing design requirements (design rule).

[0163] Understandably, the first output device 1313 has a strong driving capability, thus eliminating the need for an additional buffer between two adjacent static random access memories (SRAMs) 130 to increase signal strength, which helps to reduce the distance between the two adjacent SRAMs 130. Furthermore, the SRAMs 130 are equipped with electrostatic discharge protection, eliminating the need for additional protection devices between the two adjacent SRAMs 130, further reducing the distance between them.

[0164] That is, in the embodiments of this application, multiple static random access memories 130 can be arranged closely, and the distance between two adjacent static random access memories 130 only needs to meet the design requirements. There is no need to reserve channel space for the lead-out traces 1101, buffer devices and protection devices, which improves the integration of the semiconductor structure 100.

[0165] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor structure, characterized by, It includes storage particles and logic particles; the storage particles and the logic particles are stacked and bonded together; The storage particle includes a static random access memory (SRAM), which includes a storage structure layer and a storage interconnect layer. The storage interconnect layer is stacked on one side of the storage structure layer. The storage structure layer includes a storage device, and the storage interconnect layer includes a first interconnect metal. The storage device is coupled to the first interconnect metal. The storage chip also includes a lead-out trace, one end of which is coupled to the first interconnect metal, and the other end of which is disposed on the surface of the storage chip near the logic chip.

2. The semiconductor structure of claim 1, wherein, The extension direction of the lead-out trace is parallel to the stacking direction of the memory chip and the logic chip.

3. The semiconductor structure according to claim 1 or 2, characterized in that The first interconnect metal includes multiple metal layers; the multiple metal layers include a first metal layer and a second metal layer, the first metal layer being closer to the logic particle than the second metal layer; the lead-out trace is coupled to the first metal layer.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that, The first interconnect metal includes a first output port; the static random access memory includes a first output device, which is coupled between the first output port and the memory device; The first output device includes a first fin field-effect transistor; the number of fins of the first fin field-effect transistor is greater than or equal to 10 and less than or equal to 40.

5. The semiconductor structure according to claim 4, characterized in that, The first interconnect metal includes a first input port; the static random access memory further includes a bypass unit, which is coupled to the first input port; When the input voltage of the bypass unit is greater than a set voltage threshold, the bypass unit is turned on. And / or, the bypass unit is turned on when the input current of the bypass unit is greater than a set current threshold.

6. The semiconductor structure according to claim 5, characterized in that, The bypass unit includes a bypass device and a bypass trace. The bypass device is disposed in the memory structure layer, and the bypass trace is disposed in the memory interconnect layer. The bypass device and the bypass trace are coupled together.

7. The semiconductor structure according to any one of claims 5 to 6, characterized in that, The lead-out traces include input lead-out traces and output lead-out traces; the input lead-out traces are coupled to the first input port, and the output lead-out traces are coupled to the first output port.

8. The semiconductor structure according to any one of claims 1 to 7, characterized in that, The logic particle includes a standard cell, and the lead-out trace is coupled to the standard cell; the orthographic projection of the lead-out trace on the logic particle falls within the range of the standard cell.

9. The semiconductor structure according to any one of claims 1 to 8, characterized in that, The number of static random access memories is multiple, and the multiple static random access memories are spaced apart; the distance between any two adjacent static random access memories is less than 2 micrometers.

10. The semiconductor structure according to any one of claims 1 to 9, characterized in that, It also includes a bonding layer; the bonding layer is stacked between the storage particle and the logic particle, and the storage particle and the logic particle are mixed-bonded through the bonding layer.

11. A method for fabricating a semiconductor structure, characterized in that, include: Form the lead-out routing; One end of the lead-out trace is coupled to the first interconnect metal of the storage particle, and the first interconnect metal is coupled to the storage device of the storage particle; the other end of the lead-out trace is disposed on the first surface of the storage particle. The storage particle is bonded to the logic particle; wherein the first surface is the surface of the storage particle adjacent to the logic particle.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that, Forming the aforementioned lead-out trace includes: A connecting hole is formed on the first surface, the connecting hole exposing other interconnect metals of the storage particle, the other interconnect metals being located on the side of the first interconnect metal close to the logic particle and coupled to the interconnect metal; The lead-out trace is formed within the connecting hole.

13. A processor, characterized in that, include: Packaging structure; The semiconductor structure as described in any one of claims 1 to 10, wherein the packaging structure encapsulates the semiconductor structure.

14. An electronic device, characterized in that, include: Circuit board; The processor as described in claim 13 is disposed on one side of the circuit board and coupled to the circuit board.

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