Register addressing method, instruction processing apparatus, target processor, system on chip, and computing device

Abstract

Provided in the embodiments of the present disclosure are a register addressing method, an instruction processing apparatus, a target processor, a system on chip, and a computing device. The register addressing method is applied to a target processor, and comprises: acquiring a register addressing instruction for a target register in a target processor, wherein a register bit width of the target processor and an operation data bit width of same are different, and the register addressing instruction comprises operands of the register bit width; on the basis of the operation data bit width, determining a target operand from the operands of the register bit width; and on the basis of the target operand, executing an addressing operation on the target register. Relax-extend addressing is implemented, and operand extension is implemented without the need to add additional software instructions, thereby reducing the number of software instructions, and improving the speed and efficiency of register addressing; and the complexity of a compiler and a runtime system is simplified, thereby improving the data processing efficiency and overall performance of a target processor and improving the addressing efficiency.

Description

Register addressing methods, instruction processing units, target processors, systems-on-a-chip and computing devices

[0001] This disclosure claims priority to Chinese Patent Application No. 202411932006.2, filed with the China Patent Office on December 25, 2024, entitled “Register Addressing Method, Instruction Processing Apparatus, Target Processor, System-on-Chip and Computing Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the technical field of microprocessors, and particularly to a register addressing method, instruction processing apparatus, target processor, system-on-a-chip, and computing device. Background Technology

[0003] With the development of microprocessor technology, in order to support the needs of different application scenarios, the register bit width (generally the register bit width of general-purpose registers, i.e., GPR length) and the operation data bit width of processors have gradually diversified. For example, 64 (64-bit instruction architecture, i.e., register bit width is 64 bits) lp32 (integer, long and pointer size, the operation data width for integer, long data and pointer types is 32 bits) allows the use of 64-bit registers for efficient operation compared to 32 lp32 and 64 lp64, but still maintains a 32-bit width for integer, long data and pointer type operation data. This can save memory and bandwidth in applications that do not require a full 64-bit address space, while taking advantage of the 64-bit register to accelerate computation.

[0004] Currently, when the register bit width and the operation data bit width of the processor are different, when a register addressing instruction is executed, the operation data retrieved from memory or register needs to be processed according to the operation data bit width and recorded in the target register. This requires operation bit expansion, such as sign expansion or zero expansion.

[0005] However, such bit expansion requires additional software instructions to implement these expansion operations, increasing the number of software instructions, introducing additional overhead for data processing in the target processor, reducing the performance of the target processor, and reducing register addressing efficiency. Summary of the Invention

[0006] In view of this, embodiments of this disclosure provide a register addressing method. One or more embodiments of this disclosure also relate to an instruction processing apparatus, a target processor, a system-on-a-chip, a computing device, a computer-readable storage medium, and a computer program product, to address the technical deficiencies existing in the prior art.

[0007] According to a first aspect of the present disclosure, a register addressing method is provided, applied to a target processor, comprising:

[0008] Retrieve register addressing instructions for target registers in the target processor, where the register bit width and the operation data bit width of the target processor are different, and the register addressing instructions include the operation bits of the register bit width;

[0009] The target operation bit is determined from the operation bits of the register bit width based on the operation data bit width;

[0010] Based on the target operation bits, an addressing operation is performed on the target register.

[0011] According to a second aspect of the present disclosure, an instruction processing apparatus is provided, comprising:

[0012] The instruction fetching module is configured to fetch register addressing instructions for a target register in the target processor, wherein the register bit width and the operation data bit width of the target processor are different, and the register addressing instructions include the operation bits of the register bit width;

[0013] The operation bit determination module is configured to determine the target operation bit from the operation bits of the register bit width based on the operation data bit width.

[0014] The addressing module is configured to perform addressing operations on the target register based on the target operation bits.

[0015] According to a third aspect of the present disclosure, a target processor is provided, the target processor including a target register and an instruction processing means, wherein the register bit width and the operation data bit width of the target processor are different;

[0016] An instruction processing unit is configured to acquire a register addressing instruction for a target register, determine the target operation bit from the operation bits of the register bit width based on the operation data bit width, and perform an addressing operation on the target register based on the target operation bit, wherein the register addressing instruction includes the operation bits of the register bit width.

[0017] According to a fourth aspect of the embodiments of this disclosure, a system-on-a-chip is provided, comprising:

[0018] The control unit and multiple on-chip components, including the target processor;

[0019] The control unit is used to control and manage multiple on-chip components, and the target processor is used to execute computer programs / instructions that implement the steps of the above method when executed by the target processor.

[0020] According to a fifth aspect of the present disclosure, a computing device is provided, comprising:

[0021] Memory and system-on-a-chip;

[0022] The memory is used to store computer programs / instructions, and the system on-chip is used to execute the computer programs / instructions, which, when executed by the system on-chip, implement the steps of the above method.

[0023] According to a sixth aspect of the present disclosure, a computer-readable storage medium is provided that stores a computer program / instructions that, when executed by a processor, implement the steps of the above-described method.

[0024] According to a seventh aspect of the present disclosure, a computer program product is provided, including a computer program / instructions that, when executed by a processor, implement the steps of the above-described method.

[0025] One embodiment of this disclosure provides a register addressing method applied to a target processor, comprising: obtaining a register addressing instruction for a target register in the target processor, wherein the register bit width and the operation data bit width of the target processor are different, and the register addressing instruction includes operation bits of the register bit width; determining a target operation bit from the operation bits of the register bit width based on the operation data bit width; and performing an addressing operation on the target register based on the target operation bit.

[0026] By employing hardware assistance, the appropriate operands are automatically selected and used for addressing. When the register bit width and operand data bit width of the target processor differ, the target operand is determined directly from the operands of the register bit width based on the operand data bit width. This ignores operands other than the target operand in the register bit width, achieving relaxed extended addressing. No additional software instructions are needed to expand the operand size, thereby reducing the number of software instructions and avoiding the additional overhead caused by operations such as sign extension or zero extension. This directly improves the speed and efficiency of register addressing, simplifies the complexity of the compiler and runtime system, enhances the data processing efficiency and overall performance of the target processor, and improves addressing efficiency. Attached Figure Description

[0027] Figure 1 is a flowchart of a register addressing method provided in an embodiment of this disclosure;

[0028] Figure 2 is a flowchart of a register addressing method for a reduced instruction set architecture processor provided in an embodiment of this disclosure;

[0029] Figure 3 is a schematic diagram of the structure of an instruction processing device provided in an embodiment of the present disclosure;

[0030] Figure 4 is a structural block diagram of a target processor provided in an embodiment of the present disclosure;

[0031] Figure 5 is a structural block diagram of a system-on-a-chip provided in an embodiment of this disclosure;

[0032] Figure 6 is a structural block diagram of a computing device provided in an embodiment of this disclosure. Detailed Implementation

[0033] Numerous specific details are set forth in the following description to provide a full understanding of this disclosure. However, this disclosure can be implemented in many other ways than those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this disclosure. Therefore, this disclosure is not limited to the specific implementations disclosed below.

[0034] The terminology used in one or more embodiments of this disclosure is for the purpose of describing particular embodiments only and is not intended to be limiting of the one or more embodiments of this disclosure. The singular forms “a,” “the,” and “the” as used in one or more embodiments of this disclosure and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in one or more embodiments of this disclosure refers to and includes any or all possible combinations of one or more associated listed items.

[0035] It should be understood that although the terms first, second, etc., may be used to describe various information in one or more embodiments of this disclosure, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from one another. For example, first may also be referred to as second without departing from the scope of one or more embodiments of this disclosure, and similarly, second may also be referred to as first. Depending on the context, the word “if” as used herein may be interpreted as “when”, “in response to a determination”, or “when…”.

[0036] Furthermore, it should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in one or more embodiments of this disclosure are all information and data authorized by the user or fully authorized by all parties. Moreover, the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and corresponding operation entry points are provided for users to choose to authorize or refuse.

[0037] First, the terms and concepts involved in one or more embodiments of this disclosure will be explained.

[0038] Sign extension: A technique used to extend narrower data types (such as 32-bit integers) to wider register widths (such as 64-bit registers). During sign extension, the most significant bit (sign bit) of the data is copied to the newly added high-order bits to preserve the original sign. For example, when a 32-bit signed integer is extended to 64 bits, if the integer is negative, its most significant bit is 1, and the sign extension fills all 32 newly added high-order bits with 1s; if it is positive, it is filled with 0s. This method ensures that the value retains its original sign and value in the extended register.

[0039] Zero extension: A method for extending narrower data types to wider register widths, particularly suitable for unsigned data or addresses. During zero extension, the system adds zeros to the high-order bits of the data without altering the low-order bits. For example, when a 32-bit unsigned integer is extended to a 64-bit register, zero extension fills all 32 newly added high-order bits with 0s. This method ensures that the value remains unchanged after extension, without altering its sign.

[0040] Relaxation extension is a hardware-assisted addressing optimization technique designed to address the mismatch between register bit width and operand bit width. Traditional sign extension or zero extension methods require additional software instructions to expand the operand size, increasing instruction count and processing overhead. Relaxation extension, however, automatically selects and uses appropriate operand bits for addressing at the hardware level, directly determining the target operand from the operand size of the register, ignoring redundant high-order bits, thus avoiding the extra instructions required for sign extension or zero extension. This approach not only reduces the number of software instructions and simplifies the complexity of the compiler and runtime system but also significantly improves the speed and efficiency of register addressing. Through relaxation extension, the target processor can efficiently execute instructions in applications that do not require a full high-width address space, improving data processing efficiency and overall performance while ensuring system flexibility and efficiency across various application scenarios.

[0041] Reduced Instruction Set Computing (RISC): A processor architecture design philosophy that emphasizes using a smaller number of simple instructions to build a processor in order to improve the processor's execution efficiency and speed.

[0042] Reduced Instruction Set Computing (RISC) Processor: A processor designed based on the RISC concept, characterized by a shorter instruction pipeline, fixed instruction format, and simple addressing modes, enabling high-speed processing.

[0043] Complex Instruction Set Computing (CISC): A processor architecture design philosophy that emphasizes the use of a large number of complex instructions to build the processor in order to improve the processor's functionality and flexibility.

[0044] Complex Instruction Set Processor (CISC Processor): A processor designed based on the CISC concept, characterized by having a large number of complex instructions, each of which can perform multiple operations.

[0045] User-mode (U-mode) is a low-level privilege mode in the processor architecture, primarily used for running application code. In this mode, code cannot directly access hardware resources or execute privileged instructions, ensuring system security and stability. U-mode has limited permissions, allowing access only to the memory regions allocated to it and the non-privileged instruction set. U-mode enables ordinary applications to run in a protected environment while maintaining isolation from higher privilege levels, guaranteeing overall system security and performance.

[0046] Supervised Operational Privilege Mode (S-mode): A higher-level privilege mode in processor architecture, typically used by the operating system kernel or Virtual Machine Monitor (VMM). In S-mode, code has higher privileges than in user mode, allowing it to manage processes in user mode and access more hardware features. S-mode allows the operating system kernel to perform critical tasks such as memory management and interrupt handling while maintaining secure isolation from user-mode code. S-mode improves system flexibility and security, enabling the operating system to manage resources more effectively and maintain stable system operation.

[0047] Virtual User-Mode (VU-mode): A special user mode in processor architecture designed specifically for virtualization environments. It allows the virtual machine manager to emulate a user-mode environment for guest operating systems, enabling multiple virtual machines to run independently on the same physical hardware. VU-mode provides similar permissions and functionality to user mode, but all operations are performed within the virtualization context.

[0048] Virtual Supervised Operation Permission Mode (VS-mode): A special supervisory mode under processor architecture, designed specifically for virtualization environments. It allows the virtual machine manager to simulate a supervised mode environment for guest operating systems, thereby supporting the independent operation of multiple virtual machines on the same physical hardware. VS-mode provides permissions and functionality close to a real supervised mode, but all operations are performed within the virtualization context, ensuring isolation and security between virtual machines.

[0049] Register width (XLEN): A key parameter in the RISC-V architecture, representing the processor's integer register width and the maximum address width supported by the Basic Instruction Set Architecture (ISA). It defines the bit width of registers and data paths, determining the size of data the processor can process and the range of its address space. Common XLEN values ​​in the RISC-V specification include 32-bit, 64-bit, and 128-bit. For example, when XLEN is set to 64, it means the processor has 64-bit wide general-purpose registers and can directly address a 64-bit address space. The choice of XLEN affects system performance, power consumption, and application support capabilities. By flexibly configuring XLEN, RISC-V processors can find a balance in different application scenarios, meeting the needs of high-performance computing as well as adapting to resource-constrained environments such as embedded systems.

[0050] The Application Binary Interface (ABI) is a set of rules and conventions governing interaction between programs or between a program and the operating system. It specifies how function calls are made, the layout of data types, the use of registers, and the stack frame structure. In the RISC-V architecture, the ABI determines how the compiled binary code interacts with hardware and other software components, ensuring that code generated by different compilers can run correctly on the same platform. RISC-V supports several ABI variants, such as ILP32 and LP64, which optimize memory usage and performance based on different XLEN configurations. For example, ILP32 indicates that integers, long integers, and pointers are all 32-bit, maintaining a 32-bit data width even on 64-bit architectures to save memory bandwidth and reduce storage requirements; while LP64 indicates that long integers and pointers are 64-bit, suitable for applications requiring larger address spaces. By standardizing the ABI, the RISC-V ecosystem ensures cross-platform and cross-toolchain compatibility, facilitating software development and portability.

[0051] RV32: RISC-V 32-bit instruction set architecture, XLEN=32.

[0052] RV64: RISC-V 64-bit instruction set architecture, XLEN=64.

[0053] RV128: RISC-V 128-bit instruction set architecture, XLEN=128.

[0054] LP64: The data width for integer operations is 32 bits, while the data width for long integers and pointers is 64 bits.

[0055] ILP32: The data width for integer, long integer, and pointer operations is 32 bits.

[0056] This disclosure provides a register addressing method, and also relates to an instruction processing apparatus, a target processor, a system-on-a-chip, a computing device, a computer-readable storage medium, and a computer program product, which will be described in detail in the following embodiments.

[0057] Referring to Figure 1, Figure 1 shows a flowchart of a register addressing method provided in an embodiment of this disclosure. The method is applied to a target processor and includes the following specific steps:

[0058] Step 102: Obtain the register addressing instruction for the target register in the target processor. The register bit width and the operation data bit width of the target processor are different. The register addressing instruction includes the operation bits of the register bit width.

[0059] The target processor is a microprocessor or central processing unit (CPU) used for register addressing. The target processor supports various register width and operand data width configurations and can execute various types of instruction sets. The target processor can be a Reduced Instruction Set Computing (RISC) processor or a Complex Instruction Set Computing (CISC) processor; this is not limited here. The register width (XLEN) and operand data width (ABI) of the target processor differ. Taking RISC processors as examples, for instance, RV64ILP32 runs ILP32 ABI on a RISC-V 64-bit instruction architecture; RV128ILP32 runs ILP32 ABI on a RISC-V 128-bit instruction architecture; and RV128LP64 runs LP64 ABI on a RISC-V 128-bit instruction architecture.

[0060] Registers are small, high-speed storage units within the processor, used to temporarily store data and address information required during instruction execution. Registers are directly connected to the processor's data path, providing extremely fast access speeds and are key components for efficient instruction execution. They include, but are not limited to, various types such as general-purpose registers, status registers, and control registers, each with specific functions and uses. For example, in a 64-bit RISC-V processor, each general-purpose register can hold 64 bits of data, used to store operands, intermediate results, or address values ​​to accelerate arithmetic and logic operations and memory access.

[0061] The destination register is the register specified in the register addressing instruction, used to store the result of an operation or participate in the operation. When the target processor executes a register addressing instruction, it selects one or more destination registers to store the calculation result or as the operation source according to the encoding in the register addressing instruction. For example, a load instruction specifies register x10 as the destination register and stores the data read from memory into this register, while a store instruction specifies register x11 as the source register and writes its contents into memory.

[0062] Register addressing instructions determine the location of operands or the location where results are stored by using a target register. In one optional embodiment of this disclosure, register addressing instructions include at least one of indirect jump instructions, return instructions, load instructions, store instructions, and atomic memory operation instructions.

[0063] Register addressing instructions use the destination register to quickly access data, reducing the frequency of memory access and improving instruction execution speed. For example, the load instruction "LW x10, 0(x11)" loads 32-bit data from the memory location pointed to by address x11 into the destination register x10; the store instruction "SW x10, 0(x11)" stores the contents of the destination register x10 into the memory address specified by x11.

[0064] Indirect jump instructions are control instructions that determine the address of the next instruction to be executed based on the value in the destination register. Unlike direct jump instructions, the destination address of an indirect jump instruction is not explicitly specified in the instruction itself, but is dynamically determined through the destination register. This allows the program to flexibly change the execution path and is often used to implement advanced programming features such as function pointer calls and virtual method calls. For example, in the RISC-V architecture, JALR (Jump And Link Register) is an indirect jump instruction that can use the value in the register as the destination address for a jump.

[0065] JALR x1, 0(x5) # Use the value in register x5 as the jump target address and store the return address in x1.

[0066] A return instruction is a control instruction used to return from a subroutine or function call to the calling point based on the value in the destination register, resuming the previous execution flow. The return instruction typically reads the return address from the destination register and sets the program counter (PC) to that address, thus restoring the caller's execution environment. This is the foundation for implementing function call and return mechanisms. For example, in the RISC-V architecture, RET (Return) uses the return address stored in the link register (usually the x1 or ra register) to return:

[0067] RET# is equivalent to jalr x0, 0(x1), which means reading the return address from the x1 register and returning.

[0068] Load instructions are control instructions used to read data from memory into a target register. A type of memory access instruction (LOAD / READ), load instructions are responsible for loading data stored in memory into the target processor's target register for subsequent computation or processing. Different load instructions can read data of different sizes (such as bytes, half-words, words, etc.) as needed, and can choose whether to perform sign extension or zero extension on the data. For example, in the RISC-V architecture, the LW (Load Word) instruction is used to load 32-bit data into a register.

[0069] LW x10, 0(x8) # Load 32-bit data from the memory address pointed to by register x8 into register x10.

[0070] A store instruction is a control instruction used to write data from a destination register into memory. It is a type of memory access instruction (LOAD / READ) responsible for writing data from a destination register back to a specified location in memory. For example, in the RISC-V architecture, the SW (Store Word) instruction is used to store 32-bit data from a register into memory.

[0071] SW x10, 0(x8)# Stores the 32-bit data in register x10 to the memory address pointed to by register x8.

[0072] Atomic memory operations (AMOs) are used to perform atomic read-modify-write operations, ensuring that no race conditions occur when operating on shared memory in a multi-threaded or multi-processor environment. AMOs guarantee that even in a concurrent environment, operations on the same memory location by multiple threads or processors are sequential and indivisible. Common AMO operations include atomic swaps, atomic additions, and minimum / maximum value comparisons. For example, in the RISC-V architecture, the AMOSWAP.W instruction performs a 32-bit wide atomic swap operation.

[0073] AMOSWAP.W x10, x11, (x8)# Atomically swaps the 32-bit data in register x11 with the data at the memory location pointed to by register x8, and stores the result in x10.

[0074] The register bit width of the target processor is the maximum address width supported by the target processor's instruction set architecture (ISA). It defines the bit width of registers and data paths, determining the size of data that the target processor can process and the range of its address space. For example, in an RV64ILP32 configuration, the target processor has a 64-bit register bit width, meaning that each general-purpose register can hold 64 bits of data and can directly address a 64-bit address space.

[0075] The operand data width of a target processor is the actual width of data processed by the processor when executing register-addressed instructions; it is less than or equal to the register width. The operand data width determines the amount of data processed in each operation, affecting memory usage, bandwidth requirements, and computational efficiency. Operand data widths are typically defined by the Application Binary Interface (ABI), such as ILP32 and LP64. Different operand data widths are suitable for different types of programs and application scenarios. Narrower operand data widths can save memory and bandwidth in resource-constrained environments, while wider operand data widths provide a larger address space and support for a wider range of values. For example, in an RV64ILP32 configuration, the target processor has a 64-bit register width, but for long integer and pointer-type operand data, it still maintains a 32-bit operand data width, thus saving memory bandwidth and reducing storage requirements in applications that do not require a full 64-bit address space.

[0076] The operand bits of the register addressing instruction are the operand data recorded in the register addressing instruction, used to perform addressing operations on the target register. Since the format of the register addressing instruction is determined by the register width of the target processor, the operand bits of the register addressing instruction are also determined by the register width. For example, the operand recorded in the register addressing instruction for a register width (64 bits) is "0 (x8)".

[0077] To obtain the register addressing instruction for the target register in the target processor, one option is to directly read the register addressing instruction for the target register in the target processor from memory, and another option is to generate the register addressing instruction for the target register in the target processor through the compiler. This is not limited here.

[0078] For example, on a certain RV64ILP32 processor, the register width is 64 bits, and the application binary interface (operation data width) is 32 bits. This means that although the general-purpose registers can hold 64 bits of data, when executing instructions such as LW (Load Word), the actual width of the data loaded into the registers is 32 bits. A register addressing instruction directly reads from memory targeting the x8 registers in this processor:

[0079] LW x10, 0(x8)

[0080] The register addressing instruction includes operands with a register width (64 bits): "0(x8)" indicates that the x8 register is used as the base address register with an offset of 0, and data is loaded from the address pointed to by x8.

[0081] By obtaining register addressing instructions for the target register in the target processor, data support is provided for subsequent determination of the target operation bits.

[0082] Step 104: Based on the operation data bit width, determine the target operation bit from the operation bits of the register bit width.

[0083] The target operand is the data bit actually processed during the execution of a register-addressed instruction. When the processor's register width is greater than the operand width, the target operand is generally the valid data bit related to the current operation, without needing to consider the higher data bits that exceed the operand width. This avoids unnecessary sign extension or zero-extension operations, reduces the number of software instructions, simplifies the compiler and runtime system complexity, and improves the speed and efficiency of register addressing. For example, when executing the LW x10, 0 (x8) instruction, the target operand refers to the lower 32 bits of the x10 register. These 32 bits will be used to store the 32 bits of data read from the memory address (pointed to by the x8 register). Since the operand width is 32 bits, only these 32 bits need to be considered, and the remaining higher 32 bits of the register do not need to be concerned.

[0084] Based on the operation data bit width, the target operation bit is determined from the operation bits of the register bit width. One possible method is to determine the target operation bit from the operation bits of the register bit width based on the operation data bit width and the operation permission mode. Another possible method is to directly determine the operation bit corresponding to the operation data bit width from the operation bits of the register bit width as the target operation bit. No limitation is made here.

[0085] For example, from the 64-bit operand "0 (x8)", the target operand "the lowest 32 bits of the x10 register" corresponding to the low operand of the 32-bit operand width is directly determined.

[0086] Based on the operation data bit width, the target operation bit is determined from the operation bits of the register bit width, without relying on additional software instructions to determine the target operation bit. The hardware automatically selects the target operation bit that matches the operation data bit width, which simplifies instruction processing and improves the execution efficiency for subsequent addressing operations.

[0087] Step 106: Perform an addressing operation on the target register based on the target operation bits.

[0088] Based on the target operands, addressing operations are performed on the target register. One possible approach is to directly write the data to the target register based on the target operands. Another possible approach is to extend the target operands and write the data to the target register based on the extended target operands. For example, the high 32 bits of the x8 register retain the original value (relaxed extension). Yet another possible approach is to perform conditional addressing based on the operand privilege mode: according to the operand privilege mode, the data is written to the target register based on the target operands. This approach is not limited here.

[0089] For example, the data of the target operation bit (lower 32 bits) is written to the x10 register, while the higher 32 bits of the x10 register remain unchanged or are cleared.

[0090] In this embodiment, hardware-assisted addressing automatically selects and uses appropriate operands. When the register bit width and operand data bit width of the target processor are different, the target operand is determined directly from the operands of the register bit width based on the operand data bit width, ignoring operands other than the target operand in the register bit width. This achieves relaxed extended addressing, eliminating the need for additional software instructions to expand the operand size, thereby reducing the number of software instructions and avoiding the additional overhead caused by operations such as sign extension or zero extension. This directly improves the speed and efficiency of register addressing, simplifies the complexity of the compiler and runtime system, improves the data processing efficiency and overall performance of the target processor, and enhances addressing efficiency.

[0091] In one optional embodiment of this disclosure, the register addressing instruction corresponds to the operation permission mode; step 104 includes the following specific steps:

[0092] The target bit width is determined based on the operation data bit width and operation permission mode;

[0093] From the operands of the register bit width, determine the operands of the target bit width as the target operands.

[0094] Operational privilege modes refer to the different privilege levels a target processor operates at when executing register-addressing instructions. These modes limit the set of instructions that can be executed and the range of resources that can be accessed. Different operational privilege modes ensure system security, stability, and efficiency, while also providing necessary isolation between the operating system and applications. Operational privilege modes include, but are not limited to: user operational privilege mode, supervisory operational privilege mode, virtual user operational privilege mode, and virtual supervisory operational privilege mode.

[0095] The target bit width refers to the effective data width determined during register addressing instruction execution, based on the operand data bit width under the specified access level. It determines the actual size of the data involved in the computation, i.e., the width of the target operands actually processed by the instruction. For example, with an ABI of 32 bits, an access level of user access mode, UXL = 1, a register bit width of 64 bits, and a target bit width of 32 bits. Or, with an ABI of 32 bits, an access level of supervisory access mode, UXL = 2, a register bit width of 128 bits, and a target bit width of 64 bits.

[0096] The target-width operands represent the actual data portion to be processed during register-addressed instruction execution. These target-width operands are a subset selected from the register's operands, representing specific information about the instruction's action. This avoids unnecessary sign extension or zero-extension operations, reduces the number of software instructions, simplifies the complexity of the compiler and runtime system, and improves the speed and efficiency of register addressing. The target-width operands ensure that only necessary data is operated on, maintaining system performance while guaranteeing data processing accuracy.

[0097] The target bit width is determined based on the operation data bit width and operation permission mode. One possible approach is to identify the control bits of the status register, determine the operation permission mode, and then determine the target bit width based on the operation data bit width and the preset register bit width corresponding to the operation permission mode.

[0098] For example, the control bits of the status register are identified, the operation permission mode is determined to be the user operation permission mode, and the target bit width is determined to be the lower 32 bits based on the operation data bit width (32 bits) and the preset register bit width (UXL=1) corresponding to the user operation permission mode. From the 64-bit operand "0 (x8)", the low operation bit corresponding to the target bit width (lower 32 bits) is determined as the target operation bit "the lowest 32 bits of the x10 register".

[0099] In this embodiment, the operation permission mode is determined by identifying the control bits of the status register. Combined with the operation data bit width and the preset register bit width, the target bit width and corresponding operation bits are automatically determined. This provides a flexible and secure operating environment under different operation permission modes, enhancing the processor's adaptability and processing capabilities in various application scenarios, while ensuring data processing accuracy and maintaining overall system performance. Hardware-assisted relaxation expansion further improves instruction execution efficiency, reduces power consumption, and provides better register addressing support for applications in resource-constrained environments.

[0100] In one optional embodiment of this disclosure, the target processor includes multiple status registers, and the control bits of each status register are used to record whether the register addressing instruction is used for the corresponding operation permission mode.

[0101] Determining the target bit width based on the operation data bit width and operation permission mode includes the following specific steps:

[0102] Identify the control bits of the first status register to determine whether the register addressing instruction is in the operation permission mode corresponding to the control bit, wherein the first status register is at least one of multiple status registers;

[0103] If so, determine the target bit width based on the operation data bit width and the preset register bit width corresponding to the operation permission mode.

[0104] Status registers are critical registers in the target processor used to store the current operating state and configuration information of the system. Status registers contain a series of controls used to control and indicate various operating modes, privilege levels, and the status of interrupts and other critical events. Status registers include, but are not limited to: machine status register, supervisor status register, virtual supervisor status register, and virtual machine manager status register. Examples include the machine status register MSTATUS, supervisor status register SSTATUS, virtual supervisor status register VSSTATUS, and virtual machine manager status register HSTATUS.

[0105] The first status register is at least one of a plurality of status registers.

[0106] Control bits in the status register are flags used to control specific functions or behaviors of the processor. Control bits are typically Boolean values ​​(0 or 1). Control bits in the status register include, but are not limited to: control bits in the machine status register, control bits in the supervisory status register, control bits in the virtual supervisory status register, and control bits in the virtual machine management status register. For example:

[0107] The user-mode slack extension enable bit instructs the target processor to ignore the bit field values ​​of the target register [XLEN-1:UXLEN] when addressing in user-mode (U-mode) operation.

[0108] The privileged slack extension enable bit instructs the target processor to ignore the bit field values ​​of the target register [XLEN-1:SXLEN] when addressing in the supervisory operation privilege mode (S-mode).

[0109] The Virtual User Mode Relaxed Extension Enable bit instructs the target processor to ignore the bit field values ​​of the target register [XLEN-1:UXLEN] when addressing in Virtual User Operation Authority Mode (VU-mode).

[0110] The Virtual Privileged Mode Relaxation Extension Enable bit instructs the target processor to ignore the bit field values ​​of the target register [XLEN-1:VSXLEN] when addressing in Virtual Supervisory Operation Privileged Mode (VS-mode).

[0111] The preset register bit width corresponding to the operation permission mode is a register width pre-set according to different operation permission modes. This determines which parts of the data in the register are considered valid and participate in the operation under that permission mode. The preset register bit width ensures that even applications running in multi-permission modes can correctly access and manipulate data without unintentionally interfering with the contents of other parts. It simplifies the complexity of the compiler and runtime system and improves the speed and efficiency of register addressing. Different permission modes can have different preset register bit widths to suit their respective needs. The preset register bit widths corresponding to operation permission modes include, but are not limited to: the preset register bit widths corresponding to user operation permission modes, supervisory operation permission modes, virtual user operation permission modes, and virtual supervisory operation permission modes. For example, the numerical range of UXL, SXL, and VSXL is [1, 2, 3], where 1 represents 32 bits, 2 represents 64 bits, and 3 represents 128 bits. The target bit widths are: UXLEN represents 32*UXL (UXL != 3), SXLEN represents 32*SXL (SXL != 3), and VSXLEN represents 32*VSXL (VSXL != 3).

[0112] For example, the user-mode slack extension function enable bit is identified, the user operation permission mode corresponding to the control bit of the register addressing instruction is determined, and the target bit width is determined to be the lower 32 bits based on the operation data bit width (32 bits) and the preset register bit width (1) corresponding to the user operation permission mode.

[0113] In this embodiment, by identifying the control bits of multiple status registers, it quickly and accurately determines whether a register addressing instruction is in the corresponding operation permission mode, and automatically determines the target bit width based on the operation data bit width and the preset register bit width. Hardware-assisted relaxation expansion further optimizes system performance, reduces power consumption, enhances flexibility and security under different permission modes, and provides better support for multiple application scenarios.

[0114] In one optional embodiment of this disclosure, the first status register includes a machine status register;

[0115] Identifying the control bits of the first status register and determining whether the register addressing instruction is in the operation permission mode corresponding to the control bit includes the following specific steps:

[0116] Identify the user-mode slack extension enable bit in the machine status register to determine whether the register addressing instruction is in user operation privilege mode.

[0117] If so, the target bit width is determined based on the operation data bit width and the preset register bit width corresponding to the operation permission mode, including the following specific steps:

[0118] If so, determine the target bit width based on the operation data bit width and the preset register bit width corresponding to the user operation permission mode.

[0119] The machine status register is a critical register in the processor architecture used to store the overall system operating state and configuration information. The machine status register contains control bits that control and indicate the system's operating mode (such as user mode, supervisory mode, etc.).

[0120] User-mode slack extension enable bits are flags in the machine status register used to control specific functions or behaviors of the processor, specifically controlling the processor's behavior when addressing in User-Authority Mode (U-mode). These control bits determine how the processor processes the higher-order bits of registers, particularly when converting between operands of different widths. For example, when the user-mode slack extension enable bit is set to 1, it means that in U-mode, the processor will ignore the higher-order bits of the target register [XLEN-1:UXLEN] during addressing. This means that if XLEN is 64 bits and UXL is 1 (i.e., 32 bits), only the lower 32 bits of the register will be used as valid data when executing register addressing instructions in U-mode.

[0121] The preset register width corresponding to the user-accessible mode is the register width pre-set in user-accessible mode (U-mode). For user-accessible mode, the preset register width is usually determined by the UXL parameter. For example, if the operation data width is 32 bits, a preset register width of UXL = 1 indicates 32 bits.

[0122] For example, if the enable bit of the user-mode slack extension function in the machine status register is 1, it is determined that the register addressing instruction is in the user operation permission mode (U-mode). Based on the operation data bit width (32 bits) and the preset register bit width (UXL=1) corresponding to the user operation permission mode, the target bit width is determined to be the lower 32 bits.

[0123] In this embodiment, by identifying the user-mode slack extension enable bit in the machine status register, it is quickly determined whether the register addressing instruction is in user-accessible mode. If so, the target bit width is automatically determined based on the operation data bit width and the preset register bit width. This avoids unnecessary sign extension or zero-extension operations in user-accessible mode, reduces the number of software instructions, simplifies the complexity of the compiler and runtime system, and significantly improves the speed and efficiency of register addressing. Hardware-assisted slack extension further optimizes system performance, reduces power consumption, enhances flexibility and security under different accessibility modes, provides better support for multiple application scenarios, ensures data processing accuracy even in complex virtualization environments, and improves the overall utilization of computing resources.

[0124] In one optional embodiment of this disclosure, the first status register includes a machine status register;

[0125] Identifying the control bits of the first status register and determining whether the register addressing instruction is in the operation permission mode corresponding to the control bit includes the following specific steps:

[0126] Identify the privileged slack extension enable bit in the machine status register to determine whether the register addressing instruction is in supervised operation privilege mode;

[0127] If so, the target bit width is determined based on the operation data bit width and the preset register bit width corresponding to the operation permission mode, including the following specific steps:

[0128] If so, determine the target bit width based on the operation data bit width and the preset register bit width corresponding to the supervision operation permission mode.

[0129] The machine status register is a critical register in the processor architecture used to store the overall system operating state and configuration information. The machine status register contains control bits that control and indicate the system's operating mode (such as user mode, supervisory mode, etc.).

[0130] The privileged slack extension enable bit is a flag in the machine status register used to control specific functions or behaviors of the processor, specifically its behavior during addressing in Supervised Operational Privilege Mode (S-mode). These control bits determine how the processor processes the higher-order bits of registers, particularly when switching between operations of different widths. For example, when the privileged slack extension enable bit is set to 1, it means that in S-mode, the processor will ignore the higher-order bits of the target register [XLEN-1:SXLEN] during addressing. This means that if XLEN is 64-bit and SXL is 1 (32-bit), only the lower 32 bits of the register will be used as valid data when executing register addressing instructions in S-mode. Similarly, if SXL is 2 (64-bit), the entire 64-bit register is considered valid data.

[0131] The preset register width corresponding to the supervisory operation permission mode is the register width pre-set in supervisory operation permission mode (S-mode). For supervisory operation permission mode, the preset register width is usually determined by the SXL parameter. For example, if the operation data width is 32 bits, the preset register width SXL = 2 indicates 64 bits.

[0132] For example, if the privileged slack extension enable bit of the machine status register is 1, it is determined that the register addressing instruction is in the supervised operation privilege mode (S-mode). Based on the operation data bit width (32 bits) and the preset register bit width (SXL=2) corresponding to the supervised operation privilege mode, the target bit width is determined to be the lower 64 bits.

[0133] In this embodiment, by identifying the privileged relaxation extension enable bit of the machine status register, it is quickly determined whether the register addressing instruction is in supervised access mode. If so, the target bit width is automatically determined based on the operation data bit width and the preset register bit width, avoiding unnecessary sign extension or zero extension operations in supervised access mode, reducing the number of software instructions, simplifying the complexity of the compiler and runtime system, and significantly improving the speed and efficiency of register addressing. Hardware-assisted relaxation extension further optimizes system performance, reduces power consumption, enhances flexibility and security under different access modes, provides better support for multiple application scenarios, ensures the accuracy of data processing even in complex virtualization environments, and improves the overall utilization of computing resources.

[0134] In one optional embodiment of this disclosure, the first status register includes a supervisory status register;

[0135] Identifying the control bits of the first status register and determining whether the register addressing instruction is in the operation permission mode corresponding to the control bit includes the following specific steps:

[0136] Identify the user-mode slack extension enable bit in the supervisory status register to determine whether the register addressing instruction is in user operation privilege mode;

[0137] If so, the target bit width is determined based on the operation data bit width and the preset register bit width corresponding to the operation permission mode, including the following specific steps:

[0138] If so, determine the target bit width based on the operation data bit width and the preset register bit width corresponding to the user operation permission mode.

[0139] The supervisory status register (S-mode) is a critical register in the processor architecture used to store the system's operating status and configuration information in supervisory mode. The S-mode register contains control bits that control and indicate which mode the system is in (e.g., user mode, supervisory mode, etc.).

[0140] The user-mode slack extension enable bit is a flag bit located in the supervisory status register used to control specific functions or behaviors of the processor, specifically its behavior when addressing in User-Operating-Privilege (U-mode). These control bits determine how the processor processes the high-order bits of registers, particularly when converting between operands of different widths. For example, when the user-mode slack extension enable bit is set to 1, it means that in U-mode, the processor will ignore the high-order bits of the target register [XLEN-1:UXLEN] during addressing. This means that if XLEN is 64 bits and UXL is 1 (i.e., 32 bits), only the lower 32 bits of the register will be used as valid data when executing register addressing instructions in U-mode. This ensures that even if the register itself is 64 bits wide, memory bandwidth can be saved and storage requirements reduced in applications that do not require a full 64-bit address space.

[0141] The preset register width corresponding to the user-accessible mode is the register width pre-set in user-accessible mode (U-mode). For user-accessible mode, the preset register width is usually determined by the UXL parameter. For example, if the operation data width is 32 bits, a preset register width of UXL = 1 indicates 32 bits.

[0142] For example, if the user-mode slack extension function enable bit is identified as 1, it is determined that the register addressing instruction is in the user operation permission mode (U-mode). Based on the operation data bit width (32 bits) and the preset register bit width (UXL=1) corresponding to the user operation permission mode, the target bit width is determined to be the lower 32 bits.

[0143] In this embodiment, by identifying the user-mode relaxation extension enable bit of the supervisory status register, it is quickly determined whether the register addressing instruction is in user-accessible mode. If so, the target bit width is automatically determined based on the operation data bit width and the preset register bit width, avoiding unnecessary sign extension or zero-extension operations in user-accessible mode, reducing the number of software instructions, simplifying the complexity of the compiler and runtime system, and significantly improving the speed and efficiency of register addressing. Hardware-assisted relaxation extension further optimizes system performance, reduces power consumption, enhances flexibility and security under different accessibility modes, provides better support for multiple application scenarios, ensures data processing accuracy even in complex virtualization environments, and improves the overall utilization of computing resources.

[0144] In one optional embodiment of this disclosure, the first status register includes a virtual supervisory status register;

[0145] Identifying the control bits of the first status register and determining whether the register addressing instruction is in the operation permission mode corresponding to the control bit includes the following specific steps:

[0146] Identify the virtual user-mode relaxation extension enable bit of the virtual supervisory status register to determine whether the register addressing instruction is in virtual user operation permission mode;

[0147] If so, the target bit width is determined based on the operation data bit width and the preset register bit width corresponding to the operation permission mode, including the following specific steps:

[0148] If so, determine the target bit width based on the operation data bit width and the preset register bit width corresponding to the virtual user operation permission mode.

[0149] The Virtual Supervisory Status Register (VSCUR) is a critical register in the processor architecture used to store the system's operating status and configuration information in virtual mode. The VSCUR contains control bits that control and indicate which operating privilege mode the system is in (such as virtual user mode, virtual supervisory mode, etc.).

[0150] The Virtual User-Mode Slack Extension Enable bit is a flag in the Virtual Supervisory Status Register used to control specific functions or behaviors of the processor, specifically its behavior when addressing in Virtual User Access Mode (VU-mode). These control bits determine how the processor processes the high-order bits of registers, particularly when converting between operands of different widths. For example, when the Virtual User-Mode Slack Extension Enable bit is set to 1, it means that in VU-mode, the processor will ignore the high-order bits of the target register [XLEN-1:UXLEN] during addressing. This means that if XLEN is 64-bit and UXL is 1 (i.e., 32-bit), only the lower 32 bits of the register will be used as valid data when executing register addressing instructions in VU-mode. This ensures that even if the register itself is 64-bit wide, memory bandwidth can be saved and storage requirements reduced in applications that do not require a full 64-bit address space.

[0151] The preset register width corresponding to the Virtual User Operation Permission Mode (VU-mode) is the register width pre-set in VU-mode. For VU-mode, the preset register width is typically determined by the VUXL parameter. For example, if the operation data width is 32 bits, a preset register width of VUXL = 2 indicates 64 bits.

[0152] For example, the virtual user-mode slack extension enable bit V=1 of the virtual supervisory status register is identified, the register addressing instruction is determined to be in the virtual user operation permission mode VU-mode, and the target bit width is determined to be the lower 64 bits based on the operation data bit width (32 bits) and the preset register bit width (VUXL=2) corresponding to the virtual user operation permission mode.

[0153] In this embodiment, by identifying the user-mode relaxation extension enable bit of the virtual supervisory status register, it is quickly determined whether the register addressing instruction is in a virtual user operation permission mode. If so, the target bit width is automatically determined based on the operation data bit width and the preset register bit width, avoiding unnecessary sign extension or zero extension operations in the virtual user operation permission mode, reducing the number of software instructions, simplifying the complexity of the compiler and runtime system, and significantly improving the speed and efficiency of register addressing. Hardware-assisted relaxation extension further optimizes system performance, reduces power consumption, enhances flexibility and security under different permission modes, provides better support for multiple application scenarios, ensures the accuracy of data processing even in complex virtualization environments, and improves the overall utilization of computing resources.

[0154] In one optional embodiment of this disclosure, the first status register includes a virtual machine management status register;

[0155] Identifying the control bits of the first status register and determining whether the register addressing instruction is in the operation permission mode corresponding to the control bit includes the following specific steps:

[0156] Identify the virtual privileged state relaxation extension enable bit in the virtual machine management status register to determine whether the register addressing instruction is in the virtual supervisory operation privilege mode.

[0157] If so, the target bit width is determined based on the operation data bit width and the preset register bit width corresponding to the operation permission mode, including the following specific steps:

[0158] If so, determine the target bit width based on the operation data bit width and the preset register bit width corresponding to the virtual supervision operation permission mode.

[0159] The Virtual Machine Management Status Register (VMS Register) is a critical register in the processor architecture used to store the system's running state and configuration information within the hypervisor. The VMS Register contains control bits that control and indicate the operating permission mode (such as virtual user mode, virtual supervisor mode, etc.) in which the system is running.

[0160] The Virtual Privileged Mode (VPSM) slack extension enable bit is a flag used to control specific functions or behaviors of the processor, specifically its behavior when addressing in Virtual Supervised Operational Privileged Mode (VS-mode). These control bits determine how the processor processes the high-order bits of registers, particularly when converting between operation data of different widths. For example, when the VPSM slack extension enable bit is set to 1, it indicates that in VS-mode, the processor will ignore the high-order bits of the target register [XLEN-1:VSXLEN] during addressing. This means that if XLEN is 128 bits and VSXL is 3 (i.e., 128 bits), only 128 bits of the register will be used as valid data when executing register addressing instructions in VS-mode.

[0161] The preset register width corresponding to the Virtual Supervisory Operation Permission Mode (VS-mode) is the register width pre-set in VS-mode. For VS-mode, the preset register width is usually determined by the VSXL parameter. For example, if the operation data width is 128 bits, a preset register width of VSXL = 3 indicates 128 bits.

[0162] For example, the virtual privileged relaxation extension enable bit of the virtual machine management status register is identified as 1, the register addressing instruction is determined to be in the virtual supervisory operation privilege mode (VS-mode), and the target bit width is determined to be 128 bits based on the operation data bit width (32 bits) and the preset register bit width (VSXL = 3) corresponding to the virtual supervisory operation privilege mode.

[0163] In this embodiment, by identifying the privileged relaxation extension enable bit of the virtual machine management status register, it is quickly determined whether the register addressing instruction is in the virtual supervised operation privilege mode. If so, the target bit width is automatically determined based on the operation data bit width and the preset register bit width, avoiding unnecessary sign extension or zero extension operations in the virtual supervised operation privilege mode, reducing the number of software instructions, simplifying the complexity of the compiler and runtime system, and significantly improving the speed and efficiency of register addressing. Hardware-assisted relaxation extension further optimizes system performance, reduces power consumption, enhances flexibility and security under different privilege modes, provides better support for multiple application scenarios, ensures the accuracy of data processing even in complex virtualization environments, and improves the overall utilization of computing resources.

[0164] The register addressing method provided in this disclosure will be further described below with reference to Figure 2, taking the application of the register addressing method in a Reduced Instruction Set Architecture (RISC) processor as an example. Figure 2 shows a flowchart of the processing procedure of a register addressing method applied to a RISC processor according to an embodiment of this disclosure, including the following specific steps:

[0165] Step 202: Obtain register addressing instructions for the target register in the target processor. These instructions include, but are not limited to, indirect jump instructions, return instructions, load instructions, store instructions, and atomic memory operation (AMO) instructions, and include the register bit width of the operation bits.

[0166] Step 204: Identify the user-mode slack extension enable bit to determine whether the register addressing instruction is in user-operated privilege mode (U-mode). If the user-mode slack extension enable bit is set to 1, proceed to step 206; otherwise, proceed to step 208.

[0167] Step 206: Determine the target bit width based on the operation data bit width and the preset register bit width (UXL) corresponding to the user operation permission mode. If MSTATUS.UXL or SSTATUS.UXL is 1, the target bit width is 32 bits; if it is 2, the target bit width is 64 bits. After completion, jump to step 214.

[0168] Step 208: Identify the privileged slack extension enable bit to determine whether the register addressing instruction is in supervised operation privilege mode (S-mode). If the privileged slack extension enable bit is set to 1, proceed to step 210; otherwise, proceed to step 212.

[0169] Step 210: Determine the target bit width based on the operation data bit width and the preset register bit width (SXL) corresponding to the supervisory operation permission mode. If MSTATUS.SXL is 1, the target bit width is 32 bits; if it is 2, the target bit width is 64 bits. After completion, jump to step 214.

[0170] Step 212: Identify the user-mode relaxation extension function enable bit, and repeat steps 204 and 206.

[0171] Step 214: Identify the virtual user-mode relaxation extension function enable bit to determine whether the register addressing instruction is in virtual user access mode (VU-mode). If so, determine the target bit width based on the operation data bit width and the preset register bit width (VUXL) corresponding to the virtual user access mode. After completion, proceed to step 218.

[0172] Step 216: Identify the virtual privileged mode relaxation extension enable bit to determine whether the register addressing instruction is in Virtual Supervised Operation Privilege Mode (VS-mode). If so, determine the target bit width based on the operation data bit width and the preset register bit width (VSXL) corresponding to the Virtual Supervised Operation Privilege Mode. After completion, proceed to step 218.

[0173] Step 218: Determine the target bit width operation bits from the operation bits of the register bit width as the target operation bits.

[0174] Step 220: Perform an addressing operation on the target register based on the target operation bits.

[0175] For example, when U-mode XLEN = 64, the user-mode relaxation extension enable bit is 1 and MSTATUS.UXL = SSTATUS.UXL = 1. Therefore, when the hardware executes instructions requiring register addressing, such as indirect jumps, return instructions, load instructions, store instructions, and AMO instructions, it will ignore the [63:32] bit field values ​​of the registers and only use the [31:0] bit field values ​​for addressing. That is, the target bit width is 32 bits.

[0176] For example, when U-mode XLEN = 128, the user-mode relaxation extension enable bit is 1 and MSTATUS.UXL = SSTATUS.UXL = 1. Therefore, when the hardware executes instructions requiring register addressing, such as indirect jumps, return instructions, load instructions, store instructions, and AMO instructions, it will ignore the [127:32] bit field values ​​of the registers and only use the [31:0] bit field values ​​for addressing. That is, the target bit width is 32 bits.

[0177] For example, when U-mode XLEN = 128, the user-mode relaxation extension enable bit is 1 and MSTATUS.UXL = SSTATUS.UXL = 2. Therefore, when the hardware executes instructions requiring register addressing, such as indirect jumps, return instructions, load instructions, store instructions, and AMO instructions, it will ignore the [127:64] bit field values ​​of the registers and only use the [63:0] bit field values ​​for addressing. That is, the target bit width is 64 bits.

[0178] For example, when S-mode XLEN = 64, the privileged mode relaxation extension enable bit is 1 and MSTATUS.SXL = 1. Therefore, when the hardware executes instructions requiring register addressing, such as indirect jumps, return instructions, load instructions, store instructions, and AMO instructions, it will ignore the [63:32] bit field values ​​of the registers and only use the [31:0] bit field values ​​for addressing. That is, the target bit width is 32 bits.

[0179] For example, when S-mode XLEN = 128, the privileged mode relaxation extension enable bit is 1 and MSTATUS.SXL = 1. Therefore, when the hardware executes instructions requiring register addressing, such as indirect jumps, return instructions, load instructions, store instructions, and AMO instructions, it will ignore the [127:32] bit field values ​​of the register and only use the [31:0] bit field values ​​for addressing. That is, the target bit width is 32 bits.

[0180] For example, when S-mode XLEN = 128, the user-mode relaxation extension enable bit is 1 and MSTATUS.SXL = 2. Therefore, when the hardware executes instructions requiring register addressing, such as indirect jumps, return instructions, load instructions, store instructions, and AMO instructions, it will ignore the [127:64] bit field values ​​of the registers and only use the [63:0] bit field values ​​for addressing. That is, the target bit width is 64 bits.

[0181] This embodiment employs a hardware relaxation extension addressing scheme, avoiding the need for software to insert additional instructions for addressing, thus improving performance. It can be used in both 64ilp32 and 128ilp32 / 128lp64 ABI scenarios. It addresses the issues of reduced instruction set processors such as 64ilp32, 128ilp32, and 128lp64. Compared to previous software solutions, this solution improves performance and simplifies the compiler's work.

[0182] Corresponding to the above method embodiments, this disclosure also provides an instruction processing apparatus embodiment. FIG3 shows a schematic structural diagram of an instruction processing apparatus provided in one embodiment of this disclosure. As shown in FIG3, the instruction processing apparatus includes;

[0183] The instruction fetching module 302 is configured to fetch register addressing instructions for a target register in a target processor, wherein the register bit width and the operation data bit width of the target processor are different, and the register addressing instructions include the operation bits of the register bit width;

[0184] The operation bit determination module 304 is configured to determine the target operation bit from the operation bits of the register bit width based on the operation data bit width.

[0185] Addressing module 306 is configured to perform addressing operations on the target register based on the target operation bits.

[0186] Optionally, the register addressing instruction corresponds to the operation permission mode; the operation bit determination module 304 is further configured as follows:

[0187] The target bit width is determined based on the operation data bit width and operation permission mode; the operation bits of the target bit width are determined from the operation bits of the register bit width as the target operation bits.

[0188] Optionally, the target processor includes multiple status registers, and the control bits of each status register are used to record whether the register addressing instruction is used in the corresponding operation permission mode; the operation bit determination module 304 is further configured to:

[0189] Identify the control bit of the first status register to determine whether the register addressing instruction is in the operation permission mode corresponding to the control bit, wherein the first status register is at least one of multiple status registers; if so, determine the target bit width based on the operation data bit width and the preset register bit width corresponding to the operation permission mode.

[0190] Optionally, the first status register includes a machine status register; the operation bit determination module 304 is further configured to:

[0191] Identify the user-mode slack extension enable bit in the machine status register to determine whether the register addressing instruction is in user operation permission mode; if so, determine the target bit width based on the operation data bit width and the preset register bit width corresponding to the user operation permission mode.

[0192] Optionally, the first status register includes a machine status register; the operation bit determination module 304 is further configured to:

[0193] Identify the privileged slack extension enable bit in the machine status register to determine whether the register addressing instruction is in supervised operation privilege mode; if so, determine the target bit width based on the operation data bit width and the preset register bit width corresponding to the supervised operation privilege mode.

[0194] Optionally, the first status register includes a supervisory status register; the operation bit determination module 304 is further configured to:

[0195] Identify the user-mode slack extension enable bit in the supervisory status register to determine whether the register addressing instruction is in user operation permission mode; if so, determine the target bit width based on the operation data bit width and the preset register bit width corresponding to the user operation permission mode.

[0196] Optionally, the first status register includes a virtual supervisory status register; the operation bit determination module 304 is further configured to:

[0197] Identify the virtual user-mode relaxation extension enable bit of the virtual supervisory status register to determine whether the register addressing instruction is in virtual user operation permission mode; if so, determine the target bit width based on the operation data bit width and the preset register bit width corresponding to the virtual user operation permission mode.

[0198] Optionally, the first status register includes a virtual machine management status register; the operation bit determination module 304 is further configured to:

[0199] Identify the virtual privileged state relaxation extension enable bit in the virtual machine management status register to determine whether the register addressing instruction is in the virtual supervisory operation permission mode; if so, determine the target bit width based on the operation data bit width and the preset register bit width corresponding to the virtual supervisory operation permission mode.

[0200] Optionally, register addressing instructions include at least one of indirect jump instructions, return instructions, load instructions, store instructions, and atomic memory operation instructions.

[0201] In this embodiment, hardware-assisted addressing automatically selects and uses appropriate operands. When the register bit width and operand data bit width of the target processor are different, the target operand is determined directly from the operands of the register bit width based on the operand data bit width, ignoring operands other than the target operand in the register bit width. This achieves relaxed extended addressing, eliminating the need for additional software instructions to expand the operand size, thereby reducing the number of software instructions and avoiding the additional overhead caused by operations such as sign extension or zero extension. This directly improves the speed and efficiency of register addressing, simplifies the complexity of the compiler and runtime system, improves the data processing efficiency and overall performance of the target processor, and enhances addressing efficiency.

[0202] The above is a schematic scheme of an instruction processing device according to this embodiment. It should be noted that the technical solution of this instruction processing device and the technical solution of the above-described register addressing method belong to the same concept. For details not described in detail in the technical solution of the instruction processing device, please refer to the description of the technical solution of the above-described register addressing method.

[0203] Corresponding to the above method embodiments, this disclosure also provides a target processor device embodiment. FIG4 shows a structural block diagram of a target processor provided in one embodiment of this disclosure. As shown in FIG4, the target processor 400 includes a target register 402 and an instruction processing device 404. The register bit width and the operation data bit width of the target processor 400 are different.

[0204] The instruction processing unit 404 is configured to acquire a register addressing instruction for a target register 402, determine the target operation bit from the operation bits of the register bit width based on the operation data bit width, and perform an addressing operation on the target register 402 based on the target operation bit, wherein the register addressing instruction includes the operation bits of the register bit width.

[0205] In this embodiment, efficient addressing of registers with different bit widths is achieved by integrating the instruction processing device into the target processor. This design utilizes a hardware-assisted mechanism to automatically match the bit width of the operand data and determine the appropriate register bit for the target operand, thereby improving instruction execution efficiency without altering the original software architecture. It avoids the additional overhead introduced by bit width differences in traditional methods, such as sign extension or zero extension operations, simplifies the complexity of the compiler and runtime system, improves the processor's data throughput and overall performance, and enhances system response speed.

[0206] The above is an illustrative scheme of a target processor according to this embodiment. It should be noted that the technical solution of this target processor and the technical solution of the above-described register addressing method belong to the same concept. For details not described in detail in the technical solution of the target processor, please refer to the description of the technical solution of the above-described register addressing method.

[0207] Corresponding to the above method embodiments, this disclosure also provides an embodiment of a system-on-a-chip device. FIG5 shows a structural block diagram of a system-on-a-chip provided in one embodiment of this disclosure. As shown in FIG5, the system-on-a-chip 500 includes a control unit 502 and a plurality of on-chip components 504, wherein the plurality of on-chip components 504 includes a target processor 5042;

[0208] The control unit 502 is used to control and manage multiple on-chip components 504, and the target processor 5042 is used to execute computer programs / instructions, which implement the steps of the above method when executed by the target processor 5042.

[0209] In this embodiment, the system-on-a-chip integrates a control unit and multiple on-chip components, particularly the aforementioned target processor, enabling the entire system to process complex computer instructions more quickly and efficiently. By optimizing communication and cooperation between internal components, it reduces data processing latency and enhances multitasking capabilities. The instruction processing device can achieve efficient register addressing without relying on additional software instructions under different bit-width operation requirements, thereby improving the overall system's computational efficiency and resource utilization, and meeting the high-performance and low-power requirements of modern computing devices.

[0210] The above is an illustrative scheme of a system-on-a-chip (SoC) according to this embodiment. It should be noted that the technical solution of this SoC and the technical solution of the register addressing method described above belong to the same concept. For details not described in detail in the SoC technical solution, please refer to the description of the technical solution of the register addressing method described above.

[0211] Figure 6 shows a structural block diagram of a computing device according to an embodiment of the present disclosure. The components of the computing device 600 include a memory 610 and a system-on-a-chip 620;

[0212] The memory 610 is used to store computer programs / instructions, and the system-on-a-chip 620 is used to execute the computer programs / instructions. When executed by the system-on-a-chip 620, the computer programs / instructions implement the steps of the above-described method. The system-on-a-chip 620 and the memory 610 are connected via a bus, and the database is used to store data.

[0213] The computing device 600 also includes an access device that enables the computing device 600 to communicate via one or more networks. Examples of such networks include a Public Switched Telephone Network (PSTN), a Local Area Network (LAN), a Wide Area Network (WAN), a Personal Area Network (PAN), or a combination of communication networks such as the Internet. The access device may include one or more of any type of wired or wireless network interface (e.g., a Network Interface Controller (NIC)), such as an IEEE 802.11 Wireless Local Area Network (WLAN) wireless interface, a Worldwide Interoperability for Microwave Access (Wi-MAX) interface, an Ethernet interface, a Universal Serial Bus (USB) interface, a cellular network interface, a Bluetooth interface, or a Near Field Communication (NFC) interface.

[0214] In one embodiment of this disclosure, the aforementioned components of the computing device 600, as well as other components not shown in FIG. 6, may also be connected to each other, for example, via a bus. It should be understood that the computing device block diagram shown in FIG. 6 is merely for illustrative purposes and is not intended to limit the scope of this disclosure. Those skilled in the art can add or replace other components as needed.

[0215] The computing device 600 can be any type of stationary or mobile computing device, including mobile computers or mobile computing devices (e.g., tablet computers, personal digital assistants, laptop computers, notebook computers, netbooks, etc.), mobile phones (e.g., smartphones), wearable computing devices (e.g., smartwatches, smart glasses, etc.) or other types of mobile devices, or stationary computing devices such as desktop computers or personal computers (PCs). The computing device 600 can also be a mobile or stationary server.

[0216] The system-on-chip 620 is used to execute the following computer program / instruction, which, when executed by the processor, implements the steps of the above-described register addressing method.

[0217] The above is a schematic representation of a computing device according to this embodiment. It should be noted that the technical solution of this computing device and the technical solution of the aforementioned register addressing method belong to the same concept. Details not described in detail in the technical solution of the computing device can be found in the description of the technical solution of the aforementioned register addressing method.

[0218] An embodiment of this disclosure also provides a computer-readable storage medium storing a computer program / instructions that, when executed by a processor, implement the steps of the above-described register addressing method.

[0219] The above is an illustrative scheme of a computer-readable storage medium according to this embodiment. It should be noted that the technical solution of this storage medium and the technical solution of the above-described register addressing method belong to the same concept. For details not described in detail in the technical solution of the storage medium, please refer to the description of the technical solution of the above-described register addressing method.

[0220] An embodiment of this disclosure also provides a computer program product, including a computer program / instruction that, when executed by a processor, implements the steps of the above-described register addressing method.

[0221] The above is an illustrative scheme of a computer program product according to this embodiment. It should be noted that the technical solution of this computer program product and the technical solution of the above-described register addressing method belong to the same concept. For details not described in detail in the technical solution of the computer program product, please refer to the description of the technical solution of the above-described register addressing method.

[0222] The foregoing has described specific embodiments of this disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired results. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0223] The computer instructions include computer program code, which may be in the form of source code, object code, executable file, or some intermediate form. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording media, USB flash drive, portable hard drive, magnetic disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content contained in the computer-readable medium may be appropriately added or removed according to the requirements of patent practice. For example, in some regions, according to patent practice, computer-readable media may not include electrical carrier signals and telecommunication signals.

[0224] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the embodiments of this disclosure are not limited to the described order of actions, because according to the embodiments of this disclosure, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to the embodiments of this disclosure.

[0225] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0226] The preferred embodiments disclosed above are merely illustrative of this disclosure. The optional embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the embodiments of this disclosure. These embodiments are selected and specifically described in this disclosure to better explain the principles and practical applications of the embodiments of this disclosure, thereby enabling those skilled in the art to better understand and utilize this disclosure. This disclosure is limited only by the claims and their full scope and equivalents.

Claims

1. A register addressing method applied to a target processor, comprising: Obtain a register addressing instruction for a target register in a target processor, wherein the register bit width and the operation data bit width of the target processor are different, and the register addressing instruction includes the operation bits of the register bit width; Based on the operation data bit width, the target operation bit is determined from the operation bits of the register bit width; An addressing operation is performed on the target register based on the target operation bits.

2. The method according to claim 1, wherein the register addressing instruction corresponds to an operation permission mode; The step of determining the target operation bit from the operation bits of the register bit width based on the operation data bit width includes: The target bit width is determined based on the operation data bit width and the operation permission mode; From the operation bits of the register bit width, determine the operation bits of the target bit width as the target operation bits.

3. The method according to claim 2, wherein the target processor includes a plurality of status registers, and the control bits of each status register are used to record whether the register addressing instruction is used for the corresponding operation permission mode; Determining the target bit width based on the operation data bit width and the operation permission mode includes: Identify the control bit of the first status register and determine whether the register addressing instruction is in the operation permission mode corresponding to the control bit, wherein the first status register is at least one of the plurality of status registers; If so, the target bit width is determined based on the operation data bit width and the preset register bit width corresponding to the operation permission mode.

4. The method according to claim 3, wherein the first status register includes a machine status register; The step of identifying the control bit of the first status register and determining whether the register addressing instruction is in the operation permission mode corresponding to the control bit includes: Identify the user-mode slack extension function enable bit of the machine status register to determine whether the register addressing instruction is in user operation permission mode; If so, determining the target bit width based on the operation data bit width and the preset register bit width corresponding to the operation permission mode includes: If so, the target bit width is determined based on the operation data bit width and the preset register bit width corresponding to the user operation permission mode.

5. The method according to claim 3, wherein the first status register includes a machine status register; The step of identifying the control bit of the first status register and determining whether the register addressing instruction is in the operation permission mode corresponding to the control bit includes: Identify the privileged state slack extension function enable bit of the machine status register to determine whether the register addressing instruction is in supervised operation privilege mode; If so, determining the target bit width based on the operation data bit width and the preset register bit width corresponding to the operation permission mode includes: If so, the target bit width is determined based on the operation data bit width and the preset register bit width corresponding to the supervision operation permission mode.

6. The method according to claim 3, wherein the first status register includes a supervisory status register; The step of identifying the control bit of the first status register and determining whether the register addressing instruction is in the operation permission mode corresponding to the control bit includes: Identify the user-mode slack extension function enable bit of the supervisory status register to determine whether the register addressing instruction is in user operation permission mode; If so, determining the target bit width based on the operation data bit width and the preset register bit width corresponding to the operation permission mode includes: If so, the target bit width is determined based on the operation data bit width and the preset register bit width corresponding to the user operation permission mode.

7. The method according to claim 3, wherein the first status register includes a virtual supervisory status register; The step of identifying the control bit of the first status register and determining whether the register addressing instruction is in the operation permission mode corresponding to the control bit includes: Identify the virtual user-mode relaxation extension function enable bit of the virtual supervisory status register to determine whether the register addressing instruction is in virtual user operation permission mode; If so, determining the target bit width based on the operation data bit width and the preset register bit width corresponding to the operation permission mode includes: If so, the target bit width is determined based on the operation data bit width and the preset register bit width corresponding to the virtual user operation permission mode.

8. The method according to claim 3, wherein the first status register includes a virtual machine management status register; The step of identifying the control bit of the first status register and determining whether the register addressing instruction is in the operation permission mode corresponding to the control bit includes: Identify the virtual privileged state relaxation extension function enable bit of the virtual machine management status register to determine whether the register addressing instruction is in virtual supervisory operation permission mode; If so, determining the target bit width based on the operation data bit width and the preset register bit width corresponding to the operation permission mode includes: If so, the target bit width is determined based on the operation data bit width and the preset register bit width corresponding to the virtual supervision operation permission mode.

9. The method according to any one of claims 1-8, wherein the register addressing instruction includes at least one of indirect jump instructions, return instructions, load instructions, store instructions, and atomic memory operation instructions.

10. An instruction processing apparatus, comprising: The instruction fetching module is configured to fetch a register addressing instruction for a target register in a target processor, wherein the register bit width and the operation data bit width of the target processor are different, and the register addressing instruction includes the operation bits of the register bit width; The operation bit determination module is configured to determine the target operation bit from the operation bits of the register bit width based on the operation data bit width. The addressing module is configured to perform an addressing operation on the target register based on the target operation bit.

11. A target processor, the target processor comprising a target register and an instruction processing device, wherein the register bit width and the operation data bit width of the target processor are different; The instruction processing device is configured to acquire a register addressing instruction for the target register, determine a target operation bit from the operation bits of the register bit width based on the operation data bit width, and perform an addressing operation on the target register based on the target operation bit, wherein... The register addressing instruction includes the operation bits of the register bit width.

12. A system-on-a-chip, comprising: A control unit and multiple on-chip components, the multiple on-chip components including a target processor; The control unit is used to control and manage the plurality of on-chip components, and the target processor is used to execute a computer program / instruction that, when executed by the target processor, implements the steps of the method according to any one of claims 1 to 9.

13. A computing device, comprising: Memory and system-on-a-chip; The memory is used to store computer programs / instructions, and the system-on-a-chip is used to execute the computer programs / instructions, which, when executed by the system-on-a-chip, implement the steps of the method described in claims 1 to 9.

14. A computer-readable storage medium, wherein, The computer-readable storage medium stores a computer program that, when executed by a processor, causes the processor to perform the steps of the method as described in claims 1 to 9.

15. A computer program product, wherein, It includes a computer program that, when executed by a processor, implements the steps of the method as described in claims 1 to 9.

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