Method for forming vertical transfer transistor, and image sensor
By designing a C-shaped gate and optimizing the etching process, the problem of insufficient control range of the vertical transfer transistor was solved, improving electronic readout efficiency and image sensor performance.
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- GALAXYCORE SHANGHAI
- Filing Date
- 2025-11-14
- Publication Date
- 2026-07-02
AI Technical Summary
Existing vertical transfer transistors have limited gate control range, resulting in low electronic readout efficiency and poor turn-off, making it difficult to effectively control the transmission channel.
The gate of the vertical transfer transistor is designed to be C-shaped, surrounding the active region, and the photodiode and the floating diffusion region are connected through the active region. The etching of the gate and the floating diffusion region is optimized to reduce the electric field strength, and a shallow trench isolation structure is formed in the semiconductor substrate to reduce capacitance.
This improves the vertical transfer transistor's control over electrons, enhances readout efficiency, reduces the risk of punch-through between the photodiode and other areas, and improves the performance of the image sensor.
Smart Images
Figure CN2025134965_02072026_PF_FP_ABST
Abstract
Description
A method for forming a vertical transfer transistor and an image sensor
[0001] This application claims priority to Chinese Patent Application No. 202411954523.X, filed on December 26, 2024, entitled "A Method for Forming a Vertical Transfer Transistor and an Image Sensor", the entire contents of which are incorporated herein by reference. Technical Field
[0002] This invention relates to the field of semiconductor technology, and in particular to a method for forming a vertical transfer transistor and an image sensor. Background Technology
[0003] With the rapid development of image sensors and their increasingly widespread applications, the demands on image sensor performance are constantly rising. Pixel unit sizes are shrinking, and full-well capacitance density is rapidly increasing, placing immense pressure on charge readout. In the pixel unit structure, the design of the transfer transistor is particularly crucial for pixel readout. For pixels fabricated at advanced nodes, the transfer transistor has undergone a series of optimized designs, especially the vertical transfer transistor (VLT), which not only effectively improves readout capability but also reduces the isolation burden on the photodiode. This brings significant convenience to pixel unit design.
[0004] Vertical transfer transistors (VTIPs) protrude their bottom surface onto the photodiode, thus increasing the gate oxide area and enhancing the VTIP's control over the transmission channel. Simultaneously, a deeper VTIP bottom surface allows for a deeper photodiode, significantly reducing the risk of punch-through between the photodiode and surrounding areas, thereby further improving the photodiode's design depletion voltage. However, existing VTIP designs only partially control the transmission channel from the VTIP to the floating diffusion region. The gate control range is limited, and the further the silicon substrate is from the channel surface, the weaker the gate's control becomes, leading to low electron readout efficiency and poor turn-off. Therefore, current VTIP designs have limited control over the transmission channel, which is detrimental to electron transport. Summary of the Invention
[0005] The purpose of this invention is to provide a method for forming a vertical transfer transistor, comprising:
[0006] At least a portion of the gate of the vertical transfer transistor is C-shaped, the gate surrounds the active region, and the photodiode is connected to the floating diffusion region through the active region to form a readout channel for the photodiode.
[0007] Preferably, it further includes:
[0008] Etch the semiconductor substrate outside the vertical transfer transistor and the semiconductor substrate outside the floating diffusion region adjacent to the vertical transfer transistor to reduce the capacitance of the floating diffusion region and the capacitance of the vertical transfer transistor.
[0009] Preferably, it further includes:
[0010] The gate portion or all of the gate in the vertical transfer transistor near the floating diffusion region is over-etched to more than 100 angstroms below the surface of the active region to reduce the electric field strength between the vertical transfer transistor and the floating diffusion region, as well as the electric field strength between the vertical transfer transistor and the active region surrounded by the gate.
[0011] Preferably, it further includes:
[0012] The distance from the middle of the edge of the gate of the vertical transfer transistor near the floating diffusion region to the center of the floating diffusion region is greater than the distance from the line connecting the two ends of the gate near the floating diffusion region to the floating diffusion region, so as to reduce the electric field strength between the vertical transfer transistor and the floating diffusion region.
[0013] Preferably, it includes:
[0014] A semiconductor substrate is etched to form shallow trenches, and a dielectric material is filled into the shallow trenches to form a shallow trench isolation structure.
[0015] The dielectric material in the shallow trench isolation structure is etched down to the bottom of the shallow trench, and the gate material is filled in. The gate of the vertical transfer transistor is formed by etching the gate material once.
[0016] Preferably, it further includes:
[0017] The horizontal gate at the top of the vertical transfer transistor is made of the same material as the vertical gate located inside the trench. The gate of the C-shaped vertical transfer transistor surrounds the active region where the tap of the photodiode is located, and the opening of the C-shaped vertical transfer transistor faces the floating diffusion region.
[0018] Preferably, the width of the active region at the C-shaped opening of the gate of the vertical transfer transistor is smaller than the width at the center surrounded by the gate of the vertical transfer transistor.
[0019] Preferably, the gate of the vertical transfer transistor corresponds one-to-one with the active region it surrounds.
[0020] Preferably, the gate material comprises one or more combinations of polycrystalline silicon, doped semiconductor material, and metal material.
[0021] The present invention also provides an image sensor in which the vertical transfer transistor is formed using the vertical transfer transistor formation method described above.
[0022] This invention proposes a novel image sensor formation method based on the above-described scheme, which improves the control capability of the vertical transfer transistor (VLT). In this scheme, the gate of the VLT is designed in a C-shape, increasing the control area of the readout channel from the photodiode to the floating diffusion region, thereby enhancing the control capability of the VLT and thus improving its readout efficiency. Attached Figure Description
[0023] Other features, objects, and advantages of the invention will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings.
[0024] Figures 1 to 3 are schematic diagrams of the structure in a vertical transfer transistor formation method according to the present invention.
[0025] Throughout the figures, the same or similar reference numerals denote the same or similar devices (modules) or steps. Detailed Implementation
[0026] The present invention provides a method for forming a vertical transfer transistor (VTG), wherein, as shown in FIG1, at least a portion of the gate 200 of the vertical transfer transistor (VTG) is designed in a C-shape. For example, a portion of the gate 200 located in a trench can be designed in a C-shape, and the gate 200 surrounds an active region AA. A photodiode (PD) is connected to a floating diffusion region (FD) through the active region AA to form a readout channel for the photodiode (PD).
[0027] To achieve the C-shaped gate design, in a preferred embodiment, as shown in FIG2, the distance L1 from the middle of the edge of the vertical transfer transistor (VTG) gate 200 near the center of the floating diffusion region (FD) to the center of the floating diffusion region (FD) is designed to be greater than the distance L2 from the line connecting the two endpoints of the gate (VTG) near the two endpoints of the floating diffusion region (FD) to the floating diffusion region (FD), thereby reducing the electric field strength between the vertical transfer transistor (VTG) and the floating diffusion region (FD). Also preferably, as shown in FIG3, the width W1 of the active region AA at the opening of the C-shape of the vertical transfer transistor (VTG) gate 200 is smaller than the width W2 at the center surrounded by the vertical transfer transistor (VTG) gate 200.
[0028] Specifically, in an optional embodiment, when forming the vertical transfer transistor, the semiconductor substrate 100 outside the vertical transfer transistor (VTG) and the semiconductor substrate 100 outside the floating diffusion region (FD) adjacent to the vertical transfer transistor (VTG) are etched to reduce the capacitance of the floating diffusion region (FD) and the capacitance of the vertical transfer transistor (VTG).
[0029] Furthermore, in a preferred embodiment, a portion or all of the gate 200 of the vertical transfer transistor (VTG) near the floating diffusion region (FD) can be over-etched to more than 100 angstroms below the surface of the active region AA, in order to reduce the electric field strength between the vertical transfer transistor (VTG) and the floating diffusion region (FD), as well as the electric field strength between the vertical transfer transistor (VTG) and the active region (AA) surrounded by the gate 200.
[0030] In an optional embodiment, the horizontal gate at the top of the vertical transfer transistor (VTG) is made of the same material as the vertical gate located inside the trench. For example, the gate material can be one or more combinations of polysilicon, doped semiconductor material, and metal material. The gate 200 of the C-shaped vertical transfer transistor (VTG) surrounds the active region AA where the tap of the photodiode (PD) is located, and the opening of the C-shaped vertical transfer transistor (VTG) faces the floating diffusion region (FD). Also preferably, the gate 200 of the vertical transfer transistor (VTG) corresponds one-to-one with the active region AA it surrounds.
[0031] In an optional embodiment, during the formation of the vertical transfer transistor (VTG), a shallow trench can be formed by first etching the semiconductor substrate 100, and a dielectric material can be filled in the shallow trench to form a shallow trench isolation structure; then the dielectric material in the shallow trench isolation structure is etched down to the bottom of the shallow trench, and a gate material is filled in. The gate 200 of the vertical transfer transistor (VTG) is formed by etching the gate material once.
[0032] The present invention also provides an image sensor in which the vertical transfer transistor is formed using the vertical transfer transistor formation method described above.
[0033] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the invention. Therefore, the embodiments should be considered exemplary and not restrictive in any way. Furthermore, it is clear that the word "comprising" does not exclude other elements and steps, and the word "a" does not exclude a plural. Multiple elements recited in the apparatus claims may also be implemented by a single element. The terms "first," "second," etc., are used to denote names and do not indicate any particular order.
Claims
1. A method for forming a vertical transfer transistor, characterized in that, include: At least a portion of the gate of the vertical transfer transistor is C-shaped, the gate surrounds the active region, and the photodiode is connected to the floating diffusion region through the active region to form a readout channel for the photodiode.
2. The method of forming a vertical transfer transistor of claim 1, wherein, Also includes: Etch the semiconductor substrate outside the vertical transfer transistor and the semiconductor substrate outside the floating diffusion region adjacent to the vertical transfer transistor to reduce the capacitance of the floating diffusion region and the capacitance of the vertical transfer transistor.
3. The method of forming a vertical transfer transistor of claim 1, wherein, Also includes: The gate portion or all of the gate in the vertical transfer transistor near the floating diffusion region is over-etched to more than 100 angstroms below the surface of the active region to reduce the electric field strength between the vertical transfer transistor and the floating diffusion region, as well as the electric field strength between the vertical transfer transistor and the active region surrounded by the gate.
4. The method of forming a vertical transfer transistor of claim 1, wherein, Also includes: The distance from the middle of the edge of the gate of the vertical transfer transistor near the floating diffusion region to the center of the floating diffusion region is greater than the distance from the line connecting the two ends of the gate near the floating diffusion region to the floating diffusion region, so as to reduce the electric field strength between the vertical transfer transistor and the floating diffusion region.
5. The method of forming a vertical transfer transistor of claim 1, wherein, include: A semiconductor substrate is etched to form shallow trenches, and a dielectric material is filled into the shallow trenches to form a shallow trench isolation structure. The dielectric material in the shallow trench isolation structure is etched down to the bottom of the shallow trench, and the gate material is filled in. The gate of the vertical transfer transistor is formed by etching the gate material once.
6. The method for forming a vertical transfer transistor according to claim 1, wherein Also includes: The horizontal gate at the top of the vertical transfer transistor is made of the same material as the vertical gate located inside the trench. The gate of the C-shaped vertical transfer transistor surrounds the active region where the tap of the photodiode is located, and the opening of the C-shaped vertical transfer transistor faces the floating diffusion region.
7. The method of forming a vertical transfer transistor of claim 6, wherein, The width of the active region at the C-shaped opening of the gate of the vertical transfer transistor is smaller than the width at the center surrounded by the gate of the vertical transfer transistor.
8. The method of forming a vertical transfer transistor of claim 1, wherein, The gate of the vertical transfer transistor corresponds one-to-one with the active region it surrounds.
9. The method for forming a vertical transfer transistor according to claim 5, wherein The gate material comprises one or more combinations of polycrystalline silicon, doped semiconductor materials, and metallic materials.
10. An image sensor, comprising: The vertical transfer transistor in the image sensor is formed using the method for forming a vertical transfer transistor as described in claims 1 to 9.