Display substrate and display apparatus

Abstract

A display substrate and a display apparatus. The display substrate comprises a plurality of sub-pixels, data signal lines, and a second signal line. The plurality of sub-pixels comprise a first sub-pixel which emits red light, a third sub-pixel which emits blue light, and a second sub-pixel and a fourth sub-pixel which emit green light. The data signal lines comprise a first data signal line connected to a pixel driving circuit of the first sub-pixel, a second data signal line connected to pixel driving circuits of the second sub-pixel and the fourth sub-pixel, and a third data signal line connected to a pixel driving circuit of the third sub-pixel. Pixel columns comprise a first pixel column and a second pixel column. The first pixel column comprises the first data signal line, the third data signal line, the first sub-pixel, and the third sub-pixel. The second pixel column comprises the second data signal line, the second signal line, the second sub-pixel, and the fourth sub-pixel, and the second signal line transmits a constant voltage signal or transmits a data signal.

Description

Display substrate and display device

[0001] This application claims priority to Chinese Patent Application No. 202411932396.3, filed on December 25, 2024, entitled "Display Substrate and Display Device", the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This article relates to, but is not limited to, the field of display technology, specifically to a display substrate and a display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] On one hand, this disclosure provides a display substrate, including a display area and a bonding area located on at least one side of the display area. The display area includes a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns, a plurality of data signal lines, and at least one second signal line. At least one sub-pixel includes a pixel driving circuit and a light-emitting device connected to the pixel driving circuit. The plurality of sub-pixels include a first sub-pixel emitting red light, a third sub-pixel emitting blue light, and a second and fourth sub-pixels emitting green light. The plurality of data signal lines include a first data signal line connected to the pixel driving circuit of the first sub-pixel, and a second data signal line connected to the pixel driving circuits of the second and fourth sub-pixels. The data signal line and the third data signal line connected to the pixel driving circuit of the third sub-pixel; the plurality of pixel columns include a first pixel column and a second pixel column arranged alternately in a first direction, the first pixel column including the first data signal line, the third data signal line, and the first sub-pixel and the third sub-pixel arranged alternately in a second direction, the second pixel column including the second data signal line, the second signal trace, and the second sub-pixel and the fourth sub-pixel arranged alternately in a second direction, the first direction and the second direction intersect; the second signal trace is a signal trace that transmits a constant voltage signal, or the second signal trace and the second data signal line transmit the same data signal.

[0006] In an exemplary embodiment, the ratio of the width of the second data signal line to the width of the first data signal line is 1.2 to 1.5, and the ratio of the width of the second data signal line to the width of the third data signal line is 1.2 to 1.5, wherein the width is the dimension in the first direction.

[0007] In an exemplary embodiment, in at least one first pixel column, the first data signal line is connected to the pixel driving circuit of the first sub-pixel via a first data connection block, and the third data signal line is connected to the pixel driving circuit of the third sub-pixel via a third data connection block; the first data connection block is disposed on the side of the first data signal line close to the third data signal line and is connected to the first data signal line; the third data connection block is disposed on the side of the third data signal line close to the first data signal line and is connected to the third data signal line.

[0008] In an exemplary embodiment, at least one first pixel column further includes a first power trace and a second power trace, the first power trace and the second power trace being configured to provide a first power signal to a connected pixel driving circuit; the first power trace is connected to the pixel driving circuit of the first sub-pixel in the pixel column, and the second power trace is connected to the pixel driving circuit of the third sub-pixel in the pixel column.

[0009] In an exemplary embodiment, the binding area includes at least a plurality of data leads, the second data signal line is directly connected to the data lead, one of the first data signal line and the third data signal line is directly connected to the data lead, and the other of the first data signal line and the third data signal line is connected to the data lead via a data connection line.

[0010] In an exemplary embodiment, at least one of the data connection lines includes a first connection line extending along the first direction and a second connection line extending along the second direction. A first end of the first connection line is connected to the first data signal line or the third data signal line, a second end of the first connection line is connected to the first end of the second connection line, and a second end of the second connection line is connected to the data lead-out line. In at least one second pixel column, a break is provided between the second connection line and the second signal trace.

[0011] In an exemplary embodiment, the plurality of first pixel columns are a first type of pixel columns, and the first data signal line in the first type of pixel column is connected to the first connection line; or, the plurality of first pixel columns are a second type of pixel columns, and the third data signal line in the second type of pixel column is connected to the first connection line.

[0012] In an exemplary embodiment, the plurality of first pixel columns include a plurality of first-type pixel columns and a plurality of second-type pixel columns alternately arranged in the first direction, wherein the first data signal line in the first-type pixel column is connected to the first connection line, and the third data signal line in the second-type pixel column is connected to the first connection line.

[0013] In an exemplary embodiment, in at least one first pixel column and a second pixel column adjacent to the first pixel column, the third data signal line is connected to the first connecting line; the third data signal line is disposed on the side of the first data signal line away from the second data signal line, and the second connecting line is disposed on the side of the second data signal line away from the first data signal line; or, the third data signal line is disposed on the side of the first data signal line close to the second data signal line, and the second connecting line is disposed on the side of the second data signal line close to the first data signal line.

[0014] In an exemplary embodiment, in at least one first pixel column and a second pixel column adjacent to the first pixel column, the first data signal line is connected to the first connecting line; the first data signal line is disposed on the side of the third data signal line away from the second data signal line, and the second connecting line is disposed on the side of the second data signal line away from the third data signal line; or, the first data signal line is disposed on the side of the third data signal line close to the second data signal line, and the second connecting line is disposed on the side of the second data signal line close to the third data signal line.

[0015] In an exemplary embodiment, multiple first connecting lines are respectively connected to the first data signal line or the third data signal line through vias; from the side edge of the display area to the center line of the display area, the distance between the multiple vias and the lower edge of the display area gradually increases, or the distance between the multiple vias and the lower edge of the display area gradually decreases, the lower edge of the display area is the edge of the display area closer to the binding area, the side edge of the display area is the edge of the display area closer to the frame area, and the center line of the display area is a straight line that bisects the display area in the first direction and extends along the second direction.

[0016] In an exemplary embodiment, multiple first connecting lines are respectively disposed between the last pixel row and the lower edge of the display area, and are connected to the first data signal line or the third data signal line through vias, with the multiple vias being flush in the first direction; the last pixel row is the pixel row in the display area that is closest to the binding area, and the lower edge of the display area is the edge of the display area closer to the binding area.

[0017] In an exemplary embodiment, for a first data signal line and a second connection line connected to the same first connection line, the first pixel column where the first data signal line is located and the second pixel column where the second connection line is located are adjacent pixel columns; or, for a third data signal line and a second connection line connected to the same first connection line, the first pixel column where the third data signal line is located and the second pixel column where the second connection line is located are adjacent pixel columns.

[0018] In an exemplary embodiment, for a first data signal line and a second connection line connected to the same first connection line, there are multiple first pixel columns and multiple second pixel columns between the first pixel column where the first data signal line is located and the second pixel column where the second connection line is located; or, for a third data signal line and a second connection line connected to the same first connection line, there are multiple first pixel columns and multiple second pixel columns between the first pixel column where the third data signal line is located and the second pixel column where the second connection line is located.

[0019] In an exemplary embodiment, the display substrate includes a plurality of conductive layers in a direction perpendicular to the display substrate. The first connecting line and the second connecting line are disposed in different conductive layers, or the first connecting line and the second connecting line are disposed in the same conductive layer.

[0020] In an exemplary embodiment, the display area further includes at least one auxiliary signal trace extending along the second direction, the auxiliary signal trace being disposed between adjacent first pixel columns and second pixel columns, and the auxiliary signal trace being a signal trace for transmitting a constant voltage signal.

[0021] In an exemplary embodiment, the binding area includes at least a plurality of data leads, wherein the first data signal line, the second data signal line, and the third data signal line are directly connected to the data leads.

[0022] In an exemplary embodiment, the first pixel column further includes a first power line, and the second pixel column further includes a third power trace. The first power line and the third power trace are configured to provide a first power signal to the connected pixel driving circuit. The first power line is connected to the pixel driving circuit of the first sub-pixel in the first pixel column, and the third power trace is connected to the pixel driving circuit of the third sub-pixel in the first pixel column. Alternatively, the first power line is connected to the pixel driving circuit of the third sub-pixel in the first pixel column, and the third power trace is connected to the pixel driving circuit of the first sub-pixel in the first pixel column.

[0023] In an exemplary embodiment, the display area further includes at least one auxiliary signal trace extending along the second direction, the auxiliary signal trace being disposed between adjacent first pixel columns and second pixel columns; the first pixel column further includes a first power line, the first power line and the auxiliary signal trace being configured to provide a first power signal to a connected pixel driving circuit; the first power line is connected to the pixel driving circuit of the first sub-pixel in the first pixel column, and the auxiliary signal trace is connected to the pixel driving circuit of the third sub-pixel in the first pixel column, or, the first power line is connected to the pixel driving circuit of the third sub-pixel in the first pixel column, and the auxiliary signal trace is connected to the pixel driving circuit of the first sub-pixel in the first pixel column.

[0024] On the other hand, this disclosure also provides a display device including the aforementioned display substrate.

[0025] After reading and understanding the accompanying diagrams and detailed descriptions, other aspects can be understood. Attached Figure Description

[0026] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0027] Figure 1 is a schematic diagram of the structure of a display device;

[0028] Figure 2 is a schematic diagram of a display substrate;

[0029] Figure 3 is a schematic diagram of the planar structure of the display area in a display substrate;

[0030] Figure 4 is a schematic cross-sectional view of the display area in a display substrate;

[0031] Figure 5 is a schematic diagram of the equivalent circuit of a pixel driving circuit;

[0032] Figure 6A is a schematic diagram of the arrangement of a circuit unit according to an exemplary embodiment of the present disclosure;

[0033] Figure 6B is a schematic diagram of the arrangement of light-emitting units according to an exemplary embodiment of the present disclosure;

[0034] Figure 6C is a schematic diagram of the connection between a circuit unit and a light-emitting unit according to an exemplary embodiment of the present disclosure;

[0035] Figure 7 is a schematic diagram of the planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0036] Figure 8 is a schematic diagram of the connection structure between the data signal line and the data connection line in Figure 7;

[0037] Figure 9 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0038] Figure 10 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0039] Figure 11 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0040] Figure 12 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0041] Figure 13 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0042] Figure 14 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0043] Figure 15 is a schematic diagram of the connection structure between the data signal line and the data connection line in Figure 14;

[0044] Figure 16 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0045] Figure 17 is a schematic diagram of the connection structure between the data signal line and the data connection line in Figure 16;

[0046] Figure 18 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0047] Figure 19 is a schematic diagram of the connection structure between the data signal line and the data connection line in Figure 18;

[0048] Figure 20 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0049] Figure 21 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0050] Figure 22 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure.

[0051] Explanation of reference numerals in the attached figures:

[0052] 60—Data signal line; 61—First data signal line; 62—Second data signal line;

[0053] 63—Third data signal line; 64—Data connection electrode; 65—Second electrode plate;

[0054] 70—Data lead; 71—First connection line; 72—Second connection line;

[0055] 73—Third power supply trace; 80—First power supply trace; 81—First power supply trace;

[0056] 82—Second power supply trace; 91—First signal trace; 92—Second signal trace;

[0057] 93—Auxiliary signal trace; 100—Display area; 101—Substrate;

[0058] 102—Driving structure layer; 103—Light-emitting structure layer; 104—Encapsulation structure layer;

[0059] 200—Bounding area; 300—Border area. Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0061] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0062] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0063] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0064] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0065] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0066] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0067] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it enables the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0068] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0069] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0070] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfered corners, curved edges, and other variations.

[0071] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0072] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple light-emitting signal lines (E1 to Eo). n, m, and o can be natural numbers. The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to the scan signal lines, the light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and clock signals, transmit stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to grayscale values ​​to data signal lines D1 to Dn on a pixel-by-pixel basis. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, a scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal. An emissive driver can generate transmit signals to be provided to the emissive signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from a timing controller. For example, the emissive driver can sequentially provide transmit signals with off-level pulses to the emissive signal lines E1 to Eo. For example, the emissive driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals, provided in the form of off-level pulses, to the next stage circuit under the control of a clock signal. In an exemplary embodiment, a pixel array can be disposed on a display substrate.

[0073] Figure 2 is a schematic diagram of a display substrate. As shown in Figure 2, the display substrate may include a display area 100, a bonding area 200 located on one side of the display area 100, and a border area 300 located on other sides of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area, including multiple sub-pixels Pxij that make up a pixel array. The multiple sub-pixels Pxij are configured to display dynamic or still images, and the display area 100 may be referred to as the active area (AA). In an exemplary embodiment, the display substrate may be a flexible substrate, and therefore the display substrate may be deformable, such as being rolled, bent, folded, or rolled up.

[0074] In an exemplary embodiment, the bonding region 200 may include a lead area, a bending area, a driver chip area, and a bonding pin area arranged sequentially along a direction away from the display area. The lead area is connected to the display area 100 and includes at least data leads. The bending area is connected to the lead area and may include at least a composite insulating layer with grooves configured to bend the bonding area to the back side of the display area. The driver chip area may include an integrated circuit (IC) configured to connect to multiple data leads. The bonding pin area may include bonding pads configured to bond to an external flexible printed circuit (FPC).

[0075] In an exemplary embodiment, the bezel region 300 may include an upper bezel region on the side away from the bonding region and a side bezel region located between the bonding region and the upper bezel region. The side bezel region may include a circuit region, a power line region, a crack dam region, and a cutting region arranged sequentially along a direction away from the display region 100. The circuit region is connected to the display region 100 and may include at least a gate driving circuit connected to scan signal lines and light emission signal lines in the display region 100. The power line region is connected to the circuit region and may include at least bezel power leads extending along a direction parallel to the side edge of the display region and connected to the cathode in the display region 100. The crack dam region is connected to the power line region and may include at least a plurality of cracks formed on the composite insulating layer. The cutting region is connected to the crack dam region and may include at least a cutting groove formed on the composite insulating layer, the cutting groove being configured so that, after all film layers of the display substrate have been prepared, a cutting device cuts along the cutting groove.

[0076] In an exemplary embodiment, the lead wire area in the bonding area 200 and the power line area in the border area 300 may be provided with isolation dams. The isolation dams may extend along a direction parallel to the edge of the display area to form a ring structure surrounding the display area 100. The edge of the display area is the edge of the display area that is close to the bonding area or close to the border area.

[0077] In an exemplary embodiment, the display area 100 may include multiple data signal lines 60, and the lead-out area of ​​the bonding area 200 may include multiple data lead-out lines 70. The multiple data signal lines 60 may be sequentially arranged at predetermined intervals in a first direction X. At least one data signal line 60 is connected to multiple pixel driving circuits in a pixel column, and the data signal line 60 is configured to provide data signals to the connected pixel driving circuits. The multiple data lead-out lines 70 extend in a direction away from the display area. The first end of each data lead-out line 70 is connected to a corresponding data signal line 60 in the display area 100, and the second end of each data lead-out line 70 may extend in a fan-out manner to the driver chip area and connect to the integrated circuit, so that the data signal output by the integrated circuit is transmitted to the data signal line through the data lead-out line.

[0078] In an exemplary embodiment, the display area may have a center line O, and multiple data signal lines 60 and multiple data lead-out lines 70 on the display substrate may be symmetrically arranged relative to the center line O. The center line O may be a straight line that bisects the display area in the first direction X and extends along the second direction Y.

[0079] Figure 3 is a schematic diagram of the planar structure of a display area in a display substrate. As shown in Figure 3, the display area may include multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to a scan signal line, a light-emitting signal line, and a data signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting unit under the control of the scan signal line and the light-emitting signal line. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the sub-pixel. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0080] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel (R) that emits red light, the second sub-pixel P2 and the fourth sub-pixel P4 can be green sub-pixels (G) that emit green light, and the third sub-pixel P3 can be a blue sub-pixel (B) that emits blue light. The four sub-pixels can be arranged in an RGBG pattern.

[0081] Figure 4 is a cross-sectional schematic diagram of a display area in a display substrate, illustrating the structure of three sub-pixels in the display area. As shown in Figure 4, in the direction perpendicular to the display substrate, the display area may include a driving structure layer 102 disposed on the substrate 101, a light-emitting structure layer 103 disposed on the side of the driving structure layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display area may include other film layers, such as a touch structure layer, etc., which are not limited herein.

[0082] In an exemplary embodiment, the substrate 101 can be a flexible substrate or a rigid substrate. The driving structure layer 102 can include multiple circuit units, each of which can include at least a pixel driving circuit composed of multiple transistors and storage capacitors. The light-emitting structure layer 103 can include multiple light-emitting units, each of which can include a light-emitting device. The light-emitting device can include at least an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit of the corresponding circuit unit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of the corresponding color under the driving of the anode and cathode. The encapsulation structure layer 104 can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers can be made of inorganic materials, and the second encapsulation layer can be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers, forming an inorganic / organic / inorganic material stacked structure, which can ensure that external moisture cannot enter the light-emitting structure layer 103.

[0083] Figure 5 is an equivalent circuit diagram of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in Figure 5, the pixel driving circuit may include seven transistors (first transistor T1 to seventh transistor T7) and one storage capacitor C. The pixel driving circuit is connected to seven signal lines (first scan signal line S1, second scan signal line S2, light emission signal line EM, first initial signal line INIT1, second initial signal line INIT2, data signal line DATA, and first power supply line VDD).

[0084] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the second terminal of a first transistor, the first terminal of a second transistor T2, the gate electrode of a third transistor T3, and the first terminal of a storage capacitor C. The second node N2 is connected to the first terminal of a third transistor T3, the second terminal of a fourth transistor T4, and the second terminal of a fifth transistor T5. The third node N3 is connected to the second terminals of a second transistor T2, a third transistor T3, and a sixth transistor T6. The fourth node N4 is connected to the second terminal of a sixth transistor T6 and a seventh transistor T7.

[0085] In an exemplary embodiment, the first end of the storage capacitor C is connected to the first node N1, and the second end of the storage capacitor C is connected to the first power line VDD.

[0086] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor is connected to the first node N1.

[0087] In an exemplary embodiment, the gate electrode of the second transistor T2 is connected to the first scan signal line S1, the first terminal of the second transistor T2 is connected to the first node N1, and the second terminal of the second transistor T2 is connected to the third node N3.

[0088] In an exemplary embodiment, the gate electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3.

[0089] In an exemplary embodiment, the gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line DATA, and the second electrode of the fourth transistor T4 is connected to the second node N2.

[0090] In an exemplary embodiment, the gate electrode of the fifth transistor T5 is connected to the light-emitting signal line EM, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2.

[0091] In an exemplary embodiment, the gate electrode of the sixth transistor T6 is connected to the light-emitting signal line EM, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0092] In an exemplary embodiment, the gate electrode of the seventh transistor T7 is connected to the second scan signal line S2, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0093] In an exemplary embodiment, the first electrode of the light-emitting device EL is connected to the fourth node N4, and the second electrode of the light-emitting device EL is connected to the second power line VSS. The light-emitting device EL can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or it can be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0094] In an exemplary embodiment, the first power line VDD is configured to provide a constant first power signal to the pixel driving circuit, and the second power line VSS is configured to provide a constant second power signal to the light-emitting device, wherein the first power signal is a high-level signal and the second power signal is a low-level signal. The first initial signal line INIT1 and the second initial signal line INIT2 are configured to provide a constant first initial signal and a constant second initial signal to the pixel driving circuit, respectively, which is not limited herein.

[0095] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 in the pixel driving circuit can be either P-type transistors or N-type transistors. Using the same type of transistor in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include both P-type and N-type transistors.

[0096] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be a low-temperature polycrystalline silicon (LTPS) thin-film transistor, or an oxide thin-film transistor, or a combination of both. The active layer of the LTPS is made of low-temperature polycrystalline silicon, while the active layer of the oxide thin-film transistor is made of oxide. LTPS transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating LTPS and oxide thin-film transistors onto a single display substrate to form an LTPO (Low Temperature Polycrystalline + Oxide) display substrate leverages the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0097] An exemplary embodiment of this disclosure provides a display substrate, including a display area and a bonding area located on at least one side of the display area. The display area includes a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns, a plurality of data signal lines, and at least one second signal line. At least one sub-pixel includes a pixel driving circuit and a light-emitting device connected to the pixel driving circuit. The plurality of sub-pixels includes a first sub-pixel emitting red light, a third sub-pixel emitting blue light, and a second and fourth sub-pixels emitting green light. The plurality of data signal lines include a first data signal line connected to the pixel driving circuit of the first sub-pixel, and a second data signal line connected to the pixel driving circuits of the second and fourth sub-pixels. The data signal line and the third data signal line connected to the pixel driving circuit of the third sub-pixel; the plurality of pixel columns include a first pixel column and a second pixel column arranged alternately in a first direction, the first pixel column including the first data signal line, the third data signal line, and the first sub-pixel and the third sub-pixel arranged alternately in a second direction, the second pixel column including the second data signal line, the second signal trace, and the second sub-pixel and the fourth sub-pixel arranged alternately in a second direction, the first direction and the second direction intersect; the second signal trace is a signal trace that transmits a constant voltage signal, or the second signal trace and the second data signal line transmit the same data signal.

[0098] In an exemplary embodiment, the ratio of the width of the second data signal line to the width of the first data signal line is 1.2 to 1.5, and the ratio of the width of the second data signal line to the width of the third data signal line is 1.2 to 1.5, wherein the width is the dimension in the first direction.

[0099] In an exemplary embodiment, in at least one first pixel column, the first data signal line is connected to the pixel driving circuit of the first sub-pixel via a first data connection block, and the third data signal line is connected to the pixel driving circuit of the third sub-pixel via a third data connection block; the first data connection block is disposed on the side of the first data signal line close to the third data signal line and is connected to the first data signal line; the third data connection block is disposed on the side of the third data signal line close to the first data signal line and is connected to the third data signal line.

[0100] In an exemplary embodiment, at least one first pixel column further includes a first power trace and a second power trace, the first power trace and the second power trace being configured to provide a first power signal to a connected pixel driving circuit; the first power trace is connected to the pixel driving circuit of the first sub-pixel in the pixel column, and the second power trace is connected to the pixel driving circuit of the third sub-pixel in the pixel column.

[0101] In an exemplary embodiment, the binding area includes at least a plurality of data leads, the second data signal line is directly connected to the data lead, one of the first data signal line and the third data signal line is directly connected to the data lead, and the other of the first data signal line and the third data signal line is connected to the data lead via a data connection line.

[0102] In an exemplary embodiment, the binding area includes at least a plurality of data leads, wherein the first data signal line, the second data signal line, and the third data signal line are directly connected to the data leads.

[0103] Figure 6A is a schematic diagram of the arrangement of circuit units according to an exemplary embodiment of the present disclosure, Figure 6B is a schematic diagram of the arrangement of light-emitting units according to an exemplary embodiment of the present disclosure, and Figure 6C is a schematic diagram of the connection between circuit units and light-emitting units according to an exemplary embodiment of the present disclosure. As shown in Figures 6A, 6B, and 6C, on a plane parallel to the display substrate, the driving structure layer may include multiple circuit units forming multiple circuit rows and multiple circuit columns. A circuit row may include multiple circuit units arranged sequentially along a first direction X, and a circuit column may include multiple circuit units arranged sequentially along a second direction Y. Each circuit unit may include at least a pixel driving circuit. The light-emitting structure layer may include multiple light-emitting units forming multiple light-emitting rows and multiple light-emitting columns. A light-emitting row may include multiple light-emitting units arranged sequentially along the first direction X, and a light-emitting column may include multiple light-emitting units arranged sequentially along the second direction Y. Each light-emitting unit may include at least a light-emitting device. In an exemplary embodiment, the direction of the circuit rows and light-emitting rows may be the first direction X, and the direction of the circuit columns and light-emitting columns may be the second direction Y, with the first direction X intersecting the second direction Y.

[0104] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to a pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to a light-emitting device. In exemplary embodiments, the orthographic projection of the light-emitting unit on the substrate and the orthographic projection of the circuit unit on the substrate may at least partially overlap, or the orthographic projection of the light-emitting unit on the substrate and the orthographic projection of the circuit unit on the substrate may not overlap.

[0105] In an exemplary embodiment, "first direction X" in this disclosure and the accompanying drawings refers to a direction from left to right. In the left region of the display area, first direction X refers to the direction from the left edge of the display area to the center line of the display area; in the right region of the display area, first direction X refers to the direction from the center line of the display area to the right edge of the display area.

[0106] In an exemplary embodiment, the plurality of circuit units may include a first circuit unit Q1, a second circuit unit Q2, a third circuit unit Q3, and a fourth circuit unit Q4. In the first direction X, the first circuit unit Q1, the second circuit unit Q2, the third circuit unit Q3, and the fourth circuit unit Q4 may be periodically arranged in the first direction X to form circuit rows, with the circuit units in odd-numbered circuit rows and even-numbered circuit rows being staggered. In the second direction Y, the first circuit unit Q1 and the third circuit unit Q3 are alternately arranged in the second direction Y to form a first circuit column, and the second circuit unit Q2 and the fourth circuit unit Q4 are alternately arranged in the second direction Y to form a second circuit column.

[0107] In an exemplary embodiment, the plurality of light-emitting units may include a first light-emitting unit F1, a second light-emitting unit F2, a third light-emitting unit F3, and a fourth light-emitting unit F4. In the first direction X, the first light-emitting unit F1, the second light-emitting unit F2, the third light-emitting unit F3, and the fourth light-emitting unit F4 may be periodically arranged in the first direction X to form light-emitting rows, with the light-emitting units in odd-numbered light-emitting rows and even-numbered light-emitting rows being staggered. In the second direction Y, the first light-emitting unit F1 and the third light-emitting unit F3 are alternately arranged in the second direction Y to form a first light-emitting column, and the second light-emitting unit F2 and the fourth light-emitting unit F4 are alternately arranged in the second direction Y to form a second light-emitting column.

[0108] In an exemplary embodiment, the first light-emitting unit F1 may include at least a first anode, the second light-emitting unit F2 may include at least a second anode, the third light-emitting unit F3 may include at least a third anode, and the fourth light-emitting unit F4 may include at least a fourth anode. The pixel driving circuit in the first circuit unit Q1 is connected to the first anode of the first light-emitting unit F1 to form a first sub-pixel; the pixel driving circuit in the second circuit unit Q2 is connected to the second anode of the second light-emitting unit F2 to form a second sub-pixel; the pixel driving circuit in the third circuit unit Q3 is connected to the third anode of the third light-emitting unit F3 to form a third sub-pixel; and the pixel driving circuit in the fourth circuit unit Q4 is connected to the fourth anode of the fourth light-emitting unit F4 to form a fourth sub-pixel.

[0109] In an exemplary embodiment, a sub-pixel is formed by a connected circuit unit and a light-emitting unit; a pixel row is formed by a corresponding circuit row and a light-emitting row; a first pixel column is formed by a corresponding first circuit column and a first light-emitting column; and a second pixel column is formed by a corresponding second circuit column and a second light-emitting column. In the first direction X, the first, second, third, and fourth sub-pixels can be periodically arranged in the first direction X to form pixel rows, with corresponding sub-pixels in odd-numbered pixel rows and even-numbered pixel rows being staggered. In the second direction Y, the first and third sub-pixels are alternately arranged in the second direction Y to form a first pixel column, and the second and fourth sub-pixels are alternately arranged to form a second pixel column.

[0110] In an exemplary embodiment, the first light-emitting unit F1 can be a light-emitting unit that emits red light (which can be called a red light-emitting unit), the second light-emitting unit F2 can be a light-emitting unit that emits green light (which can be called a first green light-emitting unit), the third light-emitting unit F3 can be a light-emitting unit that emits blue light (which can be called a blue light-emitting unit), and the fourth light-emitting unit F4 can be a light-emitting unit that emits green light (which can be called a second green light-emitting unit). Thus, the first circuit unit Q1 is the circuit unit whose pixel driving circuit drives the red light-emitting unit (which can be called a red circuit unit), the second circuit unit Q2 is the circuit unit whose pixel driving circuit drives the first green light-emitting unit (which can be called a first green circuit unit), the third circuit unit Q3 is the circuit unit whose pixel driving circuit drives the blue light-emitting unit (which can be called a blue circuit unit), and the fourth circuit unit Q4 is the circuit unit whose pixel driving circuit drives the second green light-emitting unit (which can be called a second green circuit unit). The first circuit column is a circuit whose circuit units are connected to light-emitting units that emit red and blue light rays; it can be called the red-blue circuit column. The second circuit column is a circuit whose circuit units are connected to light-emitting units that emit green light rays; it can be called the green circuit column. The first pixel column is a pixel column that emits red and blue light rays; it can be called the red-blue pixel column. The second pixel column is a pixel column that emits green light rays; it can be called the green pixel column.

[0111] In an exemplary embodiment, the shape of the circuit unit may include any one or more of the following: triangle, rectangle, rhombus, pentagon, and hexagon, and the shape of the light-emitting unit may include any one or more of the following: triangle, rectangle, rhombus, pentagon, and hexagon.

[0112] Figure 7 is a schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure. As shown in Figure 7, in a plane parallel to the display substrate, the display substrate may include at least a display area 100, a bonding area 200 located on one side of the display area, and a border area located on other sides of the display area 100. In a plane perpendicular to the display substrate, the display substrate may include a driving structure layer disposed on a substrate, a light-emitting structure layer disposed on the side of the driving structure layer away from the substrate, and an encapsulation structure layer disposed on the side of the light-emitting structure layer away from the substrate. The driving structure layer may include multiple circuit units forming multiple circuit rows and multiple circuit columns. The circuit units may include at least pixel driving circuits. The light-emitting structure layer may include multiple light-emitting units forming multiple light-emitting rows and multiple light-emitting columns. The light-emitting units may include at least light-emitting devices. The light-emitting devices are connected to the corresponding pixel driving circuits and are configured to emit light of a corresponding brightness in response to the current output by the connected pixel driving circuits.

[0113] In this embodiment and subsequent embodiments, the left-side area of ​​the display area is used as an example. Sub-pixels are defined by circuit units, where one circuit unit is one sub-pixel, one circuit row is one pixel row, and one circuit column is one pixel column.

[0114] In some possible implementations, subpixels can be defined by light-emitting units, where one light-emitting unit is a subpixel, one light-emitting row is a pixel row, and one light-emitting column is a pixel column. This disclosure does not limit the scope of the implementation.

[0115] In an exemplary embodiment, the multiple circuit columns may include multiple first circuit columns (red and blue circuit columns) and multiple second circuit columns (green circuit columns). The first circuit columns and the second circuit columns may be alternately arranged in a first direction X. The first circuit column may include multiple first circuit units Q1 (red circuit units) and multiple third circuit units Q3 (blue circuit units). The first circuit units Q1 and the third circuit units Q3 may be alternately arranged in a second direction Y. The second circuit column may include multiple second circuit units Q2 (first green circuit units) and multiple fourth circuit units Q4 (second green circuit units). The second circuit units Q2 and the fourth circuit units Q4 may be alternately arranged in a second direction Y.

[0116] In an exemplary embodiment, the driving structure layer in the display area 100 may further include multiple data signal lines. The multiple data signal lines may include at least a first data signal line 61, a second data signal line 62, and a third data signal line 63. The shapes of the first data signal line 61, the second data signal line 62, and the third data signal line 63 may be straight lines or broken lines extending along the second direction Y, and are configured to provide data signals to the connected pixel driving circuit.

[0117] In an exemplary embodiment, the first data signal line 61 may be disposed in the first circuit column (first pixel column). The first data signal line 61 is connected to the pixel driving circuit of a plurality of first circuit units Q1 in the first circuit column, and provides data signals to the pixel driving circuit of the plurality of first circuit units Q1 in the first circuit column. Since the pixel driving circuit of the first circuit unit Q1 is connected to the first anode in the first light-emitting unit that emits red light, the first data signal line 61 is a data signal line for transmitting red image data signals.

[0118] In an exemplary embodiment, the third data signal line 63 may be disposed in the first circuit column (first pixel column). The third data signal line 63 is connected to the pixel driving circuit of the plurality of third circuit units Q3 in the first circuit column, and provides data signals to the pixel driving circuit of the plurality of third circuit units Q3 in the first circuit column. Since the pixel driving circuit of the third circuit unit Q3 is connected to the third anode in the third light-emitting unit that emits blue light, the third data signal line 63 is a data signal line for transmitting blue screen data signals.

[0119] In an exemplary embodiment, the second data signal line 62 may be disposed in the second circuit column (second pixel column). The second data signal line 62 is connected to the pixel driving circuits of the plurality of second circuit units Q2 and the plurality of fourth circuit units Q4 in the second circuit column, providing data signals to the pixel driving circuits of the plurality of second circuit units Q2 and the plurality of fourth circuit units Q4 in the second circuit column. Since the pixel driving circuit of the second circuit unit Q2 is connected to the second anode in the second light-emitting unit that emits green light, and the pixel driving circuit of the fourth circuit unit Q4 is connected to the fourth anode in the fourth light-emitting unit that emits green light, the second data signal line 62 is a data signal line for transmitting green image data signals.

[0120] In an exemplary embodiment, the driving structure layer in the display area 100 may further include multiple first connecting lines 71 and multiple second connecting lines 72. The shape of the first connecting lines 71 may be a straight line or a broken line extending along the first direction X, and they may be disposed in a circuit row or between two adjacent circuit rows. Multiple first connecting lines 71 may be arranged sequentially along the second direction Y. The shape of the second connecting lines 72 may be a straight line or a broken line extending along the second direction Y, and they may be disposed in a second circuit column. Multiple second connecting lines 72 may be arranged sequentially along the first direction X. The first end of the first connecting line 71 may be connected to the third data signal line 63 in the first circuit column via a via. After the first connecting line 71 extends along the first direction X or the opposite direction of the first direction X, the second end of the first connecting line 71 is connected to the first end of the second connecting line 72. After the second connecting line 72 extends along the second direction Y towards the bonding area 200, the second end of the second connecting line 72 is connected to the data lead-out line 70. In this disclosure, the interconnected first connecting lines 71 and second connecting lines 72 may be referred to as data connecting lines.

[0121] In an exemplary embodiment, multiple first connecting lines 71 can be respectively arranged in different circuit rows or between different adjacent circuit rows. A first distance can be maintained between the via that connects the first connecting line to the third data signal line and the lower edge BY of the display area. The lower edge BY of the display area can be the edge of the display area 100 near the bonding area 200, and the first distance can be a dimension in the second direction Y. In the left region of the display area, multiple first distances can gradually increase in the first direction X. In the right region of the display area, multiple first distances can gradually increase in the opposite direction of the first direction X, that is, from the side edge of the display area to the center line of the display area, the positions of multiple vias gradually move away from the bonding area 200. The side edge of the display area can be the edge of the display area near the side border area, and the center line of the display area can be a straight line that bisects the display area in the first direction X and extends along the second direction Y.

[0122] In an exemplary embodiment, for the third data signal line 63 and the second connection line 72 connected to the same first connection line 71, the first circuit column where the third data signal line 63 is located and the second circuit column where the second connection line 72 is located can be adjacent circuit columns.

[0123] In an exemplary embodiment, the plurality of first pixel columns (first circuit columns) in the display area of ​​this embodiment are all second type pixel columns, which means that the third data signal line in the pixel column is connected to the first connection line.

[0124] In an exemplary embodiment, the first data signal line 61, the second data signal line 62, and the third data signal line 63 in the display area can be divided into a first data signal line group and a second data signal line group according to whether they are connected to the first connecting line 71. The data signal lines in the first data signal line group are not connected to the first connecting line 71, while the data signal lines in the second data signal line group are connected to the first connecting line 71. In this embodiment, the data signal lines in the first data signal line group may include the first data signal line 61 and the second data signal line 62, and the data signal lines in the second data signal line group may include the third data signal line 63. That is, the first data signal line transmitting the red screen data signal and the second data signal line transmitting the green screen data signal are directly connected to the data lead-out line of the binding area, and the third data signal line transmitting the blue screen data signal is connected to the data lead-out line of the binding area through the first connecting line and the second connecting line.

[0125] In an exemplary embodiment, the driving structure layer in the binding region 200 may include multiple data leads 70. These multiple data leads 70 may extend in a direction away from the display area. A portion of the data leads 70 have their first ends connected to data signal lines in a first data signal line group in the display area, while another portion of the data leads 70 have their first ends connected to a second connection line 72 in the display area. The second ends of all the data leads 70 are connected to an integrated circuit, such that a portion of the integrated circuit's data signals are applied to the data signal lines in the first data signal line group through the data leads 70, and another portion of the integrated circuit's data signals are applied to the data signal lines in the second data signal line group through the data leads 70, the second connection line 72, and the first connection line 71.

[0126] In an exemplary embodiment, the multiple data signal lines 60, multiple first connection lines 71, multiple second connection lines 72 in the display area and the multiple data lead-out lines 70 in the binding area can be symmetrically arranged relative to the center line of the display area.

[0127] In an exemplary embodiment, the data lead 70 can be directly connected to the data signal line in the first data signal line group, and the data lead 70 can be directly connected to the second connecting line 72, or they can be connected through a via. This disclosure does not limit the connection.

[0128] In an exemplary embodiment, the driving structure layer of the display area 100 may further include multiple first signal traces 91 and multiple second signal traces 92. The shape of the first signal traces 91 may be a straight line or a broken line extending along the first direction X, and they may be disposed in a circuit row or between two adjacent circuit rows, and the multiple first signal traces 91 may be arranged sequentially along the second direction Y. The shape of the second signal traces 92 may be a straight line or a broken line extending along the second direction Y, and they may be disposed in a second circuit column, and the multiple second signal traces 92 may be arranged sequentially along the first direction X.

[0129] In an exemplary embodiment, in the first direction X, a first data signal line 61, a second data signal line 62, and a third data signal line 63 may be provided between two adjacent second connection lines 72, and a first data signal line 61, a second data signal line 62, and a third data signal line 63 may be provided between two adjacent second signal traces 92. That is, three data signal lines may be provided between two adjacent second connection lines 72, and three data signal lines may be provided between two adjacent second signal traces 92.

[0130] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include multiple conductive layers disposed on the substrate, and the film layer configuration for data signal lines and data connection lines may include:

[0131] (1) The first connecting line 71 and the second connecting line 72 can be disposed in different conductive layers, while the first data signal line 61, the second data signal line 62, the third data signal line 63, and the second connecting line 72 can be disposed in the same conductive layer. The first end of the first connecting line 71 can be connected to the third data signal line 63 through a via, and the second end of the first connecting line 71 can be connected to the second connecting line 72 through a via. For example, the conductive layer where the second connecting line 72 is located can be located on the side of the conductive layer where the first connecting line 71 is located away from the substrate.

[0132] (2) The first connecting line 71 and the second connecting line 72 can be disposed in the same conductive layer, and the first data signal line 61, the second data signal line 62 and the third data signal line 63 can be disposed in the same other conductive layer. The first end of the first connecting line 71 can be connected to the third data signal line 63 through a via, and the second end of the first connecting line 71 is directly connected to the second connecting line 72. For example, the conductive layer where the first connecting line 71 is located can be located on the side of the conductive layer where the first data signal line 61 is located that is away from the substrate.

[0133] In an exemplary embodiment, when the first connecting line 71 and the second connecting line 72 are disposed on different conductive layers, the first signal trace 91 and the first connecting line 71 can be disposed on the same layer and formed synchronously through the same patterning process. Similarly, the second signal trace 92 and the second connecting line 72 can be disposed on the same layer and formed synchronously through the same patterning process.

[0134] In an exemplary embodiment, at least one first connection line 71 and at least one first signal trace 91 may be provided in at least one circuit row or between at least one adjacent circuit row. A first break K1 may be provided between the first connection line 71 and the first signal trace 91. The first break K1 is configured to achieve mutual insulation between the first connection line 71 and the first signal trace 91.

[0135] In an exemplary embodiment, at least one second circuit array may be provided with at least one second connection line 72 and at least one second signal trace 92, and a second break K2 may be provided between the second connection line 72 and the second signal trace 92. The second break K2 is configured to achieve mutual insulation between the second connection line 72 and the second signal trace 92.

[0136] In one embodiment, the second signal trace 92 may be a signal trace that transmits a constant voltage signal, which may be a first power supply signal, a second power supply signal, a first initial signal, or a second initial signal.

[0137] In another embodiment, the second signal trace 92 may be a signal trace that transmits a data signal, which may be the data signal transmitted by the second data signal line 62. That is, the second data signal line 62 and the second signal trace 92 in a second circuit array transmit the same data signal, and the data signal lines in the second circuit array are connected in parallel.

[0138] Figure 8 is a schematic diagram of the connection structure between the data signal line and the data connection line in Figure 7, illustrating the structure of two circuit rows (the Mth circuit row and the M+1th circuit row) and two circuit columns (the Nth circuit column and the N+1th circuit column). The Nth circuit column can be the first circuit column, and the N+1th circuit column can be the second circuit column. The second circuit column can be located on one side of the first circuit column in the first direction X. The circuit unit defined by the Mth circuit row and the Nth circuit column is the first circuit unit, whose pixel driving circuit is connected to the first anode in the first light-emitting unit (red light-emitting unit). The circuit unit defined by the Mth circuit row and the N+1th circuit column is the second circuit unit, whose pixel driving circuit is connected to the second anode in the second light-emitting unit (first green light-emitting unit). The circuit unit defined by the M+1th circuit row and the Nth circuit column is the third circuit unit, whose pixel driving circuit is connected to the third anode in the third light-emitting unit (blue light-emitting unit). The circuit unit defined by the M+1th circuit row and the N+1th circuit column is the fourth circuit unit, whose pixel driving circuit is connected to the fourth anode in the fourth light-emitting unit (second green light-emitting unit).

[0139] As shown in Figure 8, the first circuit array may be provided with at least a first data signal line 61, a third data signal line 63, and a first power supply line 80. The shapes of the first data signal line 61, the third data signal line 63, and the first power supply line 80 may be straight lines or broken lines extending along the second direction Y. The third data signal line 63 may be located on one side of the first power supply line 80 in the first direction X, and the first data signal line 61 may be located on one side of the third data signal line 63 in the first direction X.

[0140] In an exemplary embodiment, the first data signal line 61 can be connected to the pixel driving circuit in the first circuit unit defined by the Mth circuit row and the Nth circuit column, the third data signal line 63 can be connected to the pixel driving circuit in the third circuit unit defined by the M+1th circuit row and the Nth circuit column, and the first power line 80 can be connected to the pixel driving circuit in the first circuit unit and the third circuit unit in the Nth circuit column.

[0141] In an exemplary embodiment, the second circuit array may be provided with at least a second data signal line 62, a first power line 80, and a second connecting line 72. The shapes of the second data signal line 62, the first power line 80, and the second connecting line 72 may be straight lines or broken lines extending along the second direction Y. The second connecting line 72 may be located on the side opposite to the first direction X of the first power line 80, and the second data signal line 62 may be located on the side opposite to the first direction X of the second connecting line 72.

[0142] In an exemplary embodiment, the second data signal line 62 can be connected to the pixel driving circuit in the second circuit unit defined by the Mth circuit row and the N+1th circuit column, and the pixel driving circuit in the fourth circuit unit defined by the M+1th circuit row and the N+1th circuit column, respectively, and the first power supply line 80 can be connected to the pixel driving circuit in the second circuit unit and the fourth circuit unit in the N+1th circuit column.

[0143] In an exemplary embodiment, the first power line 80 is configured to provide a first power signal to the connected pixel driving circuit.

[0144] In this disclosure, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In the following description, "A extends along direction B" refers to "the main body of A extends along direction B".

[0145] In an exemplary embodiment, at least one circuit unit may further include a data connection electrode 64. The data connection electrode 64 may be block-shaped (e.g., rectangular) and may be connected to the first terminal of the fourth transistor T4. For example, the fourth transistor T4 may include at least a fourth active layer, and the data connection electrode 64 may be connected to the first region of the fourth active layer via a via.

[0146] In an exemplary embodiment, in at least one first pixel column, a first data signal line 61 can be connected to the pixel driving circuit of a first sub-pixel via a first data connection block 61-1; a second data signal line 62 can be connected to the pixel driving circuits of a second sub-pixel and a fourth sub-pixel via a second data connection block 62-1; and a third data signal line 63 can be connected to the pixel driving circuit of a third sub-pixel via a third data connection block 63-1. The first data connection block 61-1 can be block-shaped (e.g., rectangular), and can be disposed on the side of the first data signal line 61 near the third data signal line 63, and connected to the first data signal line 61. The second data connection block 62-1 can be block-shaped (e.g., rectangular), and can be disposed on the side of the second data signal line 62 near the second connecting line 72, and connected to the second data signal line 62. The third data connection block 63-1 can be block-shaped (e.g., rectangular), and can be disposed on the side of the third data signal line 63 near the first data signal line 61, and connected to the third data signal line 63. The first data connection block 61-1, the second data connection block 62-1, and the third data connection block 63-1 can be connected to the data connection electrode 64 in the corresponding circuit unit through vias, thus enabling the first data signal line 61, the second data signal line 62, and the third data signal line 63 to write data signals into the first electrode of the fourth transistor T4 in the corresponding pixel driving circuit.

[0147] In an exemplary embodiment, since the first data connection block 61-1 is disposed on the side of the first data signal line 61 near the third data signal line 63, and the third data connection block 63-1 is disposed on the side of the third data signal line 63 near the first data signal line 61, both the first data connection block 61-1 and the third data connection block 63-1 are disposed between the first data signal line 61 and the third data signal line 63. This facilitates layout, reduces the area occupied by the pixel driving circuit, and helps to improve resolution.

[0148] In an exemplary embodiment, the distance between the edge of the first data connection block 61-1 near the third data signal line 63 and the edge of the third data signal line 63 near the first data connection block 61-1 can be less than the minimum distance between the first data signal line and the third data signal line 63, and the distance between the edge of the third data connection block 63-1 near the first data signal line 61 and the edge of the first data signal line 61 near the third data connection block 63-1 can be less than the minimum distance between the first data signal line and the third data signal line 63.

[0149] In an exemplary embodiment, the data connection electrode 64 in the first circuit unit and the data connection electrode 64 in the third circuit unit are located close to each other in their respective circuit units to reduce the impact on the layout of multiple transistors and multiple signal lines in the pixel driving circuit.

[0150] In an exemplary embodiment, in the first direction X, a first data signal line 61 and a second data signal line 62 may be provided between the third data signal line 63 and the second connection line 72 connected to the same first connection line 71.

[0151] In an exemplary embodiment, the first data signal line 61 may have a first width L1, the second data signal line 62 may have a second width L2, and the third data signal line 63 may have a third width L3. The first width L1, the second width L2, and the third width L3 may be the average width of the data signal lines, which is the dimension in the first direction X.

[0152] In an exemplary embodiment, the second width L2 may be greater than the first width L1, and the second width L2 may be greater than the third width L3.

[0153] In an exemplary embodiment, the ratio of the second width L2 to the first width L1 can be approximately 1.2 to 1.5, the ratio of the second width L2 to the third width L3 can be approximately 1.2 to 1.5, and the ratio of the first width L1 to the third width L3 can be approximately 0.95 to 1.05. Since the first data signal line 61 and the third data signal line 63 in the first circuit column are connected to half of the pixel driving circuits in their respective circuit columns, while the second data signal line 62 in the second circuit column is connected to all the pixel driving circuits in its respective circuit column, the load on the second data signal line 62 is different from that on the first data signal line 61 and the third data signal line 63. This disclosure, by setting the width of the second data signal line 62 to 1.2 to 1.5 times the width of the first data signal line 61 and the third data signal line 63, can effectively balance the load of different data signal lines and improve the driving performance of the pixel driving circuit.

[0154] In an exemplary embodiment, at least one first connecting line 71 may be provided between the Mth circuit row and the M+1th circuit row. The shape of the first connecting line 71 may be a straight line or a broken line extending along the first direction X. The first end of the first connecting line 71 may be connected to the third data signal line 63 in the Nth circuit column through a via, and the second end of the first connecting line 71 may be connected to the second connecting line 72 in the N+1th circuit column through a via.

[0155] In an exemplary embodiment, the display substrate may include multiple conductive layers disposed on a substrate in a direction perpendicular to the display substrate. The data connection electrode 64 and the first connection line 71 may be disposed in one conductive layer and formed synchronously through the same patterning process. The first data signal line 61, the second data signal line 62, the third data signal line 63, the second connection line 72, and the first power line 80 may be disposed in another conductive layer and formed synchronously through the same patterning process.

[0156] In an exemplary embodiment, the display substrate may further include at least one first signal trace 91 and at least one second signal trace 92. The shape of the first signal trace 91 may be a straight line or a broken line extending along the first direction X, and the shape of the second signal trace 92 may be a straight line or a broken line extending along the second direction Y.

[0157] In an exemplary embodiment, at least one first signal trace 91 may be disposed between the Mth circuit row and the M+1th circuit row, and a first break K1 may be disposed between the first connection line 71 and the first signal trace 91. The first break K1 is configured to achieve mutual insulation between the first connection line 71 and the first signal trace 91.

[0158] In an exemplary embodiment, the orthographic projection of the first power line 80 on the substrate at least partially overlaps with the orthographic projection of the first break K1 on the substrate, so that the first power line 80 can block the first break K1 from above, which can effectively eliminate the film layer difference in different areas, which is beneficial for anti-shadowing and avoids poor appearance of the display substrate.

[0159] In an exemplary embodiment, at least one second signal trace 92 may be provided in the N+1th circuit column (second circuit column), and a second break K2 may be provided between the second connection line 72 and the second signal trace 92. The second break K2 is configured to achieve mutual insulation between the second connection line 72 and the second signal trace 92.

[0160] In an exemplary embodiment, the plurality of conductive layers may include at least a first gate metal layer (GATE1), a second gate metal layer (GATE2), a first source / drain metal layer (SD1), and a second source / drain metal layer (SD2) arranged sequentially along a direction away from the substrate. The data connection electrode 64, the first connection line 71, and the first signal trace 91 may be disposed in the first source / drain metal layer. The first data signal line 61, the second data signal line 62, the third data signal line 63, the second connection line 72, the first power line 80, and the second signal trace 92 may be disposed in the second source / drain metal layer.

[0161] In an exemplary embodiment, this embodiment presents a mirrored structure. The positions of the first power line 80 in the first circuit column and the first power line 80 in the second circuit column can be substantially mirror-symmetrical with respect to the column center line. Similarly, the positions of the first data signal line 61 in the first circuit column and the second data signal line 62 in the second circuit column can be substantially mirror-symmetrical with respect to the column center line. The positions of the third data signal line 63 in the first circuit column and the second connection line 72 (second signal trace 92) in the second circuit column can be substantially mirror-symmetrical with respect to the column center line. The column center line can be a straight line located between adjacent circuit columns and extending along the second direction Y. In some possible embodiments, this embodiment can also be applied to a non-mirrored structure.

[0162] In an exemplary embodiment, the positions of the first data signal line 61 and the second data signal line 62 in this embodiment can be substantially the same as the positions of the data signal lines in the existing single data signal line scheme, and can be used as original signal lines. The third data signal line 63 and the second connecting line 72 (second signal trace 92) can be used as newly added signal lines. The third data signal line 63, as a newly added signal line, can be located on the side of the first data signal line 61 away from the second data signal line 62, and the second connecting line 72, as a newly added signal line, can be located on the side of the second data signal line 62 away from the first data signal line 61. That is, the newly added signal lines can be located outside the two original signal lines. In some possible embodiments, the third data signal line 63, as a newly added signal line, can be located on the side of the first data signal line 61 close to the second data signal line 62, and the second connecting line 72, as a newly added signal line, can be located on the side of the second data signal line 62 close to the first data signal line 61. That is, the newly added signal lines can be located inside the two original signal lines. This disclosure does not limit this.

[0163] In one embodiment, both the first signal trace 91 and the second signal trace 92 are traces for transmitting a first power signal, and the second signal trace 92 can be connected to the first signal trace 91 through a via. The first signal trace 91 and the second signal trace 92 form a mesh-like interconnected structure in the display area for transmitting the first power signal, which can effectively reduce the resistance of the first power line, effectively reduce the voltage drop of the first power signal, effectively improve the uniformity of the first power signal, effectively improve the display uniformity, and improve the display quality.

[0164] In another embodiment, both the first signal trace 91 and the second signal trace 92 are traces for transmitting the second power signal, and the second signal trace 92 can be connected to the first signal trace 91 through a via. The first signal trace 91 and the second signal trace 92 form a mesh-like interconnected structure for transmitting the second power signal in the display area, which can effectively reduce the resistance of the second power line, effectively reduce the voltage drop of the second power signal, effectively improve the uniformity of the second power signal, effectively improve the display uniformity, and improve the display quality.

[0165] In another embodiment, both the first signal trace 91 and the second signal trace 92 are traces for transmitting the first initial signal, and the second signal trace 92 can be connected to the first signal trace 91 through a via. The first signal trace 91 and the second signal trace 92 form a mesh-like interconnected structure in the display area for transmitting the first initial signal, which can effectively reduce the resistance of the first initial signal line, effectively reduce the voltage drop of the first initial signal, effectively improve the uniformity of the first initial signal, effectively improve the display uniformity, and improve the display quality.

[0166] In another embodiment, both the first signal trace 91 and the second signal trace 92 are traces for transmitting the second initial signal, and the second signal trace 92 can be connected to the first signal trace 91 through a via. The first signal trace 91 and the second signal trace 92 form a mesh-like interconnected structure for transmitting the second initial signal in the display area, which can effectively reduce the resistance of the second initial signal line, effectively reduce the voltage drop of the second initial signal, effectively improve the uniformity of the second initial signal, effectively improve the display uniformity, and improve the display quality.

[0167] In another embodiment, the first signal trace 91 and the second signal trace 92 can transmit different constant voltage signals. The first signal trace 91 can be a trace that transmits a first constant voltage signal, and the second signal trace 92 can be a trace that transmits a second constant voltage signal. The first constant voltage signal can be one of a first power supply signal, a second power supply signal, a first initial signal, and a second initial signal, and the second constant voltage signal can be another signal among the first power supply signal, the second power supply signal, the first initial signal, and the second initial signal.

[0168] In an exemplary embodiment, the fabrication process of the display substrate may include the following operations: First, a semiconductor layer (POLY) is formed on the substrate. The semiconductor layer may include at least the active layers of the first transistor T1 to the seventh transistor T7. Then, a first insulating layer covering the semiconductor layer and a first conductive layer (first gate metal layer) disposed on the first insulating layer are formed. The first conductive layer may include at least a first scan signal line, a second scan signal line, a light emission signal line, and a first electrode of a storage capacitor. Next, a second insulating layer covering the first conductive layer and a second conductive layer (second gate metal layer) disposed on the second insulating layer are formed. The second conductive layer may include at least a first initial signal line, a second initial signal line, and a second electrode of a storage capacitor. The first electrode and the second electrode constitute the storage capacitor of the pixel driving circuit. Finally, a third insulating layer covering the second conductive layer and a third conductive layer (first source / drain metal layer) disposed on the third insulating layer are formed. The third conductive layer may include at least a data connection electrode 64, a first connection line 71, a first signal trace 91, and multiple connection electrodes. Subsequently, a first planarization layer covering the third conductive layer is formed, and a fourth conductive layer (second source / drain metal layer) disposed on the first planarization layer is formed. The fourth conductive layer may include at least a first data signal line 61, a second data signal line 62, a third data signal line 63, a second connection line 72, a first power line 80, and a second signal trace 92. Then, a second planarization layer covering the fourth conductive layer is formed, and an anode conductive layer disposed on the second planarization layer is formed. The anode conductive layer may include at least a first anode of a red light-emitting unit, a second anode of a first green light-emitting unit, a third anode of a blue light-emitting unit, and a fourth anode of a second green light-emitting unit. Subsequently, a pixel definition layer, an organic light-emitting layer, a cathode, and an encapsulation structure layer are formed sequentially.

[0169] In a display substrate employing an RGBG pixel arrangement, a single data signal line is connected to multiple pixel driving circuits that drive red light-emitting units and multiple pixel driving circuits that drive blue light-emitting units in a single circuit column. Research has revealed that for pixel columns containing both red and blue light-emitting units, because the pixel driving circuits on the entire display substrate scan line by line, the data signals within the same pixel column need to be frequently switched between red and blue image data signals. Since there may be a significant voltage difference between the red and blue image data signals, this frequent switching increases the power consumption of the data driver, thus increasing the overall power consumption of the display device.

[0170] The display substrate provided in this exemplary embodiment effectively reduces the power consumption of the display device by connecting the same data signal line to the pixel driving circuit that drives the same color light-emitting unit. In this disclosure, the first data signal line transmitting red image data signal is connected to the pixel driving circuit that drives the red light-emitting unit, and the third data signal line transmitting blue image data signal is connected to the pixel driving circuit that drives the blue light-emitting unit. This avoids high-frequency switching of the data signal between the red and blue image data signals in the data signal line, effectively reducing the power consumption of the data driver and thus reducing the overall power consumption of the display device.

[0171] This disclosure reduces the impact on the layout of multiple transistors and signal lines in the pixel driving circuit by setting a portion of the data signal lines to be directly connected to the data leads of the bonding area, and another portion of the data signal lines to be connected to the data leads of the bonding area through data connection lines. It does not require any changes to the existing driving logic, is well compatible with existing manufacturing processes, and has a simple process implementation, is easy to implement, has high production efficiency, low production cost, and high yield.

[0172] This disclosure improves the driving performance of the pixel driving circuit by setting the width of the second data signal line to be greater than the widths of the first and third data signal lines, thereby effectively balancing the load of different data signal lines.

[0173] This disclosure provides a first signal trace and a second signal trace within the display area. The first signal trace and the second signal trace can transmit the same constant voltage signal or different constant voltage signals. This not only effectively reduces the resistance of the corresponding signal lines and the voltage drop of the corresponding signals, but also effectively improves the uniformity of the corresponding signals in the display substrate, thereby improving display uniformity, display quality, and display performance.

[0174] Figure 9 is a schematic diagram of another display substrate structure according to an exemplary embodiment of the present disclosure. As shown in Figure 9, the arrangement of the circuit units and the connection structure of the data signal lines in this embodiment are basically the same as those in the embodiment shown in Figure 7. The difference is that the first data signal line 61, which transmits the red screen data signal, is connected to the data lead-out line 70 of the bonding area through the first connecting line 71 and the second connecting line 72, and the third data signal line 63, which transmits the blue screen data signal, is directly connected to the data lead-out line 70 of the bonding area. That is, the data signal lines in the first data signal line group may include the second data signal line 62 and the third data signal line 63, and the data signal lines in the second data signal line group may include the first data signal line 61.

[0175] In an exemplary embodiment, the first end of the first connection line 71 can be connected to the first data signal line 61 in the first circuit array, the second end of the first connection line 71 is connected to the first end of the second connection line 72, and the second end of the second connection line 72 is connected to the data lead-out line 70.

[0176] In an exemplary embodiment, for the first data signal line 61 and the second connection line 72 connected to the same first connection line 71, the first circuit column where the first data signal line 61 is located and the second circuit column where the second connection line 72 is located can be adjacent circuit columns.

[0177] In an exemplary embodiment, the plurality of first pixel columns (first circuit columns) in the display area of ​​this embodiment are all first type pixel columns, which means that the first data signal line in the pixel column is connected to the first connection line.

[0178] The display substrate provided in this embodiment also has the technical advantages of not requiring changes to the existing driving logic and reducing the overall power consumption of the display device.

[0179] Figure 10 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure. As shown in Figure 10, the arrangement of the circuit units and the connection structure of the data signal lines in this embodiment are basically the same as those in the embodiment shown in Figure 7. The difference is that for the first data signal line 61 that transmits the red image data signal, a portion of the first data signal line 61 is directly connected to the data lead-out line 70 of the bonding area, and another portion of the first data signal line 61 is connected to the data lead-out line 70 of the bonding area through the first connecting line 71 and the second connecting line 72. For the third data signal line 63 that transmits the blue image data signal, a portion of the third data signal line 63 is directly connected to the data lead-out line 70 of the bonding area, and another portion of the third data signal line 63 is connected to the data lead-out line 70 of the bonding area through the first connecting line 71 and the second connecting line 72.

[0180] In an exemplary embodiment, the plurality of first circuit columns (first pixel columns) in the display area of ​​this embodiment may include a plurality of first-type circuit columns (first-type pixel columns) and a plurality of second-type circuit columns (second-type pixel columns). In the first-type circuit columns, the first data signal line 61 can be connected to the first connecting line 71, that is, the first data signal line 61 transmitting the red image data signal in this circuit column is connected to the data lead-out line 70 of the binding area through the first connecting line 71 and the second connecting line 72, and the third data signal line 63 transmitting the blue image data signal is directly connected to the data lead-out line 70 of the binding area. In the second-type circuit columns, the third data signal line 63 can be connected to the first connecting line 71, that is, the third data signal line 63 transmitting the blue image data signal in this circuit column is connected to the data lead-out line 70 of the binding area through the first connecting line 71 and the second connecting line 72, and the first data signal line 61 transmitting the red image data signal in this circuit column is directly connected to the data lead-out line 70 of the binding area.

[0181] In an exemplary embodiment, the first type of circuit array and the second type of circuit array can be alternately arranged in the first direction X.

[0182] In an exemplary embodiment, for a first data signal line 61 and a second connection line 72 connected to the same first connection line 71, the first circuit column containing the first data signal line 61 and the second circuit column containing the second connection line 72 can be adjacent circuit columns. For a third data signal line 63 and a second connection line 72 connected to the same first connection line 71, the first circuit column containing the third data signal line 63 and the second circuit column containing the second connection line 72 can be adjacent circuit columns.

[0183] The display substrate provided in this embodiment not only has the technical advantages of not needing to change the existing driving logic and reducing the overall power consumption of the display device, but also balances the load of the first data signal lines and the third data signal lines by directly connecting a portion of the first data signal lines and the third data signal lines to the data lead-out lines of the bonding area, and connecting another portion of the first data signal lines and the third data signal lines to the data lead-out lines of the bonding area through the first connecting line and the second connecting line, thereby improving the driving performance of the pixel driving circuit.

[0184] Figure 11 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure. As shown in Figure 11, the arrangement of the circuit units and the connection structure of the data signal lines in this embodiment are basically the same as those in the embodiment shown in Figure 7, except that the arrangement of the first connecting line 71 is different.

[0185] In an exemplary embodiment, multiple first connection lines 71 can be respectively arranged in different circuit rows or between different adjacent circuit rows. A second distance can be maintained between the via that connects the first connection line 71 to the third data signal line 63 and the lower edge BY of the display area. This second distance can be a dimension in the second direction Y. In the left region of the display area, the multiple second distances can gradually decrease in the first direction X. In the right region of the display area, the multiple first distances can gradually decrease in the opposite direction of the first direction X, that is, from the side edge of the display area to the center line of the display area, the positions of the multiple vias gradually approach the bonding area.

[0186] Figure 12 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure. As shown in Figure 12, the arrangement of the circuit units and the connection structure of the data signal lines in this embodiment are basically the same as those in the embodiment shown in Figure 7, except that the arrangement of the first connecting line 71 is different.

[0187] In an exemplary embodiment, multiple first connection lines 71 may be positioned between the last circuit row and the lower edge BY of the display area, where the last circuit row is the circuit row in the display area closest to the bonding area. A third distance may be present between the via that connects the first connection line 72 to the third data signal line 63 and the lower edge BY of the display area; this third distance may be a dimension in the second direction Y. In the first direction X, the multiple third distances may be substantially equal, meaning the positions of the multiple vias may be substantially aligned in the first direction X.

[0188] In one embodiment, since multiple first connection lines are arranged on the side of the last circuit row near the bonding area, the display area may not need to have first signal traces. In another embodiment, the display area may have multiple first signal traces, and the arrangement of the first signal traces is basically the same as that shown in the embodiment of FIG7, and this disclosure does not limit it.

[0189] In some possible implementations, multiple first connecting lines 71 may be arranged in the same circuit row or between the same adjacent circuit rows, and multiple third distances may be substantially equal along the first direction X, which is not limited herein.

[0190] The display substrate provided in this embodiment not only has the technical advantages of not needing to change the existing driving logic and reducing the overall power consumption of the display device, but also reduces the impact of vias on the display area and improves the display effect and display quality by setting multiple first connection lines on the side of the last circuit row close to the bonding area.

[0191] Figure 13 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure. As shown in Figure 13, the arrangement of the circuit units and the connection structure of the data signal lines in this embodiment are basically the same as those in the embodiment shown in Figure 7. The difference is that the arrangement of the second connection line 72 is different, and an auxiliary signal line 93 is provided between the first circuit column and the second circuit column.

[0192] In an exemplary embodiment, multiple second connection lines 72 may be disposed near the center line O of the display area, that is, in the middle region of the display area in the first direction X, and connected to the third data signal line 63 via a longer first connection line 71.

[0193] In an exemplary embodiment, for a third data signal line 63 and a second connection line 72 connected to the same first connection line 71, there may be multiple first circuit columns and multiple second circuit columns between the first circuit column where the third data signal line 63 is located and the second circuit column where the second connection line 72 is located.

[0194] In an exemplary embodiment, the auxiliary signal trace 93 may be a straight line or a broken line extending along the second direction Y, and may be disposed between the first circuit column and the second circuit column.

[0195] In an exemplary embodiment, for a display substrate with n circuit columns, the existing single data signal line scheme display substrate has n data signal lines, while this embodiment adds 1.5n signal lines. Among them, n / 2 first data signal lines 61 and n / 2 second data signal lines 62 can be used as n original signal lines, and the newly added signal lines include n / 2 third data signal lines 63, n / 2 second connecting lines 72, and n / 2 auxiliary signal lines 93.

[0196] In an exemplary embodiment, a portion of the auxiliary signal traces 93 located in the central region of the first direction X of the display area can serve as a second connecting line, while another portion of the auxiliary signal traces 93 at other locations can serve as constant voltage traces for transmitting constant voltage signals.

[0197] The display substrate provided in this embodiment not only has the technical advantages of not needing to change the existing driving logic and reducing the overall power consumption of the display device, but also effectively reduces the bezel width by setting multiple second connection lines in the middle area of ​​the display substrate, which is beneficial for achieving a narrow bezel.

[0198] Figure 14 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure, and Figure 15 is a schematic diagram of the connection structure of the data signal line and the data connection line in Figure 14. As shown in Figures 14 and 15, the arrangement of the circuit units and the connection structure of the data signal lines in this embodiment are basically the same as those in the embodiments shown in Figures 7 and 8. The difference is that the first data signal line 61, which transmits the red screen data signal, and the third data signal line 63, which transmits the blue screen data signal, are both directly connected to the data lead-out line 70 of the bonding area.

[0199] In an exemplary embodiment, on one hand, the first data signal line 61 is connected to the pixel driving circuit of a plurality of first circuit units Q1 in the first circuit column, and the third data signal line 63 is connected to the pixel driving circuit of a plurality of third circuit units Q3 in the first circuit column. On the other hand, after the first data signal line 61 and the third data signal line 63 extend along the second direction Y toward the direction close to the binding region 200, they are respectively connected to the data lead-out line 70 in the binding region 200.

[0200] In an exemplary embodiment, on one hand, the second data signal line 62 is connected to the pixel driving circuit of a plurality of second circuit units Q2 and a plurality of fourth circuit units Q4 in the second circuit column; on the other hand, the second data signal line 62 extends along the second direction Y toward the direction close to the binding region 200 and is connected to the data lead-out line 70 in the binding region 200.

[0201] In an exemplary embodiment, since both the first data signal line 61 and the third data signal line 63 are directly connected to the data lead-out line, the display area may not need to be provided with the first connection line and the second connection line.

[0202] In an exemplary embodiment, the display area 100 may be provided with a plurality of third power supply lines 73, which may be respectively provided in the second circuit column. The third power supply lines 73 are configured to provide a first power signal to a portion of the pixel driving circuit of the first circuit column.

[0203] In an exemplary embodiment, the third power supply trace 73 located in the N+1th circuit column can be connected to the second electrode plate 65 in the first circuit unit defined by the Mth circuit row and the Nth circuit column through a via, and the first power supply line 80 in the Nth circuit column can be connected to the second electrode plate 65 in the third circuit unit defined by the M+1th circuit row and the Nth circuit column through a via. That is, the pixel driving circuit driving the red light-emitting unit in the first circuit column is only connected to the third power supply trace 73, and the pixel driving circuit driving the blue light-emitting unit in the first circuit column is only connected to the first power supply line 80 in the first circuit column.

[0204] In some possible implementations, the display area 100 may not have a first signal trace. In other possible implementations, the display area 100 may have multiple first signal traces 91, and the first signal traces 91 are connected to the third power supply trace 73. Since the width of the third power supply trace 73 is smaller than the width of the first power supply trace 80, the interconnected first signal traces 91 and third power supply trace 73 can form a network connection structure for transmitting the first power supply signal, which can effectively reduce the voltage drop of the first power supply signal driving the red light-emitting unit.

[0205] In some possible implementations, the third power supply trace 73 located in the N+1th circuit column can be connected via a via to the second electrode 65 in the first circuit unit defined by the Mth circuit row and the N+2th circuit column, which is not limited herein.

[0206] In some possible implementations, the first power line 80 in the Nth circuit column can be connected to the second electrode 65 in the first circuit unit defined by the Mth circuit row and the Nth circuit column via a via, and the third power line 73 in the N+1th circuit column can be connected to the second electrode 65 in the third circuit unit defined by the M+1th circuit row and the Nth circuit column via a via. That is, the pixel driving circuit that drives the red light-emitting unit in the first circuit column is connected to the first power line 80 in the first circuit column, and the pixel driving circuit that drives the blue light-emitting unit in the first circuit column is connected to the third power line 73.

[0207] In an exemplary embodiment, the second circuit array of this embodiment is still a first power line 80, which is connected to the second electrode plate 65 in the second circuit unit and the fourth circuit unit respectively.

[0208] In this embodiment, a third power supply line is used as a power supply line in the first circuit array. The third power supply line is connected to the pixel driving circuit that drives the red light-emitting unit, and the first power supply line in the first circuit array is connected to the pixel driving circuit that drives the blue light-emitting unit. According to the working voltage requirements, separate first power supply signals can be provided to the pixel driving circuit that drives the red light-emitting unit and the pixel driving circuit that drives the blue light-emitting unit, which can effectively reduce power consumption.

[0209] Figure 16 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure, and Figure 17 is a schematic diagram of the connection structure of the data signal line and the data connection line in Figure 16. As shown in Figures 16 and 17, the arrangement of the circuit units and the connection structure of the data signal lines in this embodiment are basically the same as those in the embodiments shown in Figures 7 and 8. The difference is that an auxiliary signal line 93 is also provided between the first circuit column and the second circuit column.

[0210] In an exemplary embodiment, the auxiliary signal trace 93 may be a straight line or a broken line extending along the second direction Y, and may be disposed between the first data signal line 61 of the first circuit column (the Nth circuit column) and the second data signal line 62 of the second circuit column (the N+1th circuit column).

[0211] In an exemplary embodiment, for a display substrate with n circuit columns, the existing single data signal line scheme display substrate has n data signal lines, while this embodiment adds 1.5n signal lines. Among them, n / 2 first data signal lines 61 and n / 2 second data signal lines 62 can be used as n original signal lines, the newly added n / 2 third data signal lines 63 can be used as data signal lines for transmitting blue screen data signals, the newly added n / 2 second connecting lines 72 can be used as signal access lines for n / 2 third data signal lines 63, and the newly added n / 2 auxiliary signal lines 93 can be used as constant voltage lines for transmitting first power signals, second power signals, first initial signals, or second initial signals.

[0212] In an exemplary embodiment, the first signal trace 91 and the second signal trace 92 can be traces for transmitting a second power signal, and the auxiliary signal trace 93 can be a trace for transmitting a first initial signal or a second initial signal. This disclosure, by providing an auxiliary signal trace for transmitting the initial signal between the first circuit array and the second circuit array, and having an auxiliary signal trace with a constant potential, can effectively reduce the mutual interference between the data signal lines and pixel driving circuits in the two unit arrays.

[0213] In an exemplary embodiment, the auxiliary signal trace 93 may be a trace for transmitting a first initial signal, and at least one auxiliary signal trace 93 may be connected to the first initial signal line, with the first initial signal line and the auxiliary signal trace 93 forming a mesh-like interconnected structure for transmitting the first initial signal.

[0214] In an exemplary embodiment, the auxiliary signal trace 93 may be a trace for transmitting a second initial signal, and at least one auxiliary signal trace 93 may be connected to the second initial signal line, with the second initial signal line and the auxiliary signal trace 93 forming a mesh-like interconnected structure for transmitting the second initial signal.

[0215] In an exemplary embodiment, a portion of the auxiliary signal traces 93 may be traces for transmitting a first initial signal, while another portion of the auxiliary signal traces 93 may be traces for transmitting a second initial signal. A mesh-like interconnection structure for transmitting the first initial signal and a mesh-like interconnection structure for transmitting the second initial signal are simultaneously formed on the display substrate. In the first direction X, the auxiliary signal traces 93 for transmitting the first initial signal and the auxiliary signal traces 93 for transmitting the second initial signal can be arranged alternately.

[0216] In an exemplary embodiment, for a pixel driving circuit with an 8T1C structure, the pixel driving circuit is also connected to a third initial signal line. The auxiliary signal trace 93 can be a trace for transmitting the third initial signal, and at least one auxiliary signal trace 93 can be connected to the third initial signal line. The third initial signal line and the auxiliary signal trace 93 form a mesh-like interconnected structure for transmitting the third initial signal.

[0217] In an exemplary embodiment, a portion of the auxiliary signal traces 93 can be traces for transmitting a first initial signal, another portion can be traces for transmitting a second initial signal, and yet another portion can be traces for transmitting a third initial signal. A mesh-like interconnection structure for transmitting the first initial signal, a mesh-like interconnection structure for transmitting the second initial signal, and a mesh-like interconnection structure for transmitting the third initial signal are simultaneously formed on the display substrate. In the first direction X, the three signal traces 93 for transmitting the first initial signal, the auxiliary signal traces 93 for transmitting the second initial signal, and the three signal traces 93 for transmitting the third initial signal can be arranged periodically.

[0218] In an exemplary embodiment, the first connection line 71 and the first signal trace 91 may be disposed in the first source-drain metal layer, and the first data signal line 61, the second data signal line 62, the third data signal line 63, the second connection line 72, the second signal trace 92 and the auxiliary signal trace 93 may be disposed in the second source-drain metal layer.

[0219] In some possible implementations, the first signal trace 91 and the second signal trace 92 may be traces for transmitting a first initial signal or a second initial signal, and the auxiliary signal trace 93 may be traces for transmitting a second power signal. Alternatively, the first signal trace 91 and the second signal trace 92 may be traces for transmitting a first constant voltage signal, and the auxiliary signal trace 93 may be traces for transmitting a second constant voltage signal. This disclosure does not impose any limitations on these implementations.

[0220] In some possible implementations, the connection relationship between the data signal line and the data connection line in this embodiment can adopt the structure shown in the embodiment of Figure 9 or Figure 10. The arrangement of the first connection line 71 in this embodiment can adopt the structure shown in the embodiment of Figure 11 or Figure 12. The arrangement of the second connection line 72 in this embodiment can adopt the structure shown in the embodiment of Figure 13. The first power line in this embodiment can adopt the structure shown in the embodiment of Figure 14. This disclosure does not limit the scope of the invention.

[0221] Figure 18 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure, and Figure 19 is a schematic diagram of the connection structure of the data signal line and the data connection line in Figure 18. As shown in Figures 18 and 19, the arrangement of the circuit units and the connection structure of the data signal lines in this embodiment are basically the same as those in the embodiments shown in Figures 16 and 17, except that the position of the auxiliary signal line 93 is different.

[0222] In an exemplary embodiment, the auxiliary signal trace 93 may be a straight line or a broken line extending along the second direction Y, and may be disposed between the first power line 80 of the second circuit column (N+1 circuit column) and the first power line 80 of the first circuit column (N+2 circuit column).

[0223] In an exemplary embodiment, the signals transmitted by the first signal trace 91, the second signal trace 92, and the auxiliary signal trace 93 in this embodiment can be substantially the same as those in the embodiments shown in FIG16 and FIG17, and will not be described again here.

[0224] In some possible implementations, the auxiliary signal traces of this disclosure can be a combination of those shown in Figures 16 and 18. That is, the auxiliary signal trace 93 is not only disposed between the third data signal line 63 of the first circuit column and the second data signal line 62 of the second circuit column, but also between the second connecting line 72 of the second circuit column and the first data signal line 61 of the first circuit column. This disclosure does not limit the scope of the invention.

[0225] Figure 20 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the connection structure of data signal lines and data connection lines. As shown in Figure 20, the arrangement of circuit units and the connection structure of data signal lines in this embodiment are basically the same as those in the embodiments shown in Figures 7 and 8. The difference is that an auxiliary signal trace 93 can be provided between the first circuit column and the second circuit column, and the auxiliary signal trace 93 can serve as a power supply trace in the first circuit column.

[0226] In an exemplary embodiment, an auxiliary signal trace 93 may be provided between the first data signal line 61 of the first circuit column (Nth circuit column) and the second data signal line 62 of the second circuit column (N+1th circuit column). The auxiliary signal trace 93 is configured to provide a first power signal to a portion of the pixel driving circuit of the first circuit column.

[0227] In an exemplary embodiment, the auxiliary signal trace 93 can be connected to the second electrode 65 in the first circuit unit defined by the Mth circuit row and the Nth circuit column via a via, and the first power line 80 in the Nth circuit column can be connected to the second electrode 65 in the third circuit unit defined by the M+1th circuit row and the Nth circuit column via a via. That is, the pixel driving circuit that drives the red light-emitting unit in the first circuit column is only connected to the auxiliary signal trace 93, and the pixel driving circuit that drives the blue light-emitting unit in the first circuit column is only connected to the first power line 80 in the first circuit column.

[0228] In an exemplary embodiment, the second circuit array in this embodiment is still a first power line, which is connected to the second electrode plate 65 in the second circuit unit and the fourth circuit unit respectively.

[0229] In some possible implementations, the first signal trace 91 can be connected to the auxiliary signal trace 93. The interconnected first signal trace 91 and auxiliary signal trace 93 can form a network connection structure for transmitting the first power signal, which can effectively reduce the voltage drop of the first power signal driving the red light-emitting unit.

[0230] In some possible implementations, the first power line 80 in the Nth circuit column can be connected to the second electrode 65 in the first circuit unit defined by the Mth circuit row and the Nth circuit column via a via, and the auxiliary signal line 93 can be connected to the second electrode 65 in the third circuit unit defined by the M+1th circuit row and the Nth circuit column via a via. That is, the pixel driving circuit that drives the red light-emitting unit in the first circuit column is only connected to the first power line 80 in the first circuit column, and the pixel driving circuit that drives the blue light-emitting unit in the first circuit column is only connected to the auxiliary signal line 93.

[0231] In some possible implementations, the auxiliary signal trace 93 may be connected via a via to the second plate 65 in the first circuit unit defined by the Mth circuit row and the N+2th circuit column, which is not limited herein.

[0232] In some possible implementations, the connection relationship between the data signal line and the data connection line in this embodiment can adopt the structure shown in the embodiment of Figure 9 or Figure 10. The arrangement of the first connection line 71 in this embodiment can adopt the structure shown in the embodiment of Figure 11 or Figure 12. The arrangement of the second connection line 72 in this embodiment can adopt the structure shown in the embodiment of Figure 13. This disclosure does not limit the scope of the invention.

[0233] In this embodiment, an auxiliary signal trace is used as a power line in the first circuit array. The auxiliary signal trace is connected to the pixel driving circuit that drives the red light-emitting unit, and the first power line in the first circuit array is connected to the pixel driving circuit that drives the blue light-emitting unit. Alternatively, the auxiliary signal trace is connected to the pixel driving circuit that drives the blue light-emitting unit, and the first power line in the first circuit array is connected to the pixel driving circuit that drives the red light-emitting unit. This allows for the provision of separate power supply voltages to the pixel driving circuits that drive the red and blue light-emitting units, respectively, according to the operating voltage requirements, which can effectively reduce power consumption.

[0234] Figure 21 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the connection structure of data signal lines and data connection lines. As shown in Figure 21, the arrangement of circuit units and the connection structure of data signal lines in this embodiment are basically the same as those in the embodiments shown in Figures 7 and 8. The difference is that two power lines for transmitting the first power signal are provided in the first circuit array.

[0235] In an exemplary embodiment, the first circuit array of this embodiment may at least include a first data signal line 61, a third data signal line 63, a first power supply line 81, and a second power supply line 82. The first power supply line 81 and the second power supply line 82 are configured to provide a first power signal to the connected pixel driving circuit. The shapes of the first data signal line 61, the third data signal line 63, the first power supply line 81, and the second power supply line 82 may be straight lines or broken lines extending along the second direction Y. The second power supply line 82 may be located on one side of the first power supply line 81 in the first direction X, the third data signal line 63 may be located on one side of the second power supply line 82 in the first direction X, and the first data signal line 61 may be located on one side of the third data signal line 63 in the first direction X. The position, shape, and connection structure of the first data signal line 61 and the third data signal line 63 are substantially the same as those in the embodiments shown in Figures 7 and 8.

[0236] In an exemplary embodiment, at least one circuit unit may further include a first electrode plate (not shown) and a second electrode plate 65. The orthographic projection of the second electrode plate 65 onto the substrate at least partially overlaps with the orthographic projection of the first electrode plate onto the substrate. The first electrode plate and the second electrode plate 65 form a storage capacitor for the pixel driving circuit, and the second electrode plate 65 is connected to the first electrode of the fifth transistor T5. A first power supply trace 81 may be connected to the second electrode plate 65 in the first circuit unit defined by the Mth circuit row and the Nth circuit column via a via. A second power supply trace 82 may be connected to the second electrode plate 65 in the third circuit unit defined by the M+1th circuit row and the Nth circuit column via a via. That is, the first power supply trace 81 is only connected to the pixel driving circuit that drives the red light-emitting unit, and the second power supply trace 82 is only connected to the pixel driving circuit that drives the blue light-emitting unit.

[0237] In an exemplary embodiment, the width of the first power trace 81 may be smaller than the width of the second power trace 82. The width may be the average width of the signal line, which is the dimension in the first direction X.

[0238] In an exemplary embodiment, the second circuit array of this embodiment may be provided with at least a second data signal line 62, a second connection line 72 and a first power line 80. The position, shape and connection structure of the above signal lines are basically the same as those of the embodiments shown in FIG7 and FIG8. That is, the second circuit array is still a first power line, which is connected to the second electrode plate 65 in the second circuit unit and the fourth circuit unit respectively.

[0239] In this embodiment, the first power line in the first circuit array is split into two power lines, including a first power line and a second power line. The first power line is only connected to the pixel driving circuit that drives the red light-emitting unit, and the second power line is only connected to the pixel driving circuit that drives the blue light-emitting unit. This can provide separate first power signals to the pixel driving circuit that drives the red light-emitting unit and the pixel driving circuit that drives the blue light-emitting unit according to the working voltage requirements, which can effectively reduce power consumption.

[0240] In some possible implementations, the scheme of having two first power supply traces in the first circuit array can be applied to the embodiments shown in FIG7 and FIG8, or to the embodiments shown in FIG9 to FIG12, and this disclosure is not limited thereto.

[0241] In some possible implementations, the connection relationship between the data signal line and the data connection line in this embodiment can adopt the structure shown in the embodiments of FIG9, FIG10 or FIG11, and this disclosure does not limit it.

[0242] Figure 22 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure, illustrating the connection structure of data signal lines and data connection lines. As shown in Figure 22, the arrangement of circuit units and the connection structure of data signal lines in this embodiment are basically the same as those in the embodiments shown in Figures 7 and 8. The difference is that an auxiliary signal trace 93 can be provided between the first circuit column and the second circuit column, and two power supply traces are provided in the first circuit column.

[0243] In an exemplary embodiment, the auxiliary signal trace 93 may be a straight line or a broken line extending along the second direction Y, and may be disposed between the first data signal line 61 of the first circuit column (the Nth circuit column) and the second data signal line 62 of the second circuit column (the N+1th circuit column).

[0244] In an exemplary embodiment, the first circuit column may be provided with at least a first data signal line 61, a third data signal line 63, a first power supply line 81, and a second power supply line 82. The first power supply line 81 can be connected to the second electrode plate 65 in the first circuit unit defined by the Mth circuit row and the Nth circuit column through a via. The second power supply line 82 can be connected to the second electrode plate 65 in the third circuit unit defined by the M+1th circuit row and the Nth circuit column through a via. That is, the first power supply line 81 is only connected to the pixel driving circuit that drives the red light-emitting unit, and the second power supply line 82 is only connected to the pixel driving circuit that drives the blue light-emitting unit.

[0245] In an exemplary embodiment, the second circuit array of this embodiment may be provided with at least a second data signal line 62, a first power line 80, and a second connection line 72. The position, shape, and connection structure of the signal lines are basically the same as those in the embodiments shown in FIG7 and FIG8. That is, the second circuit array is still a first power line, which is connected to the second electrode plate 65 in the second circuit unit and the fourth circuit unit respectively.

[0246] This embodiment splits the first power line in the first circuit array into two power lines, including a first power line and a second power line. This allows for the provision of separate power supply voltages to the pixel driving circuits that drive the red light-emitting unit and the blue light-emitting unit, respectively, according to their operating voltage requirements, thereby effectively reducing power consumption.

[0247] In some possible implementations, the first signal trace 91 and the second signal trace 92 can be traces for transmitting a second power signal, and the auxiliary signal trace 93 can be a trace for transmitting a first initial signal or a second initial signal. Alternatively, the first signal trace 91 and the second signal trace 92 can be traces for transmitting a first initial signal or a second initial signal, and the auxiliary signal trace 93 can be a trace for transmitting a second power signal. Alternatively, the first signal trace 91 and the second signal trace 92 can be traces for transmitting a first constant voltage signal, and the auxiliary signal trace 93 can be a trace for transmitting a second constant voltage signal. This disclosure does not impose any limitations on these implementations.

[0248] In some possible implementations, the connection relationship between the data signal line and the data connection line in this embodiment can adopt the structure shown in the embodiment of Figure 9 or Figure 10. The arrangement of the first connection line 71 in this embodiment can adopt the structure shown in the embodiment of Figure 11 or Figure 12. The arrangement of the second connection line 72 in this embodiment can adopt the structure shown in the embodiment of Figure 13. This disclosure does not limit the scope of the invention.

[0249] The structure shown in this disclosure is merely an illustrative example. In the exemplary embodiments, the corresponding structure can be changed according to actual needs, and this disclosure does not limit it.

[0250] In exemplary embodiments, the display substrate of this disclosure can be applied to display devices with pixel driving circuits, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., and this disclosure does not limit it.

[0251] This disclosure also provides a display device, which includes the aforementioned display substrate. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, and the embodiments of the present invention are not limited thereto.

[0252] While the embodiments disclosed herein are as described above, it should be noted that these embodiments are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the specific content shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the embodiments without departing from the scope of this disclosure.

Claims

1. A display substrate, comprising a display area and a bonding area located on at least one side of the display area, the display area comprising a plurality of sub-pixels forming a plurality of pixel rows and a plurality of pixel columns, a plurality of data signal lines, and at least one second signal line, the at least one sub-pixel comprising a pixel driving circuit and a light-emitting device connected to the pixel driving circuit, the plurality of sub-pixels comprising a first sub-pixel emitting red light, a third sub-pixel emitting blue light, and a second sub-pixel and a fourth sub-pixel emitting green light; the plurality of data signal lines comprising a first data signal line connected to the pixel driving circuit of the first sub-pixel, and a second data signal line connected to the pixel driving circuits of the second sub-pixel and the fourth sub-pixel. The plurality of pixel columns include a first pixel column and a second pixel column arranged alternately in a first direction. The first pixel column includes the first data signal line, the third data signal line, and the first sub-pixel and the third sub-pixel arranged alternately in a second direction. The second pixel column includes the second data signal line, the second signal trace, and the second sub-pixel and the fourth sub-pixel arranged alternately in a second direction. The first direction and the second direction intersect. The second signal trace is a signal trace that transmits a constant voltage signal, or the second signal trace and the second data signal line transmit the same data signal.

2. The display substrate according to claim 1, wherein, The width of the second data signal line is 1.2 to 1.5 of the width of the first data signal line, and the width of the second data signal line is 1.2 to 1.5 of the width of the third data signal line, wherein the width is the dimension in the first direction.

3. The display substrate according to claim 1, wherein, In at least one first pixel column, the first data signal line is connected to the pixel driving circuit of the first sub-pixel through a first data connection block, and the third data signal line is connected to the pixel driving circuit of the third sub-pixel through a third data connection block; the first data connection block is disposed on the side of the first data signal line close to the third data signal line and is connected to the first data signal line; the third data connection block is disposed on the side of the third data signal line close to the first data signal line and is connected to the third data signal line.

4. The display substrate according to claim 1, wherein, At least one first pixel column further includes a first power trace and a second power trace, the first power trace and the second power trace being configured to provide a first power signal to the connected pixel driving circuit; the first power trace is connected to the pixel driving circuit of the first sub-pixel in the pixel column, and the second power trace is connected to the pixel driving circuit of the third sub-pixel in the pixel column.

5. The display substrate according to any one of claims 1 to 4, wherein, The binding area includes at least a plurality of data leads, the second data signal line is directly connected to the data lead, one of the first data signal line and the third data signal line is directly connected to the data lead, and the other of the first data signal line and the third data signal line is connected to the data lead through a data connection line.

6. The display substrate according to claim 5, wherein, At least one of the data connection lines includes a first connection line extending along the first direction and a second connection line extending along the second direction. A first end of the first connection line is connected to the first data signal line or the third data signal line. A second end of the first connection line is connected to the first end of the second connection line. A second end of the second connection line is connected to the data lead-out line. In at least one second pixel column, a break is provided between the second connection line and the second signal trace.

7. The display substrate according to claim 6, wherein, Multiple first pixel columns are classified as first type pixel columns, and the first data signal line in the first type pixel column is connected to the first connection line; or, multiple first pixel columns are classified as second type pixel columns, and the third data signal line in the second type pixel column is connected to the first connection line.

8. The display substrate according to claim 6, wherein, The plurality of first pixel columns include a plurality of first-type pixel columns and a plurality of second-type pixel columns alternately arranged in the first direction, wherein the first data signal line in the first-type pixel column is connected to the first connection line, and the third data signal line in the second-type pixel column is connected to the first connection line.

9. The display substrate according to claim 6, wherein, In at least one first pixel column and a second pixel column adjacent to the first pixel column, the third data signal line is connected to the first connecting line; the third data signal line is disposed on the side of the first data signal line away from the second data signal line, and the second connecting line is disposed on the side of the second data signal line away from the first data signal line; or, the third data signal line is disposed on the side of the first data signal line close to the second data signal line, and the second connecting line is disposed on the side of the second data signal line close to the first data signal line.

10. The display substrate according to claim 6, wherein, In at least one first pixel column and a second pixel column adjacent to the first pixel column, the first data signal line is connected to the first connecting line; the first data signal line is disposed on the side of the third data signal line away from the second data signal line, and the second connecting line is disposed on the side of the second data signal line away from the third data signal line; or, the first data signal line is disposed on the side of the third data signal line close to the second data signal line, and the second connecting line is disposed on the side of the second data signal line close to the third data signal line.

11. The display substrate according to claim 6, wherein, Multiple first connecting lines are respectively connected to the first data signal line or the third data signal line through vias; from the side edge of the display area to the center line of the display area, the distance between the multiple vias and the lower edge of the display area gradually increases, or the distance between the multiple vias and the lower edge of the display area gradually decreases. The lower edge of the display area is the edge of the display area closer to the binding area, the side edge of the display area is the edge of the display area closer to the frame area, and the center line of the display area is a straight line that bisects the display area in the first direction and extends along the second direction.

12. The display substrate according to claim 6, wherein, Multiple first connection lines are respectively disposed between the last pixel row and the lower edge of the display area, and are connected to the first data signal line or the third data signal line through vias, with the multiple vias being flush in the first direction; the last pixel row is the pixel row in the display area that is closest to the binding area, and the lower edge of the display area is the edge of the display area closer to the binding area.

13. The display substrate according to claim 6, wherein, For a first data signal line and a second connection line connected to the same first connection line, the first pixel column where the first data signal line is located and the second pixel column where the second connection line is located are adjacent pixel columns; or, for a third data signal line and a second connection line connected to the same first connection line, the first pixel column where the third data signal line is located and the second pixel column where the second connection line is located are adjacent pixel columns.

14. The display substrate according to claim 6, wherein, For a first data signal line and a second connection line connected to the same first connection line, there are multiple first pixel columns and multiple second pixel columns between the first pixel column where the first data signal line is located and the second pixel column where the second connection line is located; or, for a third data signal line and a second connection line connected to the same first connection line, there are multiple first pixel columns and multiple second pixel columns between the first pixel column where the third data signal line is located and the second pixel column where the second connection line is located.

15. The display substrate according to claim 6, wherein, In a direction perpendicular to the display substrate, the display substrate includes multiple conductive layers, and the first connecting line and the second connecting line are disposed in different conductive layers, or the first connecting line and the second connecting line are disposed in the same conductive layer.

16. The display substrate according to claim 6, wherein, The display area further includes at least one auxiliary signal trace extending along the second direction. The auxiliary signal trace is disposed between adjacent first pixel columns and second pixel columns, and the auxiliary signal trace is a signal trace for transmitting constant voltage signals.

17. The display substrate according to any one of claims 1 to 3, wherein, The binding area includes at least multiple data leads, and the first data signal line, the second data signal line, and the third data signal line are directly connected to the data leads.

18. The display substrate according to claim 17, wherein, The first pixel column further includes a first power line, and the second pixel column further includes a third power trace. The first power line and the third power trace are configured to provide a first power signal to the connected pixel driving circuit. The first power line is connected to the pixel driving circuit of the first sub-pixel in the first pixel column, and the third power trace is connected to the pixel driving circuit of the third sub-pixel in the first pixel column. Alternatively, the first power line is connected to the pixel driving circuit of the third sub-pixel in the first pixel column, and the third power trace is connected to the pixel driving circuit of the first sub-pixel in the first pixel column.

19. The display substrate according to any one of claims 1 to 3, wherein, The display area further includes at least one auxiliary signal trace extending along the second direction, the auxiliary signal trace being disposed between adjacent first pixel columns and second pixel columns; the first pixel column further includes a first power line, the first power line and the auxiliary signal trace being configured to provide a first power signal to the connected pixel driving circuit; the first power line is connected to the pixel driving circuit of the first sub-pixel in the first pixel column, and the auxiliary signal trace is connected to the pixel driving circuit of the third sub-pixel in the first pixel column, or, the first power line is connected to the pixel driving circuit of the third sub-pixel in the first pixel column, and the auxiliary signal trace is connected to the pixel driving circuit of the first sub-pixel in the first pixel column.

20. A display device comprising a display substrate as described in any one of claims 1 to 19.

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