Display substrate and display apparatus

Abstract

A display substrate and a display apparatus. The display substrate comprises a base and a plurality of sub-pixels arranged on one side of the base. At least some of the sub-pixels comprise a pixel drive circuit, wherein at least one pixel drive circuit comprises a plurality of transistors and at least one capacitor. The plurality of transistors at least comprise a drive transistor, and the at least one capacitor at least comprises a first capacitor, wherein a first electrode plate of the first capacitor is electrically connected to a control electrode of the drive transistor, and a second electrode plate of the first capacitor is electrically connected to a second electrode of the drive transistor; and in a direction perpendicular to the plane where the base is located, the second electrode plate of the first capacitor is located on the side of the first electrode plate of the first capacitor that is away from the base, and an orthographic projection of the first electrode plate of the first capacitor on the base at least partially overlaps with an orthographic projection of the second electrode plate of the first capacitor on the base.

Description

Display substrate, display device

[0001] This application claims priority to Chinese Patent Application No. 202411961252.0, filed on December 27, 2024, entitled “Display Substrate, Display Device”, the contents of which are to be understood as incorporated herein by reference. Technical Field

[0002] This disclosure relates to, but is not limited to, the field of display technology, specifically to a display substrate and a display device. Background Technology

[0003] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, embodiments of this disclosure provide a display substrate, including: a substrate and a plurality of sub-pixels disposed on one side of the substrate, at least some of the sub-pixels including a pixel driving circuit, at least one pixel driving circuit including a plurality of transistors and at least one capacitor, the plurality of transistors including at least a driving transistor, the at least one capacitor including at least a first capacitor, a first electrode of the first capacitor being electrically connected to the control electrode of the driving transistor, and a second electrode of the first capacitor being electrically connected to the second electrode of the driving transistor.

[0006] In a direction perpendicular to the plane of the substrate, the second plate of the first capacitor is located on the side of the first plate of the first capacitor away from the substrate, and the orthographic projection of the first plate of the first capacitor on the substrate at least partially overlaps with the orthographic projection of the second plate of the first capacitor on the substrate.

[0007] In an exemplary embodiment, the first plate of the first capacitor includes a first main body portion, and in the same sub-pixel, the orthographic projection of the first main body portion on the substrate is located within the range of the orthographic projection of the second plate of the first capacitor on the substrate.

[0008] In an exemplary embodiment, the pixel driving circuit further includes at least one connection electrode, which is located on the side of the second plate of the first capacitor away from the substrate in the same sub-pixel in a direction perpendicular to the plane of the substrate.

[0009] In an exemplary embodiment, in a direction perpendicular to the plane of the substrate, the driving transistor is located on the side of the second plate of the first capacitor away from the substrate, and the orthogonal projection of the driving transistor on the substrate is within the range of the orthogonal projection of the second plate of the first capacitor on the substrate;

[0010] The at least one connection electrode includes at least a first connection electrode, and in the same sub-pixel, the first plate of the first capacitor is electrically connected to the control electrode of the driving transistor through the first connection electrode.

[0011] In an exemplary embodiment, the first electrode of the first capacitor includes a first main body and a first connecting part. The first main body overlaps at least partially with the second electrode of the first capacitor. The orthographic projection of at least a portion of the structure of the first connecting part on the substrate does not overlap with the orthographic projection of the second electrode of the first capacitor on the substrate.

[0012] In the same sub-pixel, one end of the first connecting portion is connected to the first main body portion, and the other end is electrically connected to the control electrode of the driving transistor through the first connecting electrode. The first connecting portion is located at the edge of the first main body portion, at the position closest to the control electrode of the driving transistor.

[0013] In an exemplary embodiment, the at least one connection electrode includes the second electrode of the driving transistor, and the orthographic projection of the second electrode of the driving transistor on the substrate is within the range of the orthographic projection of the second plate of the first capacitor on the substrate.

[0014] In an exemplary embodiment, the driving transistor further includes a bottom gate, which is located between the second plate of the first capacitor and the active layer of the driving transistor in a direction perpendicular to the plane of the substrate.

[0015] In the same sub-pixel, the bottom gate of the driving transistor is electrically connected to the second plate of the first capacitor, and the bottom gate of the driving transistor at least partially overlaps with the orthographic projection of the active layer of the driving transistor onto the substrate.

[0016] In an exemplary embodiment, the display substrate further includes a plurality of control lines electrically connected to the control electrode of at least one transistor. In a direction perpendicular to the plane of the substrate, the plurality of control lines are located on the side of the second electrode of the first capacitor away from the substrate. The orthographic projection of the plurality of control lines on the substrate does not overlap with the orthographic projection of the first electrode of the first capacitor on the substrate.

[0017] In an exemplary embodiment, the plurality of transistors includes at least one first type transistor, the at least one first type transistor including at least the driving transistor, and in a direction perpendicular to the plane of the substrate, the first type transistor includes: an active layer of the first type transistor located on the side of the second plate of the first capacitor away from the substrate, a control electrode of the first type transistor located on the side of the active layer of the first type transistor away from the substrate, and a first electrode and a second electrode located on the side of the control electrode of the first type transistor away from the substrate.

[0018] The at least one capacitor further includes a second capacitor, in the same sub-pixel, the second plate of the second capacitor is electrically connected to the second plate of the first capacitor and the second electrode of the driving transistor, and the first plate of the second capacitor and the orthographic projection of the second plate of the second capacitor on the substrate at least partially overlap.

[0019] In an exemplary embodiment, the first plate of the second capacitor includes a second main body portion, and in the same sub-pixel, the orthographic projection of the second main body portion on the substrate is located within the range of the orthographic projection of the second plate of the second capacitor on the substrate.

[0020] In an exemplary embodiment, the first electrode plate of the second capacitor is disposed on the same layer as the first electrode plate of the first capacitor, and the second electrode plate of the second capacitor is disposed on the same layer as the second electrode plate of the first capacitor; in the same sub-pixel, the second capacitor and the first capacitor are arranged sequentially along the second direction.

[0021] In an exemplary embodiment, the second capacitor further includes a third plate, which is located on the side of the second capacitor away from the substrate in a direction perpendicular to the plane of the substrate.

[0022] In the same sub-pixel: the third plate of the second capacitor at least partially overlaps with the orthographic projection of the second plate of the second capacitor onto the substrate, and the third plate of the second capacitor is electrically connected to the first plate of the second capacitor.

[0023] In an exemplary embodiment, in a direction perpendicular to the plane of the substrate, the third plate of the second capacitor is located between the second plate of the second capacitor and the active layer of the first type of transistor, or the third plate of the second capacitor is disposed on the same layer as the control electrode of the first type of transistor.

[0024] In an exemplary embodiment, the second capacitor further includes a fourth electrode plate. In a direction perpendicular to the plane of the substrate, the third electrode plate of the second capacitor is located between the second electrode plate of the second capacitor and the active layer of the first type of transistor, and the fourth electrode plate of the second capacitor is disposed on the same layer as the control electrode of the first type of transistor.

[0025] In the same sub-pixel, the fourth plate of the second capacitor is electrically connected to the second plate of the second capacitor, and the orthographic projection of the fourth plate of the second capacitor onto the substrate at least partially overlaps with that of the third plate of the second capacitor.

[0026] In an exemplary embodiment, in a direction perpendicular to the plane of the substrate, the second plate of the second capacitor is located on the side of the first plate of the second capacitor away from the substrate. In the same sub-pixel: the orthographic projection of the first capacitor and the second capacitor on the substrate at least partially overlaps, and the second plate of the first capacitor serves as the first plate of the second capacitor.

[0027] In an exemplary embodiment, within the same sub-pixel, the main body of the first plate of the first capacitor is located within the range of the orthographic projection of the first plate of the second capacitor onto the substrate.

[0028] In an exemplary embodiment, in a direction perpendicular to the plane of the substrate, the second plate of the second capacitor is located between the first plate of the second capacitor and the active layer of the first type of transistor, or the second plate of the second capacitor is disposed on the same layer as the control electrode of the first type of transistor.

[0029] In an exemplary embodiment, the second capacitor further includes a third electrode plate. In a direction perpendicular to the plane of the substrate, the second electrode plate of the second capacitor is located between the first electrode plate of the second capacitor and the active layer of the first type of transistor. The third electrode plate of the second capacitor is disposed on the same layer as the control electrode of the first type of transistor. In the same sub-pixel, the third electrode plate of the second capacitor is electrically connected to the first electrode plate of the second capacitor.

[0030] In an exemplary embodiment, the second capacitor further includes a fourth plate, which is disposed on the same layer as the first plate and the second plate.

[0031] Within the same sub-pixel, the fourth plate of the second capacitor is electrically connected to the second plate of the second capacitor.

[0032] In an exemplary embodiment, the orthographic projection of the second plate of the second capacitor onto the substrate is located within the range of the orthographic projection of the third plate of the second capacitor onto the substrate.

[0033] In an exemplary embodiment, the orthogonal projections of multiple plates in the same second capacitor onto the substrate at least partially overlap.

[0034] In an exemplary embodiment, the plurality of transistors further includes at least one second type of transistor, the second type of transistor including: an active layer of the second type of transistor, a control electrode of the second type of transistor, a first electrode and a second electrode of the second type of transistor. In a direction perpendicular to the plane of the substrate, the active layer of the second type of transistor is located on the side of the first plate of the first capacitor close to the substrate. The control electrode of the second type of transistor is disposed in the same layer as the first plate of the first capacitor. The first electrode and the second electrode of the second type of transistor are disposed in the same layer as the first electrode and the second electrode of the first type of transistor.

[0035] The second type of transistor includes a fifth transistor as a light-emitting control transistor, and the first type of transistor includes the driving transistor and a first transistor as a reset transistor; in the same sub-pixel, the driving transistor and the first capacitor's orthogonal projection on the substrate at least partially overlap; in a second direction, the first transistor and the fifth transistor are located on opposite sides of the driving transistor; in a first direction, the first transistor and the fifth transistor are located on the same side of the driving transistor, the first capacitor, and the second capacitor; the first direction intersects the second direction.

[0036] In an exemplary embodiment, the display substrate further includes a plurality of control lines extending along the first direction, the plurality of control lines including a first reset control line and a first light emission control line, the first light emission control line and the first reset control line being disposed in the same layer as the first electrode and the second electrode;

[0037] The plurality of sub-pixels form a plurality of rows of sub-pixels. The first reset control line is electrically connected to the control electrode of at least one first transistor in at least one row of sub-pixels. The first light emission control line is electrically connected to the control electrode of at least one fifth transistor in at least one row of sub-pixels. In the same sub-pixel, the first light emission control line and the first reset control line are located on opposite sides of the first capacitor. The second capacitor is located on the side of the first reset control line away from the first capacitor.

[0038] In an exemplary embodiment, the first type of transistor further includes a second transistor as a reset transistor and a fourth transistor as a data write transistor. The plurality of control lines further include a third reset control line and a scan control line. The third reset control line is disposed on the same layer as the control electrode of the first type of transistor, and the scan control line is disposed on the same layer as the first electrode and the second electrode.

[0039] The third reset control line is electrically connected to the control electrode of at least one second transistor in at least one row of sub-pixels, and the scan control line is electrically connected to at least one fourth transistor in at least one row of sub-pixels. In the same sub-pixel, in the first direction, the second transistor and the fourth transistor are located on the same side of the second capacitor. In the second direction, the second transistor and the third reset control line are located between the first transistor and the fourth transistor. The scan control line is located on the side of the third reset control line away from the first transistor. The third reset control line and the scan control line overlap with the second capacitor at least partially, and there is no overlapping area between the third reset control line and the scan control line and the first capacitor.

[0040] In an exemplary embodiment, the first type of transistor further includes a sixth transistor as a light-emitting transistor and a seventh transistor as a reset transistor, and the plurality of control lines further include a second reset control line and a second light-emitting control line, wherein the second reset control line and the second light-emitting control line are disposed on the same layer as the control electrode of the first type of transistor.

[0041] The second light-emitting control line is electrically connected to the control electrode of at least one sixth transistor in at least one row of sub-pixels, and the second reset control line is electrically connected to the control electrode of at least one seventh transistor in at least one row of sub-pixels. In the same sub-pixel, in the second direction, the sixth transistor and the second light-emitting control line are located on the side of the fourth transistor away from the second transistor, the seventh transistor and the second reset control line are located on the side of the sixth transistor away from the fourth transistor, and the sixth transistor and the seventh transistor are located on the side of the second capacitor away from the first capacitor. The second reset control line, the second light-emitting control line and the first capacitor and the second capacitor do not overlap.

[0042] Secondly, this disclosure also provides a display device, including the display substrate described in any of the above embodiments.

[0043] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0044] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shape and size of each component in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0045] Figure 1 is a schematic diagram of the structure of a display device;

[0046] Figure 2a is a schematic diagram of a display substrate;

[0047] Figure 2b shows a schematic diagram of a display substrate;

[0048] Figure 2c shows an enlarged structural diagram of the first border region;

[0049] Figure 3 is a schematic cross-sectional view of a display substrate;

[0050] Figure 4 is a schematic diagram of the equivalent circuit of a pixel driving circuit;

[0051] Figure 5a shows a schematic diagram of the structure of the display substrate provided in an embodiment of this disclosure;

[0052] Figure 5b is a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0053] Figure 5c shows a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0054] Figure 5d is a schematic diagram of the structure of a display substrate provided in an exemplary embodiment of the present disclosure;

[0055] Figure 6a shows a cross-sectional structure at position M1-M1 in Figure 5a;

[0056] Figure 6b shows a cross-sectional structural diagram of the M2-M2 position in Figure 5b;

[0057] Figure 6c shows a cross-sectional structural diagram of the M3-M3 position in Figure 5c;

[0058] Figure 6d shows a cross-sectional structure at position M4-M4 in Figure 5d;

[0059] Figure 7a shows a schematic diagram of a planar structure of a capacitor structure provided in an exemplary embodiment of the present disclosure;

[0060] Figure 7b shows a cross-sectional structural diagram of the M5-M5 position in Figure 7a;

[0061] Figure 7c shows a schematic diagram of a planar structure of a capacitor structure provided in an exemplary embodiment of the present disclosure;

[0062] Figure 7d shows a cross-sectional structural diagram of the M6-M6 position in Figure 7c;

[0063] Figure 7e shows a schematic diagram of a planar structure of a capacitor structure provided in an exemplary embodiment of the present disclosure;

[0064] Figure 7f shows a cross-sectional structural diagram of the M7-M7 position in Figure 7e;

[0065] Figure 7g shows a schematic diagram of a planar structure of a capacitor structure provided in an exemplary embodiment of the present disclosure;

[0066] Figure 7h shows a cross-sectional structural diagram of the M8-M8 position in Figure 7g;

[0067] Figure 8 is a schematic diagram of a display substrate after a first semiconductor layer pattern has been formed, according to an exemplary embodiment of the present disclosure.

[0068] Figure 9a is a schematic diagram of a display substrate after the formation of the first conductive layer pattern according to an exemplary embodiment of the present disclosure.

[0069] Figure 9b is a schematic diagram of the first conductive layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0070] Figure 10a is a schematic diagram of a display substrate after the formation of a second conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0071] Figure 10b is a schematic diagram of the second conductive layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0072] Figure 11a is a schematic diagram of a display substrate after the formation of a third conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0073] Figure 11b is a schematic diagram of the third conductive layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0074] Figure 12a is a schematic diagram of a display substrate after a second semiconductor layer pattern has been formed, according to an exemplary embodiment of the present disclosure.

[0075] Figure 12b is a schematic diagram of the second semiconductor layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0076] Figure 13a is a schematic diagram of a display substrate after the fourth conductive layer pattern is formed, according to an exemplary embodiment of the present disclosure.

[0077] Figure 13b is a schematic diagram of the fourth conductive layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0078] Figure 14 is a schematic diagram of a display substrate after the formation of the sixth insulating layer pattern according to an exemplary embodiment of the present disclosure;

[0079] Figure 15a is a schematic diagram of a display substrate after the fifth conductive layer pattern is formed, according to an exemplary embodiment of the present disclosure.

[0080] Figure 15b is a schematic diagram of the fifth conductive layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0081] Figure 16 is a schematic diagram of the formation of a first planarization layer pattern according to an exemplary embodiment of the present disclosure;

[0082] Figure 17a is a schematic diagram of a display substrate after the formation of the sixth conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0083] Figure 17b is a schematic diagram of the sixth conductive layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0084] Figure 18 is a schematic diagram of a display substrate after the formation of a second planarization layer according to an exemplary embodiment of the present disclosure;

[0085] Figure 19a is a schematic diagram of a display substrate after an anode conductive layer pattern has been formed, according to an exemplary embodiment of the present disclosure.

[0086] Figure 19b is a schematic diagram of the anode conductive layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0087] Figure 20a is a schematic diagram of a display substrate after forming a pixel definition layer pattern according to an exemplary embodiment of the present disclosure;

[0088] Figure 20b is a schematic diagram of a pixel definition layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0089] Figure 21a is a schematic diagram of a display substrate after the formation of a third conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0090] Figure 21b is a schematic diagram of the third conductive layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0091] Figure 22 is a schematic diagram of a display substrate after the formation of the sixth insulating layer pattern according to an exemplary embodiment of the present disclosure;

[0092] Figure 23a is a schematic diagram of a display substrate after the fifth conductive layer pattern is formed, according to an exemplary embodiment of the present disclosure.

[0093] Figure 23b is a schematic diagram of the fifth conductive layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0094] Figure 24a is a schematic diagram of a display substrate after the fourth conductive layer pattern is formed, according to an exemplary embodiment of the present disclosure.

[0095] Figure 24b is a schematic diagram of the fourth conductive layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0096] Figure 25 is a schematic diagram of a display substrate after the formation of the sixth insulating layer pattern according to an exemplary embodiment of the present disclosure;

[0097] Figure 26a is a schematic diagram of a display substrate after the fifth conductive layer pattern is formed, according to an exemplary embodiment of the present disclosure.

[0098] Figure 26b is a schematic diagram of the fifth conductive layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0099] Figure 27a is a schematic diagram of a display substrate after the formation of a third conductive layer pattern according to an exemplary embodiment of the present disclosure;

[0100] Figure 27b is a schematic diagram of the third conductive layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0101] Figure 28a is a schematic diagram of a display substrate after the fourth conductive layer pattern is formed, according to an exemplary embodiment of the present disclosure.

[0102] Figure 28b is a schematic diagram of the fourth conductive layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0103] Figure 29 is a schematic diagram of a display substrate after the formation of the sixth insulating layer pattern according to an exemplary embodiment of the present disclosure;

[0104] Figure 30a is a schematic diagram of a display substrate after the fifth conductive layer pattern is formed, according to an exemplary embodiment of the present disclosure.

[0105] Figure 30b is a schematic diagram of the fifth conductive layer in a display substrate provided in an exemplary embodiment of the present disclosure;

[0106] Figure 31 is a schematic diagram of a display device provided in an embodiment of this disclosure. Detailed Implementation

[0107] The embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other. To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of some known functions and components have been omitted. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in general design.

[0108] The scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the thickness and spacing of each film layer, and the width and spacing of each signal line, can be adjusted according to actual conditions. The drawings described in this disclosure are merely structural schematic diagrams, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0109] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0110] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the direction in which each constituent element is described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0111] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0112] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0113] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged. In embodiments of this disclosure, the gate electrode can be referred to as the control electrode.

[0114] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0115] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0116] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0117] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons. Small deformations due to tolerances are possible, as are chamfers, curved edges, and other variations.

[0118] In the embodiments of this disclosure, "about" means a value that is not strictly limited and is within the range of process and measurement errors.

[0119] Figure 1 shows a schematic diagram of a display device. The display substrate may include a timing controller, a data signal driving circuit, a scan signal driving circuit, a light emission signal driving circuit, and a pixel array. The timing controller is connected to the data signal driving circuit, the scan signal driving circuit, and the light emission signal driving circuit. The data signal driving circuit is connected to multiple data signal lines (D1 to Dn), the scan signal driving circuit is connected to multiple scan signal lines (G1 to Gm), and the light emission signal driving circuit is connected to multiple light emission signal lines (E1 to Eo). The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light emission device connected to the circuit unit. The circuit unit may include a pixel driving circuit, which may be connected to the scan signal lines, the light emission signal lines, and the data signal lines (which may be referred to as data lines). In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals of specifications suitable for the data signal driving circuit to the data signal driving circuit, clock signals, scan start signals, etc. of specifications suitable for the scan signal driving circuit to the scan signal driving circuit, and clock signals, transmit stop signals, etc. of specifications suitable for the light emission signal driving circuit to the light emission signal driving circuit. The data signal driving circuit can use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data signal driving circuit can sample the grayscale values ​​using a clock signal and apply the data voltage corresponding to the grayscale value to data signal lines D1 to Dn on a pixel-by-pixel basis, where n can be a natural number. The scan signal driving circuit can generate scan signals to be provided to scan signal lines G1, G2, G3, ..., Gm by receiving clock signals, scan start signals, etc., from the timing controller. For example, the scan signal driving circuit can sequentially provide scan signals with conduction level pulses to scan signal lines G1 to Gm. For example, a scan signal driving circuit can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal, where m can be a natural number. A light-emitting signal driving circuit can generate transmit signals to be provided to light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from a timing controller. For example, a light-emitting signal driving circuit can sequentially provide transmit signals with cutoff level pulses to light-emitting signal lines E1 to Eo. For example, a light-emitting driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals, provided in the form of cutoff level pulses, to the next stage circuit under the control of a clock signal, where o can be a natural number.

[0120] Figure 2a is a schematic diagram of a planar structure of a display substrate. As shown in Figure 2a, the display substrate may include multiple pixel units P arranged in a matrix. At least one pixel unit P includes a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each of the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 includes a pixel driving circuit and a light-emitting device. The pixel driving circuits in the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 are respectively connected to a scan signal line, a data signal line, and a light-emitting signal line. The pixel driving circuits are configured to receive the data voltage transmitted by the data signal line under the control of the scan signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device. The light-emitting devices in the first sub-pixel P1, second sub-pixel P2, and third sub-pixel P3 are respectively connected to the pixel driving circuit of their respective sub-pixels. The light-emitting devices are configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of their respective sub-pixels.

[0121] In an exemplary embodiment, a pixel unit P may include a red (R) sub-pixel, a green (G) sub-pixel, and a blue (B) sub-pixel. In an exemplary embodiment, the shape of the sub-pixels in the pixel unit may be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels may be arranged horizontally side by side, vertically side by side, or in a triangular arrangement; this disclosure does not limit the specific arrangement.

[0122] Figure 2b shows a schematic diagram of a display panel structure. As shown in Figure 2b, the display panel may include a display area AA and a border area BB surrounding the display area AA. In some examples, the border area BB may include: a first border area (bottom border) B1 and a second border area (top border) arranged opposite each other in the second direction Y, and a third border area (left border) B3 and a fourth border area (right border) B4 arranged opposite each other in the first direction X. The first border area B1 is connected to the third border area B3 and the fourth border area B4, and the second border area B2 is connected to the third border area B3 and the fourth border area B4. In some examples, the display area AA may include a first edge (bottom edge) and a second edge (top edge) arranged opposite each other in the second direction Y, and a third edge (left edge) and a fourth edge (right edge) arranged opposite each other in the first direction X. The display area AA may include multiple sub-pixels Pxij arranged in a regular pattern. Each sub-pixel may include a pixel driving circuit and a light-emitting device. The first border area B1 may include a bonding circuit that connects signal lines to an external driving device. The third border area B3 and the fourth border area B4 may include a gate driving circuit and a second power supply line VSS that transmits voltage signals to the multiple sub-pixels.

[0123] Figure 2c shows a schematic diagram of the planar structure of the first bezel region B1. In a plane parallel to the display substrate, the first bezel region B1 may include a first fan-out area 11, a bending area 12, a second fan-out area 13, and a bonding area 14 arranged sequentially along the direction away from the display area AA. The bonding area 14 may include a driver chip area 141, a third fan-out area 142, and a bonding electrode area 143 arranged sequentially along the direction away from the bending area 12 of the second fan-out area 13. The first fan-out area 11 may include a data fan-out line, a first power line, and a second power line VSS. The data fan-out line is located in the middle of the first fan-out area 11 and includes multiple data connection lines. The multiple data connection lines are configured to connect the data signal lines (Data Line) of the display area AA in a fan-out routing manner. The first power line is configured to connect the high-voltage power line (VDD) of the display area AA. The second power line is a low-voltage power line (VSS) located in the third bezel region B3 and the fourth bezel region B4. The bending area 12 may include a composite insulating layer with grooves, configured to bend the bonding area 14 to the back of the display area AA. The second fan-out area 13 includes multiple data connection lines led out in a fan-out routing manner. The driver chip area 141 may house an integrated circuit (IC) 20, configured to connect to the multiple data connection lines. The bonding electrode area 143 includes multiple bonding pads, configured to bond to the flexible printed circuit (FPC) 30. In an exemplary embodiment, the integrated circuit (IC) 20 may be bonded to the driver chip area 141, and the flexible printed circuit (FPC) 30 may be bonded to the bonding electrode area 142. In an exemplary embodiment, the integrated circuit 20 (which may be referred to as a data driving circuit or driving circuit) may generate driving signals required to drive sub-pixels and may provide the driving signals to the sub-pixel Pxij located in the display area AA. For example, the driving signal may be a data signal controlling the brightness of the sub-pixel. In an exemplary embodiment, the bonding electrode area 143 may be provided with a pad including a plurality of pins, and the flexible circuit board 30 may be bonded to the pad.

[0124] Figure 3 is a cross-sectional schematic diagram of a display substrate, illustrating the structure of three sub-pixels of an OLED display substrate. As shown in Figure 3, on a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 disposed on a substrate 101, a light-emitting structure layer 103 disposed on the side of the driving circuit layer 102 away from the substrate 101, and an encapsulation layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as spacers, etc., which are not limited herein.

[0125] In an exemplary embodiment, the substrate 101 may be a flexible substrate or a rigid substrate. The driving circuit layer 102 for each sub-pixel may include multiple transistors and storage capacitors constituting the pixel driving circuit. The light-emitting structure layer 103 may include an anode 301, an organic light-emitting layer 302, and a cathode 303. The anode 301 is connected to the drain electrode of the driving transistor 210 through a via. The organic light-emitting layer 302 is connected to the anode 301, and the cathode 303 is connected to the organic light-emitting layer 302. The organic light-emitting layer 302 emits light of a corresponding color under the driving force of the anode 301 and the cathode 303. The encapsulation layer 104 may include a first encapsulation layer 401, a second encapsulation layer 402, and a third encapsulation layer 403 stacked together. The first and third encapsulation layers 401 and 403 may be made of inorganic materials, while the second encapsulation layer 402 may be made of organic materials. The second encapsulation layer 402 is disposed between the first and third encapsulation layers 401 and 403, ensuring that external moisture cannot enter the light-emitting structure layer 103.

[0126] In an exemplary embodiment, the organic light-emitting layer 302 may include stacked hole injection layer (HIL), hole transport layer (HTL), electron block layer (EBL), emitting layer (EML), hole block layer (HBL), electron transport layer (ETL), and electron injection layer (EIL). In this exemplary embodiment, the hole injection layer of all sub-pixels may be a common layer connected together, the electron injection layer of all sub-pixels may be a common layer connected together, the hole transport layer of all sub-pixels may be a common layer connected together, the electron transport layer of all sub-pixels may be a common layer connected together, and the hole block layer of all sub-pixels may be a common layer connected together. The emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron block layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0127] In an exemplary embodiment, the pixel driving circuit can be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, 8T1C, or 7T2C structure. As shown in Figure 4, the pixel driving circuit can include seven transistors (first transistor T1 to seventh transistor T76) and two capacitors C (first capacitor C1 and second capacitor C2). The pixel driving circuit can be connected to ten signal lines (data signal line DL, scan control line Gate, first reset control line Reset1, second reset control line Reset2, third reset control line Reset3, first light emission control line EM1, second light emission control line EM2, first initial signal line Vinit1, second initial signal line Vinit2, first power supply line VDD, and second power supply line VSS). In an exemplary embodiment, the third reset control line Reset3 can receive the signal from the first reset control line Reset1, which can reduce the number of gate driving circuits (GOA circuits) and is beneficial for narrowing the bezel. The pixel driving circuit will be described below with reference to Figure 4:

[0128] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, a fourth node N4, and a fifth node N5. The first node N1 is connected to the control electrode of the third transistor T3, the first terminal of the first capacitor C1, and the second electrode of the first transistor T1. The second node N2 is connected to the first electrode of the third transistor T3 and the second electrode of the fifth transistor T5. The third node N3 is connected to the second terminal of the first capacitor C1, the first terminal of the second capacitor C2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6. The fourth node N4 is connected to the second terminal of the second capacitor C2, the second electrode of the second transistor T2, and the second electrode of the fourth transistor T4. The fifth node N5 is connected to the second electrode of the sixth transistor T6, the second electrode of the seventh transistor T7, and the anode of the light-emitting device EL.

[0129] In an exemplary embodiment, the first end of the first capacitor C1 is connected to the first node N1, and the second end of the first capacitor C1 is connected to the third node N3; the first end of the second capacitor C2 is connected to the third node N3, and the second end of the second capacitor C2 may be connected to the fourth node N4.

[0130] The control electrode of the first transistor T1 is connected to the first reset control line Reset1, the first terminal of the first transistor T1 is connected to the first initial signal line Vinit1, and the second terminal of the first transistor is connected to the first node N1. When a conduction-level reset signal is applied to the first reset control line Reset1, the first transistor T1 transmits an initialization voltage to the control electrode of the third transistor T3 to initialize the charge on the control electrode of the third transistor T3.

[0131] The control electrode of the second transistor T2 is connected to the third reset control line Reset3, the first electrode of the second transistor T2 is connected to the first initial signal line Vinit1, and the second electrode of the second transistor T2 is connected to the fourth node N4. When a conduction-level reset signal is applied to the third reset control line Reset3, the second transistor T2 transmits an initialization voltage to the fourth node N4 to initialize or release the accumulated charge in the fourth node N4.

[0132] The control electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second node N2, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called the driving transistor. The third transistor T3 determines the amount of driving current flowing between the first power line VDD and the second power line VSS based on the potential difference between its control electrode and its first electrode.

[0133] The control electrode of the fourth transistor T4 is connected to the scan control line Gate, the first electrode of the fourth transistor T4 is connected to the data signal line DL, and the second electrode of the fourth transistor T4 is connected to the fourth node N4. The fourth transistor T4 can be called a switching transistor. When a conduction-level scan signal is applied to the scan control line Gate, the fourth transistor T4 causes the data voltage of the data signal line DL to be input to the pixel driving circuit.

[0134] The control electrode of the fifth transistor T5 is connected to the first light-emitting control line EM1, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the second node N2. The control electrode of the sixth transistor T6 is connected to the second light-emitting control line EM2, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light-emitting device (also the fifth node N5). The fifth transistor T5 and the sixth transistor T6 can be referred to as light-emitting transistors (or light-emitting control transistors). When a conduction-level light-emitting signal is applied to the first light-emitting control line EM1 and the second light-emitting control line EM2, the fifth transistor T5 and the sixth transistor T6 conduct, forming a driving current path between the first power supply line VDD and the second power supply line VSS, causing the light-emitting device to emit light.

[0135] The control electrode of the seventh transistor T7 is connected to the second reset control line Reset2, the first electrode of the seventh transistor T7 is connected to the second initial signal line Vinit2, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device (also the fifth node N5). When a conduction-level reset signal is applied to the second reset control line Reset2, the seventh transistor T7 transmits an initialization voltage to the first electrode of the light-emitting device EL, so as to initialize or release the accumulated charge in the first electrode of the light-emitting device EL.

[0136] In an exemplary embodiment, the second electrode of the light-emitting device EL is connected to the second power line VSS, the signal of the second power line VSS is a low-level signal, and the signal of the first power line VDD is a continuously high-level signal.

[0137] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 can be low-temperature polycrystalline silicon thin-film transistors (also known as P-type transistors), or oxide thin-film transistors (also known as N-type transistors), or a combination of low-temperature polycrystalline silicon thin-film transistors and oxide thin-film transistors. For example, in Figure 4, the first transistor T1 to the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 can be oxide thin-film transistors, and the fifth transistor T5 can be a low-temperature polycrystalline silicon thin-film transistor. Using the same type of transistor in the pixel driving circuit simplifies the process flow, reduces the manufacturing difficulty of the display panel, and improves the product yield. The active layer of the low-temperature polycrystalline silicon thin-film transistor is made of low-temperature polycrystalline silicon (LTPS), while the active layer of the oxide thin-film transistor is made of oxide semiconductor. Low-temperature polycrystalline silicon thin-film transistors (LTPTs) have advantages such as high mobility and fast charging, while oxide thin-film transistors (OTTs) have advantages such as low leakage current, low-frequency drive capability, and low power consumption. Integrating LTPTs and OTTs onto a single display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate allows for the utilization of the advantages of both, enabling low-frequency drive, reducing power consumption, and improving display quality.

[0138] In an exemplary embodiment, the light-emitting device EL can be an organic light-emitting diode (OLED), including a first electrode (anode), an organic light-emitting layer, and a second electrode (cathode) stacked together.

[0139] In the pixel driving circuit shown in Figure 4, when the data voltage of the data signal line DL changes (or fluctuates), it affects the voltage of the third node N3 (i.e., the second terminal of the driving transistor T3). The voltage of the third node N3 affects the voltage of the first node N1 (i.e., the control terminal of the driving transistor T3) through the first capacitor C1. The first node N1 usually has parasitic capacitance, which makes the voltage of the first node N1 not follow the voltage change of the third node N3 100%. When the voltage of the third node N3 fluctuates with the data voltage of the data signal line DL, the voltage fluctuation of the first node N1 (i.e., the control terminal of the driving transistor T3) is inconsistent, which causes the gate-source voltage Vgs of the third transistor T3 (i.e., the driving transistor) to be different, resulting in uneven image display.

[0140] An exemplary embodiment of this disclosure provides a display substrate, which may include: a substrate and a plurality of sub-pixels disposed on one side of the substrate, at least some of the sub-pixels including a pixel driving circuit, at least one pixel driving circuit including a plurality of transistors and at least one capacitor, the plurality of transistors including at least a driving transistor, the at least one capacitor including at least a first capacitor, a first plate of the first capacitor being electrically connected to the control electrode of the driving transistor, and a second plate of the first capacitor being electrically connected to the second electrode of the driving transistor.

[0141] In a direction perpendicular to the plane of the substrate, the second plate of the first capacitor is located on the side of the first plate of the first capacitor away from the substrate, and the orthographic projection of the first plate of the first capacitor on the substrate at least partially overlaps with the orthographic projection of the second plate of the first capacitor on the substrate.

[0142] The display substrate provided in this embodiment includes a plurality of sub-pixels. At least one sub-pixel includes a pixel driving circuit. The pixel driving circuit includes a driving transistor and a first capacitor. The first plate of the first capacitor is electrically connected to the control electrode of the driving transistor. The second plate of the first capacitor is electrically connected to the second electrode of the driving transistor. The second plate of the first capacitor is located on the side of the first plate away from the substrate. The orthographic projection of the first plate of the first capacitor on the substrate and the orthographic projection of the second plate of the first capacitor on the substrate at least partially overlap. This can reduce the parasitic capacitance of the control electrode of the driving transistor and improve display uniformity.

[0143] As shown in Figures 5a to 5d, these are schematic diagrams of the planar structure of the display substrate provided in the embodiments of this disclosure. The display substrate provided in the embodiments of this disclosure may include: a substrate and a plurality of sub-pixels Pxij disposed on one side of the substrate. At least some of the sub-pixels Pxij include a pixel driving circuit. At least one pixel driving circuit includes a plurality of transistors and at least one capacitor. The plurality of transistors include at least a driving transistor T3. The at least one capacitor includes at least a first capacitor C1. The first plate C11 of the first capacitor C1 is electrically connected to the control electrode T3g of the driving transistor T3. The second plate C12 of the first capacitor C1 is electrically connected to the second electrode L3 of the driving transistor T3.

[0144] In a direction perpendicular to the plane of the substrate, the second plate C12 of the first capacitor C1 is located on the side of the first plate C11 of the first capacitor C1 away from the substrate. The orthographic projection of the first plate C11 of the first capacitor C1 on the substrate and the orthographic projection of the second plate C12 of the first capacitor C1 on the substrate at least partially overlap, so that the second plate C12 of the first capacitor C1 can block at least a part of the structure of the first plate C11 of the first capacitor C1, thereby reducing the parasitic capacitance between the signal line on the side of the second plate C12 away from the substrate and the first plate C11 of the first capacitor C1. Since the first plate C11 of the first capacitor C1 is connected to the control electrode of the driving transistor T3, the parasitic capacitance of the control electrode of the driving transistor T3 can be reduced, and the display effect can be improved.

[0145] In an exemplary embodiment, as shown in Figures 5a to 6a, Figure 6a is a cross-sectional structural diagram along position M1-M1 in Figure 5a. The first electrode C11 of the first capacitor C1 may include a first main body C110. In the same sub-pixel Pxij, the orthographic projection of the first main body C110 on the substrate may be located within the range of the orthographic projection of the second electrode C12 of the first capacitor C1 on the substrate, so that the first main body C110 in the first electrode C11 can be completely covered by the second electrode C12 of the first capacitor C1. The second electrode C12 of the first capacitor C1 can better play a shielding role and can effectively reduce the parasitic capacitance of the first electrode C11 of the first capacitor C1.

[0146] In an exemplary embodiment, as shown in Figures 5a to 6a, the pixel driving circuit may further include at least one connecting electrode in the direction Z perpendicular to the plane of the substrate. In the same sub-pixel Pxij, the at least one connecting electrode may be located on the side of the second plate C12 of the first capacitor C1 away from the substrate 101. When the first main body C110 in the first plate C11 is covered by the second plate C2 of the first capacitor C1, even if the connecting electrode overlaps with the first main body C110 in the first plate C11 of the first capacitor C1, the signal in the connecting electrode will be shielded by the second plate C12 of the first capacitor C1, and the parasitic capacitance of the first plate C11 of the first capacitor C1 will not increase.

[0147] In an exemplary embodiment, as shown in Figures 5a to 6a, in the direction Z perpendicular to the plane where the substrate is located, the driving transistor T3 can be located on the side of the second plate C12 of the first capacitor C1 away from the substrate, and the orthogonal projection of the driving transistor T3 on the substrate is within the range of the orthogonal projection of the second plate C12 of the first capacitor C1 on the substrate.

[0148] At least one connection electrode may include at least a first connection electrode L1. In the same sub-pixel Pxij, the first plate C11 of the first capacitor C1 is electrically connected to the control electrode T3g of the driving transistor T3 through the first connection electrode L1.

[0149] In an exemplary embodiment, as shown in Figures 5a to 6a, the first electrode C11 of the first capacitor C1 may include a first main body C110 and a first connecting part CL1. The first main body C110 overlaps at least partially with the second electrode C12 of the first capacitor C1. The orthographic projection of at least a portion of the structure of the first connecting part CL1 on the substrate does not overlap with the orthographic projection of the second electrode C12 of the first capacitor C1 on the substrate.

[0150] In the same sub-pixel Pxij, one end of the first connecting part CL1 is connected to the first main body part C110, and the other end (the end that does not overlap with the second plate C12 of the first capacitor C1) is electrically connected to the control electrode T3g of the driving transistor T3 through the first connecting electrode L1. The first connecting part CL1 is located at the edge of the first main body part C110 and the closest position to the control electrode T3g of the driving transistor T3. This can minimize the line length HL1 of the first connecting electrode L1, that is, minimize the area of ​​the first node N1 (the connection node between the first plate C11 of the first capacitor C1 and the control electrode T3g of the driving transistor T3) that is not covered by the second plate C12 of the first capacitor C1 (i.e., reduce the exposed area of ​​the first node N1), thereby minimizing the parasitic capacitance of the first node N1 (i.e., the control electrode of the driving transistor T3).

[0151] In an exemplary embodiment, as shown in Figures 5a and 6a, at least one connection electrode may include the second electrode L3 of the driving transistor T3. The orthographic projection of the second electrode L3 of the driving transistor T3 onto the substrate is within the range of the orthographic projection of the second plate C12 of the first capacitor C1 onto the substrate. As can be seen in Figures 5a and 6a, although the second electrode L3 of the driving transistor T3 overlaps with the first plate C11 of the first capacitor C1, the first plate C11 of the first capacitor C1 is covered by the second plate C12 of the first capacitor C1, which can shield the signal of the second electrode L3 of the driving transistor T3. Therefore, the second electrode L3 of the driving transistor T3 will not cause an increase in the parasitic capacitance of the first node N1 (i.e., the control electrode of the driving transistor T3).

[0152] In an exemplary embodiment, the parasitic capacitance of the first node N1 is mostly generated by the film layer containing the connecting electrode (such as the third connecting electrode L3, which is usually located in the first source / drain metal layer) and the first node N1. After the main body of the first electrode C11 of the first capacitor C1 in the first node N1 (i.e., the first main body C110) is covered by the second electrode C12 of the first capacitor C1, it can effectively shield the signal of the first source / drain metal layer. Even if the connecting electrode in the first source / drain metal layer overlaps with the first main body C110 of the first capacitor C1, it can still be shielded by the second electrode C12 of the first capacitor C1, thereby reducing the parasitic capacitance between the first electrode C11 of the first capacitor C1 and the connecting electrode in the first source / drain metal layer.

[0153] In an exemplary embodiment, as shown in Figures 5a to 6a, the driving transistor T3 may further include a bottom gate T3gb. In the direction Z perpendicular to the plane where the substrate is located, the bottom gate T3gb of the driving transistor T3 may be located between the second plate C12 of the first capacitor C1 and the active layer AT3 of the driving transistor T3.

[0154] In the same sub-pixel Pxij, the bottom gate T3gb of the driving transistor T3 is electrically connected to the second plate C12 of the first capacitor C1. The bottom gate T3gb of the driving transistor T3 and the orthographic projection of the active layer AT3 of the driving transistor T3 on the substrate at least partially overlap. On the one hand, the bottom gate T3gb of the driving transistor T3 can shield the signal of the active layer AT3 of the driving transistor T3, avoid interference to the first node N1 and reduce the parasitic capacitance of the first node N1. On the other hand, the bottom gate T3gb of the driving transistor T3 can form part of the second substrate C12 of the first capacitor C1, which can increase the capacitance of the first capacitor C1 and help improve the stability of the first node N1.

[0155] In an exemplary embodiment, as shown in Figures 5a to 5d, the display substrate may further include a plurality of control lines. The control lines are electrically connected to the control electrode of at least one transistor. In a direction perpendicular to the plane of the substrate, the plurality of control lines may be located on the side of the second electrode C12 of the first capacitor C1 away from the substrate. The orthographic projection of the plurality of control lines on the substrate does not overlap with the orthographic projection of the first electrode C11 of the first capacitor C1 on the substrate. On the one hand, the absence of overlap between the orthographic projection of the plurality of control lines on the substrate and the orthographic projection of the first electrode C11 of the first capacitor C1 on the substrate can avoid the generation of parasitic capacitance between the first electrode C11 of the first capacitor C1 and the control lines. On the other hand, the fact that the plurality of control lines are located on the side of the second electrode C12 of the first capacitor C1 away from the substrate allows the first electrode C11 of the first capacitor C1 to be supported by the second electrode C12 of the first capacitor C1, thus avoiding the generation of parasitic capacitance between the first electrode C11 of the first capacitor C1 and the plurality of control lines.

[0156] In an exemplary embodiment, the plurality of transistors may include at least one first type transistor, and the at least one first type transistor includes at least a driving transistor T3. In a direction perpendicular to the plane of the substrate, the first type transistor may include: an active layer of the first type transistor located on the side of the second plate C12 of the first capacitor C1 away from the substrate, a control electrode of the first type transistor located on the side of the active layer of the first type transistor away from the substrate, and a first electrode and a second electrode located on the side of the control electrode of the first type transistor away from the substrate.

[0157] As shown in Figures 5a and 5b, at least one capacitor may further include a second capacitor C2, and the second plate C22 of the second capacitor C2 may be disposed in the same layer as the second plate C12 of the first capacitor C1; in the same sub-pixel Pxij, the second plate C22 of the second capacitor C2 is electrically connected to the second plate C12 of the first capacitor C1 and the second electrode L3 of the driving transistor T3, and the orthogonal projections of the first plate C21 and the second plate C22 of the second capacitor C2 on the substrate at least partially overlap.

[0158] In an exemplary embodiment, as shown in Figures 5a to 5d and Figures 6b to 6d, Figure 6b is a cross-sectional structural diagram of position M2-M2 in Figure 5b, Figure 6c is a cross-sectional structural diagram of position M3-M3 in Figure 5c, and Figure 6d is a cross-sectional structural diagram of position M4-M4 in Figure 5d. The first electrode C21 of the second capacitor C2 may include a second main body C210. ​​In the same sub-pixel Pxij, the orthographic projection of the second main body C210 on the substrate is located within the range of the orthographic projection of the second electrode C22 of the second capacitor C2 on the substrate. In an exemplary embodiment, in the structure of the second capacitor C2 shown in FIG5a, the orthographic projection of the second main body C210 on the substrate is located within the range of the orthographic projection of the second electrode C22 of the second capacitor C2 on the substrate. This allows the first electrode C21 of the second capacitor C2 to be shielded by the second electrode C22 of the second capacitor C2, thereby reducing the parasitic capacitance of the first electrode C21 of the second capacitor C2. The first electrode C21 of the second capacitor C2 can be connected to the second electrode of the fourth transistor T4 and the second electrode of the second transistor T2 (i.e., the fourth node N4 shown in FIG4). After the first electrode C21 of the second capacitor C2 is shielded by the second electrode C22 of the second capacitor C2, the parasitic capacitance of the fourth node N4 can be reduced.

[0159] In an exemplary embodiment, as shown in Figures 5a to 5d, the first plate C21 of the second capacitor C2 can be disposed on the same layer as the first plate C11 of the first capacitor C1, and the second plate C22 of the second capacitor C2 can be disposed on the same layer as the second plate C12 of the first capacitor C1; in the same sub-pixel Pxij, the second capacitor C2 and the first capacitor C1 can be arranged sequentially along the second direction Y.

[0160] In an exemplary embodiment, as shown in Figures 5b, 5c, 6b and 6c, the second capacitor C2 may further include a third plate C23. In the direction Z perpendicular to the plane of the substrate, the third plate C23 of the second capacitor C2 may be located on the side of the second plate C22 of the second capacitor C2 away from the substrate.

[0161] In the same sub-pixel Pxij: the orthographic projections of the third plate C23 of the second capacitor C2 and the second plate C22 of the second capacitor C2 on the substrate at least partially overlap, which can reduce the parasitic capacitance of the second plate C22 of the second capacitor C2. The third plate C23 of the second capacitor C2 can be electrically connected to the first plate C21 of the second capacitor C2. The third plate C23 and the first plate C21 of the second capacitor C2 are part of the second capacitor C2, and the second plate C22 of the second capacitor C2 is another part of the second capacitor C2, which can increase the capacitance of the second capacitor C2. This can improve the stability of the third node N3 and the fourth node N4 connected to the second capacitor C2, and improve the stability of the pixel driving circuit. In addition, the second plate C22 of the second capacitor C2 is sandwiched between the first plate C21 and the third plate C23, which can effectively reduce the parasitic capacitance of the second plate C22 (third node N3), thereby improving the stability of the pixel driving circuit.

[0162] In an exemplary embodiment, as shown in Figures 5b and 6b, in the direction Z perpendicular to the plane of the substrate, the third plate C23 of the second capacitor C2 can be located between the second plate C22 of the second capacitor C2 and the active layer of the first type of transistor, or, as shown in Figures 5c and 6c, the third plate C23 of the second capacitor C2 is disposed on the same layer as the control electrode of the first type of transistor.

[0163] In the structures shown in Figures 5b, 5c, 6b, and 6c, the first plate C21 of the second capacitor C2 is connected to the third plate C23 of the second capacitor C2 (corresponding to the fourth node N4). While increasing the capacitance of the second capacitor C2, the second plate C22 of the second capacitor C2 (corresponding to the third node N3) can also be shielded, which can reduce the parasitic capacitance of the third node N3 (i.e., the control electrode of the driving transistor T3).

[0164] In an exemplary embodiment, as shown in Figures 5d and 6d, the second capacitor C2 may further include a fourth electrode plate C24. In the direction Z perpendicular to the plane of the substrate, the third electrode plate C23 of the second capacitor C2 may be located between the second electrode plate C22 of the second capacitor C2 and the active layer of the first type of transistor. The fourth electrode plate C24 of the second capacitor C2 is disposed on the same layer as the control electrode of the first type of transistor.

[0165] In the same sub-pixel Pxij, the fourth plate C24 of the second capacitor C2 is electrically connected to the second plate C22 of the second capacitor C2 (corresponding to the third node N3). The orthographic projections of the fourth plate C24 and the third plate C23 of the second capacitor C2 on the substrate at least partially overlap. The fourth plate C24 and the second plate C22 of the second capacitor C2 can be part of the second capacitor C2 (connected to the third node N3). The first plate C21 and the third plate C23 of the second capacitor C2 can be another part of the second capacitor C2 (corresponding to the fourth node N4). The second capacitor C2 is formed by stacking multiple plates. On the one hand, this can increase the capacitance of the second capacitor C2 and improve the stability of the third node N3 and the fourth node N3 connected to the second capacitor C2, thereby providing stability for the pixel driving circuit. On the other hand, it can shield at least part of the structure of the second plate C22, reducing the parasitic capacitance of the second plate C22.

[0166] In an exemplary embodiment, among the multiple plates of the second capacitor C2, the first plate C21 and the third plate C23 can be connected to the third node N3, and the second plate C22 and the fourth plate C24 can be connected to the fourth node N4. In this way, the fourth node N4 can be used to shield the third node N3, thereby preventing the third node N3 from generating parasitic capacitance with the signal line located on the side of the second capacitor C2 away from the substrate, and improving the stability of the third node N3.

[0167] In an exemplary embodiment, the first type of transistor can be an N-type transistor, and the second type of transistor can be a P-type transistor. For example, in Figures 5a to 5d, the fifth transistor T5 can be a second type of transistor, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the sixth transistor T6, and the seventh transistor T7 can be first type of transistors.

[0168] In an exemplary embodiment, as shown in Figures 7a to 7h, Figure 7a is a plan view of a capacitor structure, Figure 7b is a cross-sectional view of Figure 7a along the M5-M5 position, Figure 7c is a plan view of a capacitor structure, Figure 7d is a cross-sectional view of Figure 7c along the M6-M6 position, Figure 7e is a plan view of a capacitor structure, Figure 7f is a cross-sectional view of Figure 7d along the M7-M7 position, Figure 7g is a plan view of a capacitor structure, and Figure 7h is a cross-sectional view of Figure 7g along the M8-M8 position. The structure is perpendicular to the plane where the substrate is located. In the Z direction of the surface, the second plate C22 of the second capacitor C2 is located on the side of the first plate C21 of the second capacitor C2 away from the substrate. In the same sub-pixel: the orthogonal projections of the first capacitor C1 and the second capacitor C2 on the substrate at least partially overlap. The second plate of the first capacitor C1 can serve as the first plate C21 of the second capacitor C2. That is, the first capacitor C1 and the second capacitor C2 are stacked. Furthermore, the second plate C12 of the first capacitor C1 and the first plate C21 of the second capacitor C2 share a single plate, which can reduce the space occupied by the capacitor and thereby increase the pixel density (PPI) of the display substrate.

[0169] In an exemplary embodiment, as shown in Figures 7a to 7h, in the same sub-pixel Pxij, the main body C110 (i.e., the first main body C110) of the first plate C11 of the first capacitor C1 can be located within the range of the orthogonal projection of the first plate C21 (which is also the second plate C12 of the first capacitor C1) on the substrate, which can reduce the parasitic capacitance of the second plate C11 (i.e., the first node N1) of the first capacitor C1.

[0170] In an exemplary embodiment, as shown in Figures 7a and 7b, in the direction Z perpendicular to the plane of the substrate, the second plate C22 of the second capacitor C2 can be located between the first plate C21 of the second capacitor C2 and the active layer of the first type of transistor, or, as shown in Figures 7c and 7d, the second plate C22 of the second capacitor C2 can be disposed on the same layer as the control electrode of the first type of transistor.

[0171] In the structures shown in Figures 7a to 7h, the first plate C11 of the first capacitor C1 is connected to the first node N1, the first plate C21 of the second capacitor C2 (which is also the second plate C12 of the first capacitor C1) is connected to the third node N3, and the second plate C22 of the second capacitor C2 is connected to the fourth node N4.

[0172] In an exemplary embodiment, as shown in Figures 7e and 7f, the second capacitor C2 may further include a third electrode plate C23. In the direction Z perpendicular to the plane of the substrate, the second electrode plate C22 of the second capacitor C2 is located between the first electrode plate C21 of the second capacitor C2 and the active layer of the first type of transistor. The third electrode plate C23 of the second capacitor C2 is disposed on the same layer as the control electrode of the first type of transistor. In the same sub-pixel, the third electrode plate C23 of the second capacitor C2 is electrically connected to the first electrode plate C21 of the second capacitor C2. Among the multiple electrodes of the second capacitor C2: the first electrode plate C21 and the third electrode plate C23 are connected to the third node N3, and the second electrode plate C22 is connected to the fourth node N4. The first electrode plate C21 and the third electrode plate C23 constitute one part of the second capacitor C2, and the second electrode plate C22 constitutes another part of the second capacitor C2. The stacking position relationship (connection relationship) of these two parts can be interchanged. For example, the second substrate C22 and the first electrode plate C21 can be connected to the third node N3, and the third electrode plate C23 can be connected to the fourth node N4.

[0173] In an exemplary embodiment, as shown in Figures 7g and 7h, the second capacitor C2 may further include a fourth electrode plate C24, which may be disposed on the same layer as the first and second electrodes of the transistor.

[0174] In the same sub-pixel, the fourth plate C24 of the second capacitor C2 is electrically connected to the second plate C22 of the second capacitor C2. The fourth plate C24 and the second plate C22 of the second capacitor C2 can be connected to the fourth node N4. The first plate C21 and the third plate C23 of the second capacitor can be connected to the third node N3. The first plate C21 and the third plate C23 constitute a part of the second capacitor C2, and the second plate C22 and the fourth plate C24 constitute another part of the second capacitor C2. The stacking position relationship (connection relationship) of these two parts can be interchanged. For example, the fourth plate C24 and the second plate C22 of the second capacitor C2 can be connected to the third node N3, and the first plate C21 and the third plate C23 of the second capacitor can be connected to the fourth node N4. Alternatively, the fourth plate C24 and the third plate C23 can be connected to the fourth node N4, and the first plate C22 and the first plate C21 can be connected to the third node N3.

[0175] In an exemplary embodiment, as shown in Figures 7e to 7h, the orthogonal projection of the second plate C22 of the second capacitor C2 onto the substrate is within the range of the orthogonal projection of the third plate C23 of the second capacitor C2 onto the substrate, which can shield the third plate C23 and reduce the parasitic capacitance of the third plate C23.

[0176] In an exemplary embodiment, as shown in Figures 7a to 7h, the orthographic projections of multiple plates in the same second capacitor C2 onto the substrate at least partially overlap, and the orthographic projections of the first capacitor C1 and the second capacitor C2 onto the substrate at least partially overlap. This can increase the capacitance on the one hand, and reduce the space occupied by the capacitor on the other hand, thereby improving the PPI.

[0177] In an exemplary embodiment, the first and second electrodes of the transistor can be located in the first source-drain metal layer SD1, and the first source-drain metal layer SD1 can be provided with multiple electrodes LSD1. The plates in the second capacitor C2 can be electrically connected to the corresponding electrodes LSD1 through corresponding vias. In the structures shown in Figures 7a and 7b: the first plate C21 of the second capacitor C2 can be connected to the corresponding electrode LSD1 through via K2SD1, connecting the first plate C21 to the third node N3; the second plate C22 of the second capacitor can be connected to the corresponding electrode LSD1 through via K3SD1, connecting the second plate C22 to the fourth node N4. In the structures shown in Figures 7c and 7d: the first plate C21 can be connected to the corresponding electrode LSD1 through via K2SD1, connecting the first plate C21 to the third node N3; the second plate C22 of the second capacitor can be connected to the corresponding electrode LSD1 through via K4SD1, connecting the second plate C22 to the fourth node N4. In the structures shown in Figures 7e and 7f: the first plate C21 can be connected to the corresponding electrode LSD1 through via K2SD1, connecting the first plate C21 to the third node N3; the second plate C22 of the second capacitor can be connected to the third node N3 through via K3SD1. The first electrode C21 and the third electrode C23 are connected to the corresponding electrode LSD1 and the third electrode C23 are connected to the third node N3 via the via K4SD1. The first electrode C21 and the third electrode C23 are connected to the third node N3 via the same electrode LSD1. In the structures shown in Figures 7g and 7h: the first electrode C21 is connected to the corresponding electrode LSD1 via the via K2SD1 and is connected to the third node N3. The second electrode C22 of the second capacitor is connected to the fourth electrode C24 via the via K3SD1 and the second electrode C22 and the fourth electrode C24 are connected to the fourth node N4. The third electrode C23 is connected to the corresponding electrode LSD1 via the via K4SD1 and is connected to the third node N3. The first electrode C21 and the third electrode C23 are connected to the third node N3 via the same electrode LSD1.

[0178] In an exemplary embodiment, in Figures 6a to 6d and Figures 7a to 7f, F1 is the first insulating layer, F2 is the second insulating layer, F3 is the third insulating layer, F4 is the fourth insulating layer, F5 is the fifth insulating layer, and F6 is the sixth insulating layer.

[0179] In an exemplary embodiment, as shown in Figures 5a to 5d, the plurality of transistors may further include at least one second type of transistor. The second type of transistor includes: an active layer of the second type of transistor, a control electrode of the second type of transistor, a first electrode and a second electrode of the second type of transistor. In a direction perpendicular to the plane of the substrate, the active layer of the second type of transistor may be located on the side of the first electrode plate C11 of the first capacitor C1 close to the substrate. The control electrode of the second type of transistor may be disposed in the same layer as the first electrode plate C11 of the first capacitor C1. The first electrode and the second electrode of the second type of transistor may be disposed in the same layer as the first electrode and the second electrode of the first type of transistor.

[0180] The second type of transistor may include a fifth transistor T5 as a light-emitting control transistor, and the first type of transistor may include a driving transistor T3 and a first transistor T1 as a reset transistor. In the same sub-pixel Pxij, the orthogonal projections of the driving transistor T3 and the first capacitor C1 on the substrate at least partially overlap. In the second direction Y, the first transistor T1 and the fifth transistor T5 may be located on opposite sides of the driving transistor T3. In the first direction X, the first transistor T1 and the fifth transistor T5 may be located on the same side of the driving transistor T3, the first capacitor C1, and the second capacitor C2. The first direction X intersects the second direction Y.

[0181] In an exemplary embodiment, as shown in Figures 5a to 5d, the display substrate may further include a plurality of control lines extending along a first direction. The plurality of control lines may include a first reset control line Reset1 and a first light emission control line EM1. The first light emission control line EM1 and the first reset control line Reset1 may be disposed on the same layer as the first electrode and the second electrode.

[0182] Multiple sub-pixels Pxij form multiple rows of sub-pixels Pxij. The first reset control line Reset1 is electrically connected to the control electrode of at least one first transistor T1 in at least one row of sub-pixels Pxij. The first light emission control line EM1 is electrically connected to the control electrode of at least one fifth transistor T5 in at least one row of sub-pixels Pxij. In the same sub-pixel Pxij, the first light emission control line EM1 and the first reset control line Reset1 can be located on opposite sides of the first capacitor C1. The second capacitor C2 is located on the side where the first reset control line Reset1 is away from the first capacitor C1. The first light emission control line EM1 and the first reset control line Reset1 do not overlap with the first capacitor C1, which can reduce the parasitic capacitance between the first capacitor C1 and the first light emission control line EM1 and the first reset control line Reset1.

[0183] In an exemplary embodiment, as shown in Figures 5a to 5d, the first type of transistor may further include a second transistor T2 as a reset transistor and a fourth transistor T4 as a data writing transistor. The multiple control lines may further include a third reset control line Reset3 and a scan control line Gate. The third reset control line Reset3 may be disposed on the same layer as the control electrode of the first type of transistor, and the scan control line Gate may be disposed on the same layer as the first electrode and the second electrode.

[0184] The third reset control line Reset3 can be electrically connected to the control electrode of at least one second transistor T2 in at least one row of sub-pixels Pxij, and the scan control line Gate can be electrically connected to at least one fourth transistor T4 in at least one row of sub-pixels Pxij. In the same sub-pixel Pxij, in the first direction X, the second transistor T2 and the fourth transistor T4 can be located on the same side of the second capacitor C2, and in the second direction Y, the second transistor T2 and the third reset control line Reset3 can be located between the first transistor T1 and the fourth transistor T4. The scan control line Gate can be located on the side of the third reset control line Reset3 away from the first transistor T1. The third reset control line Reset3 and the scan control line Gate can at least partially overlap with the second capacitor C2. The third reset control line Reset3 and the scan control line Gate do not overlap with the first capacitor C1, which can reduce the parasitic capacitance between the first capacitor C1 and the third reset control line Reset3 and the scan control line Gate.

[0185] In an exemplary embodiment, as shown in Figures 5a to 5d, the first type of transistor further includes a sixth transistor T6 as a light-emitting transistor and a seventh transistor T7 as a reset transistor. The multiple control lines may also include a second reset control line Reset2 and a second light-emitting control line EM2. The second reset control line Reset2 and the second light-emitting control line EM2 may be disposed on the same layer as the control electrode of the first type of transistor.

[0186] The second light-emitting control line EM2 can be electrically connected to the control electrode of at least one sixth transistor T6 in at least one row of sub-pixels Pxij, and the second reset control line Reset2 can be electrically connected to the control electrode of at least one seventh transistor T7 in at least one row of sub-pixels Pxij. In the same sub-pixel Pxij, in the second direction Y, the sixth transistor T6 and the second light-emitting control line EM2 can be located on the side of the fourth transistor T4 away from the second transistor T2, the seventh transistor T7 and the second reset control line Reset2 can be located on the side of the sixth transistor T6 away from the fourth transistor T4, and the sixth transistor T6 and the seventh transistor T7 can be located on the side of the second capacitor C2 away from the first capacitor C1. The second reset control line Reset2, the second light-emitting control line EM2 and the first capacitor C1 and the second capacitor C2 do not overlap, which can reduce the interference of the signals of the second reset control line Reset2 and the second light-emitting control line EM2 on the first capacitor C1 and the second capacitor C2, thereby reducing the parasitic capacitance between the first capacitor C1 and the second capacitor C2 and the second reset control line Reset2 and the second light-emitting control line EM2.

[0187] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film of a certain material fabricated on a substrate (or substrate plate) using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0188] In an exemplary embodiment, taking six sub-pixels (one sub-pixel row, six sub-pixel columns, and the pixel driving circuit adopts the 7T2C structure shown in Figure 4) in the display area (AA) as an example, the fabrication process of one display substrate may include the following operations:

[0189] (101) A substrate is prepared on a glass substrate. In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may include, but is not limited to, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, an adhesive layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer soft films, etc. The materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also called barrier layers, and the material of the adhesive layer may be amorphous silicon (a-Si). In an exemplary embodiment, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, its preparation process may include: firstly, coating a layer of polyimide on a glass substrate, curing it into a film to form a first flexible material (PI1) layer; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible material layer; then depositing an amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating another layer of polyimide on the amorphous silicon layer, curing it into a film to form a second flexible material (PI2) layer; then depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thus completing the substrate preparation.

[0190] (102) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming a first semiconductor layer pattern may include: depositing a first semiconductor thin film on a substrate, and patterning the semiconductor thin film by a patterning process to form a first semiconductor layer pattern, as shown in FIG8, FIG8 is a planar schematic diagram of the six sub-pixels after forming the first semiconductor layer.

[0191] In an exemplary embodiment, the first semiconductor layer pattern in at least a portion of the sub-pixels includes at least: the active layer AT5 of the fifth transistor T5.

[0192] In an exemplary embodiment, the shape of the active layer AT5 of the fifth transistor T5 can be in an "L" shape.

[0193] In an exemplary embodiment, the active layer of at least some of the transistors may include a first region, a second region, and a channel region located between the first region and the second region, and the first region AT51 and the second region AT52 of the active layer AT5 of the fifth transistor T5 can be separately provided.

[0194] In an exemplary embodiment, the pixel driving circuits of multiple sub-pixels form multiple rows and multiple columns, and the multiple pixel driving circuits form multiple circuit units. Among the pixel driving circuits in the same row, three adjacent pixel driving circuits can constitute a circuit unit, and the multiple circuit units can form multiple rows and multiple columns.

[0195] In an exemplary embodiment, in the same row of circuit units, the first semiconductor layers in the two nearest pixel driving circuits of two adjacent circuit units are mirror-symmetrical with respect to the first center line, and the first center line can be a straight line along the second direction Y extending between two adjacent circuit units. Taking the M-row pixel driving circuits as an example: The three pixel driving circuits of the Nth column pixel driving circuit, the (N + 1)th column pixel driving circuit, and the (N + 2)th column pixel driving circuit constitute a circuit unit, and the three pixel driving circuits of the (N + 3)th column pixel driving circuit, the (N + 4)th column pixel driving circuit, and the (N + 5)th column pixel driving circuit constitute another circuit unit. The two nearest pixel driving circuits of two adjacent circuit units are the (N + 2)th column pixel driving circuit and the (N + 3)th column pixel driving circuit, and the first semiconductor layer in the (N + 2)th column pixel driving circuit and the first semiconductor layer in the (N + 3)th column pixel driving circuit can be symmetrical with respect to the first center line between the (N + 2)th column pixel driving circuit and the (N + 3)th column pixel driving circuit.

[0196] In an exemplary embodiment, the active layers AT5 of the two nearest fifth transistors T5 in two adjacent circuit units are connected to each other to form a "ji" (Chinese character) shape structure. For example, in the Mth row pixel driving circuit, the active layer AT5 of the fifth transistor T5 in the (N + 2)th column pixel driving circuit and the active layer AT5 of the fifth transistor T5 in the (N + 2)th column pixel driving circuit are connected to each other to form a "ji" shape structure.

[0197] In an exemplary embodiment, a pixel driving circuit of a first sub-pixel, a pixel driving circuit of a second sub-pixel, and a pixel driving circuit of a third sub-pixel can be included in the same circuit unit.

[0198] In an exemplary embodiment, the first semiconductor layer may be polycrystalline silicon (p-Si), meaning the fifth transistor T5 may be an LTPS thin-film transistor. In another exemplary embodiment, patterning the first semiconductor thin film using a patterning process may include: first forming an amorphous silicon (a-Si) thin film on a first insulating film; then performing a hydrogen removal treatment on the amorphous silicon thin film; and finally performing a crystallization treatment on the dehydrogenated amorphous silicon thin film to form a polycrystalline silicon thin film. Subsequently, the polycrystalline silicon thin film is patterned to form the pattern of the first semiconductor layer.

[0199] (103) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: sequentially depositing a first insulating film and a first conductive film on a substrate on which the aforementioned pattern is formed, and patterning the first conductive film using a patterning process to form a first conductive layer pattern covering the first semiconductor layer pattern, as shown in Figures 9a and 9b. Figure 9a is a planar structural schematic diagram of six sub-pixels after the formation of the first conductive layer, and Figure 9b is a planar schematic diagram of the first conductive layer in Figure 9a. The first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0200] In an exemplary embodiment, the first conductive layer pattern may include at least: the first electrode C11 of the first capacitor C1, the first electrode C21 of the second capacitor C2, the first second initial signal line Vinit2-B, and the control electrode T5g of the fifth transistor T5.

[0201] In an exemplary embodiment, the first type of second initial signal line Vinit2-B can be a broken line structure or a strip structure extending along the first direction X; in the same sub-pixel, in the second direction Y, the first type of second initial signal line Vinit2-B can be located on the side of the first plate C21 of the second capacitor C2 away from the first plate C11 of the first capacitor C1.

[0202] In an exemplary embodiment, the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2 can be block structures, and the shape of the block structure can be polygonal, for example, it can be approximately rectangular. In an exemplary embodiment, in the same sub-pixel, in the second direction Y, the first plate C21 of the second capacitor C2 and the first plate C11 of the first capacitor C1 can be arranged sequentially.

[0203] In an exemplary embodiment, the first electrode C11 of the first capacitor C1 may include a first main body C110 (i.e., the main body of the first electrode C11) and a first connecting portion CL1. In the first direction X, the first connecting portion CL1 is located on one side of the first main body C110. The first connecting portion CL1 is configured to accommodate a subsequently formed twelfth via. The orthographic projection of the twelfth via on the substrate is within the range of the orthographic projection of the first connecting portion CL1 on the substrate, and exposes the surface of the first connecting portion CL1, so that the second electrode of the subsequently formed first transistor T1 is connected to the first electrode C11 of the first capacitor C1 through the twelfth via and the first connecting portion CL1.

[0204] In an exemplary embodiment, the first electrode plate C21 of the second capacitor C2 may include a second connecting portion CL2 and a second main body portion C210 (i.e., the main body portion of the first electrode plate C21). In the first direction X, the second connecting portion CL2 is located on one side of the second main body portion C210. ​​The second connecting portion CL2 is configured to accommodate a subsequently formed thirteenth via. The orthographic projection of the thirteenth via on the substrate is within the range of the orthographic projection of the second connecting portion CL2 on the substrate, and exposes the surface of the second connecting portion CL2, so that the second electrode of the subsequently formed second transistor T2 and the second electrode of the fourth transistor T4 are connected to the first electrode plate C21 of the second capacitor C2 through the thirteenth via and the second connecting portion CL2.

[0205] Taking the Mth row and Nth column sub-pixel as an example: In the second direction Y, the first plate C11 of the first capacitor C1 in the Mth row can be located on the side of the first plate C21 of the second capacitor C2 of the same sub-pixel near the (M-1)th row sub-pixel, and the control electrode T5g of the fifth transistor T5 can be located on the side of the main body of the first plate C11 of the first capacitor C1 of the same sub-pixel near the (M-1)th row sub-pixel; In the first direction X, the control electrode T5g of the fifth transistor T5 is located on at least part of the structure of the first plate C11 of the first capacitor C1 and the side of the first plate C21 of the second capacitor C2 near the (N-1)th column sub-pixel.

[0206] In an exemplary embodiment, the control electrode T5g of the fifth transistor T5 at least partially overlaps with the active layer AT5 of the fifth transistor T5. For example, the control electrode T5g of the fifth transistor T5 overlaps with the channel region of the active layer AT5 of the fifth transistor T5. Within the same sub-pixel, in the first direction X, the control electrode T5g of the fifth transistor T5 may be located on one side of the first plate C11 of the first capacitor C1 and the first plate C21 of the second capacitor C2. In the second direction Y, the control electrode T5g of the fifth transistor T5 may be located on the side of the first connection portion CL1 away from the first plate C21 of the second capacitor C2.

[0207] In an exemplary embodiment, in the same row of circuit units, the first conductive layer in the two nearest pixel driving circuits of two adjacent circuit units can be mirror-symmetrical with respect to the first center line. For example, the first conductive layer in the N+2th column pixel driving circuit and the first conductive layer in the N+3th column pixel driving circuit can be symmetrical with respect to the first center line between the N+2th column pixel driving circuit and the N+3th column pixel driving circuit.

[0208] In an exemplary embodiment, after the first conductive layer pattern is formed, the first conductive layer can be used as a shield to conduct the first semiconductor layer. The first semiconductor layer in the area shielded by the first conductive layer forms the channel region of the fifth transistor T5, and the first semiconductor layer in the area not shielded by the first conductive layer is conducted. That is, the first region and the second region of the active layer AT5 of the fifth transistor T5 are both conducted.

[0209] (104) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a second insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second conductive film using a patterning process to form a second insulating layer covering the first conductive layer; and a second conductive layer pattern disposed on the second insulating layer, as shown in Figures 10a and 10b. Figure 10a is a planar structural diagram of six sub-pixels after the formation of the second conductive layer, and Figure 10b is a planar schematic diagram of the second conductive layer in Figure 10a. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0210] In an exemplary embodiment, the second conductive layer pattern may include at least: the second electrode C12 of the first capacitor C1, the second electrode C22 of the second capacitor C2, and the third connecting portion CL3.

[0211] In an exemplary embodiment, the outline of the second plate C12 of the first capacitor C1 can be consistent with the outline of the first plate C11 of the first capacitor C1, and the outline of the second plate C22 of the second capacitor C2 can be consistent with the outline of the first plate C21 of the second capacitor C2. For example, the outlines of the second plates C12 of the first capacitor C1 and C22 of the second capacitor C2 can be polygons (e.g., rectangles). In an exemplary embodiment, the orthographic projection of the second plate C12 of the first capacitor C1 on the substrate overlaps with the orthographic projection of the first plate C11 of the first capacitor C1 on the substrate, and the orthographic projection of the second plate C22 of the second capacitor C2 on the substrate overlaps with the orthographic projection of the first plate C21 of the second capacitor C2 on the substrate. For example, the orthographic projection of the second plate C12 of the first capacitor C1 on the substrate can cover the orthographic projection of the first main body C110 of the first plate C11 of the first capacitor C1 on the substrate, and the orthographic projection of the second plate C22 of the second capacitor C2 on the substrate can cover the orthographic projection of the second main body C210 of the first plate C21 of the second capacitor C2 on the substrate. In an exemplary embodiment, the first plate C11 and the second plate C12 of the first capacitor C1 constitute the first capacitor C1, and the first plate C21 and the second plate C22 of the second capacitor C2 constitute the second capacitor C2.

[0212] In an exemplary embodiment, the second plate C22 of the second capacitor C2 is provided with a first opening K1. The orthographic projection of the first opening K1 on the substrate at least partially overlaps with the second connection portion CL2. The first opening K1 is configured to accommodate a subsequently formed thirteenth via. The orthographic projection of the thirteenth via on the substrate is within the range of the orthographic projection of the first opening K1 on the substrate, and exposes the surface of the second connection portion CL2, so that the second electrode of the subsequently formed second transistor T2 and the second electrode of the fourth transistor T4 are connected to the first plate C21 of the second capacitor C2 through the thirteenth via and the second connection portion CL2.

[0213] In an exemplary embodiment, in the same sub-pixel, in the second direction Y, the second plate C22 of the second capacitor C2 and the second plate C12 of the first capacitor C1 can be arranged sequentially. The second plate C22 of the second capacitor C2 can be connected to the second plate C12 of the first capacitor C1 through the third connecting part CL3. In an exemplary embodiment, the second plate C22 of the second capacitor C2, the third connecting part CL3, and the second plate C12 of the first capacitor C1 can be integrally formed.

[0214] In an exemplary embodiment, the first plate C11 of the first capacitor C1 can block the channel of the third body tube T3, thereby ensuring the electrical performance of the oxide third body tube T3.

[0215] In an exemplary embodiment, in the same row of circuit units, the second conductive layer in the two nearest pixel driving circuits of two adjacent circuit units can be mirror-symmetrical with respect to the first center line. For example, the second conductive layer in the N+2 column pixel driving circuit and the second conductive layer in the N+3 column pixel driving circuit can be symmetrical with respect to the first center line between the N+2 column pixel driving circuit and the N+3 column pixel driving circuit.

[0216] (105) Forming a third conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a third insulating film and a third conductive film on a substrate on which the aforementioned pattern is formed; patterning the second conductive film using a patterning process to form a third insulating layer covering the second conductive layer; and a third conductive layer pattern disposed on the third insulating layer, as shown in Figures 11a and 11b. Figure 11a is a planar structural diagram of six sub-pixels after the formation of the third conductive layer, and Figure 11b is a planar schematic diagram of the third conductive layer in Figure 11a. In an exemplary embodiment, the third conductive layer may be referred to as a third gate metal (GATE3) layer.

[0217] In an exemplary embodiment, the second conductive layer pattern may include at least the bottom gate T3gb of the third transistor T3.

[0218] In an exemplary embodiment, the orthographic projection of the bottom gate T3gb of the third transistor T3 onto the substrate at least partially overlaps with the orthographic projection of the second plate C12 of the first capacitor C1 onto the substrate. For example, the orthographic projection of the main portion of the bottom gate T3gb of the third transistor T3 onto the substrate may be located within the range of the orthographic projection of the second plate C12 of the first capacitor C1 onto the substrate.

[0219] (106) Forming a second semiconductor layer pattern. In an exemplary embodiment, forming a second semiconductor layer pattern may include: depositing a fourth insulating film and a second semiconductor film sequentially on a substrate on which the aforementioned pattern is formed, patterning the semiconductor film using a patterning process to form a fourth insulating layer covering the substrate, and a second semiconductor layer pattern disposed on the fourth insulating layer, as shown in Figures 12a and 12b. Figure 12a is a planar structural diagram of six sub-pixels after the formation of the second semiconductor layer, and Figure 12b is a planar schematic diagram of the semiconductor layer in Figure 12a.

[0220] In an exemplary embodiment, the second semiconductor layer pattern in at least some of the sub-pixels includes at least: the active layer AT1 of the first transistor T1, the active layer AT2 of the second transistor T2, the active layer AT3 of the third transistor T3, the active layer AT4 of the fourth transistor T4, the active layer AT6 of the sixth transistor T6, and the active layer AT7 of the seventh transistor T7.

[0221] In an exemplary embodiment, within the same sub-pixel, the active layer AT1 of the first transistor T1, the active layer AT2 of the second transistor T2, and the active layer AT4 of the fourth transistor T4 can be interconnected. For example, the active layer AT1 of the first transistor T1, the active layer AT2 of the second transistor T2, and the active layer AT4 of the fourth transistor T4 can be an interconnected integral structure.

[0222] In an exemplary embodiment, within the same sub-pixel, in the first direction X, the active layer AT1 of the first transistor T1, the active layer AT2 of the second transistor T2, the active layer AT4 of the fourth transistor T4, and the active layer AT5 of the fifth transistor T5 can be located on the same side of the active layer AT3 of the third transistor T3; in the second direction Y, the active layers AT1 of the first transistor T1, AT2 of the second transistor T2, AT4 of the fourth transistor T4, AT5 of the fifth transistor T5, and AT3 of the third transistor T3 can be located away from the active layer AT6 of the sixth transistor T6. On one side of the active layer AT7 of transistor T7, the active layers AT1 of the first transistor T1, AT2 of the second transistor T2, AT4 of the fourth transistor T4, and AT6 of the sixth transistor T6 can be located between the active layers AT5 of the fifth transistor T5 and the active layer AT7 of the seventh transistor T7. The active layer AT2 of the second transistor T2 can be located between the active layers AT1 of the first transistor T1 and AT4 of the fourth transistor T4. The active layer AT3 of the third transistor T3 can be located on the side of the active layer AT1 of the first transistor T1 away from the active layer AT2 of the second transistor T2.

[0223] In an exemplary embodiment, taking the sub-pixel at the M-th row and the N-th column as an example: in the first direction X, the active layers of the first transistor T1, the second transistor T2, the fourth transistor T4, and the fifth transistor T5 can be located on the side of the active layer of the third transistor T3 away from the sub-pixel in the (N + 1)-th column; in the second direction Y, the active layers of the first transistor T1, the second transistor T2, the fourth transistor T4, the fifth transistor T5, and the active layer of the third transistor T3 can be located on the side of the active layer of the sixth transistor T6 close to the sub-pixel in the (M - 1)-th row, the active layer of the first transistor T1 can be on the side of the active layer of the second transistor T2 away from the sub-pixel in the (M + 1)-th row, the active layer of the fourth transistor T4 can be on the side of the active layer of the second transistor T2 close to the sub-pixel in the (M + 1)-th row, the active layers of the fifth transistor T5 and the third transistor T3 can be located on the side of the active layer of the sixth transistor T6 away from the sub-pixel in the (M + 1)-th row, and the active layer of the seventh transistor T7 can be located on the side of the active layer of the sixth transistor T6 close to the sub-pixel in the (M + 1)-th row.

[0224] In an exemplary embodiment, the shapes of the active layers of the first transistor T1, the second transistor T2, the fourth transistor T4, and the sixth transistor T6 can be in an "I" shape or a strip shape, and the active layer of the third transistor T3 is in a "zhong" shape, or a strip shape or a broken line shape extending along the second direction Y.

[0225] In an exemplary embodiment, the active layers of at least some of the transistors can include a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, the first region AT11 of the active layer of the first transistor T1 can serve as the first region AT21 of the active layer of the second transistor T2, the second region AT22 of the active layer of the second transistor T2 can serve as the second region AT42 of the active layer of the fourth transistor T4, the second region AT62 of the active layer of the sixth transistor T6 can serve as the second region AT72 of the active layer of the seventh transistor T7, and the second region AT12 of the active layer of the first transistor T1, the first region AT31 and the second region AT32 of the active layer of the third transistor T3, the first region AT41 of the active layer of the fourth transistor T4, the first region AT61 of the active layer of the sixth transistor T6, and the first region AT71 of the active layer of the seventh transistor T7 can be set separately.

[0226] In an exemplary embodiment, the second semiconductor layer may be an oxide, i.e., the first transistor T1 to the fourth transistor T4, and the sixth transistor T6 to the seventh transistor T7 are oxide thin-film transistors. In an exemplary embodiment, the oxide may be any one or more of the following: indium gallium zinc oxide (InGaZnO), indium gallium zinc nitride (InGaZnON), zinc oxide (ZnO), zinc oxynitride (ZnON), zinc tin oxide (ZnSnO), cadmium tin oxide (CdSnO), gallium tin oxide (GaSnO), titanium tin oxide (TiSnO), copper aluminum oxide (CuAlO), strontium copper oxide (SrCuO), lanthanum copper sulfide oxide (LaCuOS), gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium gallium aluminum nitride (InGaAlN). In some possible implementations, the semiconductor thin film may be indium gallium zinc oxide (IGZO), which has a higher electron mobility than amorphous silicon.

[0227] (107) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: sequentially depositing a fifth insulating film and a fourth conductive film on a substrate on which the aforementioned pattern is formed; patterning the fourth conductive film using a patterning process to form a fifth insulating layer covering the second semiconductor layer; and a fourth conductive layer pattern disposed on the fifth insulating layer, as shown in Figures 13a and 13b. Figure 13a is a planar structural diagram of six sub-pixels after the formation of the fourth conductive layer, and Figure 13b is a planar schematic diagram of the fourth conductive layer in Figure 13a. In an exemplary embodiment, the fourth conductive layer may be referred to as the fourth gate metal (GATE4) layer.

[0228] In an exemplary embodiment, the fourth conductive layer pattern includes at least: a second reset control line Reset2, a second light emission control line EM2, a third reset control line Reset3, a control electrode T1g of the first transistor T1, a control electrode T3g of the third transistor T3, and a control electrode T4g of the fourth transistor T4.

[0229] In an exemplary embodiment, the second light-emitting control line EM2 can be a zigzag or strip shape extending along the first direction X of the main body. In the same sub-pixel row, in the second direction Y, the second reset control line Reset2 and the third reset control line Reset3 can be located on opposite sides of the second light-emitting control line EM2. The control electrode T3g of the third transistor T3 can be located on the side of the control electrode T1g of the first transistor T1 away from the third reset control line Reset3. The control electrode T4g of the fourth transistor T4 can be located between the second reset control line Reset2 and the third reset control line Reset3. In the first direction X, the control electrode T4g of the fourth transistor T4 and the control electrode T1g of the first transistor T1 can be located on the same side of the control electrode T3g of the third transistor T3. Taking the Mth row and Nth column sub-pixel as an example: in the second direction Y... In the first direction X, the control electrode T1g of the first transistor T1 can be located on the side of the third reset control line Reset3 away from the (M+1)th row sub-pixel, the control electrode T3g of the third transistor T3 can be located on the side of the first transistor T1's control electrode T1g away from the (M+1)th row sub-pixel, the control electrode T4g of the fourth transistor T4 can be located on the side of the third reset control line Reset3 close to the (M+1)th row sub-pixel, the second light emission control line EM2 can be located on the side of the fourth transistor T4's control electrode T4g close to the (M+1)th row sub-pixel, and the second reset control line Reset2 can be located on the side of the second light emission control line EM2 close to the (M+1)th row sub-pixel; in the first direction X, the control electrode T4g of the fourth transistor T4 and the control electrode T1g of the first transistor T1 can be located on the side of the third transistor T3's control electrode T3g close to the (N-1)th column sub-pixel.

[0230] In an exemplary embodiment, the region where the second light-emitting control line EM2 overlaps with the active layer AT6 of the sixth transistor T6 can serve as the control electrode T6g of the sixth transistor T6.

[0231] In an exemplary embodiment, the orthographic projection of the control electrode T1g of the first transistor T1 onto the substrate at least partially overlaps with the orthographic projection of the active layer AT1 of the first transistor T1 onto the substrate; the orthographic projection of the control electrode T3g of the third transistor T3 onto the substrate at least partially overlaps with the orthographic projection of the active layer AT3 of the third transistor T3 onto the substrate; and the orthographic projection of the control electrode T4g of the fourth transistor T4 onto the substrate at least partially overlaps with the orthographic projection of the active layer AT4 of the fourth transistor T4 onto the substrate.

[0232] In an exemplary embodiment, after the fourth conductive layer pattern is formed, the fourth conductive layer can be used as a shield to conduct the second semiconductor layer. The second semiconductor layer in the area shielded by the fourth conductive layer forms the channel regions of the first transistor T1 to the fourth transistor T4, the sixth transistor T6 and the seventh transistor T7. The semiconductor layer in the area not shielded by the third conductive layer is conducted, that is, the first region and the second region of the active layer AT1 of the first transistor T1 to the active layer AT4 of the fourth transistor T4 and the active layer AT6 of the sixth transistor T6 are all conducted.

[0233] (108) Forming a sixth insulating layer pattern. In an exemplary embodiment, forming a sixth insulating layer pattern may include: depositing a sixth insulating film on a substrate on which the aforementioned pattern is formed, and patterning the sixth insulating film using a patterning process to form a sixth insulating layer covering the fourth conductive layer. The sixth insulating layer has a plurality of vias, as shown in FIG14, FIG14 being a planar structural diagram of six sub-pixels after the formation of the sixth insulating layer.

[0234] In an exemplary embodiment, at least some of the vias in the sub-pixels include at least: a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11, a twelfth via V12, a thirteenth via V13, a fourteenth via V14, a fifteenth via V15, a sixteenth via V16, a seventeenth via V17, an eighteenth via V18, a nineteenth via V19, a twentieth via V20, and a twenty-first via V21.

[0235] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate lies within the orthographic projection of the active layer AT1 of the first transistor T1 onto the substrate. The sixth and fifth insulating layers within the first via V1 are etched away, exposing the surface of the first region AT11 of the active layer AT1 of the first transistor T1 (which is also the surface of the first region AT21 of the active layer AT2 of the second transistor T2). The first via V1 is configured to connect the first electrode of the subsequently formed first transistor T1 to the active layer AT1 of the first transistor T1 through the via, and the first electrode of the subsequently formed second transistor T2 to the active layer AT2 of the second transistor T2 through the via.

[0236] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate lies within the orthographic projection of the active layer AT1 of the first transistor T1 onto the substrate. The sixth and fifth insulating layers within the second via V2 are etched away, exposing the surface of the second region AT12 of the active layer AT1 of the first transistor T1. The second via V2 is configured to allow the second electrode of the subsequently formed first transistor T1 to be connected to the active layer AT1 of the first transistor T1 through the via.

[0237] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate lies within the orthographic projection of the active layer AT2 of the second transistor T2 onto the substrate. The sixth and fifth insulating layers within the third via V3 are etched away, exposing the surface of the second region AT22 of the active layer AT2 of the second transistor T2 (which is also the second region AT42 of the active layer AT4 of the fourth transistor T4). The third via V3 is configured to connect the second electrode of the subsequently formed second transistor T2 to the active layer AT2 of the second transistor T2 through the via, and to connect the second electrode of the subsequently formed fourth transistor T4 to the active layer AT4 of the fourth transistor T4 through the via.

[0238] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate lies within the orthographic projection of the active layer AT3 of the third transistor T3 onto the substrate. The sixth and fifth insulating layers within the fifth via V5 are etched away, exposing the surface of the first region AT31 of the active layer AT3 of the third transistor T3. The fifth via V5 is configured to allow the first electrode of the subsequently formed third transistor T3 to be connected to the active layer AT3 of the third transistor T3 through this via.

[0239] In an exemplary embodiment, the orthogonal projection of the fifth via V5 onto the substrate lies within the orthogonal projection of the active layer AT3 of the third transistor T3 onto the substrate. The sixth and fifth insulating layers within the fifth via V5 are etched away, exposing the surface of the second region AT32 of the active layer AT3 of the third transistor T3. The fifth via V5 is configured to allow the second electrode of the subsequently formed third transistor T3 to be connected to the active layer AT3 of the third transistor T3 through the via.

[0240] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate lies within the orthographic projection of the active layer AT4 of the fourth transistor T4 onto the substrate. The sixth and fifth insulating layers within the sixth via V6 are etched away, exposing the surface of the first region AT41 of the active layer AT4 of the fourth transistor T4. The sixth via V6 is configured to allow the first electrode of the subsequently formed fourth transistor T4 to be connected to the active layer AT4 of the fourth transistor T4 through this via.

[0241] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate lies within the orthographic projection of the active layer AT4 of the fourth transistor T4 onto the substrate. The sixth and fifth insulating layers within the seventh via V7 are etched away, exposing the surface of the second region AT42 of the active layer AT4 of the fourth transistor T4. The seventh via V7 is configured to allow the second electrode of the subsequently formed fourth transistor T4 to be connected to the active layer AT4 of the fourth transistor T4 through this via.

[0242] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate lies within the orthographic projection of the active layer AT5 of the fifth transistor T5 onto the substrate. The sixth, fifth, fourth, third, second, and first insulating layers within the seventh via V7 are etched away, exposing the surface of the first region AT51 of the active layer AT5 of the fifth transistor T5. The seventh via V7 is configured to allow the second electrode of the subsequently formed fifth transistor T5 to be connected to the active layer AT5 of the fifth transistor T5 through this via.

[0243] In an exemplary embodiment, the orthographic projection of the eighth via V8 onto the substrate lies within the orthographic projection of the active layer AT5 of the fifth transistor T5 onto the substrate. The sixth, fifth, fourth, third, second, and first insulating layers within the eighth via V8 are etched away, exposing the surface of the second region AT52 of the active layer AT5 of the fifth transistor T5. The eighth via V8 is configured to allow the second electrode of the subsequently formed fifth transistor T5 to be connected to the active layer AT5 of the fifth transistor T5 through this via.

[0244] In an exemplary embodiment, the orthogonal projection of the ninth via V9 onto the substrate lies within the orthogonal projection of the active layer AT6 of the sixth transistor T6 onto the substrate. The sixth and fifth insulating layers within the ninth via V9 are etched away, exposing the surface of the first region AT61 of the active layer AT6 of the sixth transistor T6. The ninth via V9 is configured to allow the first electrode of the subsequently formed sixth transistor T6 to be connected to the active layer AT6 of the sixth transistor T6 through this via.

[0245] In an exemplary embodiment, the orthographic projection of the tenth via V10 onto the substrate lies within the orthographic projection of the active layer AT6 of the sixth transistor T6 onto the substrate. The sixth and fifth insulating layers within the tenth via V10 are etched away, exposing the surface of the second region AT62 of the active layer AT6 of the sixth transistor T6 (which is also the second region AT72 of the active layer AT7 of the seventh transistor T7). The tenth via V10 is configured to connect the second electrode of the subsequently formed sixth transistor T6 to the active layer AT6 of the sixth transistor T6 through the via, and to connect the second electrode of the subsequently formed seventh transistor T7 to the active layer AT7 of the seventh transistor T7 through the via.

[0246] In an exemplary embodiment, the orthographic projection of the eleventh via V11 onto the substrate lies within the orthographic projection of the active layer AT7 of the seventh transistor T7 onto the substrate. The sixth and fifth insulating layers within the eleventh via V11 are etched away, exposing the surface of the second region AT72 of the active layer AT7 of the seventh transistor T7. The eleventh via V11 is configured to allow the first electrode of the subsequently formed seventh transistor T7 to be connected to the active layer AT7 of the seventh transistor T7 through the via.

[0247] In an exemplary embodiment, the orthographic projection of the twelfth via V12 onto the substrate is within the range of the orthographic projection of the first electrode C11 of the first capacitor C1 onto the substrate (the orthographic projection of the fourteenth via V14 onto the substrate may be within the range of the orthographic projection of the first connecting portion CL1 onto the substrate). The sixth, fifth, fourth, third, and second insulating layers within the fourteenth via V14 are etched away, exposing the surface of the first electrode C11 of the first capacitor C1. The fourteenth via V14 is configured to allow the second electrode of the subsequently formed first transistor T1 to be connected to the first electrode C11 of the first capacitor C1 through this via.

[0248] In an exemplary embodiment, the orthographic projection of the thirteenth via V13 onto the substrate lies within the range of the orthographic projection of the first electrode C21 of the second capacitor C2 onto the substrate (the orthographic projection of the thirteenth via V13 onto the substrate may lie within the range of the orthographic projection of the second connection CL2 onto the substrate). The sixth, fifth, fourth, third, and second insulating layers within the thirteenth via V13 are etched away, exposing the surface of the first electrode C21 of the second capacitor C2. The thirteenth via V13 is configured to allow the second electrodes of the subsequently formed second transistor T2 and fourth transistor T4 to be connected to the first electrode C21 of the second capacitor C2 through this via.

[0249] In an exemplary embodiment, the orthographic projection of the fourteenth via V14 onto the substrate lies within the range of the orthographic projection of the first second initial signal line Vinit2-B onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the fourteenth via V14 are etched away, exposing the surface of the first second initial signal line Vinit2-B. The fourteenth via V14 is configured to connect the first electrode of the seventh transistor T7 in the subsequently formed first sub-pixel to the first second initial signal line Vinit2-B through this via. In an exemplary embodiment, the fourteenth via V14 may be disposed in the first sub-pixel, while the second and third sub-pixels may not have the fourteenth via V14 disposed therein.

[0250] In an exemplary embodiment, the orthogonal projection of the fifteenth via V15 onto the substrate lies within the orthogonal projection of the second electrode C12 of the first capacitor C1 onto the substrate. The sixth, fifth, fourth, and third insulating layers within the fifteenth via V15 are etched away, exposing the surface of the second electrode C12 of the first capacitor C1. The fifteenth via V15 is configured to allow the second electrode of the subsequently formed third transistor T3 to be connected to the second electrode C12 of the first capacitor C1 through this via.

[0251] In an exemplary embodiment, the orthogonal projection of the sixteenth via V16 onto the substrate lies within the orthogonal projection of the second electrode C22 of the second capacitor C2 onto the substrate. The sixth, fifth, fourth, and third insulating layers within the sixteenth via V16 are etched away, exposing the surface of the second electrode C22 of the second capacitor C2. The sixteenth via V16 is configured to allow the first electrode of the subsequently formed sixth transistor T6 to be connected to the second electrode C22 of the second capacitor C2 through this via.

[0252] In an exemplary embodiment, the orthogonal projection of the seventeenth via V17 onto the substrate lies within the orthogonal projection of the control electrode T1g of the first transistor T1 onto the substrate. The sixth insulating layer within the seventeenth via V17 is etched away, exposing the surface of the control electrode T1g of the first transistor T1. The seventeenth via V17 is configured to allow the subsequently formed first reset control line Reset1 to be connected to the control electrode T1g of the first transistor T1 through this via.

[0253] In an exemplary embodiment, the orthogonal projection of the eighteenth via V18 onto the substrate lies within the orthogonal projection of the control electrode T4g of the fourth transistor T4 onto the substrate. The sixth insulating layer within the eighteenth via V18 is etched away, exposing the surface of the control electrode T4g of the fourth transistor T4. The eighteenth via V18 is configured to allow the subsequently formed scan control line Gate to be connected to the control electrode T4g of the fourth transistor T4 through this via.

[0254] In an exemplary embodiment, the orthogonal projection of the nineteenth via V19 onto the substrate lies within the orthogonal projection of the control electrode T5g of the fifth transistor T5 onto the substrate. The sixth, fifth, fourth, third, and second insulating layers within the nineteenth via V19 are etched away, exposing the surface of the control electrode T5g of the fifth transistor T5. The nineteenth via V19 is configured to allow the subsequently formed first light-emitting control line EM1 to connect to the control electrode T5g of the fifth transistor T5 through this via.

[0255] In an exemplary embodiment, the orthogonal projection of the twentieth via V20 onto the substrate lies within the orthogonal projection of the control electrode T3g of the third transistor T3 onto the substrate. The sixth insulating layer within the twentieth via V20 is etched away, exposing the surface of the control electrode T3g of the third transistor T3. The twentieth via V20 is configured to allow the second electrode of the subsequently formed first transistor T1 to be connected to the control electrode T3g of the third transistor T3 through the via.

[0256] In an exemplary embodiment, the orthogonal projection of the twenty-first via V21 onto the substrate lies within the orthogonal projection of the bottom gate T3gb of the third transistor T3 onto the substrate. The sixth insulating layer and the fifth insulating layer within the twenty-first via V21 are etched away, exposing the surface of the control electrode T3g of the third transistor T3. The twenty-first via V21 is configured to allow the subsequently formed third connection electrode to be connected to the control electrode T3g of the third transistor T3 through this via.

[0257] (109) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive film on a substrate on which the aforementioned pattern is formed, patterning the fifth conductive film using a patterning process, and forming a fifth conductive layer disposed on a sixth insulating layer, as shown in Figures 15a and 15b. Figure 15a is a planar structural diagram of six sub-pixels after the formation of the fifth conductive layer, and Figure 15b is a planar schematic diagram of the fifth conductive layer in Figure 15a. In an exemplary embodiment, the fifth conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0258] In an exemplary embodiment, the fifth conductive layer includes at least: a second initial signal line Vinit2-RG, a scan control line Gate, a second power connection line VSSL, a first initial signal line Vinit1, a first reset control line Reset1, a first light emission control line EM1, a first power connection line VDDL, a first connection electrode L1, a second connection electrode L2, a third connection electrode L3, a fourth connection electrode L4, a fifth connection electrode L5, a sixth connection electrode L6, a seventh connection electrode L7, and an eighth connection electrode L8.

[0259] In an exemplary embodiment, the main body of the second initial signal line Vinit2-RG, the scan control line Gate, the second power connection line VSSL, the first initial signal line Vinit1, the first reset control line Reset1, the first light emission control line EM1, and the first power connection line VDDL can be a strip-shaped structure or a zigzag structure extending along the first direction X. In the same row of sub-pixels, the two types of second initial signal lines Vinit2-RG, the scan control line Gate, the second power connection line VSSL, the first initial signal line Vinit1, the first reset control line Reset1, the first light emission control line EM1, and the first power connection line VDDL can be arranged sequentially at intervals along the second direction Y.

[0260] In an exemplary embodiment, within the same sub-pixel, in the second direction Y, the first connecting electrode L1, the third connecting electrode L3, and the sixth connecting electrode L6 may be located between the first reset control line Reset1 and the first light emission control line EM1, the first connecting electrode L1 may be located between the third connecting electrode L3 and the sixth connecting electrode L6, and the third connecting electrode L3 may be located between the first connecting electrode L1 and the first reset control line Reset1; the second connecting electrode L2, the fourth connecting electrode L4, the seventh connecting electrode L7, and the eighth connecting electrode L8 may be located between the scan control line Gate and the second type of second initial signal line Vinit2-RG, and the fourth connecting electrode L4 and the seventh connecting electrode L7 may be located on the side of the second connecting electrode L2 and the eighth connecting electrode L8 away from the second type of second initial signal line Vinit2-RG; the fifth connecting electrode L5 may be located between the scan control line Gate and the second power connection line VSSL; in the first direction X, the fourth connecting electrode L4 and the eighth connecting electrode L8 may be located on the same side of the second connecting electrode L2, the third connecting electrode L3, and the seventh connecting electrode L7.

[0261] In an exemplary embodiment, the second initial signal line Vinit2-RG can be connected to the first region AT71 of the active layer AT7 of the seventh transistor T7 located in the second and third sub-pixels of a row of sub-pixels via the eleventh via V1 in the second and third sub-pixels of that row, thereby providing a second initial signal to the seventh transistor T7 of the second and third sub-pixels in that row of sub-pixels. In an exemplary embodiment, the second initial signal line Vinit2-RG can serve as the first electrode of the second transistor T2 in the second and third sub-pixels.

[0262] In an exemplary embodiment, the scan control line Gate can be connected to the control electrode T4g of the fourth transistor T4 in a row of sub-pixels through the eighteenth via V18 in that row of sub-pixels, and is configured to provide scan signals to the control electrodes T4g of the plurality of fourth transistors T4 in that row of sub-pixels.

[0263] In an exemplary embodiment, the main body of the second power connection line VSSL can extend along the first direction X, and multiple second power connection lines VSSL are arranged at intervals along the second direction Y. These multiple second power connection lines VSSL are interconnected with subsequently formed multiple second power lines to form a grid structure, which can reduce the voltage drop of the second power lines and improve display uniformity. In an exemplary embodiment, the second power connection line VSSL is provided with multiple blocking structures ZD. The blocking structures ZD can be located in the first sub-pixel, and the orthographic projection of the blocking structure ZD on the substrate at least partially overlaps with the orthographic projection of the second capacitor on the substrate. The blocking structure ZD can be a strip structure or a zigzag structure extending along the second direction Y. In the same first sub-pixel, in the second direction Y, the blocking structure ZD can be located on the side of the second power connection line VSSL closer to the scan control line Gate.

[0264] In an exemplary embodiment, the first initial signal line Vinit1 can be connected to the first region AT11 of the active layer AT1 of the first transistor T1 in that row of sub-pixels (which is also the first region AT21 of the active layer AT2 of the second transistor T2) via a first via V1 in that row of sub-pixels, thus providing a first initial signal to the first transistor T1 and the second transistor T2 in that row of sub-pixels. In an exemplary embodiment, the first initial signal line Vinit1 can serve as the first electrode of the first transistor T1 and the first electrode of the second transistor T2.

[0265] In an exemplary embodiment, the first reset control line Reset1 can be connected to the control electrode T1g of the first transistor T1 in a row of sub-pixels through the seventeenth via V17 in that row of sub-pixels, and is configured to provide a first reset control signal to the control electrodes T1g of the plurality of first transistors T1 in that row of sub-pixels.

[0266] In an exemplary embodiment, the first light-emitting control line EM1 can be connected to the control electrode T5g of the fifth transistor T5 in the row of sub-pixels through the nineteenth via V19 in the row of sub-pixels, and is configured to provide light-emitting control signals to the control electrodes T5g of the plurality of fifth transistors T5 in the row of sub-pixels.

[0267] In an exemplary embodiment, the first power connection line VDDL can be connected to the first region AT51 of the active layer AT5 of the fifth transistor T5 in that row of sub-pixels via the seventh via V7 in that row of sub-pixels, thereby providing a first power signal to the active layer AT5 of the plurality of fifth transistors T5 in that row of sub-pixels. In an exemplary embodiment, the first power connection line VDDL can serve as the first electrode of the fifth transistor T5.

[0268] In an exemplary embodiment, the first connecting electrode L1 is approximately L-shaped, rotated 90° clockwise. The first connecting electrode L1 can be connected to the second region AT12 of the active layer AT1 of the first transistor T1 via the second via V2, to the first electrode C11 (the first connection portion CL1 on the first electrode C11 of the first capacitor C1) via the twelfth via V12, and to the control electrode T3g of the third transistor T3 via the twentieth via V20. The second region AT12 of the active layer AT1 of the first transistor T1, the first electrode C11 of the first capacitor C1, and the control electrode T3g of the third transistor T3 can be electrically connected via the first connecting electrode L1, so that the second electrode of the first transistor T1, the first electrode C11 of the first capacitor C1, and the control electrode T3g of the third transistor T3 in the same sub-pixel have the same potential. In an exemplary embodiment, the first connecting electrode L1 can serve as the second electrode of the first transistor T1.

[0269] In an exemplary embodiment, the second connection electrode L2 is generally shaped as a strip or a broken line extending along the first direction X. The second connection electrode L2 can be connected to the second region AT62 of the active layer AT6 of the sixth transistor T6 (which is also the second region AT72 of the active layer AT7 of the seventh transistor T7) through the tenth via V10. In an exemplary embodiment, the second connection electrode L2 can serve as the second electrode of both the sixth transistor T6 and the seventh transistor T7. The second connection electrode L2 is configured to be connected to the anode connection electrode of a subsequently formed light-emitting element.

[0270] In an exemplary embodiment, the third connecting electrode L3 is generally a strip-shaped structure or a zigzag structure extending along the first direction X. The third connecting electrode L3 can be connected to the second region AT32 of the active layer AT3 of the third transistor T3 via the fifth via V5, to the second plate C12 of the first capacitor C1 via the fifteenth via V15, and to the bottom gate T3gb of the third transistor T3 via the twenty-first via V21, so that the second region AT32 of the active layer AT3 of the third transistor T3, the bottom gate T3gb of the third transistor T3, and the second plate C12 of the first capacitor C1 in the same sub-pixel have the same potential. In an exemplary embodiment, the third connecting electrode L3 can serve as the second electrode of the third transistor T3. In an exemplary embodiment, the bottom gate T3gb of the third transistor T3 is electrically connected to the second plate C12 of the first capacitor C1, and can serve as the plate of the first capacitor C1, thereby increasing the capacitance of the first capacitor C1.

[0271] In an exemplary embodiment, the fourth connection electrode L4 is generally a block structure or a strip structure or a zigzag structure extending along the first direction X. The fourth connection electrode L4 can be connected to the first region AT41 of the active layer AT4 of the fourth transistor T4 through the sixth via V6. In an exemplary embodiment, the first connection electrode L1 can serve as the first electrode of the fourth transistor T4 and is configured to be connected to the subsequently formed data signal line.

[0272] In an exemplary embodiment, the fifth connecting electrode L5 is generally a strip-shaped structure or a zigzag structure extending along the first direction X. The fifth connecting electrode L5 can be connected to the second region AT42 of the active layer AT4 of the fourth transistor T4 (which is also the second region AT22 of the active layer AT2 of the second transistor T2) through the third via V3, and to the first electrode C21 of the second capacitor C2 (the second connecting portion CL2 on the first electrode C21 of the second capacitor C2) through the thirteenth via V13, so that the second region AT22 of the active layer AT2 of the second transistor T2, the first electrode C21 of the second capacitor C2, and the second region AT42 of the active layer AT4 of the fourth transistor T4 in the same sub-pixel have the same potential. In an exemplary embodiment, the fifth connecting electrode L5 can serve as the second electrode of both the second transistor T2 and the fourth transistor T4.

[0273] In an exemplary embodiment, the sixth connecting electrode L6 is generally strip-shaped or zigzag-shaped extending along the first direction X. The sixth connecting electrode L6 can be connected to the second region AT52 of the active layer AT5 of the fifth transistor T5 in that row of sub-pixels via the eighth via V8, and to the first region AT31 of the active layer AT3 of the third transistor T3 in that row of sub-pixels via the fourth via V4. In an exemplary embodiment, the sixth connecting electrode L6 can serve as the second electrode of the fifth transistor T5. In the same sub-pixel, the second region AT52 of the active layer AT5 of the fifth transistor T5 and the first region AT31 of the active layer AT3 of the third transistor T3 can be electrically connected via the sixth connecting electrode L6, so that the second region AT52 of the active layer AT5 of the fifth transistor T5 and the first region AT31 of the active layer AT3 of the third transistor T3 in the same sub-pixel have the same potential.

[0274] In an exemplary embodiment, the seventh connection electrode L7 can be a strip structure or a zigzag structure extending along the first direction X. The seventh connection electrode L7 can be connected to the first region AT61 of the active layer AT6 of the sixth transistor T6 through the ninth via V9, and to the second electrode C22 of the second capacitor C2 through the sixteenth via V16. In an exemplary embodiment, the seventh connection electrode L7 can serve as the first electrode of the sixth transistor T6. In the same sub-pixel, the first region AT61 of the active layer AT6 of the sixth transistor T6 and the second plate C22 of the second capacitor C2 can be electrically connected through the seventh connecting electrode L7, so that the first region AT61 of the active layer AT6 of the sixth transistor T6 and the second plate C22 of the second capacitor C2 in the same sub-pixel have the same potential. Since the second plate C12 of the first capacitor C1 and the second plate C22 of the second capacitor C2 are connected through the third connecting part CL3, and the second plate C12 of the first capacitor C1 is connected to the second region AT32 of the active layer AT3 of the third transistor T3 through the third connecting electrode L3, the second plate C12 of the first capacitor C1, the second plate C22 of the second capacitor C2, the second region AT32 of the active layer AT3 of the third transistor T3, and the first region AT61 of the active layer AT6 of the sixth transistor T6 have the same potential.

[0275] In an exemplary embodiment, the eighth connection electrode L8 is generally strip-shaped or zigzag-shaped extending along the first direction X. The eighth connection electrode L8 can be connected to the first region AT71 of the active layer AT7 of the seventh transistor T7 in the first sub-pixel through an eleventh via V11 located in the first sub-pixel of a row of sub-pixels, and to the first type of second initial signal line Vinit2-B in the first sub-pixel of the row of sub-pixels through a fourteenth via V14 located in the first sub-pixel of the row of sub-pixels. In an exemplary embodiment, the eighth connection electrode L8 can serve as the first electrode of the seventh transistor T7 in the first sub-pixel. In an exemplary embodiment, the eighth connection electrode L8 is located in the first sub-pixel, while the second and third sub-pixels do not have the eighth connection electrode L8.

[0276] (110) Forming a seventh insulating layer and a first planarization layer pattern. In an exemplary embodiment, forming a seventh insulating layer and a first planarization layer pattern may include: depositing a seventh insulating film on a substrate on which the aforementioned pattern is formed, then coating a first planarization film, and patterning the first planarization film and the sixth insulating film using a patterning process to form a seventh insulating layer covering the fifth conductive layer pattern and a first planarization layer disposed on the seventh insulating layer. A plurality of vias are provided on the seventh insulating layer and the first planarization layer, as shown in FIG16. FIG16 is a planar structural diagram of six sub-pixels after the formation of the first planarization layer.

[0277] In an exemplary embodiment, the plurality of vias on the seventh insulating layer and the first planarization layer may include at least: a twenty-second via V22, a twenty-third via V23, a twenty-fourth via V24, a twenty-fifth via V25, a twenty-sixth via V26, and a twenty-seventh via V27.

[0278] In an exemplary embodiment, the orthographic projection of the 22nd via V22 onto the substrate lies within the range of the orthographic projection of the second power connection line VSSL onto the substrate. The first planarization layer and the seventh insulating layer within the 22nd via V22 are etched away, exposing the surface of the second power connection line VSSL. The 22nd via V22 is configured to allow a subsequently formed second power line to be electrically connected to the second power connection line VSSL through this via. In an exemplary embodiment, the 22nd via V22 may be disposed in the first sub-pixel and the second sub-pixel.

[0279] In an exemplary embodiment, the orthographic projection of the twenty-third via V23 onto the substrate lies within the range of the orthographic projection of the first initial signal line Vinit1 onto the substrate. The first planarization layer and the seventh insulating layer within the twenty-third via V23 are etched away, exposing the surface of the first initial signal line Vinit1. The twenty-third via V23 is configured to allow a subsequently formed first initial signal connection line to be electrically connected to the first initial signal line Vinit1 through this via. In an exemplary embodiment, the twenty-third via V23 may be disposed between the second sub-pixel and the third sub-pixel.

[0280] In an exemplary embodiment, the orthographic projection of the 24th via V24 onto the substrate lies within the range of the orthographic projection of the second initial signal line Vinit2-RG onto the substrate. The first planarization layer and the seventh insulating layer within the 24th via V24 are etched away, exposing the surface of the second initial signal line Vinit2-RG. The 24th via V24 is configured to allow a subsequently formed second initial signal connection line to be electrically connected to the second initial signal line Vinit2-RG through this via. In an exemplary embodiment, the 24th via V24 may be disposed in a third sub-pixel.

[0281] In an exemplary embodiment, the orthographic projection of the 25th via V25 onto the substrate lies within the orthographic projection of the 8th connecting electrode L8 onto the substrate. The first planarization layer and the 7th insulating layer within the 25th via V25 are etched away, exposing the surface of the 8th connecting electrode L8. The 25th via V25 is configured to allow a subsequently formed first type of second initial signal connection line to be electrically connected to the first type of second initial signal line Vinit2-B through this via. In an exemplary embodiment, the 25th via V25 may be disposed within the first sub-pixel.

[0282] In an exemplary embodiment, the orthographic projection of the 26th via V26 onto the substrate lies within the range of the orthographic projection of the second connecting electrode L2 onto the substrate. The first planarization layer and the seventh insulating layer within the 26th via V26 are etched away, exposing the surface of the second connecting electrode L2. The 26th via V26 is configured to allow the anode connecting electrode of a subsequently formed light-emitting element to be electrically connected to the second connecting electrode L2 through this via.

[0283] In an exemplary embodiment, the orthographic projection of the 27th via V27 onto the substrate lies within the range of the orthographic projection of the first power connection line VDDL onto the substrate. The first planarization layer and the seventh insulating layer within the 27th via V27 are etched away, exposing the surface of the first power connection line VDDL. The 27th via V27 is configured to allow a subsequently formed first power line to be electrically connected to the first power connection line VDDL through this via. In an exemplary embodiment, the 27th via V27 may be disposed in the second sub-pixel and the third sub-pixel.

[0284] (111) Forming a sixth conductive layer pattern. In an exemplary embodiment, forming the sixth conductive layer may include: depositing a sixth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the sixth conductive film using a patterning process to form a sixth conductive layer disposed on a first planarization layer, as shown in Figures 17a and 17b. Figure 17a is a planar structural diagram of six sub-pixels after the formation of the sixth conductive layer, and Figure 17b is a planar schematic diagram of the sixth conductive layer in Figure 17a. In an exemplary embodiment, the sixth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0285] In an exemplary embodiment, the sixth conductive layer includes at least: a data signal line DL, a first power line VDD, a second power line VSS, an anode connection electrode ZL, a first initial signal connection line Vinit1L, a first second initial signal connection line Vinit2L-B, and a second second initial signal connection line Vinit2L-RG.

[0286] In an exemplary embodiment, the data signal line DL is a zigzag or strip-shaped portion extending along the second direction Y. The data signal line DL is connected to the fourth connection electrode L4 through the twenty-first via V21. Since the fourth connection electrode L4 is connected to the first region AT41 of the active layer AT4 of the fourth transistor T4 through the via, the connection between the data signal line DL and the first electrode of the fourth transistor T4 is realized, and the data signal is written to the fourth transistor T4. In an exemplary embodiment, in the same pixel unit, the orthographic projection of at least a portion of the occlusion structure ZD in the first sub-pixel onto the substrate is located between the orthographic projection of the second capacitor in the first sub-pixel onto the substrate and the orthographic projection of the data signal line DL in the second sub-pixel onto the substrate. This can shield the signal interference of the data signal line DL in the second sub-pixel to the second capacitor C2 in the first sub-pixel to a certain extent, thereby reducing signal crosstalk and improving the display effect.

[0287] In an exemplary embodiment, the first power line VDD is a zigzag or strip-shaped portion extending along the second direction Y. The first power line VDD is connected to the first power connection line VDDL through the twenty-first via V21. Since the first power connection line VDDL is connected to the first region AT51 of the active layer AT5 of the fifth transistor T5 through the via, the connection between the first power line VDD and the fifth transistor T5 is realized, and the power signal is written to the first terminal of the fifth transistor T5.

[0288] In an exemplary embodiment, the anode connection electrode ZL can be in the shape of an "I" or a strip structure or a zigzag structure extending along the second direction Y. The anode connection electrode ZL can be connected to the second connection electrode L2 through the twenty-sixth via V26. Since the second connection electrode L2 is connected to the second region AT62 of the active layer AT6 of the sixth transistor T6 (which is also the second region AT72 of the active layer AT7 of the seventh transistor T7) through the via, the connection between the anode connection electrode ZL and the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 is realized.

[0289] In an exemplary embodiment, the first initial signal connection line Vinit1L can be a zigzag or strip shape extending along the second direction Y of the main body. The first initial signal connection line Vinit1L can be connected to the first initial signal line Vinit1 through the twenty-third via V23. Since the first initial signal line Vinit1 is connected to the first region AT11 of the active layer AT1 of the first transistor T1 and the first region AT21 of the active layer AT2 of the second transistor T2 through the via, the connection between the first initial signal connection line Vinit1L and the first region AT11 of the active layer AT1 of the first transistor T1 and the first region AT21 of the active layer AT2 of the second transistor T2 is realized, and the initial signal is written into the first region AT11 of the active layer AT1 of the first transistor T1 and the first region AT21 of the active layer AT2 of the second transistor T2. Multiple first initial signal connection lines Vinit1L and multiple first initial signal lines Vinit1 are interconnected to form a grid structure, so that the first initial signals received by adjacent first transistors T1 and second transistors T2 are basically consistent, which helps to improve the uniformity of panel display, avoid display defects of display substrate, and ensure the display effect of display substrate.

[0290] In an exemplary embodiment, the first type of second initial signal connection line Vinit2L-B can be a zigzag or strip shape extending along the second direction Y of the main body. The first type of second initial signal connection line Vinit2L-B can be connected to the eighth connection electrode L8 in the first sub-pixel through the twenty-fifth via V25. Since the eighth connection electrode L8 is connected to the first region AT71 of the active layer AT7 of the seventh transistor T7 in the first sub-pixel and the first type of second initial signal line Vinit2-B through the via, the connection between the first type of second initial signal connection line Vinit2L-B and the first region AT71 of the active layer AT7 of the seventh transistor T7 in the first sub-pixel and the first type of second initial signal line Vinit2-B is realized. Multiple first type of second initial signal connection lines Vinit2L-B interconnect to form a grid structure, ensuring that the second initial signals received by the seventh transistor T7 in adjacent first sub-pixels are essentially consistent. This is beneficial for improving the uniformity of the panel display, avoiding display defects in the display substrate, and ensuring the display effect of the display substrate.

[0291] In an exemplary embodiment, the second type of second initial signal connection line Vinit2L-RG can be a zigzag or strip shape extending along the second direction Y of the main body. The second type of second initial signal connection line Vinit2L-RG can be connected to the second type of second initial signal line Vinit2-RG through the twenty-fourth via V24. Since the second type of second initial signal line Vinit2-RG is connected to the first region AT1 of the active layer AT7 of the seventh transistor T7 in the second and third sub-pixels through the via, the connection between the second type of second initial signal connection line Vinit2L-RG and the first region AT71 of the active layer AT7 of the seventh transistor T7 in the second and third sub-pixels is realized, and the initial signal is written into the first region AT71 of the active layer AT7 of the seventh transistor T7 in the second and third sub-pixels. Multiple second-type second initial signal connection lines Vinit2L-RG are interconnected to form a grid structure, which makes the second initial signals received by the seventh transistor T7 in adjacent second and third sub-pixels basically consistent. This helps to improve the uniformity of the panel display, avoid display defects in the display substrate, and ensure the display effect of the display substrate.

[0292] In an exemplary embodiment, within the same pixel unit, in the first direction X, the first initial signal connection line Vinit1L can be located between the pixel driving circuit of the second sub-pixel and the pixel driving circuit of the third sub-pixel, and the signal lines closest to both sides of the first initial signal connection line Vinit1L are the first power line VDD. The pixel driving circuit of the second sub-pixel and the pixel driving circuit of the third sub-pixel are respectively provided with a first power line VDD, and the pixel driving circuit of the first sub-pixel and the pixel driving circuit of the second sub-pixel are respectively provided with a second power line VSS. The second type of second initial signal connection line Vinit2L-RG can be located in the pixel driving circuit of the third sub-pixel, and the first type of second initial signal connection line Vinit2L-B can be located in the pixel driving circuit of the first sub-pixel.

[0293] In an exemplary embodiment, within the same pixel unit, in a first direction: the pixel driving circuit of the first sub-pixel, the pixel driving circuit of the second sub-pixel, and the pixel driving circuit of the third sub-pixel are arranged sequentially. In the first sub-pixel, the data signal line DL, the first type of second initial signal connection line Vinit2L-B, and the second power line VSS can be arranged sequentially at intervals along the first direction X, and the anode connection electrode ZL can be located on the side of the second power line VSS away from the first type of second initial signal connection line Vinit2L-B. In the second sub-pixel, the data signal line DL, the second power line VSS, and the first power line VDD can be arranged sequentially at intervals along the first direction X, and the anode connection electrode ZL can be located between the second power line VSS and the first power line VDD. In the third sub-pixel, the first power line VDD and the second type of second initial signal connection line Vinit2L-RG can be arranged sequentially at intervals along the first direction X, and the anode connection electrode ZL can be located between the second type of second initial signal connection line Vinit2L-RG and the first power line VDD.

[0294] Thus, the driving circuit layer is fabricated on the substrate. The driving circuit layer has pixel driving circuits for multiple sub-pixels. Figures 8 to 17b show schematic diagrams of the planar structure of the pixel driving circuits for sub-pixels in the display substrate. In an exemplary embodiment, in the direction perpendicular to the plane of the display substrate, the driving circuit layer may include a first semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a second semiconductor layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer sequentially disposed on the substrate.

[0295] In an exemplary embodiment, in a direction perpendicular to the plane of the display substrate, the driving circuit layer may include a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a fifth insulating layer, a sixth insulating layer, a seventh insulating layer, and a first planarization layer. The first insulating layer is disposed between the first semiconductor layer and the first conductive layer, the second insulating layer is disposed between the first conductive layer and the second conductive layer, the third insulating layer is disposed between the second conductive layer and the third conductive layer, the fourth insulating layer is disposed between the third conductive layer and the second semiconductor layer, the fifth insulating layer is disposed between the second semiconductor layer and the fourth conductive layer, the sixth insulating layer is disposed between the fourth conductive layer and the fifth conductive layer, and the seventh insulating layer and the first planarization layer are disposed between the fifth conductive layer and the sixth conductive layer.

[0296] In an exemplary embodiment, after the driving circuit layer is fabricated, a light-emitting structure layer is fabricated on the driving circuit layer. The fabrication process of the light-emitting structure layer may include the following operations: forming a second planarization layer pattern, wherein at least an anode via is provided on the second planarization layer; forming an anode pattern (i.e., an anode conductive layer), wherein the anode is connected to the anode connecting electrode through the anode via; forming an anode pixel definition layer, wherein a pixel opening is provided on the pixel definition layer, and the pixel opening exposes the anode; forming an organic light-emitting layer using a vapor deposition or inkjet printing process, wherein a cathode is formed on the organic light-emitting layer; and forming an encapsulation layer, wherein the encapsulation layer may include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together, wherein the first and third encapsulation layers may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is disposed between the first and third encapsulation layers to ensure that external moisture cannot enter the light-emitting structure layer. The steps for fabricating the light-emitting structure layer are as follows:

[0297] (112) Forming a second planarization layer pattern. In an exemplary embodiment, forming a second planarization layer pattern may include: coating a second planarization film on a substrate on which the aforementioned pattern is formed, and patterning the second planarization film using a patterning process to form a second planarization layer covering the pattern of the fifth conductive layer. The second planarization layer is provided with a plurality of vias, as shown in FIG18, FIG18 being a planar structural diagram of six sub-pixels after the formation of the second planarization layer.

[0298] In an exemplary embodiment, the plurality of vias may include at least: a twenty-eighth via V28.

[0299] In an exemplary embodiment, each sub-pixel's via includes at least a twenty-eighth via V28. The orthographic projection of the twenty-eighth via V28 onto the substrate lies within the range of the orthographic projection of the anode connection electrode ZL onto the substrate. The second planarization layer within the twenty-eighth via V28 is removed, exposing the surface of the anode connection electrode ZL. The twenty-eighth via V28 is configured to allow a subsequently formed anode to be electrically connected to the anode connection electrode ZL through the via.

[0300] (113) Forming an anode conductive layer pattern. In an exemplary embodiment, forming an anode conductive layer pattern may include: depositing an anode conductive film on a substrate on which the aforementioned pattern is formed, and patterning the anode conductive film using a patterning process to form an anode conductive layer pattern disposed on a second planarization layer, as shown in Figures 19a to 19b. Figure 19a is a planar structural schematic diagram of six sub-pixels after the anode conductive layer is formed, and Figure 19b is a planar schematic diagram of the anode conductive layer in Figure 19a.

[0301] In an exemplary embodiment, the anode conductive layer pattern may include at least a plurality of anodes AN, which may include: a first anode AN1, a second anode AN2 and a third anode AN3. The area where the first anode AN1 is located may form a blue light-emitting unit that emits blue light, the area where the second anode AN2 is located may form a green light-emitting unit that emits green light, and the area where the third anode AN3 is located may form a red light-emitting unit that emits red light.

[0302] In an exemplary embodiment, the first anode AN1, the second anode AN2, and the third anode AN3 can be connected to the anode connection electrode ZL in the corresponding sub-pixel through the twenty-seventh via V27. Since the anode connection electrode ZL in the sub-pixel is electrically connected to the second electrode of the sixth transistor T6 (which is also the second electrode of the seventh transistor T7) through the via, the first anode AN1, the second anode AN2, and the third anode AN3 can be connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7 through the anode connection electrode ZL, respectively, thereby enabling the pixel driving circuit to drive the light-emitting device to emit light.

[0303] In an exemplary embodiment, the anode AN may include an anode body portion AN01 and an anode connecting portion AN02. The anode body portion AN01 may be a rectangular structure. One end of the anode connecting portion AN02 is connected to the anode body portion AN01, and the other end is electrically connected to the anode connecting electrode ZL through a twenty-eighth via V28. The anode connecting portion AN02 may be a strip-shaped structure or a block-shaped structure extending along a first direction X or a second direction Y. The anode connecting portion AN02 may be configured to compensate for the differences in parasitic capacitance between multiple sub-pixels caused by signal traces. By setting the anode connecting portion AN02, the parasitic capacitance of multiple sub-pixels can be kept basically consistent, thereby improving the display uniformity of the display substrate.

[0304] (114) Forming a pixel definition layer pattern. In an exemplary embodiment, forming a pixel definition layer pattern may include: depositing a pixel definition layer film on a substrate on which the aforementioned pattern is formed, and patterning the pixel definition layer using a patterning process to form a pixel definition layer pattern disposed on an anode conductive layer, as shown in Figures 20a and 20b. Figure 20a is a schematic diagram of the planar structure of six sub-pixels after the pixel definition layer is formed, and Figure 20b is a schematic diagram of the planar structure of the pixel definition layer in Figure 20a.

[0305] In an exemplary embodiment, the pixel definition layer pattern may include multiple pixel openings K, each exposing an anode AN. In an exemplary embodiment, the orthographic projection of a pixel opening K onto the substrate lies within the range of the orthographic projection of the anode AN onto the substrate. In an exemplary embodiment, the pixel opening K may include a first sub-pixel pixel opening K01, a second sub-pixel pixel opening K02, and a third sub-pixel pixel opening K03. The orthographic projection of the first sub-pixel pixel opening K01 onto the substrate overlaps with the orthographic projection of the first anode AN1 onto the substrate; the orthographic projection of the second sub-pixel pixel opening K02 onto the substrate overlaps with the orthographic projection of the second anode AN2 onto the substrate; and the orthographic projection of the third sub-pixel pixel opening K03 onto the substrate overlaps with the orthographic projection of the third anode AN3 onto the substrate.

[0306] In an exemplary embodiment, the first conductive layer, second conductive layer, third conductive layer, fourth conductive layer, and fifth conductive layer can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo, Ti / Al / Ti, etc. The first insulating layer, second insulating layer, third insulating layer, fourth insulating layer, and fifth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON). They can be single-layer, multi-layer, or composite layers.

[0307] In an exemplary embodiment, taking six sub-pixels (one sub-pixel row, six sub-pixel columns, and the pixel driving circuit adopts the 7T2C structure shown in Figure 4) in the display area (AA) as an example, the preparation process of another display substrate can be the same as the above steps (101) to (114), with the following differences: the third conductive layer formed in the above step (105) can be as shown in Figures 21a to 21b. Figure 21a is a planar structural diagram of the six sub-pixels after the formation of the third conductive layer, and Figure 21b is a structural schematic diagram of the third conductive layer in Figure 21a. The difference between the third conductive layer shown in Figure 21b and the third conductive layer shown in Figure 11b is that: in the pattern of the third conductive layer shown in Figure 21b, a third electrode C23 of the second capacitor C2 is added. The orthographic projection of the third electrode C23 of the second capacitor C2 on the substrate at least partially overlaps with the orthographic projection of the second electrode C22 of the second capacitor C2 on the substrate. The third electrode C23 of the second capacitor C2 is provided with a second opening K2. The second opening K2 is set to accommodate the subsequently formed ninth via V9 and sixteenth via V16.

[0308] The sixth insulating layer formed in step (108) above can be as shown in Figure 22. The difference between the sixth insulating layer shown in Figure 22 and the sixth insulating layer shown in Figure 14 is that a twenty-ninth via V29 is added to the pattern of the sixth insulating layer shown in Figure 22. The orthographic projection of the twenty-ninth via V29 on the substrate at least partially overlaps with the orthographic projection of the third electrode C23 of the second capacitor C2 on the substrate. The sixth and fifth insulating layers within the twenty-ninth via V29 are etched away, exposing the surface of the third electrode C23 of the second capacitor C2. The twenty-ninth via V29 is configured to allow the subsequently formed fifth connection electrode to be connected to the third electrode C23 of the second capacitor C2 through this via.

[0309] The fifth conductive layer formed in step (109) above can be shown in Figures 23a and 23b. Figure 23a is a planar structural diagram of the six sub-pixels after the formation of the fifth conductive layer, and Figure 23b is a schematic diagram of the structure of the fifth conductive layer in Figure 23a. The difference between the fifth conductive layer shown in Figure 23b and the fifth conductive layer shown in Figure 15b is that in the pattern of the fifth conductive layer shown in Figure 23b, the fifth connecting electrode L5 can also be electrically connected to the third plate C23 of the second capacitor C2 through the twenty-ninth via V29, so that the second region AT22 of the active layer AT2 of the second transistor T2, the first plate C21 of the second capacitor C2, and the second capacitor C2 in the same sub-pixel are connected. The third electrode plate C23 and the second region AT42 of the active layer AT4 of the fourth transistor T4 have the same potential. The first electrode plate C21 of the second capacitor C2 is electrically connected to the third electrode plate C23 of the second capacitor C2. On the one hand, this can increase the capacitance of the second capacitor C2. On the other hand, the second electrode plate C22 of the second capacitor C2 is located between the first electrode plate C21 and the third electrode plate C23 of the second capacitor C2. This can shield the third node N3 (the third node N3 is the connection node between the second electrode of the sixth transistor T6 and the second electrode plate C22 of the second capacitor C2) and reduce the parasitic capacitance of the third node N3 and the signal lines of other film layers.

[0310] In an exemplary embodiment, taking six sub-pixels (one sub-pixel row, six sub-pixel columns, and the pixel driving circuit adopts the 7T2C structure shown in Figure 4) in the display area (AA) as an example, the fabrication process of another display substrate can be the same as steps (101) to (114) above, with the following differences:

[0311] The fourth conductive layer formed in the above step (107) can be shown in Figures 24a to 24b. Figure 24a is a planar structure diagram of the six sub-pixels after the formation of the fourth conductive layer. Figure 24b is a schematic diagram of the structure of the fourth conductive layer in Figure 24a. The difference between the fourth conductive layer shown in Figure 24b and the fourth conductive layer shown in Figure 13b is that: in the pattern of the fourth conductive layer shown in Figure 24b, a third electrode C23 of the second capacitor C2 is added. The orthographic projection of the third electrode C23 of the second capacitor C2 on the substrate at least partially overlaps with the orthographic projection of the second electrode C22 of the second capacitor C2 on the substrate. A second opening K2 is provided on the third electrode C23 of the second capacitor C2. The second opening K2 is set to accommodate the subsequently formed ninth via V9 and sixteenth via V16.

[0312] The sixth insulating layer formed in step (108) above can be as shown in Figure 25. The difference between the sixth insulating layer shown in Figure 25 and the sixth insulating layer shown in Figure 14 is that a twenty-ninth via V29 is added to the pattern of the sixth insulating layer shown in Figure 25. The orthographic projection of the twenty-ninth via V29 on the substrate at least partially overlaps with the orthographic projection of the third electrode C23 of the second capacitor C2 on the substrate. The sixth insulating layer inside the twenty-ninth via V29 is etched away, exposing the surface of the third electrode C23 of the second capacitor C2. The twenty-ninth via V29 is configured to allow the subsequently formed fifth connecting electrode to be connected to the third electrode C23 of the second capacitor C2 through this via.

[0313] The fifth conductive layer formed in step (109) above can be shown in Figures 26a and 26b. Figure 26a is a planar structural diagram of six sub-pixels after the formation of the fifth conductive layer, and Figure 26b is a schematic diagram of the structure of the fifth conductive layer in Figure 26a. The difference between the fifth conductive layer shown in Figure 26b and the fifth conductive layer shown in Figure 15b is that in the pattern of the fifth conductive layer shown in Figure 26b, the fifth connecting electrode L5 can also be connected to the third plate C23 of the second capacitor C2 through the twenty-ninth via V29, so that the second region AT22 of the active layer AT2 of the second transistor T2 in the same sub-pixel, the first plate C21 of the second capacitor C2, and the third plate C23 of the second capacitor C2 can be connected to the active layer AT2 of the second transistor T2 in the same sub-pixel. The second region AT42 of the active layer AT4 of the fourth transistor T4 and the first plate C21 of the second capacitor C2 are electrically connected to the third plate C23 of the second capacitor C2. On the one hand, this can increase the capacitance of the second capacitor C2. On the other hand, the second plate C22 of the second capacitor C2 is located between the first plate C21 and the third plate C23 of the second capacitor C2. This can shield the third node N3 (the third node N3 is the connection node between the second electrode of the sixth transistor T6 and the second plate C22 of the second capacitor C2) and reduce the parasitic capacitance of the third node N3 to the signal lines of other film layers.

[0314] In an exemplary embodiment, taking six sub-pixels (one sub-pixel row, six sub-pixel columns, and the pixel driving circuit adopts the 7T2C structure shown in Figure 4) in the display area (AA) as an example, the fabrication process of another display substrate can be the same as steps (101) to (114) above, with the following differences:

[0315] The third conductive layer formed in the above step (105) can be shown in Figures 27a to 27b. Figure 27a is a planar structure diagram of the six sub-pixels after the formation of the third conductive layer. Figure 27b is a schematic diagram of the structure of the third conductive layer in Figure 27a. The difference between the third conductive layer shown in Figure 27b and the third conductive layer shown in Figure 11b is that: in the pattern of the third conductive layer shown in Figure 27b, a third electrode C23 of the second capacitor C2 is added. The orthographic projection of the third electrode C23 of the second capacitor C2 on the substrate at least partially overlaps with the orthographic projection of the second electrode C22 of the second capacitor C2 on the substrate. A second opening K2 is provided on the third electrode C23 of the second capacitor C2. The second opening K2 is set to accommodate the subsequently formed ninth via V9 and sixteenth via V16.

[0316] The fourth conductive layer formed in the above step (107) can be shown in Figures 28a to 28b. Figure 28a is a planar structural diagram of the six sub-pixels after the formation of the fourth conductive layer. Figure 28b is a schematic diagram of the structure of the fourth conductive layer in Figure 28a. The difference between the fourth conductive layer shown in Figure 28b and the fourth conductive layer shown in Figure 13b is that: in the pattern of the fourth conductive layer shown in Figure 28b, a fourth electrode C24 of the second capacitor C2 is added. The orthographic projection of the fourth electrode C24 of the second capacitor C2 on the substrate at least partially overlaps with the orthographic projection of the second electrode C22 and the third electrode C23 of the second capacitor C2 on the substrate. The fourth electrode C24 of the second capacitor C2 is provided with a second opening K2 and a third opening K3. The second opening K2 is set to accommodate the subsequently formed ninth via V9 and sixteenth via V16, and the third opening K3 is set to accommodate the subsequently formed twenty-ninth via V29.

[0317] The sixth insulating layer formed in step (108) above can be as shown in Figure 29. The difference between the sixth insulating layer shown in Figure 29 and the sixth insulating layer shown in Figure 14 is that: in the pattern of the sixth insulating layer shown in Figure 29, a twenty-ninth via V29 and a thirtieth via V30 are added. The orthographic projection of the twenty-ninth via V29 on the substrate is located within the range of the orthographic projection of the third electrode C23 of the second capacitor C2 on the substrate. The sixth and fifth insulating layers in the twenty-ninth via V29 are etched away, exposing the surface of the third electrode C23 of the second capacitor C2. The twenty-ninth via V29 is configured to allow the subsequently formed fifth connection electrode to be connected to the third electrode C23 of the second capacitor C2 through the via. The sixth insulating layer in the thirtieth via V30 is etched away, exposing the surface of the fourth electrode C24 of the second capacitor C2. The thirtieth via V30 is configured to allow the subsequently formed seventh connection electrode to be connected to the fourth electrode C24 of the second capacitor C2 through the via.

[0318] The fifth conductive layer formed in step (109) above can be shown in Figures 30a and 30b. Figure 30a is a planar structural diagram of the six sub-pixels after the formation of the fifth conductive layer, and Figure 30b is a schematic diagram of the structure of the fifth conductive layer in Figure 30a. The difference between the fifth conductive layer shown in Figure 30b and the fifth conductive layer shown in Figure 15b is that: in the fifth conductive layer pattern shown in Figure 26b, the fifth connecting electrode L5 can also be connected to the third plate C23 of the second capacitor C2 through the twenty-ninth via V29, so that the second region AT22 of the active layer AT2 of the second transistor T2, the first plate C21 of the second capacitor C2, the third plate C23 of the second capacitor C2, and the second region AT42 of the active layer AT4 of the fourth transistor T4 in the same sub-pixel have the same potential; the seventh connecting electrode L7 can also be connected to the fourth plate C24 of the second capacitor C2 through the thirtieth via V30, so that the same In each sub-pixel, the first region AT61 of the active layer AT6 of the sixth transistor T6, the second plate C22 of the second capacitor C2, and the fourth plate C24 of the second capacitor C2 have the same potential. The first plate C21 of the second capacitor C2 is electrically connected to the third plate C23 of the second capacitor C2 (corresponding to the fourth node N4), and the second plate C22 of the second capacitor C2 is electrically connected to the fourth plate C24 of the second capacitor C2 (corresponding to the third node N3). On the one hand, this can increase the capacitance of the second capacitor C2. On the other hand, the second plate C22 of the second capacitor C2 is located between the first plate C21 and the third plate C23 of the second capacitor C2, which can shield the third node N3 (the third node N3 is the connection node between the second electrode of the sixth transistor T6 and the second plate C22 of the second capacitor C2), and reduce the parasitic capacitance of the third node N3 and the signal lines of other film layers. In Figure 30a, the first plate C21 and the third plate C23 of the second capacitor C2 are connected to the fourth node N4, and the second plate C2 and the fourth plate C24 of the second capacitor C2 are connected to the third node N3. The fourth plate C24 of the second capacitor C2, as a point node N3, is not shielded, and the shielding effect on the third node N3 is slightly poor. The first plate C21 and the third plate C23 of the second capacitor C2 can be connected to the third node N3, and the second plate C22 and the fourth plate C24 of the second capacitor C2 can be connected to the fourth node N4. This way, the third node N3 can be well shielded, and large parasitic capacitances can be avoided between the third node N3 and other signal lines in the conductive film layer.

[0319] In exemplary embodiments, the sub-pixel rows and sub-pixel columns described in this disclosure can be understood as the rows and columns of pixel driving circuits in a sub-pixel. The anode in a sub-pixel is connected to the pixel driving circuit in the corresponding sub-pixel, but the position of the anode of a sub-pixel does not necessarily correspond completely to the row and column of the pixel driving circuit it is connected to. For example, the orthographic projection of the anode AN3 of the third sub-pixel on the substrate may overlap with the orthographic projections of the pixel driving circuits of the second and third sub-pixels on the substrate. The orthographic projection of the anode AN2 of the second sub-pixel on the substrate may overlap with the orthographic projections of the pixel driving circuits of the second and third sub-pixels on the substrate. The orthographic projection of the anode AN1 of the first sub-pixel on the substrate may overlap with the orthographic projection of the pixel driving circuit of the first sub-pixel on the substrate.

[0320] The structures and fabrication processes described above in this disclosure are merely illustrative examples. In the exemplary embodiments, the corresponding structures and patterning processes can be modified and added or reduced as needed. The display substrates in this disclosure can be applied to other display devices with pixel driving circuits, such as quantum dot displays, etc. This disclosure does not limit them.

[0321] This disclosure also provides a display device, as shown in FIG31. The display device may include the display substrate of any of the foregoing embodiments. The display device may be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0322] The display substrate and display device provided in this disclosure include a display substrate comprising a plurality of sub-pixels, at least one sub-pixel including a pixel driving circuit, the pixel driving circuit including a driving transistor and a first capacitor, the first plate of the first capacitor being electrically connected to the control electrode of the driving transistor, the second plate of the first capacitor being electrically connected to the second electrode of the driving transistor, the second plate of the first capacitor being located on the side of the first plate of the first capacitor away from the substrate, the orthographic projection of the first plate of the first capacitor on the substrate and the orthographic projection of the second plate of the first capacitor on the substrate at least partially overlap, which can reduce the parasitic capacitance of the control electrode of the driving transistor and improve display uniformity.

[0323] The accompanying drawings of the embodiments disclosed herein only relate to the structures involved in the embodiments of this disclosure; other structures can be referred to in a general design.

[0324] Where there is no conflict, the features of the embodiments disclosed herein can be combined with each other to obtain new embodiments.

[0325] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of these embodiments and is not intended to limit the scope of these embodiments. Any person skilled in the art to which these embodiments pertain may make any modifications and changes to the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the patent protection scope of these embodiments shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, comprising: The substrate and a plurality of sub-pixels disposed on one side of the substrate, at least some of the sub-pixels include a pixel driving circuit, at least one pixel driving circuit includes a plurality of transistors and at least one capacitor, the plurality of transistors include at least a driving transistor, the at least one capacitor includes at least a first capacitor, the first plate of the first capacitor is electrically connected to the control electrode of the driving transistor, and the second plate of the first capacitor is electrically connected to the second electrode of the driving transistor. In a direction perpendicular to the plane of the substrate, the second plate of the first capacitor is located on the side of the first plate of the first capacitor away from the substrate, and the orthographic projection of the first plate of the first capacitor on the substrate at least partially overlaps with the orthographic projection of the second plate of the first capacitor on the substrate.

2. The display substrate according to claim 1, wherein, The first plate of the first capacitor includes a first main body portion, and in the same sub-pixel, the orthographic projection of the first main body portion on the substrate is located within the range of the orthographic projection of the second plate of the first capacitor on the substrate.

3. The display substrate according to claim 1 or 2, wherein, The pixel driving circuit further includes at least one connecting electrode, which is located on the side of the second plate of the first capacitor away from the substrate in the same sub-pixel in a direction perpendicular to the plane of the substrate.

4. The display substrate according to claim 3, wherein, In a direction perpendicular to the plane of the substrate, the driving transistor is located on the side of the second plate of the first capacitor away from the substrate, and the orthogonal projection of the driving transistor on the substrate is within the range of the orthogonal projection of the second plate of the first capacitor on the substrate; The at least one connection electrode includes at least a first connection electrode, and in the same sub-pixel, the first plate of the first capacitor is electrically connected to the control electrode of the driving transistor through the first connection electrode.

5. The display substrate according to claim 4, wherein, The first electrode of the first capacitor includes a first main body and a first connecting part. The first main body overlaps at least partially with the second electrode of the first capacitor. The orthographic projection of at least a portion of the structure of the first connecting part on the substrate does not overlap with the orthographic projection of the second electrode of the first capacitor on the substrate. In the same sub-pixel, one end of the first connecting portion is connected to the first main body portion, and the other end is electrically connected to the control electrode of the driving transistor through the first connecting electrode. The first connecting portion is located at the edge of the first main body portion, at the position closest to the control electrode of the driving transistor.

6. The display substrate according to claim 4, wherein, The at least one connection electrode includes the second electrode of the driving transistor, and the orthographic projection of the second electrode of the driving transistor on the substrate is within the range of the orthographic projection of the second plate of the first capacitor on the substrate.

7. The display substrate according to claim 4, wherein, The driving transistor further includes a bottom gate, which is located between the second plate of the first capacitor and the active layer of the driving transistor in a direction perpendicular to the plane of the substrate. In the same sub-pixel, the bottom gate of the driving transistor is electrically connected to the second plate of the first capacitor, and the bottom gate of the driving transistor at least partially overlaps with the orthographic projection of the active layer of the driving transistor onto the substrate.

8. The display substrate according to claim 1 or 2 further includes a plurality of control lines, the control lines being electrically connected to the control electrode of at least one transistor, wherein in a direction perpendicular to the plane of the substrate, the plurality of control lines are located on the side of the second electrode of the first capacitor away from the substrate, and the orthographic projection of the plurality of control lines on the substrate does not overlap with the orthographic projection of the first electrode of the first capacitor on the substrate.

9. The display substrate according to claim 1 or 2, wherein, The plurality of transistors includes at least one first type transistor, the at least one first type transistor including at least the driving transistor, and in a direction perpendicular to the plane of the substrate, the first type transistor includes: an active layer of the first type transistor located on the side of the second plate of the first capacitor away from the substrate, a control electrode of the first type transistor located on the side of the active layer of the first type transistor away from the substrate, and a first electrode and a second electrode located on the side of the control electrode of the first type transistor away from the substrate. The at least one capacitor further includes a second capacitor, in the same sub-pixel, the second plate of the second capacitor is electrically connected to the second plate of the first capacitor and the second electrode of the driving transistor, and the first plate of the second capacitor and the orthographic projection of the second plate of the second capacitor on the substrate at least partially overlap.

10. The display substrate according to claim 9, wherein, The first plate of the second capacitor includes a second main body portion, and in the same sub-pixel, the orthographic projection of the second main body portion on the substrate is located within the range of the orthographic projection of the second plate of the second capacitor on the substrate.

11. The display substrate according to claim 9, wherein, The first plate of the second capacitor is disposed on the same layer as the first plate of the first capacitor, and the second plate of the second capacitor is disposed on the same layer as the second plate of the first capacitor. Within the same sub-pixel, the second capacitor and the first capacitor are arranged sequentially along the second direction.

12. The display substrate according to claim 11, wherein, The second capacitor further includes a third plate, which is located on the side of the second capacitor away from the substrate in a direction perpendicular to the plane of the substrate; In the same sub-pixel: the third plate of the second capacitor at least partially overlaps with the orthographic projection of the second plate of the second capacitor onto the substrate, and the third plate of the second capacitor is electrically connected to the first plate of the second capacitor.

13. The display substrate according to claim 12, wherein, In a direction perpendicular to the plane of the substrate, the third plate of the second capacitor is located between the second plate of the second capacitor and the active layer of the first type of transistor, or the third plate of the second capacitor is disposed on the same layer as the control electrode of the first type of transistor.

14. The display substrate according to claim 12, wherein, The second capacitor also includes a fourth electrode plate. In a direction perpendicular to the plane of the substrate, the third electrode plate of the second capacitor is located between the second electrode plate of the second capacitor and the active layer of the first type of transistor, and the fourth electrode plate of the second capacitor is disposed on the same layer as the control electrode of the first type of transistor. In the same sub-pixel, the fourth plate of the second capacitor is electrically connected to the second plate of the second capacitor, and the orthographic projection of the fourth plate of the second capacitor onto the substrate at least partially overlaps with that of the third plate of the second capacitor.

15. The display substrate according to claim 9, wherein, In a direction perpendicular to the plane of the substrate, the second plate of the second capacitor is located on the side of the first plate of the second capacitor away from the substrate. In the same sub-pixel: the orthographic projections of the first capacitor and the second capacitor on the substrate at least partially overlap, and the second plate of the first capacitor serves as the first plate of the second capacitor.

16. The display substrate according to claim 15, wherein, Within the same sub-pixel, the main body of the first plate of the first capacitor is located within the range of the orthographic projection of the first plate of the second capacitor onto the substrate.

17. The display substrate according to claim 15, wherein, In a direction perpendicular to the plane of the substrate, the second plate of the second capacitor is located between the first plate of the second capacitor and the active layer of the first type of transistor, or the second plate of the second capacitor is disposed on the same layer as the control electrode of the first type of transistor.

18. The display substrate according to claim 15, wherein, The second capacitor also includes a third electrode plate. In a direction perpendicular to the plane of the substrate, the second electrode plate of the second capacitor is located between the first electrode plate of the second capacitor and the active layer of the first type of transistor. The third electrode plate of the second capacitor is disposed on the same layer as the control electrode of the first type of transistor. Within the same sub-pixel, the third plate of the second capacitor is electrically connected to the first plate of the second capacitor.

19. The display substrate according to claim 18, wherein, The second capacitor also includes a fourth plate, which is disposed on the same layer as the first plate and the second plate; Within the same sub-pixel, the fourth plate of the second capacitor is electrically connected to the second plate of the second capacitor.

20. The display substrate according to claim 18 or 19, wherein, The orthographic projection of the second plate of the second capacitor onto the substrate lies within the range of the orthographic projection of the third plate of the second capacitor onto the substrate.

21. The display substrate according to any one of claims 15 to 19, wherein, The orthogonal projections of multiple plates in the same second capacitor onto the substrate at least partially overlap.

22. The display substrate according to claim 9, wherein, The plurality of transistors further includes at least one second type of transistor, the second type of transistor comprising: an active layer of the second type of transistor, a control electrode of the second type of transistor, a first electrode and a second electrode of the second type of transistor, wherein, in a direction perpendicular to the plane of the substrate, the active layer of the second type of transistor is located on the side of the first electrode plate of the first capacitor closer to the substrate, the control electrode of the second type of transistor is disposed in the same layer as the first electrode plate of the first capacitor, and the first electrode and the second electrode of the second type of transistor are disposed in the same layer as the first electrode and the second electrode of the first type of transistor; The second type of transistor includes a fifth transistor as a light-emitting control transistor, and the first type of transistor includes the driving transistor and a first transistor as a reset transistor; in the same sub-pixel, the driving transistor and the first capacitor's orthogonal projection on the substrate at least partially overlap; in a second direction, the first transistor and the fifth transistor are located on opposite sides of the driving transistor; in a first direction, the first transistor and the fifth transistor are located on the same side of the driving transistor, the first capacitor, and the second capacitor; the first direction intersects the second direction.

23. The display substrate according to claim 22 further includes a plurality of control lines extending along the first direction, the plurality of control lines including a first reset control line and a first light emission control line, the first light emission control line and the first reset control line being disposed in the same layer as the first electrode and the second electrode; The plurality of sub-pixels form a plurality of rows of sub-pixels. The first reset control line is electrically connected to the control electrode of at least one first transistor in at least one row of sub-pixels. The first light emission control line is electrically connected to the control electrode of at least one fifth transistor in at least one row of sub-pixels. In the same sub-pixel, the first light emission control line and the first reset control line are located on opposite sides of the first capacitor. The second capacitor is located on the side of the first reset control line away from the first capacitor.

24. The display substrate according to claim 23, wherein, The first type of transistor also includes a second transistor as a reset transistor and a fourth transistor as a data write transistor. The plurality of control lines also include a third reset control line and a scan control line. The third reset control line is disposed on the same layer as the control electrode of the first type of transistor, and the scan control line is disposed on the same layer as the first electrode and the second electrode. The third reset control line is electrically connected to the control electrode of at least one second transistor in at least one row of sub-pixels, and the scan control line is electrically connected to at least one fourth transistor in at least one row of sub-pixels. In the same sub-pixel, in the first direction, the second transistor and the fourth transistor are located on the same side of the second capacitor. In the second direction, the second transistor and the third reset control line are located between the first transistor and the fourth transistor. The scan control line is located on the side of the third reset control line away from the first transistor. The third reset control line and the scan control line overlap with the second capacitor at least partially, and there is no overlapping area between the third reset control line and the scan control line and the first capacitor.

25. The display substrate according to claim 24, wherein, The first type of transistor also includes a sixth transistor as a light-emitting transistor and a seventh transistor as a reset transistor. The plurality of control lines also include a second reset control line and a second light-emitting control line, which are disposed on the same layer as the control electrode of the first type of transistor. The second light-emitting control line is electrically connected to the control electrode of at least one sixth transistor in at least one row of sub-pixels, and the second reset control line is electrically connected to the control electrode of at least one seventh transistor in at least one row of sub-pixels. In the same sub-pixel, in the second direction, the sixth transistor and the second light-emitting control line are located on the side of the fourth transistor away from the second transistor, the seventh transistor and the second reset control line are located on the side of the sixth transistor away from the fourth transistor, and the sixth transistor and the seventh transistor are located on the side of the second capacitor away from the first capacitor. The second reset control line, the second light-emitting control line and the first capacitor and the second capacitor do not overlap.

26. A display device comprising a display substrate as described in any one of claims 1 to 25.

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