Communication method and apparatus

Abstract

The present application provides a communication method and apparatus. In the method, a communication apparatus performs first-stage lifting on a first matrix (for example, a base matrix) to obtain a second matrix, which is used for obtaining a check matrix, and then performs LDPC encoding or LDPC decoding by means of the obtained check matrix. By means of the above implementation, it is beneficial to increasing the scale of the check matrix, thereby optimizing the decoding threshold.

Description

Communication methods and devices

[0001] This application claims priority to Chinese Patent Application No. CN202411922682.1, filed on December 23, 2024, entitled "Communication Method and Apparatus", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of communication technology, and in particular to a communication method and apparatus. Background Technology

[0003] Low-density parity check (LDPC) codes are a type of linear block coding with sparse parity check matrices. They are characterized by flexible structure and low decoding complexity, and have been selected by the 3rd generation partnership project (3GPP) as the coding scheme for 5th generation (5G) data channels.

[0004] However, there is significant room for optimization in the decoding threshold of LDPC codes. For example, the performance of existing new radio (NR) LDPC codes suffers severe degradation at extremely high code rates. Furthermore, increasing the decoding complexity of LDPC codes leads to a decrease in parallelism and increases the complexity of hardware implementation. Therefore, optimizing the decoding threshold of LDPC codes without increasing decoding complexity is an urgent problem to be solved. Summary of the Invention

[0005] This application provides a communication method and apparatus for optimizing the decoding threshold of LDPC codes and improving user experience.

[0006] Firstly, this application provides a communication method. This method can be executed by a first communication device. The first communication device can support LDPC encoding; therefore, the first communication device can also be called an encoding device. This application does not limit the type of the first communication device. For example, the first communication device can be a first communication equipment, or the first communication device can be a component within a first communication equipment. Exemplarily, the first communication equipment can be a terminal device or a network device. In this application, components can include at least one of a processor, circuit, logic module, software module or software code, chip, or chip system. Possible forms of terminal devices and network devices will be described later, and will not be elaborated here.

[0007] In the communication method provided in the first aspect, a second matrix is ​​obtained, the second matrix comprising a recurring first set derived from a first matrix. The first set consists of all or a portion of the information columns in the first matrix. Alternatively, the first set consists of all or a portion of the information columns in the first matrix and one or more core check columns in the first matrix. The second matrix is ​​used to determine a check matrix, which is used to perform low-density parity-check (LDPC) encoding on the bit sequence to be encoded, obtaining the encoded bit sequence.

[0008] The parity check matrix used by the first communication device is determined based on a second matrix, which includes a first set of repeated occurrences from the first matrix. This improves the performance of the LDPC code. The reasons are analyzed below.

[0009] The degree distribution of the parity-check matrix is ​​a crucial factor determining the performance of LDPC codes. For example, the performance of LDPC codes includes one or more of the following: error correction capability during encoding and decoding, decoding complexity, convergence speed, and decoding threshold. The degree distribution of the parity-check matrix generally includes column weight distribution and row weight distribution. Column weight distribution refers to the distribution of column weights with respect to the number of columns in the parity-check matrix, while row weight distribution refers to the distribution of row weights with respect to the number of rows. The row weight refers to the number of non-zero elements in that row. Assuming a base matrix has 10 columns, with 6 columns having a weight of 3 and 4 columns having a weight of 2, the column weight distribution is as follows: columns with a weight of 3 account for 60%, and columns with a weight of 2 account for 40%. For two parity check matrices with different numbers of columns, the parity check matrix with more columns has more optional column redistribution. More optional column redistribution is conducive to realizing a larger degree distribution design space, which is conducive to finding a parity check matrix with a better degree distribution in a larger degree distribution design space, thereby improving the performance of LDPC codes.

[0010] The second matrix includes the first set of repeated occurrences in the first matrix. This is advantageous in obtaining a second matrix with more columns than the first matrix. Therefore, compared to obtaining a parity check matrix based on the first matrix, obtaining a parity check matrix with more columns based on the second matrix is ​​advantageous in obtaining a parity check matrix that supports a larger degree distribution design space, thereby helping to optimize the performance of LDPC codes.

[0011] The sparsity of the parity-check matrix (PCM) means that most of its elements are zero, which is beneficial for improving the performance of LDPC codes, such as increasing their convergence speed and reducing the hardware decoding complexity. Columns with smaller column weights in the PCM can be called orthogonal positions. Increasing the number of orthogonal positions in the PCM improves its orthogonality (i.e., sparsity), thus enhancing the performance of LDPC codes.

[0012] Assuming the first set of the first matrix includes M orthogonal positions, and the second matrix includes the first set of the first matrix that appears N times, then the second matrix includes at least (N+1)×M orthogonal positions, which is beneficial to improving the orthogonality of the parity check matrix obtained based on the second matrix, thereby improving the performance of the LDPC code.

[0013] The first set consists of all or part of the information columns in the first matrix. This helps to avoid improving the core check columns and extended check columns in the first matrix, thereby allowing for more flexible setting of the encoding structure of the core check columns in the first matrix, simplifying hardware coding, and optimizing the trap set of the core check columns.

[0014] The first set consists of all or part of the information columns of the first matrix and one or more core check columns. This helps to avoid boosting the extended check columns in the first matrix, thereby preventing the extended check columns in the first matrix from appearing repeatedly in the second matrix and reducing the complexity of LDPC code encoding and decoding.

[0015] In one implementation, after obtaining the second matrix, the verification matrix can be determined based on the second matrix.

[0016] In one implementation, after obtaining the second matrix but before obtaining the parity matrix, other processing can be performed on the second matrix. In one possible implementation, column operations and / or row operations can be performed on the second matrix. Column operations can include at least one of expanding columns, deleting columns, or adjusting the order of columns, and row operations can include at least one of expanding rows, deleting rows, or adjusting the order of rows. In one possible implementation, the values ​​of one or more elements in the second matrix can be adjusted.

[0017] In one implementation, after obtaining the parity check matrix, LDPC encoding can be performed on the bit sequence to be encoded based on the parity check matrix to obtain the encoded bit sequence.

[0018] In one implementation, after performing LDPC encoding on the bit sequence to be encoded, the encoded bit sequence can be transmitted. This application does not limit the method of transmitting the encoded bit sequence. For example, the encoded bit sequence can be transmitted through the chip's input / output (I / O) ports, or it can be transmitted through an antenna.

[0019] In one implementation, the encoded bit sequence can be transmitted to a second communication device via a wireless channel, and the second communication device or a second communication unit within the second communication device can support LDPC decoding.

[0020] Secondly, this application provides a communication method. This method can be executed by a second communication device. The second communication device can support LDPC decoding; therefore, the second communication device can also be called a decoding device. This application does not limit the type of the second communication device. For example, the second communication device can be a second communication equipment, or the second communication device can be a component within a second communication equipment (the implementation of the component is similar to the description in the first aspect, and will not be repeated here). Exemplarily, the second communication equipment can be a terminal device or a network device.

[0021] In the communication method provided in the second aspect, a second matrix is ​​obtained, the second matrix comprising a first set of recurring occurrences, the first set being derived from a first matrix. The first set consists of all or a portion of the information columns in the first matrix. Alternatively, the first set consists of all or a portion of the information columns in the first matrix and one or more core check columns in the first matrix. The second matrix is ​​used to determine a check matrix, the check matrix being used to perform low-density parity-check (LDPC) decoding on the bit sequence to be decoded, obtaining the decoded bit sequence.

[0022] The parity check matrix used by the second communication device is determined based on a second matrix, which includes a first set of repeated occurrences from the first matrix. This improves the performance of the LDPC code. The reasons are analyzed below.

[0023] The degree distribution of the parity-check matrix (PCM) is a crucial factor determining the performance of LDPC codes. For example, the performance of LDPC codes includes one or more of the following: error correction capability during encoding and decoding, decoding complexity, convergence speed, and decoding threshold. The degree distribution of the PCM generally includes column redistribution and row redistribution. Column redistribution refers to the distribution of column weights with the number of columns in the PCM, while row redistribution refers to the distribution of row weights with the number of rows. The row weight refers to the number of non-zero elements in that row. For two PCMs with different numbers of columns, the PCM with more columns has more possible column redistributions. More possible column redistributions allow for a larger degree distribution design space, facilitating the optimization of the PCM with a better degree distribution within that larger space, thereby improving the performance of the LDPC code.

[0024] The second matrix includes the first set of repeated occurrences in the first matrix. This is advantageous in obtaining a second matrix with more columns than the first matrix. Therefore, compared to obtaining a parity check matrix based on the first matrix, obtaining a parity check matrix with more columns based on the second matrix is ​​advantageous in obtaining a parity check matrix that supports a larger degree distribution design space, thereby helping to optimize the performance of LDPC codes.

[0025] The sparsity of the parity-check matrix (PCM) means that most of its elements are zero, which is beneficial for improving the performance of LDPC codes, such as increasing their convergence speed and reducing the hardware decoding complexity. Columns with smaller column weights in the PCM can be called orthogonal positions. Increasing the number of orthogonal positions in the PCM improves its orthogonality (i.e., sparsity), thus enhancing the performance of LDPC codes.

[0026] Assuming the first set of the first matrix includes M orthogonal positions, and the second matrix includes the first set of the first matrix that appears N times, then the second matrix includes at least (N+1)×M orthogonal positions, which is beneficial to improving the orthogonality of the parity check matrix obtained based on the second matrix, thereby improving the performance of the LDPC code.

[0027] The first set consists of all or part of the information columns in the first matrix. This helps to avoid improving the core check columns and extended check columns in the first matrix, thereby allowing for more flexible setting of the encoding structure of the core check columns in the first matrix, simplifying hardware coding, and optimizing the trap set of the core check columns.

[0028] The first set consists of all or part of the information columns of the first matrix and one or more core check columns. This helps to avoid boosting the extended check columns in the first matrix, thereby preventing the extended check columns in the first matrix from appearing repeatedly in the second matrix and reducing the complexity of LDPC code encoding and decoding.

[0029] In one implementation, after obtaining the second matrix, the verification matrix can be determined based on the second matrix.

[0030] In one implementation, after obtaining the second matrix but before obtaining the parity matrix, other processing can be performed on the second matrix. In one possible implementation, column operations and / or row operations can be performed on the second matrix. Column operations can include at least one of expanding columns, deleting columns, or adjusting the order of columns, and row operations can include at least one of expanding rows, deleting rows, or adjusting the order of rows. In one possible implementation, the values ​​of one or more elements in the second matrix can be adjusted.

[0031] In one implementation, after obtaining the parity check matrix, LDPC decoding can be performed on the bit sequence to be decoded based on the parity check matrix to obtain the decoded bit sequence.

[0032] In one implementation, the bit sequence to be decoded can be received before performing LDPC decoding. This application does not limit the method of receiving the bit sequence. For example, the bit sequence can be received through the chip's I / O port, or it can be received through an antenna. Optionally, the bit sequence received through the antenna is an encoded bit sequence transmitted via a wireless channel. This encoded bit sequence can be the encoded bit sequence described in the first aspect.

[0033] Below, based on the first or second aspect, this application also provides one or more optional implementation methods.

[0034] In one implementation, the first set, comprising all or a portion of the information columns in the first matrix and one or more core verification columns in the first matrix, specifically includes: the core verification columns in the first set having an odd number of column weights (i.e., the number of non-zero elements) greater than 1. Improving the core verification columns with odd column weights greater than 1 helps to increase hardware utilization and support the requirement for fast convergence. Here, an odd number refers to an integer not divisible by 2; for example, 1, 3, 5, 7, and 9 are all odd numbers.

[0035] In one implementation, the second matrix further includes a second set that appears once, the second set being derived from the first matrix.

[0036] In one implementation, the first set and the second set do not overlap; in other words, the first set and the second set do not include the same columns in the first matrix. In another implementation, the first set appearing repeatedly in the second matrix and the second set appearing once in the second matrix do not overlap; in other words, the first set appearing repeatedly in the second matrix and the second set appearing once in the second matrix do not include the same columns in the second matrix.

[0037] In one implementation, the second set is the parity check column in the first matrix, and / or the second set is the perforated information column in the first matrix. The inclusion of the perforated information column in the second set helps to minimize the increase in the number of perforations in the parity check matrix, thereby preventing a deterioration in LDPC code encoding and decoding performance due to excessive perforations. Simultaneously, maintaining a partial perforation structure can improve the decoding threshold of the LDPC code.

[0038] In one implementation, the first matrix further includes a third set that does not appear in the second matrix.

[0039] In one implementation, the third set is either the punched information columns in the first matrix, or the columns with larger column weights in the first matrix. Columns with larger column weights are also called high-weight columns, which can refer to columns whose weight exceeds a column weight threshold. High-weight columns are generally information columns or core verification columns. The column weight threshold can be predefined or preconfigured. Optionally, the column weight threshold is 3. In this way, one copy of the punched information columns in the first matrix can be retained in the second matrix, and punching processing can then be performed on the retained punched information columns in the second matrix. This helps to ensure that the number of punches in each verification matrix does not increase as much as possible, avoiding performance degradation due to too many punches, while maintaining some punched structure can improve the decoding threshold for maximum performance.

[0040] In one implementation, the second matrix used to determine the check matrix specifically includes: the check matrix is ​​determined based on the second matrix and the translation values ​​corresponding to the non-zero elements in the second matrix; wherein, the translation values ​​corresponding to the non-zero elements in the second matrix are determined based on the translation values ​​corresponding to the non-zero elements in the first matrix. In this way, by storing the translation values ​​of the non-zero elements (or non-zero positions) in the first matrix based on the protocol, the translation values ​​of the non-zero elements in the second matrix can be determined, eliminating the need to additionally store the translation values ​​of the non-zero elements in the second matrix and saving storage resources.

[0041] In one implementation, the translation value corresponding to the non-zero element in the first set in the second matrix is ​​determined by the translation value corresponding to it in the first matrix.

[0042] In one implementation, determining the translation value of a non-zero element in the first set corresponding to its corresponding translation value in the second matrix by the translation value in the first matrix specifically includes: the translation value of a non-zero element in the first set corresponding to its corresponding translation value in the second matrix is ​​determined by adding a first value to the translation value in the first matrix; or, the translation value of a non-zero element in the first set corresponding to its corresponding translation value in the second matrix is ​​determined by multiplying the translation value in the first matrix by a second value; or, the translation value of a non-zero element in the first set corresponding to its corresponding translation value in the second matrix is ​​determined by adding a first value to the translation value in the first matrix and the translation value of a non-zero element in the first set corresponding to its corresponding translation value in the second matrix is ​​determined by multiplying the translation value in the first matrix by a second value.

[0043] Wherein, the first value and / or the second value are predefined or preconfigured values, and the first value and / or the second value can be constants or values ​​obtained through operations. The translation value corresponding to the non-zero element in the first set in the second matrix is ​​determined by adding the first value to its corresponding translation value in the first matrix, and the translation value corresponding to the non-zero element in the first set in the second matrix is ​​determined by multiplying the second value by its corresponding translation value in the first matrix. This can be understood as follows: the translation value corresponding to the non-zero element in the first set in the second matrix is ​​determined by adding the first value to the translation value corresponding to the non-zero element in the first matrix and then multiplying it by the second value; or it can be understood as follows: the translation value corresponding to the non-zero element in the first set in the second matrix is ​​determined by multiplying the second value to the translation value corresponding to the non-zero element in the first matrix and then adding it to the first value.

[0044] In one implementation, the translation value corresponding to the non-zero element in the second set in the second matrix is ​​the same as its translation value in the first matrix. Thus, by storing the translation values ​​of the non-zero elements (or non-zero positions) in the first matrix based on the protocol, the translation values ​​of the non-zero elements in the second set that appear only once in the second matrix can be determined, eliminating the need to separately store the translation values ​​of the non-zero elements in the second set that appear only once in the second matrix, thereby saving storage resources.

[0045] In one implementation, the number of columns in the second matrix is ​​greater than the number of columns in the first matrix.

[0046] In one implementation, the first matrix can be a base graph (BG) defined in the data channel coding scheme of a wireless communication protocol, or a submatrix of that base graph. For example, the base graph can be BG1 or BG2 defined by 3GPP in the 5G data channel coding scheme. The submatrix of the base graph can include a portion of the rows and all the columns of the base graph, or all the rows and a portion of the columns of the base graph, or a portion of the rows and a portion of the columns of the base graph. In this application, the base graph is also referred to as the base map.

[0047] Thirdly, this application provides a communication device comprising multiple functional modules. These multiple functional modules interact to implement a method as described in the first aspect or any possible implementation of the first aspect; correspondingly, the communication device can be the first communication device mentioned in the first aspect.

[0048] Optionally, the multiple functional modules include a first processing module, which is used to obtain a second matrix. The second matrix can be understood by referring to the second matrix described in any one or more of the implementation methods introduced above.

[0049] Optionally, the multiple functional modules include a second processing module, which is used to obtain a verification matrix based on the second matrix obtained by the first processing module. The verification matrix can be understood by referring to the verification matrix described in any one or more of the implementation methods introduced above.

[0050] Optionally, the multiple functional modules also include a third processing module, which is used to perform LDPC encoding on the bit sequence to be encoded based on the parity check matrix obtained by the second processing module, so as to obtain the encoded bit sequence.

[0051] Optionally, multiple functional modules may also include a transceiver unit, which can be used to transmit the encoded bit sequence obtained by the third processing module.

[0052] The technical effects achieved by the functional modules of the communication device in the third aspect of this application can be specifically referred to in the first aspect or any one or more implementations of the first aspect, and will not be repeated here.

[0053] Fourthly, this application provides a communication device comprising multiple functional modules. These functional modules interact to implement a method as described in the second aspect or any possible implementation thereof; correspondingly, the communication device can be the second communication device mentioned in the second aspect.

[0054] Optionally, the multiple functional modules include a first processing module, which is used to obtain a second matrix. The second matrix can be understood by referring to the second matrix described in any one or more of the implementation methods introduced above.

[0055] Optionally, the multiple functional modules include a second processing module, which is used to obtain a verification matrix based on the second matrix obtained by the first processing module. The verification matrix can be understood by referring to the verification matrix described in any one or more of the implementation methods introduced above.

[0056] Optionally, the multiple functional modules also include a third processing module, which is used to perform LDPC decoding on the bit sequence to be decoded based on the parity check matrix obtained by the second processing module, so as to obtain the decoded bit sequence.

[0057] Optionally, some functional modules also include a transceiver unit, which can be used to perform receiving operations. For example, the transceiver unit is used to receive a bit sequence to be decoded.

[0058] The technical effects achieved by the functional modules of the communication device in the fourth aspect of this application can be specifically referred to in the second aspect or any one or more implementations of the second aspect, and will not be repeated here.

[0059] Fifthly, this application provides a communication device including at least one processor, which is configured to execute a computer program stored in a memory to implement the method as described in the first aspect and any implementation thereof, or the processor is configured to execute a computer program stored in a memory to implement the method as described in the second aspect and any implementation thereof.

[0060] Optionally, the communication device also includes a memory. At least one processor is coupled to the memory.

[0061] Sixthly, this application provides a chip or chip system including at least one processor for supporting a communication device in implementing the method described in the first aspect or any implementation thereof, or in implementing the method described in the second aspect or any implementation thereof. For example, the chip may be a baseband chip, a modem chip, a system-on-chip (SoC) chip (such as an SoC chip containing a modem core), a system-in-a-package (SIP) chip, or a communication module, etc.

[0062] In one possible design, the chip or chip system may further include a memory for storing program instructions and data necessary for the communication device. The chip system may be composed of chips or may include chips and other discrete devices. Optionally, the chip system may also include interface circuitry that provides program instructions and / or data to the at least one processor.

[0063] In a seventh aspect, this application provides a communication device including at least one logic circuit and an input / output interface, wherein the logic circuit is used to implement the method described in the first aspect or any implementation thereof, or to implement the method described in the second aspect or any implementation thereof.

[0064] Eighthly, this application provides a computer-readable storage medium having a computer program or instructions stored thereon, which, when executed by a processor, cause the method described in the first aspect or any implementation thereof to be performed, or the method described in the second aspect or any implementation thereof to be performed.

[0065] Ninthly, this application provides a computer program product containing instructions that, when run on a computer, cause the method described in the first aspect or any implementation thereof to be executed, or the method described in the second aspect or any implementation thereof to be executed.

[0066] In a tenth aspect, this application provides a communication system including a first communication device and a second communication device, the first communication device being used to execute the method in the first aspect or any possible implementation thereof, and the second communication device being used to execute the method in the second aspect or any possible implementation thereof.

[0067] The technical effects of any of the design methods in aspects three through ten can be found in the technical effects of the corresponding design methods in aspects one through two above, and will not be repeated here. Attached Figure Description

[0068] Figure 1 schematically illustrates the matrix structure common to the basis matrices;

[0069] Figure 2 schematically shows the matrix regions used by the matrix structure shown in Figure 1 at different code rates;

[0070] Figures 3-1 to 3-4 schematically show the results of cyclically shifting a 4x4 identity matrix (to the right) by 1, 2, 3, and 0;

[0071] Figure 4-1 schematically illustrates the list of promotion sizes in the 3GPP 38.212 protocol;

[0072] Figure 4-2 schematically shows the list of connection and translation values ​​in the BG1 section of the 3GPP 38.212 protocol;

[0073] Figure 5 schematically illustrates the lifting process of the basis matrix in a multi-side LDPC code;

[0074] Figures 6-1 to 6-3 respectively show schematic diagrams of the communication system to which this application applies;

[0075] Figure 7 schematically illustrates the flow of the communication method executed by the first communication device and the second communication device;

[0076] Figure 8 schematically illustrates an example of the first set in the first matrix;

[0077] Figure 9a schematically illustrates an example of a fourth set in the second matrix;

[0078] Figure 9b schematically shows column 1-i in the first set and column 1-i that appears once in the fourth set;

[0079] Figure 10a schematically illustrates another example of the fourth set in the second matrix;

[0080] Figure 10b schematically shows column 1-i in the first set and column 1-i that appears twice in the fourth set;

[0081] Figure 11 schematically illustrates another example of the first matrix;

[0082] Figure 12 schematically illustrates an example of a second matrix;

[0083] Figure 13 schematically illustrates another example of the first matrix;

[0084] Figure 14 schematically illustrates another example of the first matrix;

[0085] Figures 15a to 15i show the performance diagrams of LDPC codes at different code rates;

[0086] Figure 16 shows a simplified schematic diagram of the terminal structure;

[0087] Figure 17 shows a simplified schematic diagram of a RAN node. Detailed Implementation

[0088] Before introducing the technical solution of this application, the relevant technical terms involved in this application are explained. It is understood that these explanations are intended to make this application easier to understand and should not be regarded as a limitation on the scope of protection claimed in this application.

[0089] (1) Terminal equipment:

[0090] It can be a wireless terminal device capable of receiving network device scheduling and instruction information. The wireless terminal device can be a device that provides voice and / or data connectivity to the user, or a handheld device with wireless connectivity, or other processing device connected to a wireless modem.

[0091] Terminal equipment can be user equipment (UE), access terminal, user unit, user station, mobile station, mobile station, remote station, remote terminal, mobile device, user terminal, terminal, wireless communication equipment, user agent, or user device. Terminal equipment can be a device that provides voice / data connectivity to users, such as a handheld device with wireless connectivity, vehicle-mounted equipment, or vehicle-mounted mobile device. Currently, some examples of terminal devices include: smartphones, mobile phones, tablets, laptops, PDAs, mobile internet devices (MIDs), wearable devices, virtual reality (VR) devices, augmented reality (AR) devices, Internet of Things (IoT) devices, wireless terminals in industrial control, wireless terminals in autonomous driving, wireless terminals in remote medical surgery, wireless terminals in smart grids, wireless terminals in transportation safety, wireless terminals in smart cities, wireless terminals in smart homes, cellular phones, cordless phones, session initiation protocol (SIP) phones, wireless local loop (WLL) stations, and personal digital assistants (PDAs). This application does not limit the scope of terminal devices to include personal digital assistants (PDAs), handheld devices with wireless communication capabilities, computing devices, other processing devices connected to a wireless modem, wearable devices, terminal devices in 5G networks, or terminal devices in future evolved public land mobile networks (PLMNs). In vehicle-to-everything (V2X) communication, a communication terminal mounted on a vehicle is a type of terminal device, and a roadside unit (RSU) can also be considered a terminal device. A drone carrying a communication terminal can also be considered a terminal device. A terminal can also be other devices with terminal functions; for example, a terminal can also be a device that functions as a terminal in device-to-device (D2D) communication.

[0092] The wearable devices mentioned earlier, also known as wearable smart devices or smart wearable devices, are a general term for devices that utilize wearable technology to intelligently design and develop everyday wearables, such as glasses, gloves, watches, clothing, and shoes. Wearable devices are portable devices that are worn directly on the body or integrated into the user's clothing or accessories. Wearable devices are not just hardware devices, but also achieve powerful functions through software support, data interaction, and cloud interaction. Broadly speaking, wearable smart devices include those that are feature-rich, large in size, and can achieve complete or partial functions without relying on a smartphone, such as smartwatches or smart glasses, as well as those that focus on a specific application function and can be used in conjunction with other devices such as smartphones, such as various smart bracelets, smart helmets, and smart jewelry for vital sign monitoring.

[0093] The embodiments of this application do not limit the specific technology or device form used in the terminal. It is understood that a terminal can be referred to as a communication device. For example, a terminal can be understood as a device with terminal functions. For example, the device used to implement the terminal functions can be a terminal itself; it can also be a device capable of supporting the terminal in implementing those functions, such as a chip system, hardware circuitry, software modules, or a combination of hardware circuitry and software modules. This device can be installed in the terminal or can be used in conjunction with the terminal. In the embodiments of this application, the chip system can be composed of chips or can include chips and other discrete devices.

[0094] The chip can be a baseband chip, a modem chip, a system-on-chip (SoC) chip, a system-in-a-package (SIP) chip, or a communication module, etc. The chip may include a processor, memory, and a transceiver. The transceiver can be input / output circuitry or a communication interface. The processor can be an integrated processing unit, a microprocessor, or an integrated circuit on the chip.

[0095] (2) Network equipment:

[0096] Network equipment can be devices within a wireless network. For example, network equipment can be a RAN node (or device) that connects terminal devices to the wireless network, and can also be called a base station. Currently, some examples of RAN equipment include: base stations, evolved NodeBs (eNodeBs), gNBs (gNodeBs) in 5G communication systems, transmission reception points (TRPs), evolved Node Bs (eNBs), radio network controllers (RNCs), Node Bs (NBs), home base stations (e.g., home evolved Node Bs, or home Node Bs (HNBs), base band units (BBUs) or wireless fidelity (Wi-Fi) access points (APs), and terminals performing base station functions in D2D communication. Additionally, in a network architecture, network equipment can include central unit (CU) nodes, distributed unit (DU) nodes, or RAN equipment comprising both CU and DU nodes.

[0097] Optionally, RAN nodes can also be macro base stations, micro base stations, indoor stations, relay nodes, donor nodes, or radio controllers in cloud radio access network (CRAN) scenarios. RAN nodes can also be servers, wearable devices, vehicles, or in-vehicle equipment, or mobile devices mounted on vehicles. For example, the access network equipment in vehicle-to-everything (V2X) technology can be a roadside unit (RSU).

[0098] In another possible scenario, multiple RAN nodes collaborate to assist the terminal in achieving wireless access, with different RAN nodes each implementing a portion of the base station's functions. For example, RAN nodes can be CUs, DUs, CUs (control plane, CP), CUs (user plane, UP), or radio units (RUs). CUs and DUs can be configured separately or included in the same network element, such as a baseband unit (BBU). RUs can be included in radio equipment or radio units, such as remote radio units (RRUs), active antenna units (AAUs), radioheads (RHs), or remote radio heads (RRHs).

[0099] In different systems, CU (or CU-CP and CU-UP), DU, or RU may have different names, but those skilled in the art will understand their meaning. For example, in an open access network (open RAN, O-RAN, or ORAN) system, CU can also be called O-CU (open CU), DU can also be called O-DU, CU-CP can also be called O-CU-CP, CU-UP can also be called O-CU-UP, and RU can also be called O-RU. For ease of description, this application uses CU, CU-CP, CU-UP, DU, and RU as examples. Any of the units among CU (or CU-CP, CU-UP), DU, and RU in this application can be implemented through software modules, hardware modules, or a combination of software modules and hardware modules.

[0100] Communication between access network devices and terminal devices follows a specific protocol layer structure. This protocol layer may include a control plane protocol layer and a user plane protocol layer. The control plane protocol layer may include at least one of the following: radio resource control (RRC) layer, packet data convergence protocol (PDCP) layer, radio link control (RLC) layer, media access control (MAC) layer, or physical (PHY) layer, etc. The user plane protocol layer may include at least one of the following: service data adaptation protocol (SDAP) layer, PDCP layer, RLC layer, MAC layer, or physical layer, etc.

[0101] The correspondence between network elements and their achievable protocol layer functions in the ORAN system can be found in Table 1 below.

[0102] Table 1

[0103] Network devices can be other devices that provide wireless communication functions for terminal devices. The embodiments of this application do not limit the specific technology or form of the network device. For ease of description, the embodiments of this application are not limited.

[0104] Network equipment may also include core network equipment, such as the Mobility Management Entity (MME), Home Subscriber Server (HSS), Serving Gateway (S-GW), Policy and Charging Rules Function (PCRF), and Public Data Network Gateway (PDN gateway or P-GW) in 4th generation (4G) networks; and access and mobility management function (AMF), user plane function (UPF), or session management function (SMF) in 5G networks. Furthermore, this core network equipment may also include other core network equipment in 5G networks and next-generation networks of 5G networks.

[0105] In this application embodiment, the device for implementing the function of the network device can be the network device itself, or it can be any device capable of supporting the network device in implementing that function, such as a chip system, hardware circuit, software module, or hardware circuit plus software module. This device can be installed within the network device or can be used in conjunction with a base station. In the technical solutions provided in this application embodiment, the network device is used as an example to illustrate the technical solutions provided in this application embodiment. In this application embodiment, the chip system can be composed of chips, or it can include chips and other discrete components.

[0106] (3) Configuration and Pre-configuration:

[0107] This application uses both configuration and pre-configuration. Configuration refers to the network device / server sending configuration information or parameter values ​​to the terminal via messages or signaling, so that the terminal can determine communication parameters or resources for transmission based on these values ​​or information. Pre-configuration is similar to configuration; it can be parameter information or values ​​pre-negotiated between the network device / server and the terminal device, parameter information or values ​​specified by standard protocols for use by the base station / network device or terminal device, or parameter information or values ​​pre-stored in the base station / server or terminal device. This application does not limit this.

[0108] Furthermore, these values ​​and parameters can be changed or updated.

[0109] (4) Low-density parity check (LDPC) code:

[0110] LDPC codes are a channel coding scheme close to Shannon lines, characterized by high performance and low complexity. They have been adopted by 3GPP as the 5G data channel coding scheme. Currently, the main decoding algorithms for LDPC codes are Min-Sum (MS) and Belief Propagation (BP) decoding algorithms. In terms of decoding performance, BP decoding is better, but it requires a larger information storage capacity (m...). c→v The computational method is complex and not conducive to hardware implementation. Therefore, the Offset-MS and Normalized-MS decoding algorithms are currently used in practical communication systems.

[0111] Both the LDPC encoding and decoding processes are performed based on the parity-check matrix, which is generally generated from the LDPC base matrix. This base matrix can also be called the base graph (BG). A single element (or single position) in the LDPC base matrix can have a value of 0 or 1. A value of 0 represents an empty element, while a value of 1 represents an edge in the base matrix or an association between the corresponding parity check and the corresponding variable. In this application, the column weight of a single column can refer to the number of non-zero elements in that column.

[0112] The LDPC base matrix includes an information column and a parity column. The parity column includes a core parity column and extended parity columns. The information column corresponds to the information bits in the encoded bit sequence, which can also be called information bits or system bits. The parity column corresponds to the parity bits in the encoded bit sequence, which can also be called parity bits. The core parity column consists of the parity columns in the base matrix whose column weight is greater than 1. The extended parity columns are the other parity columns in the base matrix besides the core parity column.

[0113] Figure 1 schematically illustrates the matrix structure of the LDPC basis matrix. As shown in Figure 1, the LDPC basis matrix includes regions A, B, C, D, and E. Regions A through E can be referred to as submatrices A through E, respectively. As shown in Figure 1, this basis matrix is ​​an X-row, Y-column matrix, where X and Y are positive integers. Submatrice A corresponds to the 1st to y1st columns of this basis matrix, and also corresponds to the 1st to x1st rows of matrix 0, where y1 is a positive integer greater than 1 and less than Y, and x1 is a positive integer greater than 1 and less than X. Submatrice B corresponds to the y1+1th to y2th columns of matrix 0, and also corresponds to the 1st to x1st rows of matrix 0, where y2 is a positive integer greater than y1 and less than Y. Submatrice C corresponds to the y2+1th to Yth columns of matrix 0, and also corresponds to the 1st to x1st rows of matrix 0. Submatrix D corresponds to columns 1 through y2 of matrix 0, and also to rows x1+1 through X of matrix 0. Submatrix E corresponds to columns y2+1 through Y of matrix 0, and also to rows x1+1 through X of matrix 0. For example, x1 = 4, y1 = 10 or 22, y2 - y1 = 4.

[0114] The columns corresponding to submatrix A (i.e., columns 1 to y1) can be information columns, and the columns corresponding to submatrix B and submatrix C (i.e., columns y1+1 to Y) can be check columns. The columns corresponding to submatrix B (i.e., columns y1+1 to y2) can be core check columns, and the columns corresponding to submatrix C (i.e., columns y2+1 to Y) can be extended check columns. Optionally, the column weight of any column in submatrix B is greater than 1, and the column weight of any column in submatrix C is 0. Alternatively, submatrix B can be a non-lower triangular matrix, meaning that the values ​​above the diagonal of the matrix are not all 0.

[0115] Figure 2 schematically illustrates another possible structure of the LDPC basis matrix. As shown in Figure 2, this basis matrix can include a high-rate region, an all-zero region, an incremental redundancy region, and a raptor-like region. The high-rate region is the highest-rate matrix of the basis matrix, and can include submatrices A and B as shown in Figure 1. The all-zero region can be a zero matrix, where every element is 0; it can be submatric C as shown in Figure 1. The incremental redundancy region can be a low-rate matrix, and can be submatric D as shown in Figure 1. The raptor-like region can be an identity matrix, and can be submatric E as shown in Figure 1.

[0116] In the 5G data channel coding scheme, 3GPP defines two types of basis matrices, called BG1 and BG2, respectively. BG1 and BG2 have a common matrix structure as shown in Figure 1 or Figure 2.

[0117] In Figure 1, the columns within the dashed rectangles represent punctured columns in the basis matrix. In terms of matrix characteristics, punctured columns have a relatively large column weight. In terms of transmission characteristics, the bits corresponding to the punctured columns in the encoded bit sequence are not transmitted; consequently, the receiver does not need to receive this part of the information. Therefore, the bits corresponding to the punctured bits in the bit sequence to be decoded (such as the log-likelihood ratio) can be set to 0. This application does not limit the position and number of punctured columns in the basis matrix. Taking BG1 or BG2 as examples, the first two columns of the basis matrix can be punctured columns.

[0118] It is understandable that the base matrix shown in Figure 1 or Figure 2 is designed for the lowest bitrate. In Figure 2, the black dashed lines represent different bitrate truncation matrix regions. When higher bitrates are required, a portion of the base matrix shown in Figure 1 or Figure 2 can be truncated to generate the parity check matrix. For example, the parity check matrix can be generated based on the high bitrate regions shown in Figure 1 and Figure 2 (i.e., submatrix A and submatrix B). When the bitrate is low, the matrix region used to generate the parity check matrix can be an extended version of the high bitrate region shown in Figure 2. This extended region can include, in addition to the high bitrate region, at least one of the following: an incremental redundancy region, an all-zero region, or a Laputa-like region.

[0119] For example, in 5G peak throughput scenarios (longer code lengths, varying information counts such as 1k-2k or greater than 8k), a parity check matrix can be generated based on the high code rate region of BG1. This high code rate region can include submatrix A (e.g., 22 columns) and submatrix B (e.g., 4 columns) of BG1, with 2 punctured columns. The generated parity check matrix supports a code rate of 22 / (22+4-2) = 11 / 12 ≈ 0.917. Alternatively, the number of punctured columns can be increased to allow the generated parity check matrix to support a code rate slightly higher than 0.917.

[0120] (5) Quasi-cyclic low-density parity check (QC-LDPC):

[0121] QC-LDPC code is a type of LDPC code that has a QC structure. QC-LDPC code avoids bad structures such as short loops and improves code distance by setting the translation amount of each block.

[0122] The QC-LDPC code used in practice is represented by a base matrix BG, where elements are either 0 or 1. The 1s in the base matrix BG are expanded into a cyclic shift matrix, and the 0s are expanded into a zero matrix of the corresponding size. After expansion, the parity check matrix is ​​obtained. The BG graphical model of the QC-LDPC code is BG = (X, Y, F), where X corresponds to the variables, Y corresponds to the parity check equation, and F represents the edge relationships. The expansion factor is Z. c After QC expansion, we obtain the Tanner graph, which is a bipartite graph G = (V, C, E), where V is the variable node, C is the check node, and E is its edge relationship, corresponding to the number of columns of the check matrix N = |V| = Z. c |X|, the number of rows in the parity check matrix M = |C| = Z c The number of non-zero elements in the parity check matrix is ​​|E|=Z|F|.

[0123] BG can also be written in matrix form as H. BG Based on the basis matrix H BG And the lifting value Zc (lifting size) can be used to transform the basis matrix H BG It is expanded into a complete parity-check matrix for encoding or decoding. Zc can also be called the expansion factor, boost factor, expansion value, expansion coefficient, boost size, etc.

[0124] The lifting process involves transforming matrix H BG The elements in the matrix are promoted to a Zc×Zc square matrix, where 0 is promoted to a Zc×Zc matrix of 0s, and 1 is promoted to an identity matrix (circularly shifted P to the right). i,j The matrix, where P i,j This represents the shifting value (SV) corresponding to the i-th row and j-th column. Taking a 4x4 identity matrix as an example, the results of cyclically shifting (or shifting by value) 1, 2, 3, and 0 (to the right) this identity matrix are shown in Figures 3-1 to 3-4, respectively.

[0125] The storage content of translation values ​​in 5G LDPC codes generally includes a lifting size list and a translation value list, with each row of the translation value list corresponding one-to-one with the lifting size list. Figure 4-1 schematically shows the lifting size list in the 3GPP 38.212 protocol, and Figure 4-2 schematically shows the connection and translation value list in the BG1 part of the 3GPP 38.212 protocol. In the list shown in Figure 4-1, the first column represents the set index (denoted as i). LS The second column represents the promotion-size set corresponding to the respective set index. The main characteristic is that the j-th row of the promotion-size list... Where a j ∈{2,3,5,7,9,11,13,15}, max(k j)∈{7,7,6,5,5,5,4,4}; The row index of the lift size corresponds one-to-one with the column index of the shift value. That is, the lift size in each row of the lift size list corresponds to a set of shift values. When performing rate matching, the lift size is determined first, and then the corresponding shift value is selected to construct the check matrix.

[0126] (6) Multi-edge LDPC code is an improved LDPC code. The elements in the basis matrix of the multi-edge LDPC code can be 0, 1 or integers greater than 1. In the process of expanding the elements in the basis matrix of the multi-edge LDPC code to obtain the parity matrix, the elements greater than 1 are expanded to the sum of multiple cyclic shift matrices.

[0127] For ease of description, some terms are defined here. For example, the number of multiple edges in a basis matrix refers to the sum of the number of positions in the basis matrix that have multiple edges. A position has a multiple edge if the element corresponding to that position is greater than 2. Figure 5 schematically illustrates a multi-edge LDPC code. In the basis matrix (BG) shown in Figure 5, there are a total of 5 positions with multiple edges; therefore, the number of multiple edges is 5. The multiplicity of a multiple edge refers to the value of the multiple edge in BG at a given position. In Figure 5, the multiplicity of the multiple edge in the first row and first column is 3, and the multiplicity of the multiple edge in the first row and second column is 2. The maximum multiplicity of a multiple edge refers to the maximum value of the multiple edges at all positions in BG. As shown in Figure 5, the maximum multiplicity of the multiple edges in BG is 3.

[0128] (7) For block parallel decoding architecture, throughput can be calculated as follows: Where N ldpc N is the code length. frame f is the number of packets decoded simultaneously. clk f is the number of clock cycles. clk For the operating frequency, N iteration N represents the number of decoding iterations. Zc C represents the number of QC blocks using the decoding matrix. layer This represents the number of decoding clock cycles per line. As can be seen from the throughput calculation formula, the main factor affecting throughput is N. Zc , which is the number of non-zero numbers in the decoding matrix during one round of decoding iteration.

[0129] The previous article introduced how to calculate throughput in QC-LDPC codes, multi-side LDPC codes, and block parallel decoding architectures. The following section analyzes the performance of QC-LDPC codes and multi-side LDPC codes respectively.

[0130] The decoding threshold and decoding complexity of QC-LDPC codes are determined by the size of the base graph. The design goal of LDPC codes is often to achieve a high decoding threshold, and density evolution theory dictates that column redistribution is the most significant factor affecting the decoding threshold. Therefore, optimizing the degree distribution is a major problem in code construction. The degree distribution refers to the column redistribution of the parity-check matrix. For smaller base graphs, this results in a poor degree distribution in the parity-check matrix generated based on that base graph, corresponding to a higher decoding threshold. At higher code rates, the performance of existing new radio (NR) LDPC codes is severely compromised. For larger base graphs, with poor orthogonality, the parallelism of encoding based on that base graph is low, and hardware implementation is complex.

[0131] Compared to single-sided LDPC codes (such as QC-LDPC codes), multi-sided LDPC codes have a larger degree distribution design space to obtain a better degree distribution, which in turn corresponds to a lower decoding threshold.

[0132] However, multi-sided LDPC codes are difficult to implement due to decoding challenges. In contrast, the parity-check matrix of a single-sided LDPC code is completely orthogonal within each QC unit, thus supporting a block-parallel decoding architecture for parallel reading, computation, and storage, offering advantages such as low latency and high hardware utilization. However, the parity-check matrix of multi-sided LDPC codes is correlated within each QC unit, making parallel reading, computation, or storage impossible, resulting in high latency, low hardware utilization, and uneven hardware utilization.

[0133] To address this issue, this application proposes a multi-stage boosting LDPC code scheme. By introducing a multi-edge-like structure, it solves the problem of limited degree distribution and small design space inherent in single-sided QC-LDPC. Furthermore, maintaining orthogonality during the boosting of the basis matrix to the parity check matrix contributes to the lower hardware decoding complexity of this LDPC code.

[0134] The solution provided in this application will be introduced below in conjunction with application scenarios.

[0135] The method provided in this application can be used in various communication systems. For example, the communication system can be a long-term evolution (LTE) system, a 5th generation (5G) communication system, a wireless fidelity (WiFi) system, a 3rd generation partnership project (3GPP) related communication system, a communication system evolving after 5G, or a system integrating multiple systems, etc. This application does not limit the communication system. 5G can also be referred to as NR, and communication systems evolving after 5G can be called future communication systems. This application can also be applied to three major application scenarios: device-to-device (D2D) communication, vehicle-to-everything (V2X) communication, machine-to-machine (M2M) communication, machine-type communication (MTC), Internet of Things (IoT) communication systems, narrowband Internet of Things (NB-IoT) systems, Global System for Mobile Communications (GSM), Enhanced Data Rate for GSM Evolution (EDGE), Wideband Code Division Multiple Access (WCDMA), Code Division Multiple Access 2000 (CDMA2000), Time Division-Synchronization Code Division Multiple Access (TD-SCDMA), Long Term Evolution (LTE), and next-generation 5G mobile communication systems. These three application scenarios include enhanced mobile broadband (V2D). Broadband (eMBB), ultra-reliable low-latency communication (URLLC), and enhanced machine-type communication (eMTC).

[0136] Figure 6-1 shows a schematic diagram of the communication system. It is understood that Figure 6-1 is merely a schematic diagram and does not constitute a limitation on the applicable scenarios of the technical solutions provided in this application. As shown in Figure 6-1, the communication system 1000 may include a radio access network (RAN) 100. Optionally, the communication system 1000 may also include a core network 200 and an Internet 300. The RAN 100 includes at least one RAN node (as shown in Figure 6-1, 110a and 110b, collectively referred to as 110), and may also include at least one terminal device (as shown in Figure 6-1, 120a-120j, collectively referred to as 120). The RAN 100 may also include other RAN nodes, such as wireless relay devices and / or wireless backhaul devices (not shown in Figure 6-1). The terminal device 120 is wirelessly connected to the RAN node 110, and the RAN node 110 is wirelessly or wiredly connected to the core network 200. The core network equipment in core network 200 and the RAN node 110 in RAN100 can be independent and different physical devices, or they can be the same physical device that integrates the logical functions of the core network equipment and the logical functions of the RAN node.

[0137] As mentioned earlier, RAN nodes and core network equipment can be collectively referred to as network equipment. In the communication system shown in Figure 6-1, terminal equipment can communicate with each other, network equipment can communicate with each other, and network equipment can communicate with terminal equipment via wired or wireless means, respectively.

[0138] As shown in Figure 6-2, taking a network device as a base station as an example, a base station can perform communication-related services with one or more terminal devices, and different terminal devices can also perform communication-related services.

[0139] Figure 6-3 illustrates another communication system. Information generated by the source is transmitted through the channel after source coding, channel coding, and modulation by the transmitting device. The receiving device demodulates the received signal to obtain the sequence to be decoded, such as the Log Likelihood Ratio (LLR) sequence. This sequence then undergoes channel decoding and source recovery to obtain the decoded information, which is then sent to the destination. The scheme provided in this application can be applied to the channel decoding part, modifying the decoding into a universal decoding method that is effective for any coding scheme. Therefore, it is not limited to channel coding.

[0140] The method provided in this application will now be described using the first and second communication devices in a communication system as examples.

[0141] As described above, the first communication device can support LDPC encoding. The first communication device can be a first communication equipment, or it can be a component within the first communication equipment. Similarly, as described above, the second communication device can support LDPC decoding. The second communication device can be a second communication equipment, or it can be a component within the second communication equipment. The first communication equipment can be a transmitting device, and the second communication equipment can be a receiving device; or, the first communication equipment can be a receiving device, and the second communication equipment can be a transmitting device. The implementation of the component is similar to the first aspect described above, and will not be repeated here.

[0142] This application does not limit the types of the first and second communication devices. For example, the first and second communication devices can be different terminal devices in a communication system, or they can be different network devices in a communication system, or they can be a terminal device and a network device in a communication system, or they can be a network device and a terminal device in a communication system, respectively. Optionally, the first and second communication devices transmit data wirelessly.

[0143] This application uses the example of a first communication device performing LDPC encoding using a parity-check matrix. However, the first communication device can also perform LDPC encoding using the generator matrix of the LDPC code, or based on the LDPC base matrix and shift values; this approach is not limited to any particular method. The generator matrix of the LDPC code is a matrix used to transform the bit sequence to be encoded into the encoded bit sequence.

[0144] Figure 7 schematically illustrates the flow of a communication method executed by the first communication device and the second communication device. As shown in Figure 7, the communication method may include steps S701 to S703.

[0145] S701. The first communication device performs LDPC encoding on the bit sequence to be encoded based on the parity check matrix to obtain the encoded bit sequence.

[0146] The bit sequence to be encoded can be the binary sequence obtained by the first communication device converting the data to be transmitted. The bit sequence to be encoded can be a non-all-zero sequence. The bit sequence to be encoded can contain an information bit sequence, which can be a payload information bit sequence, or a bit sequence containing payload information bits and cyclic redundancy check (CRC) bits.

[0147] After obtaining the bit sequence to be encoded, the first communication device can perform LDPC encoding on the bit sequence based on the parity check matrix to obtain the encoded bit sequence. The encoded bit sequence can also be called the encoded codeword.

[0148] This application does not limit the specific method by which the first communication device performs LDPC encoding on the bit sequence to be encoded based on the parity check matrix. In one possible implementation, the first communication device can convert the parity check matrix into a generator matrix, and then use the generator matrix and the bit sequence to be encoded to generate the encoded bit sequence.

[0149] The encoded bit sequence may include information bits, or it may include information bits and redundant bits. The redundant bits may include parity bits, or it may include parity bits and padding bits.

[0150] The check matrix used by the first communication device can be obtained based on a second matrix. The second matrix includes a first set of recurring occurrences, wherein the first set is derived from the first matrix.

[0151] S702, The first communication device sends the encoded bit sequence, and the second communication device receives the bit sequence to be decoded;

[0152] After obtaining the encoded bit sequence, the first communication device can transmit the encoded bit sequence. This application does not limit the method by which the first communication device transmits the encoded bit sequence. Taking a chip in a first communication device as an example, the first communication device can transmit the encoded bit sequence through the chip's I / O ports. Optionally, the first communication device can then transmit the encoded bit sequence through an antenna. Taking a first communication device with an antenna as an example, for instance, if the first communication device is a first communication device, the first communication device can transmit the encoded bit sequence through the antenna.

[0153] After the first communication device sends the encoded bit sequence, the encoded bit sequence is transmitted to the second communication device via the channel. The second communication device can decode the received encoded bit sequence; therefore, this application refers to the encoded bit sequence received by the second communication device as the bit sequence to be decoded.

[0154] Optionally, the channel may include a wireless channel. Since the encoded bit sequence may change in the channel (e.g., due to noise or fading), the encoded bit sequence transmitted by the first communication device and the bit sequence to be decoded received by the second communication device may differ. The bit sequence to be decoded received by the second communication device can be understood as an encoded bit sequence containing noise.

[0155] This application does not limit the method by which the second communication device receives the bit sequence to be decoded. Taking a chip in a second communication device as an example, the second communication device can receive the bit sequence to be decoded through an antenna, and then the second communication device can receive the bit sequence to be decoded through the chip's I / O ports. Taking a second communication device with an antenna as an example, for instance, if the second communication device is a second communication device, the second communication device can receive the bit sequence to be decoded through the antenna.

[0156] S703, the second communication device performs LDPC decoding on the bit sequence to be decoded based on the parity check matrix to obtain the decoded bit sequence.

[0157] In order to ensure that the decoded bit sequence obtained by the second communication device is the same as the bit sequence before encoding by the first communication device (i.e., the bit sequence to be encoded in S701), the encoding method used by the first communication device for the bit sequence to be encoded and the decoding method used by the second communication device for the bit sequence to be decoded can correspond to each other.

[0158] In one possible implementation, the first communication device sends first information to the second communication device, the first information instructing the second communication device on the decoding method of the bit sequence to be decoded, the decoding method corresponding to the encoding method of the bit sequence to be encoded by the first communication device.

[0159] In another possible implementation, the second communication device sends second information to the first communication device, the second information indicating the encoding method of the bit sequence to be encoded by the first communication device, the encoding method corresponding to the decoding method of the bit sequence to be decoded by the second communication device.

[0160] In another possible implementation, the third communication device sends the second information and the first information to the first communication device and the second communication device, respectively. This application does not limit the type of the third communication device; for example, the third communication device may be a third communication equipment or a component of a third communication equipment, and the third communication equipment may be a terminal device or a network device.

[0161] This application does not limit the transmission method of the first and second information. Optionally, the first information may be carried in downlink control information (DCI), sidelink control information (SCI), radio resource control (RRC) messages, or medium access control control element (MAC-CE) messages or signaling. Similarly, optionally, the second information may be carried in DCI, SCI, RRC messages, or MAC-CE messages or signaling.

[0162] The correspondence between the encoding and decoding methods can include the encoding and decoding methods being based on the same type of codeword. For example, both the encoding and decoding methods are based on LDPC codes, or the encoding and decoding methods are respectively LDPC encoding and LDPC decoding. The correspondence between LDPC encoding and LDPC decoding can also include the LDPC encoding and LDPC decoding being based on the same parity-check matrix. For example, the parity-check matrix used by the second communication device to perform LDPC decoding is the same as the parity-check matrix used by the first communication device to perform LDPC encoding. Accordingly, the parity-check matrix used by the second communication device to perform LDPC decoding is determined based on the second matrix described above.

[0163] The parity-check matrix used by the first and second communication devices is determined based on the second matrix, which includes a first set of repeated occurrences from the first matrix. This improves the performance of the LDPC code. The reasons are analyzed below.

[0164] The degree distribution of the parity-check matrix (PCM) is a crucial factor determining the performance of LDPC codes. For example, the performance of LDPC codes includes one or more of the following: error correction capability during encoding and decoding, decoding complexity, convergence speed, and decoding threshold. The degree distribution of the PCM generally includes column redistribution and row redistribution. Column redistribution refers to the distribution of column weights with the number of columns in the PCM, while row redistribution refers to the distribution of row weights with the number of rows. The row weight refers to the number of non-zero elements in that row. For two PCMs with different numbers of columns, the PCM with more columns has more possible column redistributions. More possible column redistributions allow for a larger degree distribution design space, facilitating the optimization of the PCM with a better degree distribution within that larger space, thereby improving the performance of the LDPC code.

[0165] The second matrix includes the first set of repeated occurrences in the first matrix. This is advantageous in obtaining a second matrix with more columns than the first matrix. Therefore, compared to obtaining a parity check matrix based on the first matrix, obtaining a parity check matrix with more columns based on the second matrix is ​​advantageous in obtaining a parity check matrix that supports a larger degree distribution design space, thereby helping to optimize the performance of LDPC codes.

[0166] The sparsity of the parity-check matrix (PCM) means that most of its elements are zero, which is beneficial for improving the performance of LDPC codes, such as increasing their convergence speed and reducing the hardware decoding complexity. Columns with smaller column weights in the PCM can be called orthogonal positions. Increasing the number of orthogonal positions in the PCM improves its orthogonality (i.e., sparsity), thus enhancing the performance of LDPC codes.

[0167] Assuming the first set of the first matrix includes M orthogonal positions, and the second matrix includes the first set of the first matrix that appears N times, then the second matrix includes at least (N+1)×M orthogonal positions, which is beneficial to improving the orthogonality of the parity check matrix obtained based on the second matrix, thereby improving the performance of the LDPC code.

[0168] As described above, the second matrix includes the repeated first set. For ease of description, the repeated first set in the second matrix can be called the fourth set, and it is assumed that the first set repeats N times in the fourth set, where N is a positive integer. Therefore, the second matrix includes the fourth set, which is the first set repeated N times. This application does not limit the number of times the first set repeats in the fourth set; for example, N = 1, 2, 3, or 4, etc.

[0169] The first and fourth sets will be introduced below with reference to the accompanying diagrams.

[0170] Figure 8 schematically illustrates the first set. As shown in Figure 8, the first set includes P columns, where P is a positive integer. These P columns are denoted as column 1-1, column 1-2, ..., column 1-P. For any two columns in the matrix in the accompanying figures of this application, it is assumed that the index of the left column is less than the index of the right column.

[0171] Taking N=1 as an example, Figure 9a schematically illustrates an example of the fourth set in the second matrix. As shown in Figure 9a, the fourth set includes column 1-1, column 1-2, ..., column 1-P, which appears once. Therefore, the first set, which appears once, can be understood as including each column in the first set that appears once.

[0172] Figure 9b schematically illustrates column 1-i in the first set and column 1-i repeated once in the fourth set, where i is a positive integer less than P. As shown in Figure 9b, column 1-i repeated once can be understood as including two copies of column 1-i, or as including column 1-i and a copy of column 1-i, or as being obtained by promoting each element in column 1-i to a corresponding promotion matrix. The promotion matrix corresponding to a single element can be a 1x2 matrix, and the value of each element in the promotion matrix corresponding to a single element is the same as the value of the corresponding element. For example, for an element in column 1-i with a value of 0, the corresponding promotion matrix is ​​a 1x2 matrix, and the value of each element in this matrix is ​​0. For example, for an element in column 1-i with a value of 1, the corresponding promotion matrix is ​​a 1x2 matrix, and the value of each element in this matrix is ​​1.

[0173] Taking N=2 as an example, Figure 10a schematically illustrates another example of the fourth set in the second matrix. As shown in Figure 10a, the fourth set includes column 1-1, which appears twice, column 1-2, ..., which appears twice, and column 1-P, which appears twice. Therefore, the first set that appears twice can be understood as including each column in the first set that appears twice.

[0174] Figure 10b schematically illustrates column 1-i in the first set and column 1-i repeated twice in the fourth set, where i is a positive integer less than P. As shown in Figure 10b, column 1-i repeated twice can be understood as including three copies of column 1-i, or as including column 1-i and two copies of column 1-i, or as being obtained by promoting each element in column 1-i to its corresponding promotion matrix. The promotion matrix corresponding to a single element can be a 1x3 matrix, and the value of each element in the promotion matrix corresponding to a single element is the same as the value of the corresponding element. For example, for an element in column 1-i with a value of 0, the corresponding promotion matrix is ​​a 1x3 matrix, and the value of each element in this matrix is ​​0. For example, for an element in column 1-i with a value of 1, the corresponding promotion matrix is ​​a 1x3 matrix, and the value of each element in this matrix is ​​1.

[0175] Following the analogy from Figures 9a, 9b, 10a, and 10b, the fourth set (i.e., the first set repeated N times) can be understood as including column 1-1, column 1-2, ..., column 1-P repeated N times from the first set. That is, the fourth set includes every column in the first set repeated N times. For any column in the first set, the column repeated N times can be understood as including N+1 copies of that column, or as including that column and N copies of that column, or as being obtained by promoting (or replacing) each element in that column with the corresponding promotion matrix. The fourth set, being the first set repeated N times, can be understood as being obtained by replacing each element in the first set with the corresponding promotion matrix. The promotion matrix corresponding to a single element can be a 1-row, N+1-column matrix, and the value of each element in the promotion matrix corresponding to a single element is the same as the value of the corresponding element.

[0176] As mentioned earlier, the first set is derived from the first matrix. This application does not limit the method of determining the first set from the first matrix. The following example illustrates how the first set is determined.

[0177] In the first way of determining the first set, the first set includes all columns of the first matrix. Optionally, the second matrix can be the fourth set introduced above. Assuming the first matrix is ​​the first set shown in Figure 8, then, taking N=1 as an example, the second matrix can be the fourth set shown in Figure 9a; taking N=2 as an example, the second matrix can be the fourth set shown in Figure 10a.

[0178] Suppose the first set has P columns, and the fourth set is the first set that appears N times. Then, the first matrix has P columns, and the second matrix has (N+1)×P columns. The second matrix has more columns than the first matrix.

[0179] The first matrix can be the LDPC base matrix described above, or a portion of the LDPC base matrix. Optionally, the first matrix includes a portion of the information columns in the LDPC base matrix, or includes all the information columns in the LDPC base matrix, or includes all the information columns in the LDPC base matrix and a portion of the core check columns, or includes all the information columns in the LDPC base matrix and all the core check columns.

[0180] After obtaining the first matrix, the first communication device can replace each element in the first matrix with a corresponding lifting matrix to obtain the second matrix. As mentioned earlier, the lifting matrix corresponding to a single element can be a 1-row, N+1-column matrix, and the value of each element in the lifting matrix corresponding to a single element is the same as the value of the corresponding element. Thus, the number of columns in the second matrix is ​​N+1 times that of the first matrix.

[0181] In the second way of determining the first set, the first set includes a portion of the columns of the first matrix.

[0182] Based on the second determination method of the first set, in the first example of the second matrix, all columns in the first matrix other than the first set are the second set. The second matrix includes not only the first set that appears N times repeatedly from the first matrix, but also the second set that appears once from the first matrix.

[0183] Figure 11 schematically illustrates another example of the first matrix. As shown in Figure 11, the first matrix comprises a first set of P columns and a second set of Q columns, where P and Q are both positive integers. The P columns in the first set are denoted as column 1-1, column 1-2, ..., column 1-P. The Q columns in the second set are denoted as column 2-1, column 2-2, ..., column 2-Q.

[0184] Taking N=1 as an example, Figure 12 schematically illustrates one example of the second matrix. As shown in Figure 12, the second matrix includes a fourth set and a second set. The fourth set can be understood by referring to the relevant content above, and will not be repeated here.

[0185] Suppose the first set has P columns and the second set has Q columns. Then the first matrix has P+Q columns, and the second matrix has (N+1)×P+Q columns. The second matrix has more columns than the first matrix.

[0186] The first matrix can be the LDPC base matrix described above, or a portion of the LDPC base matrix. Optionally, the first matrix includes a portion of the information columns in the LDPC base matrix, or includes all the information columns in the LDPC base matrix, or includes all the information columns and a portion of the core check columns in the LDPC base matrix, or includes all the information columns and all the core check columns in the LDPC base matrix, or includes all the information columns, all the core check columns and a portion of the extended check columns in the LDPC base matrix, or includes all the information columns, all the core check columns and all the extended check columns in the LDPC base matrix.

[0187] Figure 11 uses the columns of the first set as adjacent columns P in the first matrix and the columns of the second set as adjacent columns Q in the first matrix as an example. Furthermore, it takes the second set to the right of the first set, meaning the column indices in the second set are greater than the indices of any column in the first set. This application does not limit the position of the columns in the first set within the first matrix, nor does it limit the position of the columns in the second set within the first matrix.

[0188] The following example, using the first matrix as an example, illustrates how to determine the first and second sets.

[0189] In the first example of the first matrix, all columns in the first matrix are information columns. Correspondingly, columns in the first set and columns in the second set are also information columns.

[0190] Optionally, the second set consists of the punched information columns in the first matrix, and the first set consists of all columns in the first matrix except for the second set. This helps to minimize the increase in the number of punches in the parity check matrix, thereby avoiding a deterioration in LDPC code encoding and decoding performance due to too many punches. At the same time, maintaining some punched structure can improve the decoding threshold of the LDPC code. This application does not limit the method for determining the punched information columns. Optionally, the first communication device can determine the punched information columns in the first matrix according to a protocol. For example, the second set includes the first and second columns of the first matrix.

[0191] In the second example of the first matrix, the first matrix includes an information column and a core verification column. Based on the fact that the first matrix includes an information column and a core verification column, the method for determining the first set and the second set is described below.

[0192] In one implementation, the first set comprises all information columns in the first matrix, and the second set comprises all core check columns in the first matrix. This avoids boosting the core check columns in the first matrix, allowing for more flexible configuration of their encoding structure, simplifying hardware coding, and optimizing the trap sets of the core check columns. The second set includes all core check columns in the first matrix. This preserves the complete structure of the core check columns while preventing an increase in their frequency in the second matrix. This avoids excessive loops and trap sets in the check matrix due to special shift values ​​or connection relationships of the core check columns, thus preventing instability in encoding and decoding performance caused by excessive loops and trap sets in the check matrix.

[0193] In another implementation, the second set includes all the core check columns of the first matrix, and also includes a portion of the information columns in the first matrix. The first set includes all other information columns in the first matrix except for those in the second set. Optionally, the information columns in the second set are the punched information columns in the first matrix. Including punched information columns in the second set helps to minimize the increase in the number of punches in the check matrix, thus avoiding a deterioration in LDPC code encoding and decoding performance due to excessive punches. At the same time, maintaining a partial punched structure can improve the decoding threshold of the LDPC code.

[0194] In another implementation, the first set includes all information columns and a subset of core verification columns in the first matrix, while the second set includes all core verification columns in the first matrix other than those in the first set. Optionally, the core verification columns in the first set are odd-numbered core verification columns with a weight greater than 1. Improving the weight of these odd-numbered core verification columns (greater than 1) helps improve hardware utilization and supports the requirement for fast convergence.

[0195] In another implementation, the second set includes a subset of information columns from the first matrix, and the first set includes all other information columns from the first matrix except those in the second set. Furthermore, the first set also includes a subset of core verification columns from the first matrix, and the second set also includes all other core verification columns from the first matrix except those in the first set. Optionally, the information columns in the second set are punched information columns, and the core verification columns in the first set are odd-numbered core verification columns with a weight greater than 1. Improving the weight of these odd-numbered core verification columns (greater than 1) helps improve hardware utilization and supports the requirement for fast convergence.

[0196] In a third example of the first matrix, the first matrix includes an information column, a core check column, and an extended check column. Based on the fact that the first matrix includes an information column, a core check column, and an extended check column, the method for determining the first set and the second set in the first matrix is ​​described below.

[0197] In one implementation, the first set comprises all information columns in the first matrix, and the second set comprises all core check columns and all extended check columns in the first matrix. This avoids boosting the core check columns in the first matrix, allowing for more flexible configuration of their encoding structure, thus simplifying hardware coding and optimizing the trap sets of the core check columns. The second set includes all core check columns in the first matrix. This helps maintain the complete structure of the core check columns while preventing an increase in their frequency in the second matrix. This avoids excessive loops and trap sets in the check matrix due to special shift values ​​or connection relationships of the core check columns, thereby preventing instability in encoding and decoding performance caused by excessive loops and trap sets in the check matrix.

[0198] In another implementation, the second set includes all core check columns and all extended check columns in the first matrix. The second set also includes a subset of information columns from the first matrix, and the first set includes all other information columns from the first matrix except those in the second set. Optionally, the second set consists of the punched information columns in the first matrix. Including all core check columns in the first matrix helps to preserve the complete structure of the core check columns while avoiding an increase in their frequency in the second matrix. This prevents excessive loops and trap sets in the check matrix due to special translation values ​​or connection relationships of the core check columns, thus avoiding instability in encoding and decoding performance caused by excessive loops and trap sets in the check matrix. Including punched information columns in the second set helps to minimize the increase in the number of punches in the check matrix, thus preventing a deterioration in LDPC code encoding and decoding performance due to excessive punches. Maintaining some punched structure can also improve the decoding threshold of the LDPC code.

[0199] In another implementation, the first set includes all information columns and a subset of core verification columns in the first matrix, while the second set includes all other core verification columns in the first matrix except those in the first set, and all extended verification columns in the first matrix. Optionally, the core verification columns in the first set are odd-numbered core verification columns with a weight greater than 1. Improving the weight of these odd-numbered core verification columns (greater than 1) helps improve hardware utilization and supports the requirement for fast convergence.

[0200] In another implementation, the second set includes a subset of information columns from the first matrix, and the first set includes all other information columns from the first matrix except those in the second set. Furthermore, the first set also includes a subset of core check columns from the first matrix, and the second set includes all other core check columns from the first matrix except those in the first set. Additionally, the second set includes all extended check columns from the first matrix. Optionally, the information columns in the second set are punched information columns, and the core check columns in the first set are odd-numbered core check columns with a weight greater than 1. Improving the weight of these odd-numbered core check columns (greater than 1) helps improve hardware utilization and supports the requirement for fast convergence.

[0201] After obtaining the first matrix, the first communication device can determine the first set and the second set in the first matrix according to the method for determining the first set and the second set, and then perform a promotion operation or a promotion operation and a deletion operation on the first matrix to obtain the second matrix.

[0202] For example, the first communication device determines a first set in the first matrix, replaces each element of the first set with a corresponding lifting matrix to obtain a fourth set, and the fourth set and the second set form a second matrix. As described above, the lifting matrix corresponding to a single element can be a 1-row, N+1-column matrix, and the value of each element in the lifting matrix corresponding to a single element is the same as the value of the corresponding element. Assuming the number of columns in the first set is P and the number of columns in the second set is Q, then the number of columns in the first matrix is ​​P+Q, and the number of columns in the second matrix is ​​(N+1)×P+Q. The number of columns in the second matrix is ​​greater than the number of columns in the first matrix.

[0203] Alternatively, for example, the first communication device replaces each element in the first matrix with a corresponding lifting matrix. The lifted first matrix comprises N+1 copies of the first set and N+1 copies of the second set. Assuming the first set has P columns and the second set has Q columns, then the first matrix has P+Q columns, and the lifted first matrix has (N+1)×(P+Q) columns. Then, the first communication device determines N+1 copies of the second set from the lifted first matrix and deletes N copies of the second set from these N+1 copies, obtaining a second matrix. The deleted first matrix comprises N+1 copies of the first set and 1 copy of the second set, and the second matrix has (N+1)×P+Q columns. Since the first matrix has P+Q columns, the second matrix has more columns than the first matrix.

[0204] Taking BG1 of the first matrix 5G as an example, optionally, the first set can be the region elevation corresponding to columns 1 to 22 of BG1 of 5G, and all rows (or rows 1 to 46, or rows 1 to 22, or rows 1 to 44). The second set can be columns 23 to N2 of BG1 of 5G. Here, N2 can be the largest column number of BG1 of 5G, or 45, 67, or 68. N = 1, 2, or 3, etc.

[0205] Based on the premise that the first set includes a portion of the columns of the first matrix, in a second example of the second matrix, the columns of the first matrix other than the first set include the second and third sets. The second matrix includes the repeated first set and the second set appearing once, but does not include the third set. That is, the first and second sets in the first matrix are used to construct the second matrix, but the third set in the first matrix is ​​not used to construct the second matrix.

[0206] Figure 13 schematically illustrates another example of the first matrix. As shown in Figure 13, the first matrix comprises a first set of P columns, a second set of Q columns, and a third set of R columns, where P, Q, and R are all positive integers. The P columns in the first set are denoted as column 1-1, column 1-2, ..., column 1-P. The Q columns in the second set are denoted as column 2-1, column 2-2, ..., column 2-Q. The R columns in the third set are denoted as column 3-1, column 3-2, ..., column 3-R.

[0207] Taking N=1 as an example, the second matrix can be seen in Figure 12. The fourth set can be understood by referring to the relevant content above, and will not be repeated here.

[0208] Suppose the first set has P columns and the second set has Q columns. Then the first matrix has P + Q + R columns, and the second matrix has (N + 1) × P + Q columns. Optionally, N × P is greater than R, and correspondingly, the second matrix has more columns than the first matrix. Optionally, P is greater than R.

[0209] The first matrix can be the LDPC base matrix described above, or a portion of the LDPC base matrix. Optionally, the first matrix includes a portion of the information columns in the LDPC base matrix, or includes all the information columns in the LDPC base matrix, or includes all the information columns and a portion of the core check columns in the LDPC base matrix, or includes all the information columns and all the core check columns in the LDPC base matrix, or includes all the information columns, all the core check columns and a portion of the extended check columns in the LDPC base matrix, or includes all the information columns, all the core check columns and all the extended check columns in the LDPC base matrix.

[0210] Figure 13 uses the following example: columns from the first set are adjacent columns P in the first matrix; columns from the second set are adjacent columns Q in the first matrix; and columns from the third set are adjacent columns R in the first matrix. Furthermore, the second set is located to the right of the first set (meaning the column indices in the second set are greater than any column indices in the first set), and the third set is located to the left of the first set (meaning the column indices in the third set are less than any column indices in the first set). This application does not limit the positions of the columns from the first set, the second set, or the third set in the first matrix. The following example, using the first matrix as a case study, illustrates how the first, second, and third sets are determined.

[0211] In the first example of the first matrix, all columns in the first matrix are information columns. Correspondingly, the columns in the first set, the second set, and the third set are all information columns. Based on the fact that all columns in the first matrix are information columns, the method for determining the first set, the second set, and the third set is described below.

[0212] Optionally, the second set consists of punched columns in the first matrix, and the third set consists of columns with high column weights in the first matrix. The first set includes all other columns in the first matrix except for the second and third sets. This helps to minimize the increase in the number of punches in the parity check matrix, thus preventing a deterioration in LDPC code encoding and decoding performance due to excessive punches. Maintaining some punched structure can also improve the decoding threshold of the LDPC code. The inclusion of punched columns in the second set helps to minimize the increase in the number of punches in the parity check matrix, thus preventing a deterioration in LDPC code encoding and decoding performance due to excessive punches. Maintaining some punched structure can also improve the decoding threshold of the LDPC code. Because convergence speed is fast in high-throughput scenarios, high column weights have a significant impact on convergence speed and result in low hardware utilization. Therefore, the third set consists of columns with high column weights. This helps to prevent the second matrix from containing columns with high column weights from appearing in the first matrix, thus reducing the maximum column weight of the second matrix and improving the decoding efficiency of the LDPC code.

[0213] In this application, a column with high column weight can refer to a column whose weight is greater than or equal to the column weight threshold. Columns with high column weight are generally information columns or core verification columns. The column weight threshold can be predefined or preconfigured. Optionally, the column weight threshold is 3.

[0214] In the second example of the first matrix, the first matrix includes an information column and a core verification column. Based on the fact that the first matrix includes an information column and a core verification column, the method for determining the first set, the second set, and the third set is described below.

[0215] Optionally, the third set consists of the punched information columns in the first matrix. Using punched information columns in the third set helps improve the convergence speed of LDPC codes.

[0216] Based on the fact that the third set is the punched information column in the first matrix, optionally, the first set includes all other information columns in the first matrix except for the punched information columns, and the second set includes all core check columns in the first matrix. The second set includes all core check columns in the first matrix. This helps to preserve the complete structure of the core check columns while avoiding an increase in the frequency of core check columns appearing in the second matrix. This prevents the presence of too many loops and trap sets in the check matrix due to special translation values ​​or connection relationships of the core check columns, thus avoiding instability in encoding and decoding performance caused by excessive loops and trap sets in the check matrix.

[0217] Based on the third set being the punched information columns in the first matrix, optionally, the first set includes other information columns in the first matrix besides the punched information columns and a portion of the core verification columns in the first matrix, and the second set includes other core verification columns in the first matrix besides the core verification columns in the first set. Optionally, the core verification columns in the first set are odd-numbered core verification columns with a weight greater than 1. Improving the weight of odd-numbered core verification columns with a weight greater than 1 is beneficial for improving hardware utilization and supporting the requirement of fast convergence.

[0218] Optionally, the third set consists of columns with high column weights in the first matrix. Because convergence is fast in high-throughput scenarios, high column weights have a significant impact on convergence speed and low hardware utilization. Therefore, having the third set consist of columns with high column weights helps to prevent the second matrix from containing columns with high column weights from appearing in the first matrix, thereby reducing the maximum column weight of the second matrix and improving the decoding efficiency of LDPC codes.

[0219] The third set consists of the columns with the largest overlap in the first matrix. Optionally, the first set can consist of all information columns in the first matrix except for the third set, and the second set can consist of all core check columns in the first matrix except for the third set. This helps avoid boosting the core check columns in the first matrix, thus allowing for more flexible configuration of the encoding structure of the core check columns in the first matrix, thereby simplifying hardware coding and optimizing the trap set of the core check columns.

[0220] Based on the fact that the third set consists of the columns with the largest overlap in the first matrix, optionally, the second set includes all core check columns in the first matrix except for the third set. The second set also includes a portion of the information columns in the first matrix, and the first set includes other information columns in the first matrix besides the second and third sets. Optionally, the information columns in the second set are the punched information columns in the first matrix. Including punched information columns in the second set helps to minimize the increase in the number of punches in the check matrix, thereby avoiding a deterioration in LDPC code encoding and decoding performance due to too many punches. At the same time, maintaining some punched structure can improve the decoding threshold of the LDPC code.

[0221] Based on the fact that the third set consists of columns with high column weights in the first matrix, optionally, the first set includes all information columns in the first matrix except for the third set and a portion of the core verification columns in the first matrix, and the second set includes the remaining core verification columns in the first matrix excluding the first and third sets. Optionally, the core verification columns in the first set are core verification columns with an odd number of column weights greater than 1. Improving the core verification columns with an odd number of column weights greater than 1 helps to improve hardware utilization and support the requirement for fast convergence.

[0222] Based on the fact that the third set consists of columns with high column weights in the first matrix, optionally, the second set includes a portion of the information columns in the first matrix, and the first set includes all other information columns in the first matrix besides the second and third sets. Furthermore, the first set also includes a portion of the core verification columns in the first matrix, and the second set also includes all other core verification columns in the first matrix besides the first and third sets. Optionally, the information columns in the second set are punched information columns, and the core verification columns in the first set are core verification columns with an odd number of column weights greater than 1. Improving the core verification columns with an odd number of column weights greater than 1 helps improve hardware utilization and supports the requirement for fast convergence.

[0223] In the third example of the first matrix, the first matrix includes an information column, a core check column, and an extended check column. Based on the fact that the first matrix includes an information column, a core check column, and an extended check column, the method for determining the first set, the second set, and the third set in the first matrix is ​​described below.

[0224] Optionally, the third set consists of the punched information columns in the first matrix. Using punched information columns in the third set helps improve the convergence speed of LDPC codes.

[0225] The third set consists of punched information columns in the first matrix. Optionally, the first set includes all information columns in the first matrix except for the punched information columns. The second set includes all core check columns and all extended check columns in the first matrix. Including all core check columns in the second set helps to preserve the complete structure of the core check columns while avoiding an increase in the frequency of their appearance in the second matrix. This prevents the presence of too many loops and trap sets in the check matrix due to special translation values ​​or connection relationships of the core check columns, thus avoiding instability in encoding and decoding performance caused by excessive loops and trap sets in the check matrix.

[0226] Based on the third set being the punched information columns in the first matrix, optionally, the first set includes all other information columns in the first matrix except for the punched information columns, and a portion of the core check columns in the first matrix. The second set includes all other core check columns in the first matrix except for the core check columns in the first set, and all extended check columns in the first matrix. Optionally, the core check columns in the first set are odd-numbered core check columns with a weight greater than 1. Improving the weight of odd-numbered core check columns with a weight greater than 1 helps improve hardware utilization and supports the requirement for fast convergence.

[0227] Optionally, the third set consists of columns with high column weights in the first matrix. Because convergence is fast in high-throughput scenarios, high column weights have a significant impact on convergence speed and low hardware utilization. Therefore, having the third set consist of columns with high column weights helps to prevent the second matrix from containing columns with high column weights from appearing in the first matrix, thereby reducing the maximum column weight of the second matrix and improving the decoding efficiency of LDPC codes.

[0228] Based on the fact that the third set consists of the columns with the largest overlap in the first matrix, optionally, the first set consists of all information columns in the first matrix excluding the third set, and the second set consists of all core check columns in the first matrix excluding the third set and all extended check columns in the first matrix. This helps avoid boosting the core check columns and extended check columns in the first matrix, thus allowing for more flexible configuration of the encoding structure of the core check columns in the first matrix, thereby simplifying hardware coding and optimizing the trap set of the core check columns.

[0229] Based on the fact that the third set consists of the columns with the largest overlap in the first matrix, optionally, the second set includes all core check columns in the first matrix except for the third set and all extended check columns in the first matrix. The second set also includes a portion of the information columns in the first matrix, and the first set includes the other information columns in the first matrix besides the second and third sets. Optionally, the information columns in the second set are the punched information columns in the first matrix. Including punched information columns in the second set helps to minimize the increase in the number of punches in the check matrix, thereby avoiding a deterioration in LDPC code encoding and decoding performance due to too many punches. At the same time, maintaining some punched structure can improve the decoding threshold of the LDPC code.

[0230] Based on the fact that the third set consists of columns with high column weights in the first matrix, optionally, the first set includes all information columns in the first matrix except for the third set and a portion of the core verification columns in the first matrix. The second set includes the other core verification columns in the first matrix except for the first and third sets and all extended verification columns in the first matrix. Optionally, the core verification columns in the first set are odd-numbered core verification columns with a column weight greater than 1. Improving the weight of odd-numbered core verification columns with a column weight greater than 1 is beneficial for improving hardware utilization and supporting the requirement of fast convergence.

[0231] Based on the fact that the third set consists of columns with high column weights in the first matrix, optionally, the second set includes a portion of the information columns in the first matrix, and the first set includes all other information columns in the first matrix except for the second and third sets. Furthermore, the first set also includes a portion of the core check columns in the first matrix, and the second set includes all other core check columns in the first matrix except for the first and third sets, as well as all extended check columns of the first matrix. Optionally, the information columns in the second set are punched information columns, and the core check columns in the first set are core check columns with an odd number of column weights greater than 1. Improving the core check columns with an odd number of column weights greater than 1 helps improve hardware utilization and supports the requirement for fast convergence.

[0232] After obtaining the first matrix, the first communication device can determine the first set, second set, and third set respectively in the first matrix according to the method for determining the first set, second set, and third set. Then, the first communication device can obtain the second matrix by performing promotion and deletion operations on the first matrix, such that the second matrix includes the second set and the first set that appears N times.

[0233] For example, the first communication device replaces each element of the first matrix with a corresponding lifting matrix. As described above, the lifting matrix corresponding to a single element can be a 1-row, N+1-column matrix, and the value of each element in the lifting matrix corresponding to a single element is the same as the value of the corresponding element. Accordingly, the lifted first matrix includes N+1 copies of the first set, N+1 copies of the second set, and N+1 copies of the third set. Assuming the number of columns in the first set is P, the number of columns in the second set is Q, and the number of columns in the third set is R, then the number of columns in the first matrix is ​​P+Q+R, and the number of columns in the lifted first matrix is ​​(N+1)×(P+Q+R). Then, the first communication device determines N+1 copies of the second set and N+1 copies of the third set in the lifted first matrix, and deletes N copies of the second set from the N+1 copies of the second set and N+1 copies of the third set from the N+1 copies of the third set, obtaining the second matrix. The deleted first matrix includes N+1 copies of the first set and 1 copy of the second set, and the number of columns in the second matrix is ​​(N+1)×P+Q. Since the number of columns in the first matrix is ​​P+Q+R, when N×P is greater than R, the number of columns in the second matrix is ​​greater than the number of columns in the first matrix.

[0234] Alternatively, for example, the first communication device deletes the third set from the first matrix. Thus, the deleted first matrix includes the first and second sets, but no longer includes the third set. Then, the first communication device determines the first set from the deleted first matrix and replaces each element in the first set with a corresponding promotion matrix. As described earlier, the promotion matrix corresponding to a single element can be a 1-row, N+1-column matrix, and the value of each element in the promotion matrix corresponding to a single element is the same as the value of the corresponding element. Accordingly, the promoted first matrix includes N+1 copies of the first set and 1 copy of the second set. Assuming the first set has P columns, the second set has Q columns, and the third set has R columns, then the first matrix has P+Q+R columns, and the promoted first matrix has (N+1)×P+Q columns. When N×P is greater than R, the second matrix has more columns than the first matrix.

[0235] Taking BG1 of 5G as an example, optionally, the first set can be columns 3 to N1 of 5G's BG1, the second set can be columns N1+1 to 68 of 5G's BG1, and the third set can be columns 1 and 2 of 5G's BG1. Here, N1 = 22 or 26. The second matrix can include the first set that appears N times and the second set that appears once. Taking N1 = 26 and N = 1 as an example, the second matrix can include columns 3 to 26, columns 3 to 26, and columns 27 to 68 of 5G's BG1, representing all rows of BG1.

[0236] Based on the premise that the first set includes a portion of the columns of the first matrix, in a third example of the second matrix, all columns of the first matrix other than those in the first set constitute the third set. The second matrix includes repeated occurrences of the first set but excludes the third set. That is, the first set in the first matrix is ​​used to construct the second matrix, while the third set in the first matrix is ​​not used to construct the second matrix.

[0237] Figure 14 schematically illustrates another example of the first matrix. As shown in Figure 14, the first matrix comprises a first set of P columns and a third set of R columns, where P and R are both positive integers. The P columns in the first set are denoted as column 1-1, column 1-2, ..., column 1-P. The R columns in the third set are denoted as column 3-1, column 3-2, ..., column 3-R.

[0238] Taking N=1 as an example, the second matrix can be referenced from the fourth set shown in Figure 9a. The fourth set can be understood by referring to the relevant content above, and will not be repeated here.

[0239] Suppose the first set has P columns and the third set has R columns. Then the first matrix has P+R columns, and the second matrix has (N+1)×P columns. Optionally, N×P is greater than R, and correspondingly, the second matrix has more columns than the first matrix. Optionally, P is greater than R.

[0240] The first matrix can be the LDPC base matrix described above, or a portion of the LDPC base matrix. Optionally, the first matrix includes a portion of the information columns in the LDPC base matrix, or includes all the information columns in the LDPC base matrix, or includes all the information columns and a portion of the core check columns in the LDPC base matrix, or includes all the information columns and all the core check columns in the LDPC base matrix, or includes all the information columns, all the core check columns and a portion of the extended check columns in the LDPC base matrix, or includes all the information columns, all the core check columns and all the extended check columns in the LDPC base matrix.

[0241] Figure 14 uses the example of columns in the first set being adjacent columns P in the first matrix, and columns in the third set being adjacent columns R in the first matrix, with the third set located to the right of the first set (meaning the column indices in the third set are greater than any column indices in the first set). This application does not limit the position of columns in the first set within the first matrix, nor does it limit the position of columns in the second set within the first matrix. The following example, using the first matrix as a case study, illustrates how the first and second sets are determined.

[0242] In the first example of the first matrix, all columns in the first matrix are information columns. Correspondingly, columns in both the first and third sets are information columns. Based on the premise that all columns in the first matrix are information columns, the method for determining the first and third sets is described below.

[0243] Optionally, the third set consists of the punched information columns in the first matrix, and the first set consists of all other information columns in the first matrix except for the punched information columns. Having the punched information columns in the third set helps improve the convergence speed of LDPC codes.

[0244] Optionally, the third set consists of the columns with high column weights in the first matrix, while the first set consists of all columns in the first matrix except for those with high column weights. Because convergence is fast in high-throughput scenarios, high column weights significantly impact convergence speed and reduce hardware utilization. Therefore, using columns with high column weights in the third set helps prevent the second matrix from containing columns with high column weights from appearing in the first matrix, thus reducing the maximum column weight of the second matrix and improving the decoding efficiency of LDPC codes.

[0245] In the second example of the first matrix, the first matrix includes an information column and a core verification column. Based on the fact that the first matrix includes an information column and a core verification column, the method for determining the first set and the third set is described below.

[0246] Optionally, the third set consists of the punched information columns in the first matrix. The first set includes all other information columns in the first matrix except for the punched information columns, as well as all the core check columns of the first matrix. Having punched information columns in the third set helps improve the convergence speed of LDPC codes.

[0247] Optionally, the third set consists of columns with high column weights in the first matrix, and the first set includes all other columns in the first matrix except for the third set. Because convergence is fast in high-throughput scenarios, high column weights have a significant impact on convergence speed and result in low hardware utilization. Therefore, having the third set consist of columns with high column weights helps to prevent the second matrix from containing columns with high column weights from appearing in the first matrix, thereby reducing the maximum column weight of the second matrix and improving the decoding efficiency of LDPC codes.

[0248] After obtaining the first matrix, the first communication device can determine the first set and the third set in the first matrix according to the method for determining the first set and the third set. Then, the first communication device can obtain the second matrix by performing a promotion operation and a deletion operation on the first matrix, such that the second matrix includes the first set that appears N times repeatedly, but does not include the third set.

[0249] For example, the first communication device replaces each element of the first matrix with a corresponding lifting matrix. As described above, the lifting matrix corresponding to a single element can be a 1-row, N+1-column matrix, and the value of each element in the lifting matrix corresponding to a single element is the same as the value of the corresponding element. Accordingly, the lifted first matrix includes N+1 copies of the first set, N+1 copies of the second set, and N+1 copies of the third set. Assuming the number of columns in the first set is P and the number of columns in the third set is R, then the number of columns in the first matrix is ​​P+R, and the number of columns in the lifted first matrix is ​​(N+1)×(P+R). Then, the first communication device determines N+1 copies of the third set in the lifted first matrix and deletes N+1 copies of the third set from the N+1 copies of the third set to obtain the second matrix. The deleted first matrix includes N+1 copies of the first set, and the number of columns in the second matrix is ​​(N+1)×P. Since the number of columns in the first matrix is ​​P+R, when N×P is greater than R, the number of columns in the second matrix is ​​greater than the number of columns in the first matrix.

[0250] Alternatively, for example, the first communication device deletes the third set from the first matrix. Thus, the deleted first matrix includes the first set but no longer includes the third set. Then, the first communication device replaces each element in the deleted first matrix with a corresponding promotion matrix. As described above, the promotion matrix corresponding to a single element can be a 1-row, N+1-column matrix, and the value of each element in the promotion matrix corresponding to a single element is the same as the value of the corresponding element. Accordingly, the promoted first matrix includes N+1 copies of the first set but does not include the second set.

[0251] Optionally, for any two columns in the first set, the order of their indices in the second matrix is ​​the same as the order of their indices in the first matrix. For example, for columns 1-1 and 1-2 in the first set, the indices of column 1-1 are less than those of column 1-2 in the first matrix shown in Figure 8, and the indices of column 1-1 are still less than those of column 1-2 in the second matrix shown in Figure 9a or Figure 10a.

[0252] Optionally, for any two columns in the second set, the order of their indices in the second matrix is ​​the same as the order of their indices in the first matrix. For example, for columns 2-1 and 2-2 in the second set, in the first matrix shown in Figure 11, the indices of column 2-1 are less than those of column 2-2, and in the second matrix shown in Figure 12, the indices of column 2-1 are still less than those of column 2-2.

[0253] Optionally, each column in the second matrix is ​​derived from the first matrix, and the order of any two columns in the first matrix is ​​the same as the order of those two columns in the second matrix.

[0254] In one possible implementation, the first communication device can determine the translation values ​​corresponding to non-zero elements in the second matrix based on the translation values ​​corresponding to the non-zero elements in the first matrix. For example, the first communication device can store or retrieve the translation values ​​corresponding to each non-zero element in the first matrix. For instance, the first matrix can be the basis matrix described above, and the first communication device can determine the translation values ​​corresponding to each non-zero element in the basis matrix using the lists shown in Figure 4-1 and Figure 4-2. The first communication device can then determine the translation values ​​corresponding to the non-zero elements in the second matrix based on the translation values ​​corresponding to the non-zero elements in the first matrix.

[0255] Optionally, the translation value of the non-zero element in the second set in the second matrix is ​​the same as its translation value in the first matrix. Taking any column (denoted as column j) in the second set of the first matrix as an example, the second matrix includes one column j. For ease of description, this application refers to column j in the second matrix as column j'. For any non-zero element in column j, it appears not only in column j of the first matrix but also in column j' of the second matrix. The translation value of the non-zero element in column j (assuming it is located in the m-th row) in the first matrix can be understood as the translation value of the non-zero element in the m-th row of column j in the first matrix. The translation value of the non-zero element in column j (assuming it is located in the m-th row) in the second matrix can be understood as the translation value of the non-zero element in the m-th row of column j' of the second matrix.

[0256] Optionally, the translation value of a non-zero element in the first set in the second matrix is ​​determined by its corresponding translation value in the first matrix. Taking any column (denoted as column j) in the second set of the first matrix as an example, the second matrix includes N+1 columns j. For ease of description, this application refers to column j in the second matrix as column j'. For any non-zero element in column j, it not only appears in column j of the first matrix, but also appears repeatedly in the N+1 columns j' of the second matrix. The translation value of a non-zero element in column j (assuming it is located in the m-th row) in the first matrix can be understood as the translation value corresponding to the non-zero element in the m-th row of column j in the first matrix. The translation value of a non-zero element in column j (assuming it is located in the m-th row) in the second matrix can be understood as the translation values ​​corresponding to the non-zero elements (i.e., the N+1 non-zero elements) in the m-th row of the N+1 columns j' of the second matrix.

[0257] For ease of description, the non-zero element in the m-th row of column j of the first matrix is ​​called element 0, and the non-zero elements in the m-th row of the 1st column j', the 2nd column j', ..., the N+1th column j' are called element 1, element 2, ..., element N+1, respectively. This application does not limit the order of the N+1 columns j'; for example, the N+1 columns j' can be arranged from left to right, or in ascending order of column number.

[0258] In one possible implementation, the translation value corresponding to element 1 is the same as the translation value corresponding to element 0. The translation values ​​corresponding to elements 2 through N+1 can be determined or derived from the translation value corresponding to element 0. Correspondingly, the translation values ​​corresponding to elements 2 through N+1 can be different from the translation value corresponding to element 0. For example, the translation values ​​corresponding to elements 2 through N+1 can be derived from Zc and / or a predetermined rule. The predetermined rule can be adding a predetermined value and / or multiplying by a fixed constant based on the translation value corresponding to element 0 or element 1. In this way, by storing the translation values ​​of each non-zero element (or non-zero position) in the first matrix based on the protocol, the first communication device can determine the translation values ​​of each non-zero element in the second matrix without having to store the translation values ​​of each non-zero element in the second matrix separately, thus saving the storage resources of the first communication device.

[0259] In one possible implementation, the translation value corresponding to element p+1 is derived or determined from the translation value corresponding to element p, where p is a positive integer greater than or equal to 1 and less than N+1, and the translation value corresponding to element 1 can be the translation value corresponding to element 0.

[0260] In one possible implementation, the shift values ​​of the non-zero elements in the first matrix and the shift values ​​of the non-zero elements in the second matrix are determined by the row and column sequence.

[0261] The first communication device can store one or more sequences corresponding to a first matrix, where each sequence corresponds to a row and / or column of the first matrix, i.e., each row / column in the first matrix corresponds to an element in the sequence. In one possible implementation, one sequence simultaneously corresponds to both a row and a column of the first matrix. In another possible implementation, sequence 1 is a row sequence with the number of elements equal to the number of rows, and sequence 2 is a column sequence with the number of elements equal to the number of columns. A possible correspondence is sequential, where the i-th row / i-th column corresponds to the i-th element of sequence 1 / sequence 2. In yet another possible implementation, multiple sequences correspond to matrix rows and columns, such as multiple sequences corresponding to rows and multiple sequences corresponding to columns. Hereinafter, this stored sequence will be referred to as a row-column sequence, and the default correspondence is that each row and column corresponds to a sequence, and this is a sequential correspondence.

[0262] The row and column sequences are used to establish the relationship between the base matrix and the translation values. Specifically, each non-zero position in the base matrix corresponds to a row number i and a column number j. The row number i corresponds to an element R(i) in the row sequence R, and the column number j corresponds to an element C(j) in the column sequence. This corresponds to the calculation of the translation value. The elements involved in the calculation include R(i), C(j), the lift size, and the relevant parameters corresponding to the lift size. Finally, the translation value corresponding to the non-zero position in the i-th row and j-th column of the base matrix is ​​obtained.

[0263] The shift values ​​of the non-zero elements in the second matrix can be determined based on the column sequence elements, the lift size, and the relevant parameters corresponding to the lift size. The column sequence elements corresponding to the non-zero elements in the second matrix can be determined by the row and column sequences of the first matrix. Assuming column j of the first matrix corresponds to column k of the second matrix, the column sequence elements corresponding to column k of the second matrix can be derived from the column sequence elements C(j) of the first matrix. For example, the values ​​of these column sequence elements corresponding to these k columns of the second matrix can be the inverse of C(j), the l-th power of the inverse of C(j), or C(j) to the power of l, etc.

[0264] Figures 15a to 15i illustrate the performance of LDPC codes at different code rates (CR). In Figures 15a to 15i, the horizontal axis represents decoding complexity, and the vertical axis represents the signal-to-noise ratio (SNR) at which the block error rate (BLER) reaches 1e-2. The curve marked with an asterisk (*) (referred to as curve 1) represents the performance of the LDPC code (referred to as LDPC code 1) in this application, while the curve marked with a circle represents the performance of the LDPC code (referred to as LDPC code 2) in the existing protocol. The parity-check matrix used in LDPC code 1 is obtained based on the method shown in Figure 8, while the parity-check matrix used in LDPC code 2 is obtained by improving NR BG1 according to the existing protocol. In any of Figures 15a to 15i, curve 1 shows a performance gain in sizing complexity compared to curve 2 when the number of iterations (i.e., decoding complexity) is lower. In other words, with lower decoding complexity, for the same BLER, the signal-to-noise ratio (SNR) of the LDPC code in this application is lower than that of the LDPC code in existing protocols. That is, compared to the LDPC code in existing protocols, the LDPC code in this application can reduce the SNR while maintaining lower decoding complexity, thus exhibiting a superior decoding threshold. Therefore, performing multi-stage improvements on BG1 according to the scheme in this application can improve convergence speed and provide performance advantages in high-throughput scenarios.

[0265] The preceding text describes the communication apparatus provided in the third aspect of this application. As can be understood from the communication apparatus described in the third aspect, the communication apparatus may include a first processing unit, and optionally, the communication apparatus may further include at least one of a second processing module, a third processing module, or a transceiver unit. Optionally, the communication apparatus may be the first communication apparatus described above, and the steps performed by each functional module in the communication apparatus can be understood by referring to the steps performed by the first communication apparatus described above to achieve the corresponding functions.

[0266] The preceding text describes the communication apparatus provided in the fourth aspect of this application. As can be understood from the communication apparatus described in the fourth aspect, the communication apparatus may include a first processing unit, and optionally, the communication apparatus may further include at least one of a second processing module, a third processing module, or a transceiver unit. Optionally, the communication apparatus may be the second communication apparatus described above, and the steps performed by each functional module in the communication apparatus can be understood by referring to the steps performed by the second communication apparatus described above to achieve the corresponding functions.

[0267] The preceding text also describes a communication apparatus provided in the fifth aspect of this application. This communication apparatus includes at least one processor for executing a computer program stored in a memory, such that the processor performs the steps or processes as described in the examples above for the first or second communication apparatus.

[0268] The preceding text also describes a chip (or chip device or chip system) provided in the sixth aspect of this application. This chip includes a processor for calling computer programs or instructions stored in memory, causing the processor to execute the steps or processes performed by the first or second communication device in the preceding examples. Optionally, the processor is coupled to the memory via an interface.

[0269] In this application, the processor or chip mentioned anywhere may be a general-purpose central processing unit, a microprocessor, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or one or more integrated circuits for controlling the execution of a program that controls the methods provided in any of the above embodiments. The memory mentioned anywhere above may be read-only memory (ROM) or other types of static storage devices capable of storing static information and instructions, such as random access memory (RAM).

[0270] The preceding text also describes a communication device provided in the seventh aspect of this application, which includes at least one logic circuit and an input / output interface. The logic circuit is used to implement the steps or processes performed by the first or second communication device in the preceding examples.

[0271] The preceding text also describes a computer-readable storage medium provided in the eighth aspect of this application, which includes computer instructions that, when executed on a computer, cause the computer to perform the steps or processes performed by the first or second communication device in the preceding examples.

[0272] The preceding text also describes a computer program product including computer instructions provided in the ninth aspect of this application, which, when run on a computer, causes the computer to perform steps or processes as performed by the first or second communication device in the preceding example.

[0273] The preceding text also describes a communication system provided in the tenth aspect of this application, which includes all or part of the devices in the communication system shown in FIG6-1, or includes a first communication device and a second communication device in the example shown in FIG7.

[0274] In this application, the processing unit can be implemented by at least one processor or processor-related circuitry. Specifically, the processor may include a modem chip, or a SoC chip or SIP chip containing a modem core. The transceiver unit can be implemented by a transceiver or transceiver-related circuitry. The transceiver unit may also be referred to as a communication module or communication interface. The storage module can be implemented by at least one memory.

[0275] Optionally, in this application, when the communication device is a circuit or chip responsible for communication functions, such as a modem chip or a SoC chip or SIP chip containing a modem core, the function of the processing unit can be implemented by a circuit system in the aforementioned chip that includes one or more processors or processing cores. The function of the transceiver unit can be implemented by the interface circuit or data transceiver circuit on the aforementioned chip.

[0276] In this application, when the communication device is a terminal, Figure 16 shows a simplified schematic diagram of the terminal structure. As shown in Figure 16, the terminal includes a processor, a memory, and a transceiver. The memory can store computer program code, and the transceiver includes a transmitter 1631, a receiver 1632, a radio frequency circuit (not shown in the figure), an antenna 1633, and input / output devices (not shown in the figure).

[0277] The processor is primarily used for processing communication protocols and data; controlling the terminal; executing software programs; and processing data from those programs. The memory is primarily used for storing software programs and data. The radio frequency (RF) circuitry is primarily used for converting baseband signals to RF signals and processing RF signals. The antenna is primarily used for transmitting and receiving RF signals in the form of electromagnetic waves. Input / output devices may include touchscreens, displays, or keyboards. These devices are primarily used for receiving user input and outputting data to the user. Some types of terminals may not have input / output devices.

[0278] When data is transmitted, the processor performs baseband processing on the data to be transmitted and outputs a baseband signal to the radio frequency (RF) circuit. The RF circuit then processes the baseband signal and transmits it outwards as electromagnetic waves via an antenna. When data is sent to the terminal, the RF circuit receives the RF signal through the antenna. The RF circuit converts the RF signal back into a baseband signal and outputs it to the processor. The processor converts the baseband signal back into data and processes that data. For ease of explanation, Figure 16 only shows one memory, processor, and transceiver. In actual terminal products, there may be one or more processors and one or more memories. Memory can also be called storage medium or storage device, etc. Memory can be independent of the processor or integrated with it; this embodiment does not limit this.

[0279] In the embodiments of this application, the antenna and radio frequency circuit with transceiver function can be regarded as the transceiver unit of the terminal, and the processor with processing function can be regarded as the processing unit of the terminal.

[0280] As shown in Figure 16, the terminal includes a processor 1610, a memory 1620, and a transceiver 1630. The processor 1610 can also be referred to as a processing unit, processing board, processing unit, or processing device, etc. The transceiver 1630 can also be referred to as a transceiver unit, transceiver, or transceiver device, etc.

[0281] Optionally, the devices in transceiver 1630 used to implement the receiving and / or transmitting functions can be considered as transceiver units. A transceiver may also be referred to as a transceiver module, transceiver circuit, etc.

[0282] Processor 1610 is used to execute the processing actions performed by the first or second communication device in the previous example. Transceiver 1630 is used to execute the transmission and reception actions performed by the first or second communication device in the previous example. It should be understood that FIG16 is merely an example and not a limitation, and the terminal including the transceiver unit and the processing unit described above may not depend on the structure shown in FIG16.

[0283] When the communication device 1600 is a chip, the chip includes a processor, a memory, and a transceiver. The transceiver can be an input / output circuit or a communication interface. The processor can be a processing unit integrated on the chip, a microprocessor, or an integrated circuit. In the above method embodiments, the terminal's sending operation can be understood as the chip's output, and the terminal's receiving operation in the above method embodiments can be understood as the chip's input.

[0284] In this application, when the communication device is a RAN node, such as a gNB or a base station, Figure 17 shows a simplified schematic diagram of a base station structure. The base station includes parts 1710, 1720, and 1730.

[0285] The 1710 section is mainly used for baseband processing and controlling the base station; the 1710 section is usually the control center of the base station, which can be called the processor, and is used to control the base station to perform the processing operations of the communication device in the above method embodiment.

[0286] Part 1720 is primarily used to store computer program code and data.

[0287] Section 1730 is primarily used for transmitting and receiving radio frequency (RF) signals, as well as converting RF signals to baseband signals. Section 1730 is commonly referred to as a transceiver unit, transceiver module, transceiver, transceiver circuit, or transceiver. The transceiver module of section 1730, also known as a transceiver, includes antenna 1733 and RF circuitry (not shown in the figure), where the RF circuitry is mainly used for RF processing. Optionally, the device in section 1730 used for receiving can be considered a receiver, and the device used for transmitting can be considered a transmitter; that is, section 1730 includes receiver 1732 and transmitter 1731. The receiver can also be called a receiving unit, receiver circuit, or receiving unit, and the transmitter can be called a transmitting module, transmitter, or transmitting circuit.

[0288] Sections 1710 and 1720 may include one or more circuit boards, each of which may include one or more processors and one or more memories. The processors are used to read and execute programs from the memories to implement baseband processing functions and control the base station. If multiple circuit boards exist, they can be interconnected to enhance processing capabilities. As an alternative implementation, multiple circuit boards may share one or more processors, multiple circuit boards may share one or more memories, or multiple circuit boards may simultaneously share one or more processors.

[0289] For example, in one implementation, the transceiver module in section 1730 is used to perform the transceiver actions performed by the first or second communication device in the previous example. The processor in section 1710 is used to perform processing-related actions performed by the first or second communication device in the previous example.

[0290] It should be understood that Figure 17 is merely an example and not a limitation, and the network devices described above, including processors, memory, and transceivers, may not depend on the structure shown in Figure 17.

[0291] When the communication device 1700 is a chip, the chip includes a transceiver, a memory, and a processor. The transceiver can be an input / output circuit or a communication interface; the processor can be a processor integrated on the chip, a microprocessor, or an integrated circuit. In the above method embodiments, the transmitting operation of the RAN node can be understood as the chip's output, and the receiving operation of the RAN node in the above method embodiments can be understood as the chip's input.

[0292] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the explanations and beneficial effects of the relevant contents in any of the above-mentioned devices can be referred to the corresponding method embodiments provided above, and will not be repeated here.

[0293] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, or indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0294] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0295] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0296] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the essential contribution of the technical solution of this application, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, ROM, RAM, magnetic disks, or optical disks.

[0297] In this application, unless otherwise specified, the same or similar parts between the various embodiments can be referred to each other. In the various embodiments of this application, and the various methods / designs / implementations within each embodiment, unless otherwise specified or logically conflicting, the terminology and / or descriptions between different embodiments and between the various methods / designs / implementations within each embodiment are consistent and can be mutually referenced. The technical features in different embodiments and the various methods / designs / implementations within each embodiment can be combined to form new embodiments, methods, or implementations based on their inherent logical relationships. The following descriptions of the embodiments of this application do not constitute a limitation on the scope of protection of this application.

[0298] In this application embodiment, "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, "at least one of A, B, and C" includes A, B, C, AB, AC, BC, or ABC. Furthermore, unless otherwise specified, the ordinal numbers such as "first" and "second" mentioned in this application embodiment are used to distinguish multiple objects and are not used to limit the order, sequence, priority, or importance of multiple objects.

[0299] In the embodiments of this application, "send" and "receive" refer to the direction of signal transmission. For example, "send information to XX" can be understood as the destination of the information being XX, which may include direct transmission via the air interface or indirect transmission by other units or modules via the air interface. "Receive information from YY" can be understood as the source of the information being YY, which may include direct reception from YY via the air interface or indirect reception from YY by other units or modules via the air interface. "Send" can also be understood as the "output" of the chip interface, and "receive" can also be understood as the "input" of the chip interface. In other words, sending and receiving can occur between devices, such as between network devices and terminal devices, or within a device, such as between components, modules, chips, software modules, or hardware modules within the device via a bus, wiring, or interface. It is understood that information may undergo necessary processing, such as encoding and modulation, between the source and destination of the information transmission, but the destination can understand the valid information from the source. Similar expressions in this application can be understood in a similar way and will not be elaborated further.

[0300] In the embodiments of this application, "instruction" can include direct and indirect instructions, as well as explicit and implicit instructions. The information indicated by a certain piece of information (hereinafter referred to as instruction information) is called the information to be instructed. In specific implementation, there are many ways to indicate the information to be instructed, such as, but not limited to, directly indicating the information to be instructed, such as the information to be instructed itself or its index. It can also indirectly indicate the information to be instructed by indicating other information, where there is an association between the other information and the information to be instructed; or it can only indicate a part of the information to be instructed, while the other parts are known or pre-agreed upon. For example, the instruction can be implemented by using a pre-agreed (e.g., protocol predefined or pre-configured) arrangement of various information, thereby reducing the instruction overhead to a certain extent. This application does not limit the specific method of instruction. It is understood that for the sender of the instruction information, the instruction information can be used to indicate the information to be instructed; for the receiver of the instruction information, the instruction information can be used to determine the information to be instructed.

[0301] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art can understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A communication method, characterized in that, include: Obtain a second matrix, which includes a first set of repeated occurrences, the first set being derived from the first matrix; Wherein, the first set is all or part of the information columns in the first matrix; or, the first set is all or part of the information columns in the first matrix and one or more core verification columns in the first matrix; The second matrix is ​​used to determine the parity check matrix, which is used to perform low-density parity check (LDPC) encoding on the bit sequence to be encoded.

2. A communication method, characterized in that, include: Obtain a second matrix, which includes a first set of repeated occurrences, the first set being derived from the first matrix; Wherein, the first set is all or part of the information columns in the first matrix; or, the first set is all or part of the information columns in the first matrix and one or more core verification columns in the first matrix; The second matrix is ​​used to determine the parity check matrix, which is used to perform low-density parity check (LDPC) decoding on the bit sequence to be decoded.

3. The method according to claim 1 or 2, characterized in that, The first set comprises all or a portion of the information columns in the first matrix and one or more core verification columns in the first matrix, specifically including: In the first set, the column weights of the core verification columns are odd numbers greater than 1.

4. The method according to any one of claims 1-3, characterized in that, The second matrix also includes a second set that appears once, which is derived from the first matrix; The second set is the verification column in the first matrix, and / or the second set is the punched information column in the first matrix.

5. The method according to any one of claims 1-4, characterized in that, The first matrix also includes a third set, which does not appear in the second matrix; The third set is either the punched information column in the first matrix, or the column in the first matrix whose column weight is greater than the column weight threshold.

6. The method according to any one of claims 1-5, characterized in that, The second matrix used to determine the check matrix specifically includes: The verification matrix is ​​determined based on the second matrix and the translation values ​​corresponding to the non-zero elements in the second matrix; wherein, the translation values ​​corresponding to the non-zero elements in the second matrix are determined based on the translation values ​​corresponding to the non-zero elements in the first matrix.

7. The method according to claim 6, characterized in that, The translation value of the non-zero element in the first set in the second matrix is ​​determined by the translation value of the element in the first matrix.

8. The method according to claim 7, characterized in that, The translation value corresponding to the non-zero element in the first set in the second matrix is ​​determined by its corresponding translation value in the first matrix, specifically including: The translation value of the non-zero element in the first set corresponding to the element in the second matrix is ​​determined by adding the translation value of the element in the first matrix to the first value; and / or, The translation value corresponding to the non-zero element in the first set in the second matrix is ​​determined by multiplying its corresponding translation value in the first matrix by a second value.

9. A communication device, characterized in that, It includes at least one processor for executing computer programs or instructions to cause the method as described in any one of claims 1 to 8 to be implemented.

10. The apparatus as claimed in claim 9, characterized in that, The device further includes a memory that stores the computer program or instructions.

11. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program or instructions, which, when executed, implement the method as described in any one of claims 1 to 8.

12. A computer program product, characterized in that, It includes a computer program or instructions, which, when executed, implement the method as described in any one of claims 1 to 8.

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