Thin film transistor and method of manufacturing the same

Abstract

The present disclosure relates to transistors comprising a substrate (10) and a low dimensional material (20). A source electrode (55a) and drain electrode (55b) are arranged on the material. A channel is defined by the carbon-based material in a region extending between the source electrode and the drain electrode. The transistor comprises a gate structure arranged on the material in an area of the channel. The gate structure comprises a gate dielectric (25g) arranged on the material and extending from the source electrode to the drain electrode. The gate structure also comprises a gate electrode (30g) arranged on the gate dielectric and a spacer dielectric arranged also on the gate dielectric. The spacer dielectric (40g) is arranged in a first space between the gate electrode and the source electrode and in a second space between the gate electrode and the drain electrode. The present disclosure also relates to a method for manufacturing such a transistor.

Description

IDEADED S.L. DECEMBER 23, 2025 P008WO P5580PC00THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME

[0001] The present application claims the benefit of European patent application n° EP24383462.9 filed on December 24, 2024. The present disclosure relates to thin film transistors. In particular, the present disclosure relates to thin film transistors comprising low dimensional materials. The present disclosure also relates to the manufacture of thin film transistors using a self-alignment method.BACKGROUND

[0002] A field effect transistor (FET) comprises three main terminals: source, drain and gate. A fourth terminal is associated with the body or substrate but is commonly connected to the source, so that the FET is controlled as a three-terminal device. Current can flow from the source to the drain via a channel created in an active, e.g., semiconducting, material, the conductivity of which is controlled by the voltage applied to the gate.

[0003] Both source and drain are commonly arranged on a two-dimensional plane and formed on a surface of a substrate, thus providing a so-called planar transistor. The length of the channel is defined by the distance between the source and the drain. In order to modulate the conductivity of the channel, voltage is applied to a gate electrode, which is arranged in an area between the source and the drain, and which is separated from the active material forming the channel by means of a gate dielectric. Upon application of the voltage to the gate electrode, current can flow between the source and the drain.

[0004] Transistors have scaled down drastically over the last decades as predicted by Moore’s law. Transistor channel length has gone from a few micrometres to just a few nanometres. This downscaling has allowed increased integration of transistors in a single chip and has improved the performance of the manufactured devices.

[0005] The manufacturing processes involved in such miniaturization are complex and require sophisticated techniques such as extreme ultraviolet (EUV) lithography. In particular, the alignment of the different parts of the transistor, i.e. gate, source, drain, and channel, is extremely challenging. The use of such complex techniques results in more expensivelithographic machines to accomplish the high degree of accuracy for the required fine alignment. Specifically, limits can be reached in the resolution available in existing optical lithographic techniques.

[0006] Furthermore, conventional manufacturing processes for thin film transistors with low dimensional materials involve lift-off steps, which have some associated challenges, e.g. poor adhesion of the resist layer to the substrate leading to incomplete lift-off, incomplete lift-off resulting in residual material remaining in the substrate, redeposition of lifted material, limited profile definition, tearing of thin films during the lift-off process, or non-uniform deposition of the resist layers. Overall, the lift-off steps involve high complexity, which requires very precise control of multiple steps. Small deviations can lead to significant defects on the manufactured transistors.

[0007] Conventional transistors use silicon, Si, as the active material, i.e. as the material defining the channel of the transistor. Nevertheless, other materials are being evaluated as an alternative for the active material of transistors due to the limitations of silicon. Indeed, the electron mobility in bulk materials like Si drops significantly as we move into the nanoscale, so a shift to different materials seems necessary to continue with the downscaling. Hence, low dimensional materials have been proposed as candidates to replace Si for the channel in field effect transistors.

[0008] Low dimensional materials exhibit physical properties that lie somewhere between those of individual atoms and those of bulk, i.e. macroscopic, materials. The low dimensionality results in unique electronic properties, which are especially adequate for the design and manufacture of field effect transistors. In particular, carbon nanotubes (CNTs) can be employed in field effect transistors, in which they can be configured to act as the transistor channel.

[0009] The use of novel materials comes with its own challenges, which relate particularly to the delicate structure and nanoscale dimensions of such novel materials. Specifically, some manufacturing steps may comprise selective etching of certain materials with minimum affectation of other surrounding and / or underlying materials. Consequently, advanced techniques for material etching are indispensable for the fabrication of transistors because they provide the precision, scalability, and complexity required to produce high performance and miniaturized transistors.

[0010] During transistor manufacturing, etching processes may be used for pattern transfer, i.e. for transferring patterns from a photolithographically defined mask onto an underlyingmaterial. Such patterning may be needed for defining transistor parts. As an example, the manufacture of field effect transistors may demand the precise removal of a dielectric oxide layer at specific locations on an area of the substrate to create the required intricate patterns and structures. In some cases, etching of the dielectric oxide layer, while leaving an underlying material functionally intact, may be demanded.

[0011] However, etching of dielectric oxide layers with minimal affectation of underlying materials is particularly challenging when dealing with transistors involving the use of low dimensional materials, e.g. carbon nanotubes, graphene, transition metal dichalcogenides (TMDs), etc.. Hence, difficulties are encountered when selectively etching gate dielectrics, such as hafnium oxide, HfC>2, without damaging the carbon nanotubes acting as the transistor channel. Unfortunately, such damage results in defective transistors, or in transistors with limited performance.

[0012] Different techniques are available for etching dielectric materials, such as wet etching, e.g. HF etching, or dry etching with Reactive Ion Etching (RIE). These techniques exhibit some limitations or drawbacks when it comes to their application in the fabrication of devices comprising low dimensional materials. Those limitations include, among others, the following: safety and environmental concerns, limited technical performance due to poor selectivity, difficult control, or damage to low dimensional materials.

[0013] In summary, the continued need for increased integration of field effect transistors has resulted in different architectures and in the use of novel materials, e.g. low dimensional materials. However, there is still a need for transistor designs and manufacturing methods that preserve, or even improve, the performance of field effect transistors while enabling miniaturization to achieve an even larger integration.

[0014] In examples of the present disclosure, improved field effect transistors, comprising low dimensional materials, are provided. Furthermore, in examples of the present disclosure, manufacturing methods that reduce at least some of the aforementioned drawbacks are provided.SUMMARY

[0015] In an aspect of the disclosure, a planar thin film transistor is provided. The transistor comprises a substrate and a low dimensional material arranged on the substrate. A source electrode is arranged on the low dimensional material. A drain electrode is also arranged on the low dimensional material. The drain electrode is spaced apart from the source electrode.

[0016] A channel of the transistor is defined by the low dimensional material in a region extending between the source electrode and the drain electrode. Furthermore, the transistor comprises a gate structure arranged on the low dimensional material in an area corresponding to the channel of the transistor. The gate structure comprises a gate dielectric arranged on the low dimensional material. The gate dielectric extends from the source electrode to the drain electrode. The gate structure also comprises a gate electrode arranged on the gate dielectric and a spacer dielectric arranged on the gate dielectric. The spacer dielectric is arranged in a first space between the gate electrode and the source electrode and in a second space between the gate electrode and the drain electrode.

[0017] According to this aspect of the disclosure, a field-effect transistor with improved performance is achieved. In particular, low dimensional materials, e.g. carbon nanotubes, exhibit high carrier mobility, which results in faster switching speeds than conventional transistors based on silicon channels. Lower power consumption or enhanced thermal conductivity are further advantages of the transistor according to the present disclosure.

[0018] Furthermore, the arrangement of the spacer dielectric to electrically isolate the gate electrode and the respective source and drain electrodes according to this aspect of the disclosure provides additional advantages. In the prior art, it is known to provide a dielectric to isolate the different transistor terminals. However, in such known solutions, the dielectric is not arranged on top of the gate dielectric, i.e. it is not integrated with the gate structure as in the present disclosure. Conversely, known solutions comprise spacer dielectric material, or dielectric spacers, extending from the active material and arranged in spaces or slots provided at the interfaces between the gate structure and each of the drain electrode and source electrode. As a result, the dielectric spacers in the prior art solutions take up space of the device footprint.

[0019] In the present disclosure, by arranging the spacer dielectric on the gate dielectric, unwanted doping or contamination of the active layer, i.e. of the highly sensitive low dimensional material, is avoided. Indeed, by preventing direct contact between the spacer dielectric and the active material, the risk of diffusion of additional contaminants from the spacer dielectric into the low dimensional material is mitigated.

[0020] Moreover, the integration of the spacer dielectric on the gate structure increases the performance of the devices due to further considerations. Indeed, such integration allows the use of a more extended gate dielectric because no space is taken up at the interfaces between the gate structure and the source and drain electrodes. Hence, according to this aspect of the disclosure, the gate dielectric extends all the way from the source electrode to the drainelectrode. As a result, an improved field effect can be obtained. Given a manufacturing process with a certain node size, e.g. 5 nanometres (nm), the present aspect provides improved performance because the architecture of the device permits full space availability for the gate dielectric. In other words, the architecture according to the present disclosure results in an optimized utilization of the footprint of the transistor such that, given a certain node size, higher integration and performance are provided.

[0021] In another aspect of the disclosure, a method for manufacturing a planar self-aligned thin-film transistor is provided. The method comprises providing a low dimensional material on a substrate, and depositing a first gate dielectric layer on the low dimensional material. The first gate dielectric layer is configured to act as a gate dielectric of the transistor, that is, the portion of the first gate dielectric layer deposited at the region of the gate becomes the gate dielectric of the transistor. The method also comprises depositing a first metallic layer on the first gate dielectric layer, the first metallic layer being configured as a gate electrode. A gate region is defined by photolithography. Subsequently, the first metallic layer is etched except in the defined gate region.

[0022] Then, the method comprises conformally depositing a layer of a spacer dielectric material. Subsequently, the method comprises anisotropically etching the first gate dielectric layer and the spacer dielectric material layer in a direction substantially perpendicular to the substrate such that the first gate dielectric layer and the spacer dielectric material layer are selectively removed in regions wherein the layer of spacer dielectric material is arranged substantially parallel to the substrate. Such etching is carried out without substantially etching the underlying low dimensional material. Conversely, the anisotropic etching is such that the spacer dielectric material layer and the first gate dielectric layer are substantially unetched in the regions wherein the layer of spacer dielectric material is arranged substantially perpendicular to the substrate. These latter regions substantially correspond to the edges of the gate structure.

[0023] The method then comprises conformally depositing a second metallic layer. The second metallic layer is configured as a source electrode and as a drain electrode of the transistor. In other words, the second metallic layer acts as the source electrode and the drain electrode in the corresponding regions of the transistor footprint. Accordingly, a source region and a drain region are defined at opposed ends of the gate region by photolithography. The method according to this aspect of the disclosure also comprises etching the second metallic layer except in the defined source and drain regions.

[0024] According to this aspect of the disclosure, an improved method for manufacturing field effect transistors is provided. In particular, the method offers advantages during the manufacturing sequence, and it also allows the manufacture of transistors with enhanced performance.

[0025] The manufacturing method according to this aspect of the disclosure allows defining the source and drain regions at opposed ends of the gate region in a single step by using the materials already present in the gate region as a mask during the manufacturing. In this manner, a self-alignment system is provided, which avoids the use of complex alignment steps. Therefore, the manufacturing process can be conducted with an improved accuracy independently of the lithographic machine employed.

[0026] Furthermore, the method does not comprise lift-off processes. Instead, the construction of the transistor parts is primarily carried out by means of material etching processes. In particular, this is achieved by means of the careful selective removal of the first gate dielectric layer and the spacer dielectric material layer. Therefore, a precise and selective etching, which is capable of maintaining the underlying low dimensional material substantially unetched, is accomplished for those dielectrics. Maintaining the underlying low dimensional material substantially unetched is understood as maintaining the low dimensional material with no etching damage, i.e. without breaks or physical discontinuities. Hence, even if point defects may exist, these are not inducing any such physical discontinuities, i.e. separation between different portions, on the low dimensional material. Accordingly, the low dimensional material maintains its functionality in the manufactured device.

[0027] Moreover, the method allows a very precise definition of the spacer dielectric arranged on the gate dielectric between the gate electrode and the respective source and drain electrodes. More specifically, the thickness of the spacer dielectric, which defines the distance between the gate electrode and each of the source and drain electrodes, can be finely adjusted. In particular, the etching of the layer of spacer dielectric material is not only selective, but also highly anisotropic. In this manner, the vertical walls of the conformally deposited spacer dielectric are not etched away and they are maintained in a controlled manner. This allows a precise definition of the characteristics of the spacer dielectric arranged between the gate electrode and the corresponding source and drain electrodes.

[0028] Throughout the present disclosure, it may be understood that low dimensional materials are materials that exhibit at least one spatial dimension that is reduced to the nanoscale, such that electrons become confined. Low dimensional materials can include zerodimensional, one-dimensional or two-dimensional materials. Zero-dimensional, 0D, materials,are materials in which electrons are confined in all three dimensions, e.g. quantum dots. Onedimensional, 1 D, materials are those in which electrons can move freely in only one dimension. As an example, carbon nanowires or carbon nanotubes are 1D materials. Furthermore, low dimensional materials can also include two dimensional, 2D, materials, in which electrons can move freely in two dimensions, i.e. in a sheet-like structure or plane. Graphene is an example of a 2D material.

[0029] Throughout the present disclosure, the terms gate region, source region, and drain region, are understood as referring to the physical areas in the transistor footprint corresponding to the gate, source, and drain terminals of the transistor. Therefore, the terms gate region, source region, and drain region refer to the areas occupied by the gate structure, the source electrode, and the drain electrode in an already manufactured or completed transistor. Accordingly, those terms refer also to the physical areas in the transistor footprint that, during the manufacturing process of the transistor, are intended for such gate structure, source electrode and drain electrode.

[0030] In the present disclosure, the terms low-k and high-k dielectrics or materials are given their well-established meaning for the skilled person (see, e.g. “Dielectric Films for Advanced Microelectronics”, Banklanov et. Al, 2007). Hence, the terms high and low are not used as quantitative indicators for the dielectric constant, but as identifiers for different types of materials. It is commonly known that high-k dielectrics refer to materials with a high dielectric constant as compared to silicon dioxide, SiC>2. Conversely, low-k dielectrics refer to materials with a small relative dielectric constant relative to silicon dioxide (see also, e.g. “High and Low dielectric constant materials”, Singh R. and Ulrich R. K., The Electrochemical Society, Summer 1999).BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Non-limiting examples of the present disclosure will be described in the following, with reference to the drawings, in which:Figures 1A and 1B schematically illustrate a side view (Fig. 1A) and a top view (Fig. 1B) of a transistor according to an example of the disclosure;Figure 2 shows a flowchart illustrating a method for manufacturing a transistor according to the disclosure;Figure 3 schematically illustrates an example of a plasma processing apparatus for use in a method according to the disclosure;Figure 4 shows a flowchart illustrating an example of a method for establishing a source region and a drain region of a transistor;Figures 5A - 5U schematically illustrate a sequence of steps in both a top and a cross-sectional view of an example of a method for manufacturing a transistor according to the disclosure; Figures 6A - 6C schematically illustrate a cross-sectional view of manufacturing steps used in an example comprising a double gate dielectric layer;Figures 7A and 7B schematically illustrate a side view (Fig. 7A) and a top view (Fig. 7B) of another example of a transistor;Figure 8 shows a flowchart illustrating an example of a method for manufacturing a transistor like the one depicted in Figures 7A - 7B;Figures 9A - 9T schematically illustrate a sequence of steps in both a top and a cross-sectional view of a method for manufacturing a transistor according to the example of Figures 7A - 7B; Figures 10A - 10D schematically illustrate other transistor examples;Figures 11A - 11C schematically illustrate some manufacturing steps employed for the manufacturing of a transistor according to the variant depicted in Figure 10C;Figures 12A - 12B schematically illustrate a methodology to determine a thickness of a spacer dielectric; andFigures 13A - 13C show different experimental results obtained for the measurement of spacer dielectric thicknesses.DETAILED DESCRIPTION OF EXAMPLES

[0032] Reference will now be made in detail to one or more examples. Each example is provided by way of explanation only, not as a limitation. In fact, it will be apparent to those skilled in the art that various modifications and variations can be made in the present disclosure. It is intended that the present disclosure covers such modifications and variations as come within the scope of the appended claims and their equivalents. Furthermore, drawings are intended to illustrate the different examples and manufacturing process. For the sake ofclarity, dimensions of the different elements are not at scale to facilitate identification of the different components.

[0033] Figure 1A schematically illustrates a side view of a transistor 1 according to the disclosure, whereas Figure 1B illustrates a top view of the transistor 1. The transistor 1 comprises a substrate 10 and a low dimensional material 20 arranged on the substrate 10. A source electrode 55a is arranged on the low dimensional material 20. A drain electrode 55b is also arranged on the low dimensional material 20. The drain electrode 55b is spaced apart from the source electrode 55a.

[0034] A channel of the transistor 1 is defined by the low dimensional material 20 in a region extending between the source electrode 55a and the drain electrode 55b. Furthermore, the transistor 1 comprises a gate structure 2 arranged on the low dimensional material 20 in an area corresponding to the channel of the transistor 1. The gate structure 2 comprises a gate dielectric 25g arranged on the low dimensional material 20 and extending from the source electrode 55a to the drain electrode 55b. The gate structure 2 also comprises a gate electrode 30g arranged on the gate dielectric 25g. Moreover, the gate structure 2 further comprises a spacer dielectric 40g arranged on the gate dielectric 25g in a first space between the gate electrode 30g and the source electrode 55a and also in a second space between the gate electrode 30g and the drain electrode 55b.

[0035] A field-effect transistor 1 with proper performance is achieved. Specifically, the low dimensional material 20 exhibits high carrier mobility. In an example, the low dimensional material 20 may comprise a carbon-based low dimensional material.

[0036] Furthermore, increased efficiency is provided by the integration of the spacer dielectric 40g in the gate structure 2. The integration of the spacer dielectric 40g decreases parasitic capacitances between the gate electrode 30g and either the source 55a or the drain 55b electrodes of the transistor 1, while allowing optimization of the footprint of the transistor 1. In particular, a more extended gate dielectric 25g can be employed as no space is taken up at the interfaces between the gate structure 2 and the source 55a and drain 55b electrodes. This results in an improved field effect. Hence, given a manufacturing process with a certain node size, e.g. 5 nanometres (nm), improved performance can be achieved because the architecture of the transistor 1 permits full space availability for the gate dielectric 25g.

[0037] Furthermore, the arrangement of the spacer dielectric 40g on top of the gate dielectric 25g prevents direct contact between the spacer dielectric 40g and the low dimensional material 20, i.e. the active material of the transistor 1. Consequently, unwanteddoping or contamination of the active layer, which may arise from the diffusion of material from the spacer dielectric 40g to the low dimensional material 20, is avoided.

[0038] In an example of the disclosure, the thickness of the spacer dielectric 40g may be less than 1500 nanometres, specifically less than 25 nanometres. In particular, the thickness of the spacer dielectric 40g may be between 4 and 25 nanometres. And, more particularly, between 4 and 10 nanometres. As also illustrated in Figure 1A, the first space and the second space, i.e. the space between the gate electrode 30g and the corresponding source electrode 55a and drain electrode 55b, may exhibit a substantially constant width as measured in a direction parallel to the substrate. In other words, the spacer dielectric 40g arranged in those first and second spaces may also exhibit a uniform width as we move vertically upwards, i.e. perpendicularly to the substrate 10, from the surface of the gate dielectric 25g. Furthermore, the spacer dielectric 40g may be flush with the gate dielectric 25g, i.e. an outer perimeter of the gate dielectric 25g in a plane parallel to the substrate 10 may substantially coincide with an outer perimeter of the spacer dielectric 40g.

[0039] As indicated, the spacer dielectric 40g plays an important role in order to electrically isolate the source electrode 55a and the drain electrode 55b from the gate electrode 30g. In this example, a transistor 1 with an extremely thin spacer dielectric 40g, also referred to as dielectric spacers, may be provided while fulfilling such functionality. The provision of such small dielectric spacers 40g may increase the level of miniaturization of the transistor 1. Furthermore, electrical properties of the transistor 1 may also be enhanced. For instance, the on / off current ratio of the transistor 1 may be increased due to a better electrostatic control. Transconductance of the transistor 1 may be increased, thus leading to better signal amplification. More details regarding the provision of such small dielectric spacers 40g will be provided below while describing the manufacturing method.

[0040] On the other hand, the provision of a spacer dielectric 40g with a thickness of at least 4 nanometres may provide an adequate insulation between the gate electrode 30g and the source and drain electrodes 55a, 55b in a reliable manner. Hence, by using a thickness of at least 4 nanometres, the presence of pores or defects in the spacer dielectric 40g may be significantly mitigated. In particular, the use of a spacer dielectric 40g with a thickness in the range from 4 -25 nanometres allows a controlled deposition, which is uniform and repetitive.

[0041] Different materials may be used for the spacer dielectric 40g. In particular, the spacer dielectric 40g may comprise a low-k material. The use of a low-k material may improve the functionality of the transistor 1 by reducing spacer capacitance thus lowering the parasitic capacitances. In this manner, the switching velocity of the transistor 1 may be increased. Thismay be particularly convenient in high frequency applications. Alternatively, the spacer dielectric 40g may comprise SiC>2 (silicon oxide).

[0042] As with the spacer dielectric 40g, different dielectric materials may be used for the gate dielectric 25g of the gate structure 2 in order to optimize the performance of the transistor 1. Hence, as known by the skilled person, the gate dielectric 25g plays a key role as an insulating layer between the gate electrode 30g and the channel of the transistor 1. Furthermore, the gate dielectric 25g enables the field-effect operation of the transistor 1. In particular, in examples of the disclosure, the first gate dielectric 25g may comprise a high-k dielectric, e.g. AI2O3 (aluminium oxide or alumina) or HfC>2 (hafnium oxide or hafnia). In other examples, two-dimensional (2D) materials such as hBN (hexagonal boron nitride) may be employed.

[0043] In order to optimize the performance of the transistor 1, in an example of the disclosure, the gate dielectric 25g may comprise a double structure. Hence, the gate dielectric 25g may comprise a portion of a first gate dielectric layer arranged on the low dimensional material 20, and a portion of a second layer of a second dielectric material arranged on the first layer. The use of such a double layer architecture for the gate dielectric 25g may provide advantages during the manufacturing of the transistor 1 as shown in more detail below. Moreover, the performance of the transistor 1 may also benefit from the use of such a double layer architecture depending on the nature of the selected materials.

[0044] Specifically, in a variant of this example, the first gate dielectric, i.e. the dielectric directly in contact with the low dimensional material 20, may comprise a post-transition metal oxide, a transition metal oxide, or a fluorocarbon polymer. The second gate dielectric may comprise a high-k dielectric material, such as HfC>2.

[0045] The use of a high-k material, e.g. HfC>2, as the second dielectric material may be useful to enhance the overall capacitance of the gate structure 2, thus reducing leakage currents and improving gate control.

[0046] Different low dimensional materials may be used in examples of the disclosure. Those may include 1D materials, such as carbon nanotubes or WS2 nanotubes. Hence, in an example of the disclosure, the low dimensional material 20 may comprise a one-dimensional material. Specifically, in a variant, the low dimensional material 20 may comprise a single carbon nanotube (CNT). Furthermore, the source electrode 55a and the drain electrode 55b may be arranged at opposing ends on the carbon nanotube.

[0047] Different types of carbon nanotubes (CNTs) such a single-walled carbon nanotubes (SWCNTs) or multi-walled carbon nanotubes (MWCNTs) may be considered depending on the intended performance. In particular, the use of carbon nanotubes may result in a transistor 1 with enhanced properties due to their high carrier mobility and excellent thermal conductivity.

[0048] In another example, the low dimensional material 20 may comprise a two-dimensional material. In some examples, the two-dimensional material may be a two-dimensional material, or a two-dimensional transitional metal dichalcogenide (TMD) material such as a MX2 material wherein the M is a transition-metal and the X is a chalcogen. Particularly, the MX2 material may be selected from at least one of the following: M0S2, WeS2 or WS2. Furthermore, the two-dimensional material may comprise graphene. In other examples, a two-dimensional material comprising graphene oxide or graphane may be provided.

[0049] Figure 2 shows a flowchart of a method 100 for manufacturing a planar thin-film transistor 1 according to the disclosure. Reference will also be made to the numerals used in Figures 5A-5LI to further illustrate the method 100.

[0050] The method 100 comprises, in block 105, providing a low dimensional material 20 on a substrate 10. Block 110 comprises depositing a first gate dielectric layer 25 on the low dimensional material 20. The first gate dielectric layer 25 is configured to act as a gate dielectric 25g of the transistor 1, i.e. the first gate dielectric layer 25 corresponds to the gate dielectric 25g when taking into account the portion of the first gate dielectric layer 25 arranged at the region of the gate structure 2. The method 100 also comprises, in block 115, depositing a first metallic layer 30 on the first gate dielectric layer 25. The first metallic layer 30 is configured to act as a gate electrode 30g of the transistor 1. As in the previous case, the first metallic layer 30 corresponds to the gate electrode 30g in the region of the gate structure 2 shown in Figures 1A or 1B.

[0051] Furthermore, block 120 comprises defining a gate region 22 by using e.g., photolithography. The gate region 22 corresponds to the physical area intended for the gate structure 2 of the transistor 1. Then, in block 125, the first metallic layer 30 is etched except in the defined gate region 22. Method 100 also comprises conformally depositing a spacer dielectric material layer 40 in block 130. Subsequently, the method 100 comprises anisotropically etching the first gate dielectric layer 25 and the spacer dielectric material layer 40 in a direction substantially perpendicular to the substrate 10 in block 135. The etching is such that the first gate dielectric layer 25 and the spacer dielectric material layer 40 are selectively removed in regions wherein the layer of spacer dielectric material 40 is arrangedsubstantially parallel to the substrate 10. The anisotropic etching in block 135 is also such that the spacer dielectric material layer 40 and the first gate dielectric layer 25 are substantially unetched in regions wherein the layer of spacer dielectric material 40 is arranged substantially perpendicular to the substrate 10.

[0052] As a result of the step carried out in block 135, the resulting spacer dielectric 40g may be flush with the gate dielectric 25g. Furthermore, the remaining spacer dielectric 40g may exhibit a substantially constant width as measured in a direction parallel to the substrate 10. The width may substantially correspond to the thickness of the conformally deposited spacer dielectric material layer 40. Moreover, as shown in more detail below with reference to Figures 5A-5LI, the width of the spacer dielectric 40g may also determine the dimensions of a first space and a second space between the gate electrode 30g and the source and drain electrodes 55a, 55b.

[0053] The method 100 then comprises, in block 140, conformally depositing a second metallic layer 45. The second metallic layer 45 is configured to act as a source electrode 55a and as a drain electrode 55b of the transistor 1. A source region 5a and a drain region 5b are defined at opposed ends of the gate region 22 by photolithography in block 145. The second metallic layer 45 is etched in all areas except in such defined source region 5a and drain region 5b in block 150. As mentioned above, the source region 5a and the drain region 5b are understood as physical areas corresponding to the source and the drain terminals of the transistor 1, i.e. to the physical areas wherein the source electrode 55a and the drain electrode 55b are arranged once the transistor 1 is fully manufactured.

[0054] This method 100 offers advantages during the manufacturing sequence, and it also allows the manufacture of a transistor 1 with enhanced performance. In particular, the described method 100 allows defining the source 5a and drain 5b regions at opposed ends of the gate region 22 by using the materials already present in the gate region 22 as a mask during the manufacturing. This will be shown in more detail below, with reference to Figures 5A - 5U. In this manner, a self-alignment process is achieved, thus reducing the complexity of the manufacturing process while increasing reliability.

[0055] Specifically, method 100 offers advantages due to the critical step carried out in block 135. This block comprises the selective etching of dielectric materials, i.e. the first gate dielectric layer 25 and the spacer dielectric material layer 40, while maintaining the underlying low dimensional material 20 substantially unetched.

[0056] By using the term “unetched” in the context of the underlying low dimensional material 20 being substantially unetched, the term “unetched” may define a feature of a material that does not present “etching damage”, i.e., there are substantially no physical discontinuities in a layer made of an “unetched” material. The term “etching damage” may be understood as localized mechanical breaks in the atomic lattice of the low dimensional material, leading to a physical discontinuity in a layer made of the low dimensional material, i.e., there is a physical separation between a first portion and a second portion of the layer.

[0057] The method 100 according to the present disclosure allows a very precise definition of the spacer dielectric 40g of the transistor 1 as the etching of the spacer dielectric material layer 40 is not only selective, but also highly anisotropic. In this manner, the vertical walls of the conformally deposited layer of spacer dielectric material 40 are not etched away and they are maintained in a controlled manner. This allows a highly precise definition of the characteristics of the spacer dielectric 40g arranged between the gate electrode 30g and the corresponding source 55a and drain 55b electrodes. Furthermore, and as already described with reference to Figure 1A, the spacer dielectric 40g is integrated in the gate structure 2, i.e. the spacer dielectric 40g is arranged on top of the gate dielectric 25g of the gate structure 2, thus optimizing the footprint of the transistor 1.

[0058] In an example of the disclosure, the method 100 may comprise using an apparatus 90 like the one schematically depicted in Figure 3. Hence, anisotropically etching the first gate dielectric layer 25 and the spacer dielectric material layer 40 in block 135 may comprise placing the substrate 10 (carrying the different materials deposited until block 135) in a substrate holder 96 in a vacuum chamber 97. A chlorine-based gas may be introduced in the vacuum chamber 97 and a pressure in the vacuum chamber 97 may be adjusted to a predetermined value. Specifically, the gas mixture may only contain chlorine-based gases such as Ch and / or BCh, with no other gases introduced in the mixture.

[0059] The method 100 may further comprise connecting a radiofrequency power source 92 to the substrate 10 for generating a bias voltage. Specifically, in case an apparatus 90 like the one depicted in Figure 3 is used in an example, the radiofrequency power source 92 may be connected to the substrate holder 96, so that it may be operatively coupled to the substrate 10. The radiofrequency power source 92 may be operated at a power such that a power density of less than 0.19 W / cm2may be obtained when dividing the power of the radiofrequency power source by the substrate area.

[0060] According to this example, a plasma 98 may be generated in the vacuum chamber 97 by the radiofrequency power. The resulting radicals and ions may then chemically reactwith the dielectric layers to be etched in a highly selective manner. Furthermore, the radiofrequency power source 92 may induce an acceleration of ions in the plasma 98 towards the substrate 10, i.e. along a substantially vertical direction 99, thus favouring anisotropic etching. In particular, acceleration of the ions results in physical etching, which allows enhancing the etch rate in a highly directional manner. Accordingly, the spacer dielectric material layer 40 may be etched, not only in a selective manner, but also in a highly anisotropic form. Hence, the vertical walls of the layer of spacer dielectric material 40, e.g. in the areas surrounding the gate electrode 30g, may be etched at a much lower rate. Consequently, such vertical walls may be substantially maintained, thus creating sharp and well-defined patterns giving place to the spacer dielectric 40g providing electrical insulation between the source 55a and drain 55b electrodes and the gate electrode 30g.

[0061] In particular, by combining the use of chlorine-based gases and a low power for the radiofrequency power source 92, etching damage of the delicate low dimensional material 20 may be avoided. Operation of the radiofrequency power source 92 at relatively low power values may permit a controlled etch of the spacer dielectric material layer 40 and, even more importantly, of the first gate dielectric layer 25 arranged directly on top of the low dimensional material 20. Such control may prevent undesired effects such as over-etching, thus minimizing the risk of damaging the underlying material. The use of chlorine-based gases provides chemical selectivity, so that only the dielectric layers, i.e. the spacer dielectric material layer 40 and the first gate dielectric layer 25, are chemically affected. In particular, chlorine-based gases are highly reactive with metal oxides, thus creating volatile byproducts that are easy to remove.

[0062] In a variant of this example, and as also shown in Figure 3, the apparatus 90 may be configured as a reactive ion etcher (RIE) with inductively coupled plasma (ICP). Hence, a second radiofrequency power source 94 may be provided. The second radiofrequency power source 94 may be connected to a coil 93. A high frequency, e.g. 13.56 MHz, may be used to energize a gas mixture into a plasma 98 through inductive coupling. To this end, the coil 93 may be arranged surrounding the vacuum chamber 97. In this variant, creation of the plasma 98 may be further enhanced and controlled by inductive coupling with such second radiofrequency power source 94. This second radiofrequency power source 94 may also be operated at low power values. Specifically, the second radiofrequency power source 94 may be operated at a power such that a power density of less than 1.23 W / cm2may be obtained when dividing the corresponding power by the substrate 10 area, specifically the power density may be comprised between 0 W / cm2and 0.31 W / cm2, more specifically between 0.15 W / cm2and 0.31 W / cm2. Operation of the first and second radiofrequency power sources 92, 94, may be swapped or even carried out in a simultaneous form.

[0063] According to this example, a further improved etching of the spacer dielectric material layer 40 and of the first gate dielectric layer 25 may be obtained. Hence, a low power Reactive Ion Etching (RIE), combining chemical and physical mechanisms, may be provided, which may allow a precise and selective removal of the first gate dielectric layer 25 deposited on the low dimensional material 20 without affecting the latter.

[0064] The adjustment of the pressure inside the vacuum chamber 97 may be implemented by controlling a vacuum pump system and / or by controlling the cross-section of an evacuation line 95, e.g. by using a controllable exhaust valve. The pressure in the vacuum chamber 97 may influence the dynamics, e.g. etch rate, and characteristics of the etching process, e.g. selectivity or anisotropy. Specifically, the pressure may affect a balance between chemical and physical etching mechanisms.

[0065] In a variant, not only a low power, but also a low pressure, may be employed. In particular, improved anisotropy may be achieved by operating at low pressures whereas energy of the ion bombardment may be kept relatively low by using a low bias voltage. To this end, a low power of, e.g. between 5W and 15W, may be defined for the radiofrequency power source 92. Furthermore, adjusting the pressure in the vacuum chamber 97 to a predetermined value in this variant may comprise adjusting the pressure to a value of less than 10 mTorr. Specifically, the pressure in the vacuum chamber 97 may be adjusted to a value in a range from 1 mTorr to 10 mTorr or, even more specifically, to a value of approximately 5 mTorr. The flow rates of the etching gases may also be controlled. Thus, in this variant of the disclosure, flow rates of approximately 10 standard cubic centimetres per minute (seem) and 20 seem may be used for BCh and Ch, respectively. As a result, a highly controlled etch rate may be achieved. An etch rate of less than 2 nm / min, specifically an etch rate of approximately 1.3 nm / min, may be obtained.

[0066] Furthermore, still other process parameters may also have an influence. In particular, the temperature of the substrate 10 may also play a role in the dynamics and characteristics of the etching process. Specifically, slow chemical reactions and reduced etch rate may be obtained when using low temperatures in chemistry-dominated processes. Furthermore, low temperatures may improve selectivity in cases where such slower reactions reduce the etching of a sensitive masking material, such as photoresist. Moreover, low temperatures may facilitate the deposition of polymer on sidewalls, thus aiding anisotropic etching by protecting the sidewalls and preventing lateral etching, i.e. undercutting. The use oflow temperatures during the process may also help reduce thermal stress on the processed sample.

[0067] The described method 100 is not limited to a specific material for the spacer dielectric material layer 40 and for the first gate dielectric layer 25. Hence, by adjusting the process parameters, e.g. gas flow rates, pressure, or power settings, the process may be tailored to different dielectric oxides.

[0068] Overall, by providing two separate radiofrequency power sources 92, 94 as shown in Figure 3, independent control of both ion energy on the substrate 10, which is mostly determined by the voltage bias induced by the radiofrequency power source 92, and plasma density, which can be adjusted by the inductive coupling induced by the second radiofrequency power source 94, is provided. As a result, a proper control on the etching process is obtained.

[0069] As already mentioned, the gate dielectric material plays a significant role in the performance of the transistor 1. In some examples, a gate dielectric 25g comprising a multilayer structure may be selected. Hence, in an example, the method 100 may comprise depositing a second gate dielectric layer (not shown) on the first gate dielectric layer 25. The first 25 and second gate dielectrics layers may be configured to act as the gate dielectric 25g. The first gate dielectric layer 25, i.e. the dielectric in direct contact with the low dimensional material 20, may comprise a low-k dielectric material and the second gate dielectric layer may comprise a high-k dielectric material.

[0070] Apart from the above-mentioned advantages for the performance of the transistor 1 , such a double-layer or stack configuration may also increase the efficiency and reliability of the manufacturing process. Specifically, the block 135 of method 100 shown in Figure 2 may be facilitated and / or optimized. Hence, in a variant of this method 100, the spacer dielectric material layer 40 and the second gate dielectric layer may be etched with a dry etching process as described above. Then, the first gate dielectric layer 25 may be carried out with wet etching.

[0071] Accordingly, a dry etching process may be carried out for the etching of the layer of spacer dielectric material 40 and the second dielectric layer down to an interface with the first gate dielectric layer 25. To this end, a similar process to the one described above may be employed. In particular, an apparatus 90 like the one depicted in Figure 3 may be used. Nevertheless, because in this case the underlying material is another dielectric material, i.e. the first gate dielectric layer 25, a less critical process may be considered. In other words, the selectivity of the etching process may become less critical as the underlying material is also a material that needs to be removed and not the low dimensional material 20. For this reason, amore aggressive dry etching process may be carried out to increase the efficiency, i.e. the speed, of the overall manufacturing sequence. Such etching may comprise the use of higher powers and / or the addition of Ar in the gas mixture to further accelerate the etching of the spacer dielectric material layer 40 and the second dielectric layer by Ar ion bombardment. In any case, the conditions of the dry etching may also be adjusted so as to primarily etch the spacer dielectric material layer 40 and the second dielectric layer while not significantly affecting the first gate dielectric layer 25, i.e. the dielectric layer arranged on top of the low dimensional material 20.

[0072] Subsequently, after dry etching the second dielectric layer, the first gate dielectric layer 25 may be effectively etched by means of a wet etching process, which may be highly selective thus avoiding any significant damage to the underlying low dimensional material 20. Different wet etching strategies may be used depending on the nature of the first gate dielectric layer 25. Hence, post-transition metal oxides such as ZnO or AI2O3 may be easily wet etched by dilute HCI and weak alkaline NaOH or KOH solutions, respectively, without affecting the underlying low dimensional material 20. In case transition metal oxides like TiO2 or ZrO2 are used for the first gate dielectric layer 25, different etchings may be considered. In particular, a safe mixture of NH4OH and H2O2 may be used for etching TiO2, whereas a strong HF etchant may be used to remove ZrO2. As in the previous case, none of those etchant solutions damage the low dimensional material 20. However, wet etching is highly isotropic. Accordingly, a small undercut, i.e. an undercut under the second gate dielectric, may result in the gate region 22 as a result of the wet etching used for the first gate dielectric layer 25.

[0073] Coming back to the flowchart of the fabrication method 100 shown in Figure 2, the source 5a and drain regions 5b are defined in block 145. To this end, photolithography is used to define them at opposed ends of the gate region 22. In particular, and as shown in more detail below with reference to Figures 5A-5LI, a photoresist 50 is used, which is cured in an area corresponding to the gate region 22, the source region 5a, and the drain region 5b, during a photolithography step.

[0074] After defining the source 5a and drain 5b regions at opposed ends of the gate region 22, the second metallic layer 45 is etched in block 150 such that metal remains only in the previously defined source 5a and drain 5b regions. In this manner, the source electrode 55a and the drain electrode 55b are established.

[0075] The flowchart of Figure 4 schematically describes a process 200 to implement such block 150. This will be further clarified below with reference to Figures 5A-5LI.

[0076] Hence, process 200 may comprise, in block 205, etching the second metallic layer 45 and the low dimensional material 20 except in the areas defined by the gate region 22, the source region 5a, and the drain region 5b. To this end, the previously mentioned photoresist 50, used to define the source 5a and drain 5b regions, may be removed from those areas where it is not cured such that the second metallic layer 45 may be left exposed. Subsequently, a Reactive Ion Etching (RIE) process may be carried out to etch the second metallic layer 45 and the low dimensional material 20 in all exposed areas.

[0077] The cured photoresist 50 protecting the gate region 22, source region 5a, and drain region 5b may be removed in block 210. A planarization layer 60, e.g. SiC>2, may then be deposited in block 215. The thickness of the planarization layer 60 may be at least such that an upper surface of the planarization layer 60 in an area not in the gate region 22 may be at a higher height with respect to the substrate 10 than an upper surface of the gate electrode 30g. The planarization layer 60 may have a thickness in a range from 300 nanometres (nm) to 5 micrometres ( .m).

[0078] Subsequently, in block 220, chemical mechanical polishing (CMP) of the planarization layer 60 and the second metallic layer 45 may be carried out. In particular, polishing may be carried out until the second metallic layer 45 in the gate region 22 is entirely removed. In this manner, the existing short circuit between the source region 5a and the drain region 5b may be eliminated by introducing a discontinuity in the second metallic layer 45 in the gate region 22. As a result, the second metallic layer 45 may only remain in the corresponding source region 5a and drain region 5b, where it may constitute the corresponding source electrode 55a and drain electrode 55b, respectively.

[0079] Subsequently, vias may be carried out through the planarization layer 60 to facilitate electrical contact with the second metallic layer 45, i.e. with the source 55a and drain 55b electrodes.

[0080] Further advantages, details and / or examples of the present disclosure will be explained below with reference to Figures 5A-5LI, which schematically depict a sequence of steps for manufacturing a transistor 1 according to an example of the present disclosure. It is understood that the sequence shown in Figures 5A - 5U is provided as an example for illustrative purposes. In particular, some of the depicted steps may be eliminated, combined, or modified in other variants as known by the skilled person.

[0081] As shown in Figure 5A, a substrate 10 may be first provided. The substrate 10 may comprise different materials. For instance, the substrate 10 may be a silicon substrate, e.g. asilicon wafer. Furthermore, the substrate 10 may comprise a dielectric coating such as a thermally grown oxide. The thermally grown oxide may have a thickness in the range of 250 to 300 nanometres. In such cases, the low dimensional material 20 may be provided on top of such coating. In still other examples, the substrate may comprise glass or plastic substrates like polyimide, PET, or PEN. Moreover, different substrate sizes may be used in different examples of the disclosure. Hence, substrates 10 with an area in a range from 5 cm2to 4000 cm2may be employed. After providing the substrate 10, this may be thoroughly cleaned using, e.g. acetone, isopropanol and ultrapure water, and finally it may be dried-out using N2.

[0082] In some examples, an adhesion dielectric layer (not shown) may be deposited on the substrate 10. The adhesion dielectric layer may be deposited by Atomic Layer Deposition (ALD) and it may exhibit a thickness of approximately 10 nm. Alternative deposition techniques, such as chemical vapor deposition, CVD, physical vapor deposition, PVD, or spin coating, may be used in other examples. The adhesion dielectric layer may comprise HfC>2, and it may be used as a good and controllable adhesion layer for the low dimensional material 20. The low dimensional material may be deposited in a subsequent step as shown in Figure 5B.

[0083] Different low dimensional materials 20 may be provided. Those may include onedimensional 1D materials, such as carbon nanotubes. The one-dimensional material 20 may comprise one or more carbon nanotubes. Specifically, different types of carbon nanotubes, CNTs, such a single-walled carbon nanotubes, SWCNTs, or multi-walled carbon nanotubes, MWCNTs, may be considered depending on the intended application.

[0084] Furthermore, different methods may be carried for the provision of the low dimensional material 20 on the substrate 10. Hence, in examples comprising carbon nanotubes, these may be first obtained by e.g. chemical vapor deposition (CVD) or Arc discharge. Subsequently, the obtained carbon nanotubes may be pre-purified. Then, the carbon nanotubes may be dispersed in an aqueous solution, and this may be deposited on the substrate 10, e.g. by spin coating. As an example, the substrate 10 may be spin-coated by rotating the substrate 10 at 1500 rpm for 30 seconds, thus achieving a uniform film. The solvent may be removed after the deposition. To this end, the substrate 10 may be annealed at approximately 120 °C for a period of about 10 minutes. With this approach, moderate temperatures may be needed for the provision of the low dimensional material 20 on the substrate 10. Accordingly, a wide range of materials may be used for the substrate 10. Furthermore, the use of a solution of prefabricated carbon nanotubes, or other 1D materials, may facilitate use of materials with predetermined characteristics. In particular, semiconductingcarbon nanotubes, or either single wall or multiple wall carbon nanotubes, may be chosen for the fabrication of the device depending on the intended application.

[0085] Alternatively, low dimensional materials such as carbon nanotubes may be grown directly on the substrate 10. More specifically, the method may comprise growing carbon nanotubes by means of Chemical Vapor Deposition (CVD). In order to grow carbon nanotubes on the substrate 10 by means of CVD, a first step comprising deposition of catalyst particles may be carried out. The specific locations of the catalyst particles may be defined by patterning with lithography, followed by deposition of a solution containing the catalyst particles. The solvent may be dried, and the excess catalyst may be removed by a lift-off procedure. After formation of the catalyst particles on the surface of substrate 10, the substrate 10 may be placed in a CVD reactor. The CVD process may use hydrogen, H2, argon, Ar, and methane, CH4, and the carbon nanotube growth process may be carried out at high temperatures in the range of 900°C. Based on the parameters of the process, carbon nanotubes of different characteristics, e.g. length, may be obtained.

[0086] In other examples of the disclosure, the low dimensional material 20 may comprise a two-dimensional carbon-based material or a two-dimensional transitional metal dichalcogenide (TMD) material such as a MX2 material wherein the M is a transition-metal and the X is a chalcogen. Particularly, the MX2 material may be selected from at least one of the following: M0S2, WeS2 or WS2. Furthermore, the two-dimensional material may comprise graphene. In other examples, a two-dimensional material comprising graphene oxide or graphane may be provided.

[0087] Said 2D materials may also be grown via, e.g., chemical vapor deposition (CVD) or atomic layer deposition (ALD). They may be subsequently transferred to the substrate 10 by means of e.g. spin coating deposition or chemical deposition by dip coating.

[0088] After deposition of the low dimensional material 20, an inspection may be carried out to ensure uniformity and / or proper alignment and distribution of the material. This may be particularly relevant when using 1 D materials, such as carbon nanotubes, as device fabrication may require precise aligning and positioning of the 1D material.

[0089] Figure 5C corresponds to the deposition of the first gate dielectric layer 25. In an example, the first gate dielectric layer 25 may comprise HfC>2 and it may exhibit a thickness of about 10 nm. Different deposition techniques may be envisaged. In an example, the HfC>2 may be deposited by Atomic Layer Deposition, ALD. Specifically, alternating cycles of H2O and tetrakis(dimethylamido)hafnium, TDMAH, precursors in an ALD chamber may be carried out.A deposition temperature of 130 °C may be selected, whereas precursor temperatures of 90 °C and 20 °C may be employed for the TDMAH and the H2O respectively. With these conditions, a slow deposition rate in the order of 1 A per cycle may be achieved. Accordingly, these conditions may ensure precise and consistent growth of the HfCh film, i.e. of the first gate dielectric layer 25.

[0090] This first gate dielectric layer 25 may be configured to act as the gate dielectric 25g of the corresponding gate structure 2 of the transistor 1. Other dielectric materials, specifically comprising high-k materials, may be envisaged in other examples. After this step, the low dimensional material 20 may become sandwiched between the adhesion dielectric layer (if present) and the first gate dielectric layer 25. In this manner, the first gate dielectric layer 25 may, not only be used for the gate dielectric of the transistor 1 , but also to protect the low dimensional material 20 during subsequent manufacturing steps.

[0091] In the next step (Figure 5D), a first metallic layer 30 may be deposited. Different metals, such as Palladium (Pd), may be selected. Besides, different deposition techniques may be employed. As an example, the first metallic layer 30 may be obtained by sputtering. In a variant of this example, the substrate 10 may be rotated during deposition to improve uniformity of the first metallic layer 30. The first metallic layer 30 may exhibit a thickness in a range from 20 nm to 100 nm, specifically a thickness of about 40 nm. The first metallic layer 30 may be configured to act as the gate electrode 30g of the finished transistor 1. In other words, the first metallic layer 30 in the gate region 22 may correspond to the gate electrode 30g as shown in Figures 1A and 1B. In an example, a metallic adhesion layer may be provided to improve the adhesion of the first metallic layer 30. As an example, a Titanium (Ti) layer may be used in cases comprises use of Palladium (Pd) for the first metallic layer 30.

[0092] Following the deposition of the first metallic layer 30, a series of photolithographic steps may be carried out to define the gate region 22 of the transistor 1. To this end, a photoresist 35 may be deposited as shown in Figure 5E. Spin coating may be used for the deposition of the photoresist 35. Before depositing the photoresist 35, a substrate 10 preparation sequence may be used. Specifically, the substrate 10 (with the low dimensional material 20, the first gate dielectric layer 25, and the first metallic layer 30 already deposited), may be cleaned with acetone to remove surface contaminants. Subsequently, the substrate 10 may be baked on a hot plate at 100 °C for 10 minutes. Then, before applying the photoresist 35, the substrate 10 may be cooled on a cold plate for about 2 minutes.

[0093] The photoresist 35 may then be illuminated with a laser to define the gate region 22 in the photoresist 35 as shown in Figure 5F. An alignment mark region, e.g. a cross-shapedregion, may also be defined in the photoresist 35. The alignment mark may be used for coarse alignment at later stages of the manufacturing sequence of the example. Subsequently, the photoresist 35 may undergo a curing process, e.g. by baking the substrate 10 on a hot plate at 110 °C for 75 seconds, and a developing process to remove the non-cured photoresist 35 (Figure 5G), thus leaving the first metal layer 30 exposed except in the gate region 22 and in the region of the alignment mark.

[0094] A selective etching of the first metallic layer 30 may then be carried out as shown in Figure 5H. With such selective etching, the first metallic layer 30 may be removed in all locations except in those areas protected by the cured photoresist 35. In order to etch the first metallic layer 30, a dry etching, e.g. a Reaction Ion Etching (RIE) process, may be carried out. After this process, the first gate dielectric layer 25 may be exposed, except in the gate region 22 and in the alignment mark region. In the gate region 22, the first metallic layer 30 may then constitute the gate electrode 30g. The photoresist 35 in the gate region 22 and in the alignment mark region may be then removed as schematically depicted in Figure 5I.

[0095] The next step in the manufacturing sequence may comprise the conformal deposition of the spacer dielectric material layer 40 (Figure 5J). It is important to ensure a uniform and conformal deposition as the spacer dielectric material layer 40 should cover both the horizontal surface of the substrate 10 and the vertical walls of the existing nanostructures. In particular, the spacer dielectric material layer 40 may form vertical walls at the edges of the gate electrode 30g. To this end, Atomic Layer Deposition (ALD) may be used for the deposition. The thickness of the spacer dielectric material layer 40 may be in a range between 4 to 25 nanometres, specifically, the spacer dielectric material layer 40 may exhibit a thickness of about 4, 5, 6 or 10 nanometres. Different materials may be used for the spacer dielectric material layer 40. In some examples, HfC>2 may be selected. Alternatively, in other examples, a low-k material may be preferred to improve the functionality of the transistor 1 by reducing the parasitic capacitances. Furthermore, electrical properties of the transistor 1 may also be enhanced. For instance, the on / off current ratio of the transistor 1 may be increased due to a better electrostatic control. After deposition of the layer of spacer dielectric material 40, an inspection may be carried out to ensure that the spacer dielectric material layer 40 covers all the surfaces, specifically the vertical walls of the gate structure 2, and that the thickness of the layer is substantially uniform.

[0096] An important manufacturing step may be carried out next. As shown in Figure 5K, a selective and anisotropic etching of the first gate dielectric layer 25 and the spacer dielectric material layer 40 may be implemented. On the one hand, the first gate dielectric layer 25 andthe spacer dielectric material layer 40 may be selectively removed while maintaining the underlying low dimensional material 20 substantially unetched in regions wherein the layer of spacer dielectric material 40 is arranged substantially parallel to the substrate 10. On the other hand, the spacer dielectric material layer 40 and the first gate dielectric layer 25 may be substantially unetched in the regions wherein the layer of spacer dielectric material 40 is arranged substantially perpendicular to the substrate 10, i.e. at the edges of the gate electrode 30g and at the edges of the alignment mark. In this manner, the integrity of the low dimensional material 20 may be favoured, while controlled walls of the spacer dielectric material layer 40 may be maintained at the edges of the gate electrode 30g, thus resulting in the spacer dielectric 40g. This highly precise etching process may comprise an etching process like the one described above with reference to block 135 of the flowchart of Figure 2. After this etching step, the gate structure 2 comprising the gate dielectric 25g, gate electrode 30g, and spacer dielectric 40g may be obtained.

[0097] As shown in Figure 5K, as a result of this manufacturing step, the spacer dielectric 40g may be arranged flush with the gate dielectric 25g. Consequently, the spacer dielectric 40g may be provided on the gate dielectric 25g such that the horizontal surface of the gate dielectric 25g is entirely covered by the gate conductor 30g and by the spacer dielectric 40g. Moreover, as also shown in Figure 5K, the spacer dielectric 40g arranged in the spaces between the gate conductor 30g and the source and drain electrodes 55a, 55b may exhibit a substantially constant width as measured in a direction parallel to the substrate 10.

[0098] The selective etching of the spacer dielectric material layer 40 may be tailored for different dielectric materials. Thus, some of the etching parameters, e.g. gas mixture, pressure, temperature, or powers used for the first radiofrequency power source 92 or the second radiofrequency power source 94 (if present), may be tuned. In any case, low power densities may be maintained to ensure a slow and controllable etching.

[0099] As also mentioned above, in some examples the gate dielectric layer may comprise a first gate dielectric layer 25 and a second gate dielectric layer 25’. Such second gate dielectric layer 25’ may be deposited on top of the first gate dielectric layer 25, i.e. right after the step shown in Figure 5C, which, in these examples, may be modified as shown in Figure 6A. In these examples, the selective and anisotropic etching schematically depicted in Figure 5K may comprise two separate steps. Such separate steps are schematically illustrated in Figures 6B and 6C. Firstly, a dry etching process like the one described above may be carried out for the etching of the spacer dielectric material layer 40 and the second gate dielectric layer 25’. This first dry etching process may comprise a RIE etching process, which may result in ananisotropic etching allowing the vertical walls of the spacer dielectric material layer 40 to remain substantially unetched as shown in Figure 6B. The conditions of the RIE etching may be adjusted to prevent etching of the first gate dielectric layer 25. Secondly, as shown in Figure 6C, the first gate dielectric layer 25 may be etched by means of wet etching in a highly sensitive manner such that the low dimensional material 20 remains unetched. Due to the isotropic nature of the wet etching process, a small undercut may arise as also shown in Figure 6C.

[0100] In still some other examples, the spacer dielectric material layer 40 may also comprise a multiple spacer structure (not shown), i.e. conformally depositing a spacer dielectric material layer 40 may comprise depositing a plurality of sub-layers of different dielectric materials. Indeed, the use of a multiple structure for the spacer dielectric 40g may also provide increased flexibility and versality in the properties of the manufactured transistor 1. In these other examples, equivalent etching steps to the ones already described may be implemented to obtain the corresponding gate structure 2. In particular, in such examples, anisotropically etching the first gate dielectric layer 25 and the spacer dielectric material layer 40 may comprise using different etching parameters for the plurality of sub-layers forming the spacer dielectric 40g.

[0101] After definition of the gate structure 2, the next goal in the manufacturing sequence according to this example may be the definition of the source 5a and drain 5b regions. To this end, a number of steps may be carried out as described below.

[0102] First, a second metallic layer 45 may be deposited as illustrated in Figure 5L. This second metallic layer 45 may be configured to act as the source 55a and drain 55b electrodes of the transistor 1. Sputtering may be used for the deposition of the second metallic layer 45. Palladium, Pd, may also be selected for the second metallic layer 45, which may exhibit a thickness in a range from 40 to 80 nm, specifically a thickness of about 60nm.

[0103] Subsequently, a photolithography step may be carried out to define the source 5a and drain 5b regions. In particular, a photoresist 50 may be first deposited (Figure 5M). Subsequently, the photoresist 50 may be illuminated in the areas corresponding to the gate region 22, and to the source 5a and drain 5b regions at opposed ends of the gate region 22 as shown in Figure 5N. The alignment mark may be used for coarse alignment. A subsequent curing and development step may be carried out (Figure 50) to remove the non-cured photoresist 50. In this manner, the second metallic layer 45 may be left exposed in all regions except in the gate region 22, the source region 5a, and the drain region 5b.

[0104] Figure 5P schematically depicts the next manufacturing step, which comprises the etching of both the second metallic layer 45 and the low dimensional material 20 in all areas of the substrate 10 not protected by the photoresist 50, i.e. in all areas not corresponding to the different active terminals (gate, source and drain) of the transistor 1. The cured photoresist 50 may be removed after the etching, thus giving place to the scenario of Figure 5Q.

[0105] As clearly seen in Figure 5Q, at this stage, a short circuit may exist between the source 5a and the drain 5b regions as the second metallic layer 45 may extend in a continuous manner over the gate structure 2 in the gate region 22. The following steps are addressed at eliminating such short circuit.

[0106] In order to remove the mentioned short circuit, two main steps may be conducted. First, as shown in Figure 5R, a relatively thick planarization layer 60 may be deposited. In an example, the dielectric may comprise silicon dioxide, SiC>2. The thickness of the planarization layer 60 may be at least such that an upper surface of the planarization layer 60 in an area not in the gate region 22 may be at a larger height with respect to the substrate 10 than an upper surface of the gate electrode 30g. This manufacturing step corresponds to the previously mentioned block 215 in the flowchart of Figure 4. In examples, the planarization layer 60 may comprise an oxide material layer.

[0107] Subsequently, and in accordance with block 220 of the flowchart of Figure 4, a chemical mechanical polishing of the planarization layer 60 and the second metallic layer 45 may be carried out as schematically depicted in Figure 5S. In particular, polishing may be carried out until the second metallic layer 45 in the gate region 22 is entirely removed. In this manner, the short circuit between the source region 5a and the drain region 5b may be eliminated by introducing a discontinuity in the second metallic layer 45 in the gate region 22 and by preventing any direct contact between the second metallic layer 45 and the gate electrode 30g, which may become isolated by the spacer dielectric 40g. As a result, and as also shown in Figure 5S, the second metallic layer 45 may only remain in the corresponding source region 5a and drain region 5b, where it may constitute the corresponding source electrode 55a and drain electrode 55b respectively.

[0108] At this stage, a functional transistor 1 may be already achieved. However, in order to facilitate electrical contact to the different terminals, vias may be carried out in the back-end process as shown in Figure 5T. Therefore, vias 75 may be defined in the planarization layer 60 to expose contact portions of the source electrode 55a and the drain electrode 55b. Subsequently, vias 75 may be filled with a conductor, e.g. a metal, to define the electrical contacts 70 for both the source electrode 55a and the drain electrode 55b.

[0109] As shown above, the thickness of the spacer dielectric 40g plays a significant role in the performance and characteristics of the transistor 1. The thickness of this spacer dielectric 40g can be tuned by controlling the operating parameters during the manufacture of the transistor 1. A methodology may be used to calibrate and test the process. An example of such a methodology will be described with reference to Figures 12A and 12B.

[0110] As shown in Figure 12A, a substrate 610 may be provided, and a structure 620 comprising a protruding portion may be provided on the substrate 610. The protruding portion may be equivalent (e.g. in size and shape) to the gate electrode 30g of the transistor 1. Then, a spacer dielectric layer 630 may be conformally deposited. ALD may be used for the deposition and an equivalent process the one used during the manufacture of the transistor 1 may be employed (see, e.g. Fig. 5J above, and corresponding description). By using a conformal deposition process, the thickness, 5S, of the spacer dielectric layer 630 may be substantially uniform. In particular, the same thickness may be obtained on the sidewalks, i.e. on the vertical walls, of the protruding portion of the structure 620, which represents the gate electrode 30g, and on the corresponding horizontal surfaces.

[0111] Subsequently, a controlled and anisotropic Reactive Ion Etching (RIE) process may be carried out. Again, an equivalent process to the one utilized during the fabrication of the transistor 1 may be employed (see, e.g. Fig. 5K above and corresponding description).

[0112] As a result of this process, the spacer dielectric layer 630 may be etched anisotropically. Specifically, as explained with reference to, e.g. Figure 5K above, the anisotropic etching may be designed to etch the spacer dielectric layer 630 in those areas wherein the spacer dielectric layer 630 is substantially parallel to the substrate 610. However, in this case, a protective layer may be arranged on a certain portion of the structure 620. In this manner, as shown schematically in Figure 12B, the spacer dielectric layer 630 may be removed from all regions except from the vertical sidewalls, where it may constitute the spacer dielectric 40g when in a transistor 1, and from the area protected by the protective resin.

[0113] An indirect measurement of the thickness of the spacer dielectric, i.e. of the spacer dielectric layer on the sidewalls of the protruding portion of the structure 620, may be carried out by using the portion of spacer dielectric layer 630 protected by the resin. In particular, as also shown in Figure 12B, the thickness of the spacer dielectric layer 630 may be measured by Atomic Force Microscopy (AFM). The lateral resolution of AFM may not allow the direct measurement of the width of the spacer dielectric layer 630 on the vertical sidewalls. However, the height of the step indicated in Figure 12B (see circled area) may be measured. Bearing in mind that the thickness of the spacer dielectric layer 630 is uniform, the height of the step mayprovide an indirect (but accurate) measurement of the width of the spacer, i.e. of the thickness, 8s, of the spacer dielectric layer 630.

[0114] In order to determine the height of the step shown in Figure 12B, an AFM image of the region of the step (circled in the figure) may be obtained. From said image, the average height at each side of the step, i.e. at the top side of the step and at the bottom side of the step, may be determined. In particular, each of the two sides may be identified by the darkness at each side of the step (darker colour at the bottom side of the step). Subsequently, the difference between those heights may be determined to calculate the height of the step itself which, as mentioned above (and as shown in Fig. 12B), corresponds to the thickness, 8S, of the spacer dielectric layer 630. And, consequently, to the width of the spacer dielectric on the sidewalls of the protruding member of the structure 620, which is equivalent to the spacer dielectric 40g arranged on the sidewalls of the gate electrode 30g of the transistor 1.

[0115] Experimental results obtained according to this methodology are shown in Figures 13A - 13B. As illustrated, the method of the present disclosure allows obtaining spacer dielectrics with widths in the range of 4 to 10 nanometres in a reliable and consistent manner. In particular, spacer dielectrics with thicknesses of 4,8 nm (Fig. 13A), 6,6 nm (Fig. 13B), and 11,4 nm (Fig. 13C) are given as illustrative examples.

[0116] As previously indicated, the use of low-k dielectric materials as spacer dielectric between the gate conductor and the respective source electrode and drain electrode offers technical advantages, especially when dealing with high frequency applications. In that vein, a transistor comprising an air gap between the gate structure and the source and drain electrodes may be beneficial. An air gap is understood as a substantially empty or hollow space between the different parts, i.e. between the gate structure and the source and drain electrodes. Figure 7A schematically illustrates a side view of a transistor 111 with such an air gap, whereas Figure 7B illustrates a top view of the transistor 111. The transistor 111 comprises a substrate 310 and a low dimensional material 320 arranged on the substrate 310. A source electrode 365a is arranged on the low dimensional material 320. A drain electrode 365b is also arranged on the low dimensional material 320. The drain electrode 365b is spaced apart from the source electrode 365a.

[0117] A channel of the transistor 111 is defined by the low dimensional material 320 in a region extending between the source electrode 365a and the drain electrode 365b. Furthermore, the transistor 111 comprises a gate structure 32 arranged on the low dimensional material 320. The gate structure 32 is positioned in an area corresponding to the channel of the transistor 111, i.e. in an area that lies above the channel of the transistor 111. The gatestructure 32 comprises a gate dielectric 330g arranged on the low dimensional material 320. The gate dielectric 330g is arranged within a space defined by the separation between the source electrode 365a and the drain electrode 356b. The gate structure 32 also comprises a gate electrode 340g arranged on the gate dielectric 330g.

[0118] Moreover, the transistor 111 comprises an air gap 400 between the gate electrode 340g and the source electrode 365a and also between the gate electrode 340g and the drain electrode 365b.

[0119] Similarly to the field-effect transistor 1 shown in Figures 1A and 1B, a field-effect transistor 111 with improved performance is also provided in this case. Specifically, the low dimensional material 320 exhibits high carrier mobility, which results in faster switching speeds than conventional transistors based on silicon channels.

[0120] Furthermore, the air gap 400, which may be filled with air or even vacuum, constitutes a very low-k dielectric. Accordingly, very low parasitic capacitances are present in the transistor 111. In particular, by using vacuum, the smallest dielectric constant possible may be obtained. In this manner, very high switching velocities can be obtained with the transistor 111 according to the design of Figures 7A - 7B.

[0121] In order to optimize the footprint of the transistor 111 , a very small air gap 400 may be provided. Hence, in an example, the width of the air gap 400, i.e. the distance between the gate structure 32 or, more particularly, between the gate electrode 340g and either the source electrode 365a or the drain electrode 365b, may be less than 5 nanometres. Specifically, in an example, the width of the air gap 400 may be of approximately 3 nm. The provision of such a small air gap 400 may increase the level of miniaturization of the transistor 111. In order to achieve a transistor 111 with such small features, a process as described below with reference to Figure 8 and Figures 9A - 9T may be employed.

[0122] Different dielectric materials may be used for the gate dielectric 330g of the gate structure 32 in order to optimize the performance of the transistor 111. In particular, the gate dielectric 330g may comprise a high-k dielectric, e.g. AI2O3 (aluminium oxide or alumina) or HfC>2 (hafnium oxide or hafnia). In other examples, two-dimensional (2D) materials such as hBN (hexagonal boron nitride) may be employed.

[0123] As with the transistor 1 described with reference to Figures 1A - 1B, different materials can also be used for the low dimensional material 320 in the transistor 111 of Figures 7A - 7B. These materials may include 1D materials, such as carbon nanotubes, e.g. SWCNT,or WS2 nanotubes. In other cases, the low dimensional material 320 may comprise a two-dimensional material, e.g. graphene, WS2 or M0S2.

[0124] Figure 8 shows a flowchart of a method 500 for manufacturing a planar thin-film transistor 111. Reference will also be made to the numerals used in Figures 9A - 9T to further illustrate the method 500.

[0125] The method 500 comprises, in block 505, providing a low dimensional material 320 on a substrate 310 (Figure 9B). The substrate 310 may comprise, e.g. a silicon wafer. In some examples, a native SiC>2 layer may be provided on the surface of the substrate 310. Specifically, a SiC>2 layer with a thickness of 300 nm may be used. As in previously described examples, different methods, e.g. spin coating, may be used for the deposition of the low dimensional material 320.

[0126] Block 510 comprises depositing a first dielectric layer 330 on the low dimensional material 320 (Figure 9C). The first dielectric layer 330 is configured to act as a gate dielectric 330g of the transistor 111, i.e. the first dielectric layer 330 corresponds to the gate dielectric 330g (see Figures 7A - 7B) when taking into account the portion of the first dielectric layer 330 arranged on the region of the gate structure 32. Atomic Layer Deposition (ALD) may be used for the deposition of the first dielectric layer 330. In an example, AI2O3 may be used for the first dielectric layer 330. In such example, a thickness higher than 1 nm may be used. Specifically, a thickness in a range from 5 nm to 10 nm may be employed. In other examples, the first dielectric layer 330 may comprise 2D materials, e.g. hBN. In such case, a thickness higher than 0,4 nm, e.g. 1 nm, may be selected.

[0127] The method 300 also comprises, in block 515, depositing a first metallic layer 340 on the first dielectric layer 330 (Figure 9D). The first metallic layer 340 is configured to act as a gate electrode 340g of the transistor 111. That is, the first metallic layer 340 corresponds to the gate electrode 340g in the region of the gate structure 32 shown in Figures 7A or 7B. Different metals, e.g. Palladium (Pd), may be used. In examples, the thickness of the first metallic layer 340 may be higher than 5 nm. Specifically, in some examples, a thickness in excess of 15 nm may be selected. Subsequently, in block 520, a second dielectric layer 350 may be deposited on the first metallic layer 340 (Figure 9E). ALD may also be used for the deposition of the second dielectric layer 350. Either the same material or a different material than in the first dielectric layer 330 may be employed. In examples wherein the same material is used for the first dielectric layer 330 and the second dielectric layer 350, the latter may be thicker to facilitate subsequent manufacturing steps.

[0128] A gate region 322 is then defined by means of photolithography in block 525 (Figures 9F-9H). To this end, a photoresist 360 may be deposited on the second dielectric layer 350. The photoresist 360 may be cured to define the gate region 322, and then the non-cured photoresist may be removed (Figure 9H). Upon definition of the gate region 322, the method 500 comprises, in block 530, etching of the first metallic layer 340 and the second dielectric layer 350 until the first dielectric layer 330 except in the gate region 322 (Figure 9I). Reactive Ion Etching (RIE) may be used for the etching. After this etching process, the cured photoresist 360 protecting the gate region 322 may be removed (Figure 9J).

[0129] Method 500 proceeds with the deposition of still a third dielectric layer 370 (Figure 9K) in block 535. ALD may be used for the deposition of the third dielectric layer 370. As shown in Figure 9K, the thickness of the third dielectric layer 370 may be sufficient to completely surround the already formed gate electrode 340g, i.e. the portion of the first metallic layer 340 remaining after previous steps. In an example, the first dielectric layer 330, the second dielectric layer 350, and the third dielectric layer 370 may comprise the same dielectric material. In other examples, different materials may be used for the different layers.

[0130] Block 540 comprises a critical step during the manufacturing method 500. Hence, as shown in Figure 9L, block 540 comprises the etching (both anisotropic and isotropic) of the first 330, second 350, and third 370 dielectric layers. Importantly, as also depicted, the etching is such that the first metallic layer 340 in the gate region 322, i.e. the gate electrode 340g, remains surrounded by dielectric material. Furthermore, the etching is such that the low dimensional material 320 is substantially unetched. In order to achieve such a result, an equivalent etching process to the one described above with reference to block 135 of the method 100 of Figure 2 may be employed. Accordingly, an apparatus 90 like the one schematically depicted in Figure 3 may be used. Hence, in order to achieve the required control and selectivity, a chlorine-based gas may be used. Furthermore, a plasma may be generated in a highly controlled manner by selecting the appropriate power values for the radiofrequency power source(s). Specifically, the etching in block 540 may comprise a combination of a first anisotropic dry etching, which may be carried out with the apparatus 90, and a second isotropic wet etching, e.g. and HF vapor etch.

[0131] Upon etching of the dielectric layers in block 540, next steps are concerned with the manufacturing of the source electrode 365a and the drain electrode 365b of the transistor 111. To this end, a second metallic layer 380 is deposited in block 545 (Figure 9M). Different metals, e.g. Palladium (Pd), Titanium (Ti), or even combinations of these or other metals, can be envisaged in different examples. Subsequently, a source region 355a and a drain region 355b,i.e. the regions in the footprint of the transistor 111 wherein the source electrode 365a and the drain electrode 365b are finally disposed, are defined in block 550.

[0132] The definition of the source region 355a and the drain region 355b may be carried by photolithography as schematically shown in Figures 9N - 9P. In particular, a photoresist 390 may be deposited (Figure 9N) and the photoresist 390 may be cured in the regions corresponding to the source region 355a and the drain region 355b (Figure 90). Said regions may be disposed at opposite sides of the already defined gate region 322. The source region 355a and the drain region 355b may be spaced apart by a longitudinal gap extending in a plane substantially parallel to the substrate 310 and extending in the direction of the previously defined gate region 322. Specifically, the longitudinal gap may exhibit a certain minimum width to ensure electrical isolation between the source region 355a and the drain region 355b. Subsequently, the non-cured photoresist 390 may be removed (Figure 9P), such that only the source region 355a and the drain region 355b may be covered, i.e. protected, by the photoresist 390.

[0133] An etching of the second metallic layer 380 is carried out, e.g. by Reactive Ion Etching (RIE), in all areas except in the source region 355a and the drain region 355b in block 555 (Figure 9Q). This etching results in the formation of the source electrode 365a and the drain electrode 365b. In an example, the low dimensional material 320 may also be etched in the etching carried out in block 555. Subsequently, the photoresist 390 may be removed as depicted in Figure 9R. Next, in block 560, the method 500 comprises an anisotropic etching of the second dielectric layer 350 arranged on top of the first metallic layer 340, i.e. on top of the gate electrode 340g. In particular, block 560 may comprise a RIE etching to remove the second dielectric layer 350 in an area corresponding to the longitudinal gap defined between the source region 355a and the drain region 355b in previous block 550. This is more clearly shown in Figure 9S.

[0134] Then, in order to create the air gap 400 between the gate electrode 340g and each of the source electrode 365a and drain electrode 365b, an isotropic etching may be carried out in block 565 (Figure 9T). This isotropic etching may be configured to substantially remove the dielectric layers arranged at an upper and lateral surface of the remaining first metallic layer 340, i.e. of the gate electrode 340g, while maintaining the first dielectric layer 330 arranged in between the gate electrode 340g and the low dimensional material 320. In other words, the isotropic etching in block 565 may be configured to remove all the dielectric material except for the gate dielectric 330g. However, as also schematically depicted in Figure 9T, the isotropic nature of the etching may result in the formation of undercuts in the gate dielectric 330g.

[0135] In another example, the method 500 may be modified such that the etching processes carried out in blocks 555 and 560 may be combined. In particular, two different recipes may be used, which may be adjusted in real-time. Indeed, after removal of the second metallic layer 380 and the low dimensional material 320, a set of parameters may be changed so as to proceed with the etching of the second dielectric layer 350 in the area corresponding to the longitudinal gap between the source region 355a and the drain region 355b.

[0136] In another variant, the gate dielectric 330g may result from a combination of different dielectric layers. Hence, on top of the first dielectric layer 330, a further dielectric layer may be provided. In this manner, a modified transistor 112, like the one depicted in Figure 10A, may be achieved. Hence, in this example, the dielectric arranged between the gate electrode 340g and the low dimensional material 320 may comprise a first portion resulting from a first dielectric layer 330 (as in the transistor 111 described above) and a second portion 430 resulting from a further dielectric layer deposited on top of the first dielectric layer 330.

[0137] In order to manufacture such a modified transistor 112 and, referring again for support to Figures 9A - 9T, the process may comprise the deposition of a double dielectric layer instead of a single layer in the step depicted in Figure 9C. Hence, instead of depositing only a first dielectric layer 330, a plurality of layers or sub-layers may be deposited. Subsequent steps may be substantially equivalent to those described with reference to Figures 9D to 9H. However, the etching described with reference to Figure 9I may comprise the etching of not only the first metallic layer 340 and the second dielectric layer 350, but also of the newly added further dielectric layer which, in this case, would then result in the portion 430 arranged underneath the gate electrode 340g as also depicted in Figure 10A. From this point on, substantially equivalent manufacturing steps may be carried out except that, in order to produce the modified transistor 112 depicted in Figure 10A, the anisotropic and isotropic etching explained with reference to Figure 9L may be selective, not only in regard to the low dimensional material 320, but also in regard to the newly added further dielectric layer.

[0138] Different materials may be used for the additional layer giving place to the second portion 430 of the gate dielectric in the modified transistor 112 of Figure 10A. Specifically, the additional layer may comprise a high-k material, such as HfC>2. In this manner, the properties of the gate structure 32 may be changed and adjusted for different operational requirements.

[0139] Still another example of a transistor 113 is schematically depicted in Figure 10B. In this example, a capping or top dielectric layer 440 may be arranged on top of the gate electrode 340g. Referring again to Figures 9A - 9T, the manufacture of this modified transistor 113 may comprise an additional manufacturing step between the steps depicted in Figures 9D and 9E.Hence, a new step, comprising the deposition of a capping dielectric layer 440 on the first metallic layer 340 may be included. Different metals and different deposition technologies may be envisaged in an equivalent manner as for the other metallic layers of the device. Subsequently, upon deposition of the second dielectric layer 350, the newly considered capping dielectric layer 440 may be sandwiched between the first metallic layer 340 and the second dielectric layer 350. As a result, the etching shown in Figure 9I, i.e. corresponding to block 530 in Figure 8, may involve not only the etching of the first metallic layer 340 and the second dielectric layer 350, but also of the newly added capping dielectric layer 440.

[0140] The subsequent isotropic and anisotropic etching of dielectrics (Figure 9L or block 540 of Figure 8) may be conducted in a similar manner. However, in this case, only the capping dielectric layer 440 may be maintained on top of the gate electrode 340g. This aspect is also schematically depicted in Figure 10B showing the final modified transistor 113.

[0141] The manufacturing process may continue as in the previous examples, except that the last step needed in this example may correspond to Figure 9R. Hence, in this modified transistor 113, no air gaps are generated. Conversely, the dielectric material surrounding the gate electrode 340g, which includes the capping dielectric layer 440, is kept in the device. Accordingly, the final steps of Figures 9S and 9T are not carried out. In this modified transistor 113, the space between the gate electrode 340g and the source electrode 365a and drain electrode 365b is not empty but filled with a dielectric. This may result in a simplification of the manufacturing process. Even if the presence of a dielectric may induce higher parasitic capacitances than in previously shown transistors 111, 112, this modified transistor 113 may still be useful for less demanding applications.

[0142] The modified transistor 113 (Figure 10B) may also incorporate the concept of the previously discussed transistor 112 (Figure 10A). Therefore, apart from the capping dielectric layer 440, a double structure may be provided for the gate dielectric also in this case.

[0143] Still a further variation is illustrated in the transistor 114 of Figure 10C. In this further example of a transistor 114, a protection dielectric layer 450 may be included to protect the gate region during the manufacturing process. Specifically, and as shown in Figure 11 A, such a protection dielectric layer 450 may be deposited after the manufacturing step schematically depicted in Figure 9K, i.e. after the deposition of the third dielectric layer 370. Subsequently, as illustrated in Figures 11 B, a selective and anisotropic etching may be carried out to remove different dielectric layers up to a certain extent, i.e. up to an extent such that the gate electrode 340g is still surrounded by dielectric material. A further etching, in this case isotropic, may be carried out as depicted in Figure 11C. However, the isotropic etching may be selective, suchthat the protection dielectric layer 450 may not be affected by the same. After the situation depicted in Figure 11C, manufacturing steps equivalent to those described with reference to Figures 9M to 9R may be implemented to achieve the transistor 114 depicted in Figure 10C. In particular, the deposition of the second metallic layer 380 in the equivalent step to the one depicted in Figure 9M may be highly directional, i.e. by means of sputtering.

[0144] As with the previous case, the modified transistor 114 may also be combined with the modified transistor 111 shown in Figure 10A. Hence, a double gate dielectric structure may also be provided comprising both a first portion based on a first dielectric layer 330, and a second portion 430 based on a further deposited dielectric layer. Such a combination may result in another example of a transistor 115, as schematically depicted in Figure 10D.

[0145] For reasons of completeness, various aspects of the present disclosure are set out in the following numbered clauses:Clause 1. A planar thin film transistor, comprising:a substrate;a low dimensional material arranged on the substrate;a source electrode arranged on the low dimensional material;a drain electrode arranged on the low dimensional material;a channel of the transistor being defined by the low dimensional material in a region extending between the source electrode and the drain electrode;a gate structure arranged on the low dimensional material in a region corresponding to the channel of the transistor, the gate structure comprising:a gate dielectric arranged on the low dimensional material and extending from the source electrode to the drain electrode,a gate electrode arranged on the gate dielectric, anda spacer dielectric arranged on the gate dielectric in a first space between the gate electrode and the source electrode and in a second space between the gate electrode and the drain electrode.Clause 2. The transistor of clause 1, wherein a thickness of the spacer dielectric is less than 1500 nanometres, specifically less than 25 nanometres.Clause 3. The transistor of any of clauses 1 or 2, wherein the low dimensional material comprises a carbon-based low dimensional material.Clause 4. The transistor of any previous clause, wherein the spacer dielectric comprises a low-k material.Clause 5. The transistor of any previous clause, wherein the gate dielectric comprises a first layer and a second layer, the first layer comprising a first dielectric arranged on the low dimensional material, and the second layer comprisign a second dielectric arranged on the first layer.Clause 6. The transistor of clause 5, wherein the first dielectric comprises a post-transition metal oxide, a transition metal oxide, or a fluorocarbon polymer, and further wherein the second dielectric comprises a high-k dielectric.Clause 7. The transistor of any previous clause, wherein the low dimensional material comprises a one-dimensional material.Clause 8. The transistor of clause 7, wherein the low dimensional material comprises a single carbon nanotube, and further wherein the first electrode and the second electrode are arranged at opposing ends on the carbon nanotube.Clause 9. The transistor of any of clauses 1 to 6, wherein the low dimensional material comprises a two-dimensional material.Clause 10. A method for manufacturing a planar thin-film transistor, the method comprising:providing a low dimensional material on a substrate;depositing a first gate dielectric layer on the low dimensional material, the first gate dielectric layer being configured to act as a gate dielectric;depositing a first metallic layer on the first gate dielectric layer, the first metallic layer being configured as a gate conductor;defining a gate region by photolithography;etching the first metallic layer except in the defined gate region;conformally depositing a spacer dielectric material layer;anisotropically etching the first gate dielectric layer and the spacer dielectric material layer in a direction substantially perpendicular to the substrate such that the first gate dielectric layer and the spacer dielectric material layer are selectively removed in regions wherein the layer of spacer dielectric material is arranged substantially parallel to the substratesubstantially without etching the underlying low dimensional material , whereas the spacer dielectric material layer and the first gate dielectric layer are substantially unetched in the regions wherein the layer of spacer dielectric material is arranged substantially perpendicular to the substrate;conformally depositing a second metallic layer, the second metallic layer being configured as a source electrode and as a drain electrode;defining a source region and a drain region at opposed ends of the gate region by photolithography; andetching the second metallic layer except in the defined source and drain regions.Clause 11. The method of clause 10, wherein providing the low dimensional material on the substrate comprises providing a carbon-based low dimensional material.Clause 12. The method of any of clauses 10 or 11, wherein anisotropically etching the first gate dielectric layer and the spacer dielectric material layer comprises:placing the substrate in a substrate holder in a vacuum chamber;introducing a chlorine-based gas in the vacuum chamber; andconnecting a radiofrequency power source to the substrate, the radiofrequency power source being operated at a power such that a power density of less than 0.19 W / cm2is obtained when dividing the radiofrequency power by the substrate area.Clause 13. The method of any of clauses 10 to 12, comprising depositing a second gate dielectric layer on the first gate dielectric layer, the first and second gate dielectrics layers being configured to act as a gate dielectric, wherein the first gate dielectric layer comprises a low-k dielectric material and the second gate dielectric layer comprises a high-k dielectric material.Clause 14. The method of clause 13, comprising etching the second gate dielectric layer with a dry etching process, and selectively etching the first dielectric layer with wet etching.Clause 15. The method of any of clauses 10 to 14, wherein conformally depositing a spacer dielectric material layer comprises depositing a plurality of sub-layers of different dielectric materials.Clause 16. The method of clause 15, wherein anisotropically etching the first gate dielectric layer and the spacer dielectric material layer comprises using different etching parameters for the plurality of sub-layers forming the spacer dielectric layer.Clause 17. The method of any of clauses 10 to 16, wherein etching the second metallic layer except in the defined source and drain regions comprises:etching the second metallic layer and the low dimensional material except in the areas defined by the gate region, the source region, and the drain region, by using a photoresist used to define the source and drain regions by photolithography as a mask;removing the photoresist;depositing a planarization oxide layer;carrying out chemical mechanical polishing of the planarization oxide layer and the second metallic layer until the second metallic layer in the gate region is entirely removed.Clause 18. A planar thin film transistor, comprising:a substrate;a low dimensional material arranged on the substrate;a source electrode arranged on the low dimensional material;a drain electrode arranged on the low dimensional material;a channel of the transistor being defined by the low dimensional material in a region extending between the source electrode and the drain electrode;a gate structure arranged on the low dimensional material and positioned in an area corresponding to the channel of the transistor, the gate structure comprising:a gate dielectric arranged on the low dimensional material, the gate dielectric being arranged in a space between the source electrode and the drain electrode, a gate electrode arranged on the gate dielectric,the transistor comprising an air gap between the gate electrode and the source electrode and between the gate electrode and the drain electrode.Clause 19. The planar thin film transistor of clause 18, wherein the low dimensional material arranged on the substrate comprises a carbon-based low dimensional material.Clause 20. The planar thin film transistor of any of clauses 18 or 19, wherein the airgap is filled with air.Clause 21. The planar thin film transistor of any of clauses 18 or 19, wherein the air gap is in a vacuum.Clause 22. The planar thin film transistor of any of clauses 18 to 21 , wherein a width of the air gap, defined as a distance from the gate electrode to any of the source electrode and the drain electrode, is less than 5 nanometres, specifically wherein the width of the air gap is of approximately 3 nanometres.Clause 23. The planar thin film transistor of any of clause 18 to 22, wherein the gate dielectric comprises a first layer of a first dielectric arranged on the low dimensional material, and a second layer of a second dielectric arranged on the first layer.Clause 24. The planar thin film transistor of clause 23, wherein the first dielectric comprises a post-transition metal oxide, a transition metal oxide, or a fluorocarbon polymer, and further wherein the second dielectric comprises a high-k dielectric.Clause 25. The planar thin film transistor of any of clauses 18 to 24, wherein the low dimensional material comprises a one-dimensional material.Clause 26. The planar thin film transistor of clause 25, wherein the low dimensional material comprises a single carbon nanotube, and further wherein the first electrode and the second electrode are arranged at opposing ends on the carbon nanotube.Clause 27. The planar thin film transistor of any of clauses 18 to 24, wherein the low dimensional material comprises a two-dimensional material.Clause 28. A method for manufacturing a planar thin-film transistor, the method comprising:providing a low dimensional material on a substrate;depositing a first dielectric layer on the low dimensional material, the first gate dielectric layer being configured to act as a gate dielectric;depositing a first metallic layer on the first dielectric layer, the first metallic layer being configured as a gate conductor;depositing a second dielectric layer on the first metallic layer;defining a gate region by photolithography;etching the first metallic layer and the second dielectric layer until the first dielectric layer except in the defined gate region;depositing a third dielectric layer;anisotropically etching the first, second, and third dielectric layers, while leaving the low dimensional material substantially unetched, and while maintaining at least some dielectric material surrounding the first metallic layer in the gate region;depositing a second metallic layer;defining a source region and a drain region at opposed ends of the gate region by photolithography, the source region and the drain region being separated by a longitudinal gap extending in the direction of the gate region;etching the second metallic layer except in the defined source and drain regions; anisotropically etching the second dielectric layer arranged on top of the first metallic layer in an area corresponding to the longitudinal gap separating the source region and the drain region; andisotopical ly etching the second dielectric layer and the third dielectric layer to remove the dielectric material arranged in an upper and lateral surfaces of the first metallic layer, while maintaining the first dielectric layer arranged between low dimensional material and first metallic layer.Clause 29. The method of clause 28, wherein providing the low dimensional material on the substrate comprises providing a carbon-based low dimensional material.Clause 30. The method of any of clauses 28 or 29, wherein the first dielectric layer and the second dielectric layer comprise the same dielectric material.Clause 31. The method of clause 30, wherein a thickness of the second dielectric layer is larger than a thickness of the first dielectric layer.Clause 32. The method of any of claims 28 to 31, wherein anisotropically etching the first, second, and third dielectric layers, comprises:placing the substrate in a substrate holder in a vacuum chamber;introducing one or more chlorine-based gases in the vacuum chamber;connecting a radiofrequency power source to the substrate, the radiofrequency power source being operated at a power such that a power density of less than 0.19 W / cm2is obtained when dividing the radiofrequency power by an area of the substrate.Clause 33. The method of clause 32, comprising adjusting a pressure in the vacuum chamber to a predetermined value.Clause 34. The method of any of clauses 28 to 33, comprising etching the low dimensional material in all areas not corresponding to the source region, the drain region, or the gate region.Clause 35. The method of any of clause 28 to 34, wherein etching the second metallic layer except in the defined source and drain regions, and anisotropically etching the second dielectric layer arranged on top of the first metallic layer in an area corresponding to the longitudinal gap separating the source region and the drain region, comprises etching in a single etching process.Clause 36. The method of clause 35, wherein a different set of parameters are used for the etching of the second metallic layer than for the etching of the second dielectric layer.Clause 37. The method of any of clause 28 to 36, wherein a further dielectric layer is deposited on top of the first dielectric layer, the first and the further dielectrics layers being configured to act as a gate dielectric.Clause 38. The method of clause 37, wherein the first dielectric layer comprises a low-k dielectric material and the further dielectric layer deposited on top of the first dielectric layer comprises a high-k dielectric material.Clause 39. The method of any of clauses 37 or 38, wherein etching the first metallic layer and the second dielectric layer until the first dielectric layer except in the defined gate region comprises etching also the further dielectric layer except in the defined gate region.Clause 40. The method of clause 39, wherein anisotropically etching the first, second, and third dielectric layers, while leaving the low dimensional material substantially unetched, and while maintaining at least some dielectric material surrounding the first metallic layer in the gate region, comprises etching such that the remaining further dielectric layer is also substantially unetched.Clause 41. The method of any of clause 28 to 40, comprising depositing a protection dielectric layer on top of the third dielectric layer.Clause 42. The method of clause 41, wherein anisotropically etching the first, second, and third dielectric layers, while leaving the low dimensional material substantially unetched, and while maintaining at least some dielectric material surrounding the first metallic layer in thegate region, comprises a first step comprising anisotropically etching also the protection dielectric layer, followed by a second step comprising isotropically etching the first, second and third dielectric layers while leaving the remaining protection layer substantially unetched.Clause 43. A planar thin film transistor, comprising:a substrate;a low dimensional material arranged on the substrate;a source electrode arranged on the low dimensional material;a drain electrode arranged on the low dimensional material, the drain electrode being spaced apart from the source electrode;a channel of the transistor being defined by the low dimensional material in a region extending between the source electrode and the drain electrode;a gate structure arranged on the low dimensional material and contained in an area corresponding to the channel of the transistor, the gate structure comprising:a gate dielectric arranged on the low dimensional material, the gate dielectric being arranged in a space between the source electrode and the drain electrode, a gate electrode arranged on the gate dielectric, anda capping dielectric arranged on the gate electrode.Clause 44. The planar thin film transistor of clause 43, wherein the low dimensional material arranged on the substrate comprises a carbon-based low dimensional material.Clause 45. The transistor of any of clauses 43 or 44, wherein the low dimensional material comprises a one-dimensional material.Clause 46. The transistor of clause 45, wherein the low dimensional material comprises a single carbon nanotube, and wherein the first electrode and the second electrode are arranged at opposing ends on the carbon nanotube.Clause 47. The transistor of any of clauses 43 or 44, wherein the low dimensional material comprises a two-dimensional material.Clause 48. A method for manufacturing a planar thin-film transistor, the method comprising:providing a low dimensional material on a substrate;depositing a first dielectric layer on the low dimensional material, the first gate dielectric layer being configured to act as a gate dielectric;depositing a first metallic layer on the first dielectric layer, the first metallic layer being configured as a gate conductor;depositing a capping dielectric layer on the first metallic layer;depositing a second dielectric layer on the top dielectric layer;defining a gate region by photolithography;etching the first metallic layer, the capping dielectric layer, and the second dielectric layer until the first dielectric layer except in the defined gate region;depositing a third dielectric layer;anisotropically etching the first, second, and third dielectric layers, while leaving the low dimensional material substantially unetched, and while maintaining only the capping dielectric on top of the first metallic layer in the gate region;depositing a second metallic layer;defining a source region and a drain region at opposed ends of the gate region by photolithography, the source region and the drain region being separated by a longitudinal gap extending in the direction of the gate region;etching the second metallic layer except in the defined source and drain regions.Clause 49. The method of clause 48, wherein providing the low dimensional material on the substrate comprises providing a carbon-based low dimensional material.

[0146] This written description uses examples to disclose the teaching, including the preferred embodiments, and also to enable any person skilled in the art to practice the teaching, including making and using any devices or systems and performing any incorporated methods. The patentable scope is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal languages of the claims. Aspects from the various embodiments described, as well as other known equivalents for each such aspects, can be mixed and matched by one of ordinary skill in the art to construct additional embodiments and techniques in accordance with principles of this application. If reference signs related to drawings are placed in parentheses in a claim, they are solely for attempting to increase the intelligibility of the claim and shall not be construed as limiting the scope of the claim.

Claims

44CLAIMS1. A planar thin film transistor, comprising:a substrate;a low dimensional material arranged on the substrate;a source electrode arranged on the low dimensional material;a drain electrode arranged on the low dimensional material;a channel of the transistor being defined by the low dimensional material in a region extending between the source electrode and the drain electrode;a gate structure arranged on the low dimensional material in a region corresponding to the channel of the transistor, the gate structure comprising:a gate dielectric arranged on the low dimensional material and extending from the source electrode to the drain electrode,a gate electrode arranged on the gate dielectric, anda spacer dielectric arranged on the gate dielectric, the spacer dielectric being arranged in a first space between the gate electrode and the source electrode, and in a second space between the gate electrode and the drain electrode,wherein a thickness of the spacer dielectric is between 4 and 25 nanometres.

2. A planar thin film transistor, comprising:a substrate;a low dimensional material arranged on the substrate;a source electrode arranged on the low dimensional material;a drain electrode arranged on the low dimensional material;a channel of the transistor being defined by the low dimensional material in a region extending between the source electrode and the drain electrode;a gate structure arranged on the low dimensional material in a region corresponding to the channel of the transistor, the gate structure comprising:a gate dielectric arranged on the low dimensional material and extending from the source electrode to the drain electrode,a gate electrode arranged on the gate dielectric, anda spacer dielectric arranged on the gate dielectric, the spacer dielectric being arranged in a first space between the gate electrode and the source electrode, and in a second space between the gate electrode and the drain electrode,wherein the spacer dielectric comprises a low-k material, and further wherein the first space and the second space exhibit a substantially constant width as measured in45a direction parallel to the substrate, and the spacer dielectric is flush with the gate dielectric.

3. The transistor of any of claims 1 or 2, wherein the low dimensional material is a carbonbased low dimensional material.

4. The transistor of any previous claim, wherein the gate dielectric comprises a first layer and a second layer, the first layer comprisign a first dielectric arranged on the low dimensional material; and the second layer comprising a second dielectric arranged on the first layer.

5. The transistor of claim 4, wherein the first dielectric comprises a post-transition metal oxide, a transition metal oxide, or a polymer, and further wherein the second dielectric comprises a high-k dielectric.

6. The transistor of any previous claim, wherein the low dimensional material comprises a one-dimensional material.

7. The transistor of claim 6, wherein the low dimensional material comprises a single carbon nanotube, and further wherein the first electrode and the second electrode are arranged at opposing ends on the carbon nanotube.

8. The transistor of any of claims 1 to 5, wherein the low dimensional material comprises a two-dimensional material.

9. A method for manufacturing a planar thin-film transistor, the method comprising:providing a low dimensional material on a substrate;depositing a first gate dielectric layer on the low dimensional material, the first gate dielectric layer being configured to act as a gate dielectric;depositing a first metallic layer on the first gate dielectric layer, the first metallic layer being configured as a gate conductor;defining a gate region;etching the first metallic layer except in the defined gate region;conformally depositing a spacer dielectric material layer;anisotropically etching the first gate dielectric layer and the spacer dielectric material layer in a direction substantially perpendicular to the substrate such that the first gate dielectric layer and the spacer dielectric material layer are selectively removed in regions wherein the46layer of spacer dielectric material is arranged substantially parallel to the substrate substantially without etching the underlying low dimensional material, whereas the spacer dielectric material layer and the first gate dielectric layer are substantially unetched in regions wherein the spacer dielectric material layer is arranged substantially perpendicular to the substrate;conformally depositing a second metallic layer, the second metallic layer being configured as a source electrode and as a drain electrode;defining a source region and a drain region at opposed ends of the gate region by photolithography; andetching the second metallic layer except in the defined source and drain regions.

10. The method of claim 9, wherein anisotropically etching the first gate dielectric layer and the spacer dielectric material layer comprises:placing the substrate in a substrate holder in a vacuum chamber;introducing a chlorine-based gas in the vacuum chamber; andconnecting a radiofrequency power source to the substrate, the radiofrequency power source being operated at a power such that a power density of less than 0.19 W / cm2 is obtained when dividing the radiofrequency power by an area of the substrate.

11. The method of any of claims 9 or 10, comprising depositing a second gate dielectric layer on the first gate dielectric layer, the first and second gate dielectrics layers being configured to act as a gate dielectric, wherein the first gate dielectric layer comprises a low-k dielectric material and the second gate dielectric layer comprises a high-k dielectric material.

12. The method of claim 11, comprising etching the second gate dielectric layer with a dry etching process, and selectively etching the first dielectric layer with wet etching.

13. The method of any of claims 9 to 12, wherein conformally depositing a spacer dielectric material layer comprises depositing a plurality of sub-layers of different dielectric materials.

14. The method of claim 13, wherein anisotropically etching the first gate dielectric layer and the spacer dielectric material layer comprises using different etching parameters for the plurality of sub-layers forming the spacer dielectric layer.

15. The method of any of claims 9 to 14, wherein etching the second metallic layer except in the defined source and drain regions comprises:etching the second metallic layer and the low dimensional material except in the areas defined by the gate region, the source region, and the drain region, by using a photoresist used to define the source and drain regions by photolithography as a mask;removing the photoresist;depositing a planarization oxide layer;carrying out chemical mechanical polishing of the planarization oxide layer and the second metallic layer until the second metallic layer in the gate region is entirely removed.

16. A planar thin film transistor, comprising:a substrate;a low dimensional material arranged on the substrate;a source electrode arranged on the low dimensional material;a drain electrode arranged on the low dimensional material;a channel of the transistor being defined by the low dimensional material in a region extending between the source electrode and the drain electrode;a gate structure arranged on the low dimensional material and positioned in an area corresponding to the channel of the transistor, the gate structure comprising:a gate dielectric arranged on the low dimensional material, the gate dielectric being arranged in a space between the source electrode and the drain electrode, a gate electrode arranged on the gate dielectric,the transistor comprising an air gap between the gate electrode and the source electrode and between the gate electrode and the drain electrode.

17. The planar thin film transistor of claim 16, wherein the low dimensional material arranged on the substrate comprises a carbon-based low dimensional material.

18. The planar thin film transistor of any of claims 16 or 17, wherein the air gap is filled with air.

19. The planar thin film transistor of any of claims 16 or 17, wherein the air gap is in a vacuum.

20. The planar thin film transistor of any of claims 16 to 19, wherein a width of the air gap, defined as a distance from the gate electrode to any of the source electrode and the drain electrode, is less than 5 nanometres, specifically wherein the width of the air gap is of approximately 3 nanometres.

21. The planar thin film transistor of any of claims 16 to 20, wherein the gate dielectric comprises a first layer of a first dielectric arranged on the low dimensional material, and a second layer of a second dielectric arranged on the first layer.

22. The planar thin film transistor of claim 21, wherein the first dielectric comprises a posttransition metal oxide, a transition metal oxide, or a fluorocarbon polymer, and further wherein the second dielectric comprises a high-k dielectric.

23. The planar thin film transistor of any of claims 16 to 22, wherein the low dimensional material comprises a one-dimensional material.

24. The planar thin film transistor of claim 23, wherein the low dimensional material comprises a single carbon nanotube, and further wherein the first electrode and the second electrode are arranged at opposing ends on the carbon nanotube.

25. The planar thin film transistor of any of claims 16 to 24, wherein the low dimensional material comprises a two-dimensional material.

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