A semiconductor package, a semiconductor die, and methods of manufacturing.

Abstract

An encapsulated semiconductor package and a method of manufacturing thereof, the semiconductor comprising a substrate having a first substrate surface and a second substrate surface opposite to the first substrate surface, a semiconductor die having a first die surface and a second die surface opposite to the first die surface, the semiconductor die being mounted with its first die surface to the second substrate surface, and a bond clip electrically mounted to at least one clip mounting area of the semiconductor die using a solder material deposited on the at least one clip mounting area, wherein at least one solder barrier is provided adjacent to the at least one clip mounting area.

Description

[0001] TITLE

[0002] A semiconductor package, a semiconductor die, and methods of manufacturing.

[0003] BACKGROUND

[0004] Semiconductor packages are essential components in modern-day life, wherein one or more semiconductor chips (known as dies) are housed to protect the delicate chips, to manage their temperature, and to facilitate electrical connection.

[0005] To create internal connections, the semiconductor die is connected to a lead terminal by means of a bond clip or a bond wire. To ensure a proper mechanical and electrical connection solder is used to interface the respective two components. Solder is advantageous since it can be melted during application relatively easily. However, because of that low melting point, the solder may also melt during (harsh / lengthy) operation of the semiconductor package. This has resulted in the observation of solder residue at the edges of the semiconductor die of in-field tested semiconductor packages.

[0006] Solder residue at the edges of the semiconductor die can create an electrical connection between the two surface sides of the semiconductor die, thereby shorting and bypassing the semiconductor die which would cause the semiconductor package to malfunction.

[0007] SUMMARY OF THE INVENTION

[0008] It is accordingly the objective of the current disclosure to provide a semiconductor package, a semiconductor die, and methods of manufacturing, which ensure that liquified solder has reduced changes of reaching the side edges of a semiconductor die during operation.

[0009] In a first aspect, the disclosure pertains to an encapsulated semiconductor package comprising a substrate having a first substrate surface and a second substrate surface opposite to the first substrate surface, and a semiconductor die having a first die surface and a second die surface opposite to the first die surface, the semiconductor die being mounted with its first die surface to the second substratesurface. The semiconductor package further comprises a bond clip electrically mounted to at least one clip mounting area of the semiconductor die using a solder material deposited on the at least one clip mounting area. In addition, at least one solder barrier is provided adjacent to the at least one clip mounting area.

[0010] With this configuration, the at least one solder barrier can contain liquified solder in the semiconductor package and ensures that the solder cannot creep or flow towards the edges of the semiconductor die, thereby mitigating the risk of shortcircuiting and malfunctioning of the semiconductor package.

[0011] A solder barrier can be understood as a protrusion extending from the semiconductor die surface side in a substantially upward direction towards the bond clip. Preferably, the solder barrier does not touch or abut the bond clip, thereby leaving some open area for gasses and residuals to escape during the reflow soldering manufacturing process.

[0012] In a particular configuration the at least one solder barrier encompasses the at least one clip mounting area. In some cases, the solder may flow towards a preferred direction, like underneath the bond clip. In such configuration at least one solder barrier only protecting that side of the semiconductor die in which direction solder flow is most likely to occur, would already suffice. However, because of orientation of the semiconductor die or other reasons, the preferred flow / creep direction of the solder may be unknown, and in those cases, it may be advantageous to provide at least one solder barrier encompassing or surrounding the at least one clip mounting area, such that regardless the flow / creep direction the solder will always be maintained in the clip bonding area.

[0013] Typical dimensions of such solder barrier may be in the range of 1-100 pm high and 1-100 pm wide, preferably between 5-50 pm high and 5-50 pm wide. A crosssection of the solder barrier may have the shape of a square, rectangle, triangle, parallelogram or the like.

[0014] When viewed from a top side of the semiconductor die, the clip mounting area may take up some area arranged to receive solder material and a bond clip. This area may have the shape or a square, rectangle, triangle, circle, ellipse, (all with or without rounded edges) or a free-form and the at least one solder barrier encompassing the clip mounting area may have a similar configuration.In an advantageous example, the at least one solder barrier comprises a plurality of solder barriers. It is noted that the at least one clip mounting can be a plurality of clip mounting areas, each intended to accommodate a semiconductor die with solder material. Such configuration would require a plurality of solder barriers for each clip mounting areas. However, also one clip mounting area may comprise a plurality of solder barriers. A plurality of solder barriers is advantageous since capillary forces may urge or flow the liquified solder over a barrier, thereby lessening the protective properties of the solder barrier.

[0015] In particular, the interspacing between the plurality of solder barriers may be chosen such that the solder material is caught in between neighbouring solder barriers, due to capillary forces.

[0016] In particular, the plurality of solder barriers is arranged in a concentric configuration, encompassing or surrounding each other and the clip mounting area. It has been found that this concentric configuration is particularly beneficial, since it may ensure equal distancing along the entire outer perimeter of the solder barrier, such that there is no particular preferable portion for solder to collect into or flow / creep towards. Otherwise, changes of overflowing the solder barriers would be more prominent on that portion of the solder barrier.

[0017] In a further example, the clip mounting area is provided with at least one coating layer between the semiconductor die and the deposited solder material. The at least one coating layer may be utilized for improving the adhesion of the bond clip to the semiconductor die. Furthermore, the at least one coating layer may also facilitate better adhesion of the at least one solder barrier. In a preferred example, the at least one coating layer is provided on the second die surface.

[0018] In addition, a further coating layer may be provided between the at least one coating layer and the deposited solder material. A further coating layer may be provided having slightly different dimensions to the at least one coating layer. Furthermore, said further coating layer may also be used to further improve the adhesion of the bond clip to the semiconductor die. The expert in the field would understand that going from a semiconductor material to a metal bond clip would need a few transitions for properly matching material properties. When these are not matches delamination of issues with heat dissipation may arise.It should be understood that a semiconductor package may be provided with more than one semiconductor die and more than one bond clip. The wording of these two features according to the disclosure should thus not be considered limiting. Any plurality of semiconductor dies may be provided with at least one solder barrier to ensure that solder cannot creep towards the edges of said semiconductor die.

[0019] The present disclosure also pertains to a semiconductor die composed of a piece of semiconductor material having a first die surface and a second die surface opposite to the first die surface, wherein the semiconductor material comprises at least one clip mounting area structured to receive a solder material and structured to receive at least one bond clip, wherein at least one solder barrier is provided adjacent to the at least one clip mounting area.

[0020] Preferably, the at least one solder barrier encompasses at least one the clip mounting area and more in particular the at least one solder barrier comprises a plurality of solder barriers. The plurality of solder barriers is arranged in a concentric arrangement. The concentric arrangement is particularly beneficial, since it may ensure equal distancing along the entire outer perimeter of the solder barrier, such that there is no particular preferable portion for solder to collect into or flow / creep towards. Otherwise, changes of overflowing the solder barriers would be more prominent on that portion of the solder barrier.

[0021] Similarly, the at least one clip mounting area is provided with at least one coating layer between the semiconductor die and the deposited solder material, and additionally a protective layer may be provided covering the at least one solder barrier.

[0022] It is noted that in a further example of the semiconductor package or semiconductor die according to the disclosure, the at least one clip mounting area is smaller than the area of the second die surface. Preferably the at least one clip mounting area is smaller than the area of the second die surface of the semiconductor die. This is to ensure that there is still some area remaining for the at least solder barrier. Furthermore, it is preferable that the at least one clip mounting area is not adjacent to an edge of the semiconductor die.

[0023] It has been found that it is advantageous that the at least one solder barrier is made of an advanced ceramic or high performance polymer or compound (e.g. nonconducting polymer-ceramic compound) material selected from a list of advanced ceramic or high performance polymers such as: polyimide (PI), polyamide (PA),polytetrafluoroethylene (PTFE), polyetheretherketone (PEEK) polyphenylene benzobisoxazole (PBO), polybenzoxazole (PBO), polyaryletherketone (PAEK), polybenzimidazole (PBI), polyethersulfone (PES), polycarbonate (PC), polysulfone (PSU), benzocyclobutene (BCB) or polyvinyl chloride (PVC). These are materials that are mechanically sturdy and compatible to be pattern die top surface, furthermore they are not solvable in flux-removing solvents and are capable of withstanding heat during operation of the semiconductor package or during reflow soldering.

[0024] The present disclosure also pertains to a method of manufacturing a semiconductor die according to the disclosure, the method comprises the steps of providing a piece of semiconductor material having at least one clip mounting area; and forming at least one solder barrier adjacent to the at least one clip mounting area.

[0025] In particular, the forming of the at least one solder barrier is performed by means of photolithography. Photolithography is a cost efficient and high-resolution technique for manufacturing the at least one solder barrier, allowing the at least one solder barrier to be formed during the manufacturing process of a semiconductor die.

[0026] Additionally, the method of manufacturing a semiconductor die according to the disclosure may further comprise the step of providing a protective layer covering the at least one solder barrier. A protective layer may be provided on the at least one solder barrier to protect the solder barrier during reflow soldering. During this process it is known that residuals, like solder balls or gasses are formed, which may affect the surfaces of the at least one solder barrier. This would result in non-pristine surfaces for the semiconductor package during operation, which are more likely to attract liquified solder.

[0027] The protective layer can be made of a photoresist material chosen from a list of poly(methyl methacrylate), PMMA; poly(vinyl alcohol), PVA; methyl methacrylate, MMA; DNQ-Novolax, or other conventional photoresists comprising a resin, a sensitizer and a solver; and mixtures thereof. These are preferably polymers which are soluble in flux-removing solvents.

[0028] The disclosure also pertains to a method of manufacturing a semiconductor package. The method comprises the steps of:

[0029] - providing a substrate having a first substrate surface and a second substrate surface opposite to the first substrate surface;- mounting a semiconductor die according to the disclosure with its first die surface to the second substrate surface;

[0030] - depositing a solder material on the at least one clip mounting area;

[0031] - mounting a bond clip electrically to the at least one clip mounting area of the semiconductor die;

[0032] - removing the protective layer covering the at least one solder barrier of the semiconductor die; and

[0033] - encapsulating the substrate, the semiconductor die, the at least one solder barrier, and the bond clip.

[0034] BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The disclosure will now be discussed with reference to the drawings, which show in:

[0036] Figure 1 a first example of a semiconductor package according to the disclosure;

[0037] Figure 2 a second example of a semiconductor package according to the disclosure;

[0038] Figures 3a and 3b examples of a semiconductor die according to the disclosure;

[0039] Figure 4 a top view of an example of a semiconductor die according to the disclosure.

[0040] DETAILED DESCRIPTION OF THE DISCLOSURE

[0041] For a proper understanding of the disclosure, in the detailed description below corresponding elements or parts of the disclosure will be denoted with identical reference numerals in the drawings.

[0042] Figure 1 a first example of a semiconductor die 50i according to the disclosure, incorporated in a semiconductor package 10i according to the disclosure. Figure 2 depicts a second example of a semiconductor die 502according to the disclosure, incorporated in a second example of a semiconductor package 102according to the disclosure.In both the first example and in the second example of an encapsulated semiconductor package a substrate 11 is implemented. The substrate 11 has a first substrate surface 11a and a second substrate surface 11b opposite to the first substrate surface 11a. Reference numeral 50i (5O2) denotes a first example (Figure 1) as well as a second example (Figure 2) of a semiconductor die according to the disclosure. The semiconductor die 50i (5O2) has a first die surface 50a and a second die surface 50b opposite to the first die surface 50a. As shown in both Figures 1 and 2, the semiconductor die 50i (5O2) is mounted with its first die surface 50a to the second substrate surface 11b. As shown in the figures, in particular Figures 3a and 3b, the semiconductor die 50i is provided on its second die surface 50b with a clip mounting area 51. It is evident, that the at least one clip mounting area 51 is smaller than the area of the second die surface 50b of the semiconductor die 50i (5O2). The at least one clip mounting area 51 serves as the area where a bond clip is to be mounted. Accordingly, the semiconductor package 10i further comprises a bond clip 12 which is electrically and mechanically mounted to the clip mounting area 51 of the semiconductor die 50i (5O2). The mounting is done with the use of a solder material 13 that is deposited on the at least one clip mounting area 51 during the manufacturing steps of the semiconductor package.

[0043] In the prior art semiconductor packages, an encapsulant 14 is used to encapsulate the lead frame 11 (at least partly), the semiconductor die 50 (entirely), the bond clip 12 (at least partly) as well as other lead frame terminals (not shown). The expert in the field would understand that a semiconductor package may further comprise lead terminals, a gate, a source, electronic circuitry on the semiconductor and / or the substrate, and an encapsulant substantially encapsulating the semiconductor package, but at least exposing the lead terminals.

[0044] In addition to the known encapsulated semiconductor package, also at least one solder barrier 52 is provided adjacent to the at least one clip mounting area 51. This at least one barrier is denoted with reference numeral 52. The at least one solder barrier 52 serves to contain or obstruct liquified solder 13 in the semiconductor package 10i (IO2) and prevents the liquified solder from creeping or flowing towards the side edges 50c of the semiconductor die 50i (5O2). The at least one solder barrier 52 thus mitigates the risk of short-circuiting and malfunctioning of the semiconductor package 10i (IO2).The solder barrier 52 is formed as a protrusion extending from the semiconductor die surface side 50b in a substantially upward direction towards the bond clip 12. Preferably, the solder barrier 52 does not touch or abut the bond clip 12, thereby leaving some open area 15 for gasses and residuals to escape during the reflow soldering manufacturing process.

[0045] In a particular configuration the at least one solder barrier 52 encompasses the at least one clip mounting area 51. In some cases, the solder may flow towards a preferred direction, like underneath the bond clip. In such configuration at least one solder barrier 52 only protecting that side 50c of the semiconductor die 50i (5O2) in which direction solder flow is most likely to occur, would already suffice. Such example is depicted in Figure 3a, with one or more solder barriers 52 located at one side of the clip mounting area 51.

[0046] However, because of orientation of the semiconductor die 50i (5O2) or other reasons, the preferred flow / creep direction of the solder 12 may be unknown, and in those cases, it may be advantageous to provide at least one solder barrier 52 encompassing or surrounding the at least one clip mounting area 51, such that regardless the flow / creep direction the solder will always be maintained in the clip bonding area 51. This example of various concentrically arranged solder barriers 52 encompassing or surrounding the at least one clip mounting area 51 is shown in Figure 3b as well as in the top view example of Figure 4.

[0047] Typical dimensions of such solder barrier 52 may be in the range of 1-100 pm high and 1-100 pm wide, preferably between 5-50 pm high and 5-50 pm wide. A crosssection of the solder barrier 52 may have the shape of a square, rectangle, triangle, parallelogram or the like.

[0048] When viewed from a top side of the semiconductor die 50, the clip mounting area 51 may take up some area arranged to receive solder material 13 and a bond clip 12. This area may have the shape or a square, rectangle, triangle, circle, ellipse, (all with or without rounded edges) or a free-form and the at least one solder barrier encompassing the clip mounting area 51 may have a similar configuration.

[0049] In an advantageous example, the at least one solder barrier 52 comprises a plurality of solder barriers. One solder barrier 52 may suffice, but it is preferred to have a series of two, three or even more solder barriers 52 positioned in a side-by-side (or even concentric) manner as depicted in the Figures. It is noted that the at least oneclip mounting 51 can be a plurality of clip mounting areas, each intended to accommodate a semiconductor die 50 with solder material 13. Such configuration would require a plurality of solder barriers 52 for each clip mounting areas 51. However, also one clip mounting area 51 may comprise a plurality of solder barriers 52 as depicted in more detail in Figures 3a-3b and 4. A plurality of solder barriers 52 is advantageous since capillary forces may urge or flow the liquified solder 13 over a barrier 52, thereby lessening the protective properties of the solder barrier.

[0050] In particular, the interspacing x between the plurality of solder barriers 52 (see Figures 3a and 3b) may be chosen such that the solder material is caught in between neighbouring solder barriers, due to capillary forces. A minimum interspacing x can be 45 urn to 3 times the mold encapsulation filler cut size, whichever is smaller..

[0051] In particular, the plurality of solder barriers 52 is arranged in a concentric configuration, encompassing or surrounding each other and the clip mounting area 51 as shown in Figure 4. It has been found that this concentric configuration is particularly beneficial, since it may ensure equal distancing along the entire outer perimeter of the solder barrier, such that there is no particular preferable portion for solder to collect into or flow / creep towards. Otherwise, changes of overflowing the solder barriers would be more prominent on that portion of the solder barrier.

[0052] In a further example as depicted in the Figures, the clip mounting area 51 of the semiconductor die 50i (5O2) is provided with at least one coating layer 53 between the semiconductor die (the second die surface 50b) and the deposited solder material 13. The at least one coating layer 53 may be utilized for establishing an intermetallic joint between solder material 13 to the semiconfuctor die 50.. Furthermore, the at least one coating layer 53 may be the platform for at least one solder barrier to prevent solder bleed exceeding coating layer 53. In a preferred example, the at least one coating layer is provided on the second die surface 50b.

[0053] In addition, a further coating layer 54 may be provided between the at least one coating layer 53 and the deposited solder material 13. A further coating layer 54 may be provided having slightly different dimensions to the at least one coating layer 53. Coating layer 53 and 54 are part of the semiconductor die 50 and are independent from the existence of the plurality of solder barriers 52. Therefore, when viewed from a top side of the semiconductor die 50, the solder barriers 52 may be placed anywhere - as well as the interspacing x for a plurality of solder barriers - between thesemiconductor die (the second die surface 50b) and the deposited solder material 13. . The expert in the field would understand that going from a semiconductor material to a metal bond clip would need a few transitions for properly matching material properties. When these are not matches delamination of issues with heat dissipation may arise.

[0054] It should be understood that a semiconductor package may be provided with more than one semiconductor die and more than one bond clip. The wording of these two features according to the disclosure should thus not be considered limiting. Any plurality of semiconductor dies may be provided with at least one solder barrier to ensure that solder cannot creep towards the edges of said semiconductor die.

[0055] The present disclosure also pertains to a semiconductor die 50 composed of a piece of semiconductor material having a first die surface 50a and a second die surface 50b opposite to the first die surface 50a. The semiconductor material comprises at least one clip mounting area 51 structured to receive a solder material 13 and structured to receive at least one bond clip 12. At least one solder barrier 52 is provided adjacent to the at least one clip mounting area 51.

[0056] As outlined above and again with reference to the various Figures, in particular Figures 3a-3b and 4, the at least one solder barrier 52 may encompasses at least the clip mounting area 51 and more in particular the at least one solder barrier may comprises a plurality of solder barriers 52. The plurality of solder barriers 52 may be arranged in a concentric arrangement as shown in Figure 4. The concentric arrangement is particularly beneficial, since it may ensure equal distancing along the entire outer perimeter of the solder barrier, such that there is no particular preferable portion for solder to collect into or flow / creep towards. Otherwise, changes of overflowing the solder barriers would be more prominent on that portion of the solder barrier.

[0057] Alternatively, the at least one solder barrier 52 may be provided only at the side of the clip mounting area 51 (thus protecting only that side of the semiconductor die) in which direction solder flow is most likely to occur, see Figure 3a.

[0058] Similarly, the at least one clip mounting area 51 is provided with at least one coating layer 53 between the semiconductor die 50 and the deposited solder material 13, and additionally a protective layer 55 (see Figure 2) may be provided covering the at least one solder barrier 52.It is noted that in a further example of the semiconductor package 10i (IO2) or semiconductor die 50i (5O2) according to the disclosure, the at least one clip mounting area 51 is smaller than the area of the second die surface 50b. This is to ensure that there is still some area remaining for the at least solder barrier 52. Furthermore, it is preferable that the at least one clip mounting area 51 is not adjacent to a side edge 50c of the semiconductor die 50i (5O2).

[0059] It has been found that it is advantageous that the at least one solder barrier 52 is made of a material selected from a list of: polyimide (PI), polyamide (PA), polytetrafluoroethylene (PTFE), polyetheretherketone (PEEK) polyphenylene benzobisoxazole (PBO), polybenzoxazole (PBO), polyaryletherketone (PAEK), polybenzimidazole (PBI), polyethersulfone (PES), polycarbonate (PC), polysulfone (PSU), benzocyclobutene (BCB) or polyvinyl chloride (PVC). These are material that are not solvable in flux-removing solvents and are capable of withstanding heat during operation of the semiconductor package or during reflow soldering.

[0060] The present disclosure also pertains to a method of manufacturing a semiconductor die 50i (5O2) according to the disclosure, the method comprises the steps of providing a piece of semiconductor material having at least one clip mounting area 51; and forming at least one solder barrier 52 adjacent to the at least one clip mounting area 51.

[0061] In particular, the forming of the at least one solder barrier 52 is performed by means of photolithography. Photolithography is a cost efficient and high-resolution technique for manufacturing the at least one solder barrier, allowing the at least one solder barrier to be formed during the manufacturing process of a semiconductor die 50i (502).

[0062] Additionally, the method of manufacturing a semiconductor die according to the disclosure may further comprise the step of providing a protective layer 55 covering the at least one solder barrier 52. A protective layer 55 may be provided on the at least one solder barrier 52 to protect the solder barrier during reflow soldering. During this process it is known that residuals, like solder balls or gasses are formed, which may affect the surfaces of the at least one solder barrier. This would result in non-pristine surfaces for the semiconductor package during operation, which are more likely to attract liquified solder.The protective layer 55 can be made of a photoresist material chosen from a list of poly(methyl methacrylate), PMMA; poly(vinyl alcohol), PVA; methyl methacrylate, MMA; DNQ-Novolax, or other conventional photoresists comprising a resin, a sensitizer and a solver; and mixtures thereof. These are preferably polymers which are soluble in flux-removing solvents.

[0063] The disclosure also pertains to a method of manufacturing a semiconductor package 10i (IO2). The method comprises the steps of:

[0064] - providing a substrate 11 having a first substrate surface 11a and a second substrate surface 11b opposite to the first substrate surface 11a;

[0065] - mounting a semiconductor die 50i (5O2) according to the disclosure and as depicted in Figure 3a or 3b with its first die surface 50a to the second substrate surface 11b;

[0066] - depositing a solder material 13 on the at least one clip mounting area 51; - mounting a bond clip 12 mechanically and electrically to the at least one clip mounting area 51 of the semiconductor die 50i (5O2);

[0067] - removing the protective layer 55 covering the at least one solder barrier 52 of the semiconductor die 50i (5O2); and

[0068] - encapsulating the substrate 11, the semiconductor die 50, the at least one solder barrier 13, and the bond clip 12 with an encapsulant 14.LIST OF REFERENCE NUMBERS

[0069] 101-2 encapsulated semiconductor package (1stand 2ndexample) 11 substrate

[0070] 11a first substrate surface

[0071] 11b second substrate surface

[0072] 12 bond clip

[0073] 13 solder material

[0074] 14 encapsulant

[0075] 15 creeping space

[0076] 50 semiconductor die

[0077] 50a first die surface

[0078] 50b second die surface

[0079] 51 clip mounting area of the semiconductor die

[0080] 52 solder barrier (one of more)

[0081] 53 coating layer

[0082] 54 further coating layer

[0083] 55 protective layer

[0084] 56 GOV layer

[0085] x intermediate spacing

Claims

CLAIMS1. An encapsulated semiconductor package comprising:- a substrate having a first substrate surface and a second substrate surface opposite to the first substrate surface;- a semiconductor die having a first die surface and a second die surface opposite to the first die surface, the semiconductor die being mounted with its first die surface to the second substrate surface;- a bond clip electrically mounted to at least one clip mounting area of the semiconductor die using a solder material deposited on the at least one clip mounting area,wherein at least one solder barrier is provided adjacent to the at least one clip mounting area.

2. The semiconductor package according to claim 1, wherein the at least one solder barrier encompasses the at least one clip mounting area.

3. The semiconductor package according to any of the preceding claims, wherein the at least one solder barrier comprises a plurality of solder barriers.

4. The semiconductor package according to claim 2 and 3, wherein the plurality of solder barriers is arranged in a concentric configuration.

5. The semiconductor package according to any of the preceding claims, wherein the clip mounting area is provided with at least one coating layer between the semiconductor die and the deposited solder material.

6. The semiconductor package according to claim 5, further comprising a further coating layer provided between the at least one coating layer and the deposited solder material.

7. A semiconductor die composed of a piece of semiconductor material having a first die surface and a second die surface opposite to the first die surface, wherein the semiconductor material comprises at least one clip mounting area structured to receive a solder material and structured to receive at least one bond clip, wherein at least one solder barrier is provided adjacent to the at least one clip mounting area.

8. The semiconductor die according to claim 7, wherein the at least one solder barrier encompasses at least one the clip mounting area.

9. The semiconductor die according to any of the claims 7-8, wherein the at least one solder barrier comprises a plurality of solder barriers.

10. The semiconductor die according to claims 8 and 9, wherein the plurality of solder barriers is arranged in a concentric arrangement.

11. The semiconductor die according to any of the claims 7-10, wherein the at least one clip mounting area is provided with at least one coating layer between the semiconductor die and the deposited solder material.

12. The semiconductor die according to any of the claims 7-11, wherein a protective layer is provided covering the at least one solder barrier.

13. The semiconductor package or semiconductor die according to any of the preceding claims, wherein the at least one clip mounting area is smaller than the area of the second die surface.

14. The semiconductor package or semiconductor die according to any of the preceding claims, wherein the at least one solder barrier is made of a material selected from a list of: polyimide (PI), polyamide (PA), polytetrafluoroethylene (PTFE), polyetheretherketone (PEEK) polyphenylene benzobisoxazole (PBO), polybenzoxazole (PBO), polyaryletherketone (PAEK), polybenzimidazole (PBI), polyethersulfone (PES), polycarbonate (PC), polysulfone (PSU), benzocyclobutene (BCB) or polyvinyl chloride (PVC).

15. A method of manufacturing a semiconductor die as defined in one or more of the claims 7-14 comprising the steps of:- providing a piece of semiconductor material having at least one clip mounting area;- forming at least one solder barrier adjacent to the at least one clip mounting area.

16. The method of manufacturing a semiconductor die according to claim 15, wherein the forming of the at least one solder barrier is performed by means of photolithography.

17. The method of manufacturing a semiconductor die according to any of the claims 15-16, further comprising the step of:- providing a protective layer covering the at least one solder barrier.

18. The method of manufacturing a semiconductor die according to according to 17, wherein the protective layer is made of a material chosen from a list of: poly(methylmethacrylate), PMMA; poly(vinyl alcohol), PVA; methyl methacrylate, MMA; and mixtures thereof.

19. The method of manufacturing a semiconductor package, comprising the steps of:- providing a substrate having a first substrate surface and a second substrate surface opposite to the first substrate surface;- mounting a semiconductor die according to any of the claims 7-14 with its first die surface to the second substrate surface;- depositing a solder material on the at least one clip mounting area;- mounting a bond clip electrically to the at least one clip mounting area of the semiconductor die;- removing the protective layer covering the at least one solder barrier of the semiconductor die; and- encapsulating the substrate, the semiconductor die, the at least one solder barrier, and the bond clip.

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