Quantum error detection method, quantum error detection device, and quantum error detection program
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- QUNASYS INC
- Filing Date
- 2024-12-23
- Publication Date
- 2026-07-02
Smart Images
Figure JP2024045540_02072026_PF_FP_ABST
Abstract
Description
Quantum error detection method, quantum error detection device, and quantum error detection program
[0001] The disclosed technology relates to a quantum error detection method, a quantum error detection device, and a quantum error detection program.
[0002] Currently, quantum error correction codes, known as "surface codes," which are widely used when performing quantum computations, are based on the assumption of coupling only between adjacent qubits, as employed in superconducting quantum computers, etc. (For example, Reference 1: Austin G. Fowler, Matteo Mariantoni, John M. Martinis, and Andrew N. Cleland, "Surface codes: Towards practical large-scale quantum computation", Phys. Rev. A 86, 032324 - Published 18 September 2012,<https: / / journals.aps.org / pra / abstract / 10.1103 / PhysRevA.86.032324> (See reference).
[0003] On the other hand, in recent years, rapidly developing cold atom quantum computers and ion trap quantum computers possess "fully connected" properties (allowing two-qubit operations for any pair of qubits), enabling more flexible qubit manipulation. For this reason, it is believed that FTQC (Fault-Tolerant Quantum Computer) using quantum error correction codes other than surface codes can be realized when using cold atom quantum computers or ion trap quantum computers.
[0004] A representative example of quantum error correction codes other than surface codes is Steane codes (7-qubit codes) (for example, Reference 2: “Multiple-particle interference and quantum error correction”, Proceedings of the Royal Society of London. Series A: Mathematical, Physical and Engineering Sciences 452, 2551 (1996)).<https: / / royalsocietypublishing.org / doi / 10.1098 / rspa.1996.0136> ) is known.
[0005] A Steane code represents one logic qubit using a relatively small number of physical qubits, seven. Furthermore, Steane codes possess a convenient property called "transversality" with respect to all Cliffford gates. Transversality means that a gate operation on a logic qubit can be performed by performing an independent gate operation on each physical qubit. For example, a Steane code has transversality with respect to H gates. This means that to perform a logic H gate on a Steane code's logic qubit, one only needs to perform a physical H gate operation on each of the seven physical qubits. If a code lacks transversality, the physical gate operations required to perform a logic gate operation are generally complex, leading to a tendency for errors to spread easily. As mentioned above, Steane codes have transversality with respect to all Cliffford gates. For this reason, Steane codes are often used as the subject of experimental demonstrations in research on quantum devices with early error correction capabilities (Early-FTQC). Even when using codes other than Steane codes, it is preferable to minimize errors that occur during quantum computation.
[0006] However, in the prior art, there is room for improvement in reducing errors that occur when performing quantum computing.
[0007] The disclosed technology has been made in view of the above circumstances, and provides a quantum error detection method, a quantum error detection device, and a quantum error detection program capable of reducing errors that occur when performing quantum computing.
[0008] To achieve the above object, the quantum information processing method of the present disclosure is a quantum error detection code that represents one logical qubit by n １ physical qubits, and is a quantum error detection code with a code distance d １ Generate the logical state |+〉 of the first quantum error detection code, Ｌ，１ For the logical state |+〉 of the first quantum error detection code, Ｌ，１ By performing the logical Rz rotation gate operation of the first quantum error detection code, the logical state |+ θ 〉 Ｌ，１ Of the first quantum error detection code, θ 〉 Ｌ，１ For the logical state |+ θ 〉 Ｌ，１ Of the first quantum error detection code, by performing a sequence of unitary quantum gate operations, the logical state |+ ２ Of the first quantum error detection code, ２ n １ )>n θ 〉 Ｌ，２ Of the second quantum error detection code that represents one logical qubit by n θ 〉 Ｌ，２ To obtain the error syndrome of, a quantum error detection method executed by a computer.
[0009] According to the disclosed technology, an effect that errors that occur when performing quantum computing can be reduced can be obtained.
[0010] This figure shows an example of the schematic configuration of the hybrid system 100 of this embodiment. This is a schematic block diagram of a computer that functions as a classical computer 110, a control device 121, and a user terminal 130. This figure is for explaining the Cliffford+T approach. This is a diagram of a quantum circuit based on a conventional method. This figure shows the error rate of the logic state obtained by a quantum circuit based on a conventional method. This is an example of a quantum circuit for generating the logic state of a logic qubit of a Steane code. This figure is for explaining post-selection based on Steane's gadget. This is an example of a quantum circuit that generates the logic |0> state of a logic qubit of a Steane code and removes errors by post-selection. This figure shows an example of a sequence executed by the hybrid system 100 of this embodiment. This is the simulation result of the error rate when quantum computation is performed using the quantum circuit of this embodiment. This is the circuit used in the simulation. This is the circuit used in the simulation. This is an enlarged view of the circuit in Figure 9B. This is an enlarged view of the circuit in Figure 9B. This is an enlarged view of the circuit in Figure 9B. This is an enlarged view of the circuit in Figure 9B. This is an enlarged view of the circuit in Figure 9B. This is an enlarged view of the circuit in Figure 9B. This is an enlarged view of the circuit in Figure 9B. This is an enlarged view of the circuit in Figure 9B. This is an enlarged view of the circuit in Figure 9B. Logical state when the second quantum error detection code is the [[23,1,7]] code |+ θ > Ｌ，２ This is an example of a circuit for generating [something]. This is an enlarged view of the circuit in Figure 10A. This is an enlarged view of the circuit in Figure 10A. This is an enlarged view of the circuit in Figure 10A. This is an enlarged view of the circuit in Figure 10A. This is the same circuit as in Figure 5, but drawn in a different way. This is a circuit in which the CNOT gate in the circuit of Figure 11A has been swapped. This is a circuit in which the CNOT gate in the circuit of Figure 11A has been replaced with a CZ gate and an H gate. This is a diagram showing equivalent gates. This is a diagram showing equivalent gates. This is an example of a circuit that has the same function as the circuit in Figure 11A. This is a circuit in which the CNOT gate in the circuit of Figure 15A has been swapped. This is a circuit in which the CNOT gate in the circuit of Figure 15A has been replaced with a CZ gate and an H gate.
[0011] Embodiments of the disclosed technology will be described in detail below with reference to the drawings.
[0012] <Hybrid System 100 According to an Embodiment> Figure 1 shows a hybrid system 100 according to an embodiment. The hybrid system 100 of this embodiment includes a classical computer 110, which is an example of an information processing device, a quantum computer 120, and a user terminal 130. The classical computer 110, the quantum computer 120, and the user terminal 130 are connected via a computer network, such as an IP network, as shown in Figure 1.
[0013] In the hybrid system 100 of this embodiment, the quantum computer 120 performs a predetermined quantum computation in response to a request from the classical computer 110 and outputs the result of the quantum computation to the classical computer 110. The classical computer 110 outputs the calculation result corresponding to the quantum computation to the user terminal 130. As a result, the hybrid system 100 as a whole performs a predetermined computation process.
[0014] The classical computer 110 comprises a communication unit 111 such as a communication interface, a processing unit 112 such as a processor or CPU (Central Processing Unit), and an information storage unit 113 including a memory, hard disk, or other storage device or storage medium, and is configured to execute programs for each processing. The CPU is an example of a classical processor. The classical computer 110 may include one or more devices or servers. Furthermore, the program may include one or more programs, and can be recorded on a computer-readable storage medium to become a non-transient program product.
[0015] For example, the quantum computer 120 generates an electromagnetic wave to irradiate at least one of the qubits in the qubit group 123 based on information transmitted from the classical computer 110. Then, the quantum computer 120 executes a quantum circuit by irradiating at least one of the qubits in the qubit group 123 with the generated electromagnetic wave.
[0016] In the example shown in Figure 1, the quantum computer 120 comprises a control device 121 that communicates with the classical computer 110, an electromagnetic wave generator 122 that generates electromagnetic waves in response to requests from the control device 121, and a group of qubits 123 that receive electromagnetic wave irradiation from the electromagnetic wave generator 122. The electromagnetic wave generator 122 and the group of qubits 123 of the quantum computer 120 are also QPUs (Quantum Processing Units). A QPU is an example of a quantum processor. In this embodiment, "quantum computer" does not mean a computer that does not perform any calculations using classical bits, but rather a computer that includes calculations using qubits or a computer that simulates the behavior of a quantum computer. A computer that simulates the behavior of a quantum computer is, for example, a classical computer that performs quantum simulations. Furthermore, "quantum computation" in this embodiment refers to calculations performed by executing quantum algorithms, and it is not essential that a quantum computer is used as hardware. For this reason, "quantum computation" in this embodiment is a concept that includes quantum computation by a quantum computer and simulation or emulation of quantum computation by a classical computer. Furthermore, the term "computer" in this embodiment is a concept that includes both quantum computers and classical computers.
[0017] The control device 121 is a classical computer that performs operations using classical bits and substitutes for some or all of the processing described herein that is performed in the classical computer 110. The control device 121 comprises a control processing unit 121A and a control storage unit 121B. The control device 121 is an example of a quantum error detection device of this disclosure.
[0018] The user terminal 130 is a classical computer that performs calculations using classical bits. The user terminal 130 receives information input from the user and performs processing according to that information.
[0019] The classical computer 110, the control unit 121, and the user terminal 130 can be realized, for example, by the computer 50 shown in Figure 2. The computer 50 includes a central processing unit (CPU) 51, a memory 52 as a temporary storage area, and a non-volatile storage unit 53. The computer 50 also includes an input / output interface (I / F) 54 to which external devices and output devices are connected, and a read / write (R / W) unit 55 that controls the reading and writing of data to and from the recording medium. The computer 50 also includes a network I / F 56 that connects to a network such as the Internet. The CPU 51, memory 52, storage unit 53, input / output I / F 54, R / W unit 55, and network I / F 56 are connected to each other via a bus 57.
[0020] [Background of this Embodiment] As described above, Steane codes are known as an example of quantum error correction codes. Steane codes have a convenient property called "transversality" with respect to Cliffford gates. Steane codes are also called [[7,1,3]] codes. Cliffford and non-Cliffford gates will be described below.
[0021] <How to execute non-Cliffford gates in the Early-FTQC era> (What are non-Cliffford gates?) Cliffford gates correspond to a set of specific types of quantum gates. Cliffford gates include Pauli X gates, Pauli Y gates, Pauli Z gates, S gates, H gates, and CNOT gates, etc. Strictly speaking, a certain gate is used to UPU the Pauli matrix P. † A gate corresponding to a transformation that, when converted to the above format, results in a Pauli matrix, is called a Cliffford gate. Furthermore, gates that do not belong to the above-mentioned Cliffford gate category are called non-Cliffford gates.
[0022] It is known that the Cliffford gate can be executed relatively easily in surface codes or stem codes. On the other hand, it is also known that using only the Cliffford gate limits the range of quantum computations that can be performed. Furthermore, it is known that quantum computations consisting only of the Cliffford gate can be easily simulated using classical computation (for example, the Gottesman-Knill theorem). For this reason, it is also known that quantum computations consisting only of the Cliffford gate cannot surpass the capabilities of classical computation.
[0023] (Existing methods in FTQC: Cliffford+T approach) The following describes the general process for performing quantum error detection or quantum error correction in FTQC.
[0024] First, any gate to be executed is decomposed into a product of many Cliffford gates and non-Cliffford gates. For this decomposition, for example, the Solovay-Kitaev decomposition (hereinafter simply referred to as "SK decomposition") is used. Here, a gate called the T gate is typically used as the non-Cliffford gate. The T gate is a π / 4 rotation gate with respect to the Z axis in the Bloch sphere.
[0025] It is known that only one type of non-Cliffford gate is sufficient for SK decomposition. Therefore, by combining this T gate with various Cliffford gates, any quantum computation is possible.
[0026] Furthermore, as mentioned above, the Cliffford gate makes it relatively easy to perform quantum computations while maintaining quantum error tolerance.
[0027] On the other hand, in order to execute a T-gate while maintaining quantum error tolerance, an operation called magical state distillation is necessary. The cost of performing this magical state distillation operation is enormous.
[0028] Specifically, when a T-gate is executed, first, a different state is generated through magical state distillation, where |T〉=T|+〉, meaning the T-gate has already been applied. Next, a technique called gate teleportation, which uses a CNOT gate and measurement, is used to perform the gate-corresponding operation on the target qubit.
[0029] Furthermore, in SK decomposition, a quantum circuit U containing any gate is decomposed into a large number of gate sequences. For example, if a quantum circuit is U, when SK decomposition is performed on the quantum circuit U, it is decomposed into a product of H gates and T gates, such as U = HTHTTTHTHTT.... Therefore, many T gates are required to perform one gate operation, and one magic state distillation operation is required for each T gate, resulting in an enormous overall cost. This existing method of gate operation in FTQC will be referred to below as the Cliffford + T approach.
[0030] Figure 3 is a diagram illustrating the Cliffford+T approach. When the quantum circuit to be executed on the left side of Figure 3 is subjected to SK decomposition, each gate in the quantum circuit to be executed can be replaced with operations corresponding to the S gate, H gate, CNOT gate, and T gate. In this case, as shown on the right side of Figure 3, the time required to execute the T gate is enormous compared to the time required to execute the S gate, H gate, and CNOT gate. As mentioned above, executing the T gate requires magic state distillation, and this magic state distillation takes a lot of time.
[0031] (STAR Architecture) In the Cliffford+T approach described above, both Cliffford gates and non-Cliffford gates (specifically, T gates) are executed in a fault-tolerant manner. While this guarantees a certain level of computational accuracy, the cost of the T gates becomes enormous, as mentioned above.
[0032] On the other hand, recent quantum computers (e.g., NISQ devices) have limitations in terms of the number of qubits and the precision of their operations. Therefore, when performing quantum computation using recent quantum computers (e.g., NISQ devices), the procedure of decomposing a quantum circuit into numerous T-gates and performing magic state distillation on each T-gate, as described above, is not practical.
[0033] More specifically, the higher the operational precision of the quantum computer itself, the greater the degree of precision improvement achieved through error correction. Conversely, at this stage, where the operational precision of actual quantum computers is not yet very high, the benefits of performing perfect error correction are small, and it may be appropriate to perform error correction only in parts where it can be easily done.
[0034] Against this backdrop, a quantum computing architecture called STAR has been proposed in recent years (for example, Reference 3: Yutaro Akahoshi, Kazunori Maruyama, Hirotaka Oshima, Shintaro Sato, and Keisuke Fujii, "Partially Fault-Tolerant Quantum Computing Architecture with Error-Corrected Clifford Gates and Space-Time Efficient Analog Rotations", PRX Quantum 5, 010337 - Published 5 March 2024).<https: / / journals.aps.org / prxquantum / abstract / 10.1103 / PRXQuantum.5.010337> ).
[0035] In STAR, it has been proposed to abandon complete error tolerance for the non-Cliffford gates mentioned above and replace the T gates with "analog rotation gates" (for example, gates that achieve rotations of an arbitrary angle θ around a given axis, such as Rz(θ)). This eliminates the need for SK decomposition and magic state distillation, significantly reducing computational costs. On the other hand, in STAR, Cliffford gates are executed while maintaining error tolerance.
[0036] When using NISQ with limitations on the number of qubits or precision, or when using early-FTQC, a method based on "fault-tolerant Cliffford gates + non-fault-tolerant analog rotations" is expected to be optimal in terms of cost and computational accuracy. In the above-mentioned reference 3, the superiority of STAR over Cliffford+T is shown for the performance metric of quantum computers called Quantum Volume. Furthermore, the superiority of STAR over Cliffford+T is shown when considering recent quantum devices (e.g., NISQ or early-FTQC).
[0037] The STAR architecture is based on quantum devices with coupling only between adjacent qubits, such as superconducting quantum computers. On the other hand, it is also possible to perform what could be called "partially fault-tolerant quantum computing" using such analog rotations for quantum devices such as fully coupled cold atom quantum computers or ion trap quantum computers.
[0038] (Problem Setting) As mentioned above, current quantum computers have limitations in the number of qubits and computational precision. Therefore, instead of achieving full FTQC, it is considered effective to replace only some of the operations when performing quantum computation with fault-tolerant operations.
[0039] Therefore, in this embodiment, when performing error-tolerant quantum computation using Steane codes, a non-Cliffford gate is executed using an analog rotation that does not have error tolerance.
[0040] In the following, the terms physical qubit, logical qubit, physical operation, and logical operation will appear. A physical qubit is a qubit that exists physically. A logical qubit is a representation of a single qubit quantum state using multiple physical qubits according to specific rules. A logical qubit is also a group of multiple physical qubits to which the information of one qubit has been written. A logical qubit can perform quantum error detection or quantum error correction depending on the state of the multiple physical qubits. For example, suppose that when a certain quantum computation is performed, the states of three physical qubits become the same. Assume that one logical qubit is represented by these three physical qubits. For example, if the first physical qubit represents 1, the second physical qubit represents 1, and the third physical qubit represents 0, then the logical qubit will be 110. In this case, since the first and second physical qubits are 1, while the third physical qubit is 0, it is considered that an error has occurred in the third physical qubit by majority vote. Therefore, quantum error detection becomes possible, where an error occurs in the third physical qubit. Furthermore, quantum error correction becomes possible, where the state of the logical qubit is corrected to 1 by majority vote of the states of the three physical qubits.
[0041] Analog rotation R for logical qubits Ｚ The operation of (θ) is |+ θ This can be done by generating a state called a "state" as a logical qubit state and performing an operation called gate teleportation. θ > The state is |+ θ > = R Ｚ It is represented by (θ)|+〉. Since gate teleportation can be performed relatively easily, this |+ is used as the state of the logical qubit of the Steane code. θ The challenge lies in how to generate the state.
[0042] (Conventional methods and their problems) Conventional methods, as described above, θLet's consider the case where we try to generate a state. Figures 4A and 4B show a quantum circuit based on a conventional method and the logical state obtained by that quantum circuit |+ θ > Ｌ This is a diagram showing the error rate.
[0043] Specifically, the quantum circuit shown in Figure 4A first applies an analog rotation R for one physical qubit. Ｚ (θ) determines the physical state |+ θ > (The quantum state of one physical qubit) is generated, and by executing the Steane code encoding circuit, the logical state |+ θ > Ｌ This generates the logic state |+ generated by the quantum circuit in Figure 4A. The graph shown in Figure 4B represents the logic state |+ θ > Ｌ This is the numerical simulation result of the error rate.
[0044] As shown in the graph in Figure 4B, the logic state |+ generated in the quantum circuit in Figure 4A θ > Ｌ The error rate is high. Specifically, the result of numerical calculations shows that the logic state |+ generated in the quantum circuit in Figure 4A is high. θ > Ｌ The error rate is approximately 65p / 15 compared to the error rate p of a physical qubit.
[0045] (Overview and advantages of the proposed method) In this embodiment, a Steane code, which is an example of a quantum error correction code, is generated using a quantum error detection code called the [[4,1,2]] code. The Steane code is also an example of a quantum error detection code. The [[4,1,2]] code is an example of the first quantum error detection code of this disclosure. The Steane code is an example of the second quantum error detection code of this disclosure.
[0046] Specifically, in this embodiment, the logical state |+ is represented using the [[4,1,2]] code. θ > Ｌ After generating the [[4,1,2]] code, a process equivalent to converting from the Steane code to the Steane code is performed, thereby creating the logical state of the Steane code's logical qubits |+ θ > Ｌ Generates.
[0047] Specifically, in this embodiment, the logical state of the logical qubit of the Steane code is changed by the following steps: θ > Ｌ This generates the logical state of a Steane code logical qubit |+ θ > Ｌ This is an example of a quantum circuit for generating [the specified element]. The process performed in this embodiment will be described below with reference to Figure 5.
[0048] (Step 1) First, the logical state of the [[4,1,2]] sign |+> Ｌ，１ This is generated for four of the seven physical qubits. Specifically, the 200 portion of the quantum circuit shown in Figure 5 generates a logical state of the code [[4,1,2]] for four of the seven physical qubits (in the example in Figure 5, the second, fourth, fifth, and sixth physical qubits). Ｌ，１ This is generated.
[0049] Next, the logical state of the [[4,1,2]] code |+> Ｌ，１ The logical state of the [[4,1,2]] code is |+ by an operation equivalent to the logical Rz rotation of the [[4,1,2]] code. θ > Ｌ，１ This is generated. Note that the operation equivalent to logical Rz rotation can be performed by a physical rotation operation on two of the four physical qubits. Specifically, the logical Rz rotation gate 202 shown in Figure 5 (which is a physical 2-qubit Rzz rotation as an operation on physical qubits, and is therefore denoted as Rzz(θ) in Figure 5) generates a logical state |+ of the [[4,1,2]] code. θ > Ｌ，１ This is generated.
[0050] Finally, the sequence of CNOT gates 204 shown in Figure 5 is executed. This results in the logical state of the [[4,1,2]] code |+ θ > Ｌ，１ The logical state of the Steane code |+ θ > Ｌ，２ It is converted to this.
[0051] (Step 2) Logical state of Steane code converted in Step 1 |+ θ > Ｌ，２ This generally contains noise. Therefore, in this embodiment, post-selection based on Steane's gadget is performed. Specifically, quantum error detection and quantum error correction are performed by executing post-selection based on Steane's gadget 206 shown in Figure 6A. Note that the "|+" in the circuit diagram shown in Figure 6A θ > Ｌ The "encoding" corresponds to the quantum circuit shown in Figure 5. Also, the "|0〉" in the circuit diagram shown in Figure 6A. Ｌ "Encoding" can be achieved using known technologies (for example, reference 4: Goto, H. Minimizing resource overheads for fault-tolerant preparation of encoded states of the Steane code. Sci Rep 6, 19578 (2016)).<https: / / doi.org / 10.1038 / srep19578> ). Among the circuit diagrams shown in Figure 6A, "|0〉 Ｌ "Encoding" is realized, for example, by a quantum circuit like the one shown in Figure 6B. Also, X shown in Figure 6A Ｌ The 'X' represents an X basis measurement for each physical qubit that makes up a logical qubit. The 'Z' shown in Figure 6B represents a Z basis measurement for a qubit.
[0052] [Operation of the Hybrid System 100 in the Embodiment] The specific operation of the hybrid system 100 in the embodiment will now be described. In each device of the hybrid system 100, the processes shown in Figure 7 are executed.
[0053] First, in step S100, the user terminal 130 transmits to the classical computer 110 the computation target information, which is information about the computation target, and the computation method information, which is information about the computation method, both input by the user. For example, computation target information could include molecular information that is the subject of quantum chemical calculations. Computation method information could include, for example, quantum computation algorithms used in quantum computations.
[0054] Next, in step S102, the classical computer 110 receives the information to be calculated and the calculation method information transmitted from the user terminal 130.
[0055] In step S104, the classical computer 110 transmits various information necessary for quantum computation to the quantum computer 120.
[0056] In step S106, the control device 121 of the quantum computer 120 receives various information transmitted from the classical computer 110 in step S104.
[0057] Next, the control device 121 of the quantum computer 120 instructs the quantum computer 120 to perform quantum calculations according to the various information received in step S106. When the control device 121 of the quantum computer 120 instructs the quantum computer 120 to perform quantum calculations, it also performs the quantum error correction process described above.
[0058] Specifically, in step S108, the control processing unit 121A of the control device 121 reads out a quantum circuit that has been pre-stored in the control memory unit 121B. This quantum circuit is a quantum circuit as shown in Figure 5.
[0059] Next, in step S110, the control processing unit 121A of the control device 121 outputs a control signal to the quantum computer 120 instructing it to execute the quantum circuit read out in step S108. As a result, the quantum computer 120 executes the quantum circuit.
[0060] The 200 portion of the quantum circuit in Figure 5 represents a quantum error detection code that uses four of the seven physical qubits to represent one logical qubit, and is a quantum error detection code with a code distance of 2, the logical state of the code [[4,1,2]] |+> Ｌ，１ This is generated.
[0061] Next, the 202 portion of the quantum circuit in Figure 5 creates a logical state with the code [[4,1,2]] |+> Ｌ，１ By performing a logic Rz rotation gate operation on the [[4,1,2]] code, the logic state of the [[4,1,2]] code |+ θ > Ｌ，１ This is generated.
[0062] Then, the 204 portion of the quantum circuit in Figure 5 creates a logical state with the code [[4,1,2]] |+ θ > Ｌ，１ By performing a sequence of CNOT gate operations on it, the logical state of the [[4,1,2]] code |+ θ > Ｌ，１ The logical state of a Steane code represented by seven physical qubits |+ θ > Ｌ，２ It is converted to this.
[0063] Next, the logical state of the Steane code |+ θ > Ｌ，２ The error syndrome is obtained. Specifically, the logic state of the Steane code |+ is determined by an error detection circuit that performs post-selection using the Steane's gadget method, which is an example of an error detection circuit as shown in Figure 6A. θ > Ｌ An error syndrome is acquired. The error syndrome is information for detecting errors. The control processing unit 121A of the control device 121 determines whether or not an error has occurred in the quantum computation based on the error syndrome. Acquisition of the error syndrome includes outputting, extracting, detecting, observing, or storing the error syndrome in memory.
[0064] In step S112, the control device 121 transmits the result obtained in step S110 to the classical computer 110.
[0065] In step S112, the classical computer 110 receives the result transmitted from the control device 121 in step S110.
[0066] In step S114, the classical computer 110 executes various calculations based on the result obtained in step S112 to obtain the calculation result desired by the user.
[0067] In step S116, the classical computer 110 transmits the calculation result obtained in step S114 to the user terminal 130.
[0068] In step S124, the user terminal 130 receives the calculation result transmitted from the classical computer 110.
[0069] As described above, the control device 121 of the embodiment executes the above-described quantum circuit to perform a quantum error detection code that represents one logical qubit by four physical qubits for four out of seven physical qubits, and is a quantum error detection code with a code distance of 2, the logical state |+〉 of the [[4,1,2]] code Ｌ，１ is generated. Next, the control device 121 executes the above-described quantum circuit to perform a logical Rz rotation gate operation on the logical state |+〉 of the [[4,1,2]] code, thereby obtaining the logical state |+ Ｌ，１ 〉 θ of the [[4,1,2]] code. Next, the control device 121 executes the above-described quantum circuit to perform a column of CNOT gate operations on the logical state |+ Ｌ，１ 〉 θ of the [[4,1,2]] code, thereby converting the logical state |+ Ｌ，１ 〉 θ of the [[4,1,2]] code into the logical state |+ Ｌ，１ 〉 θ of the Steane code represented by seven physical qubits. Then, the control device 121 sets the logical state |+ Ｌ，２ 〉 θ of the Steane code Ｌ，２Obtain the error syndrome. This can reduce the errors that occur when performing quantum computing.
[0070] Fig. 8 shows the simulation results of the error rate when performing quantum computing using the quantum circuit shown in Fig. 5. The horizontal axis of the graph in Fig. 8 is the physical error rate, and the vertical axis is the logical error rate. As shown in Fig. 8, the logical error rate when using the quantum circuit is low, and for the error rate p of the physical qubits, the logical error rate is about 0.96p / 15.
[0071] The simulation results shown in Fig. 4B and Fig. 8 are the simulation results obtained under the following methods and experimental conditions.
[0072] (Method for calculating logical error rate) [State preparation] First, state preparation is performed by the encoding of the quantum circuits shown in Figs. 6A and 6B. In the |+ θ 〉 Ｌ encoding in Fig. 6A, the logical state |+ θ 〉 Ｌ，１ of the Steane code is generated using the proposed method (at this point, error correction has not been performed). Also, in the |0〉 Ｌ encoding in Fig. 6A, a state with error correction is generated. Specifically, the |0〉 Ｌ encoding in Fig. 6A creates two states composed of 7 physical qubits (a total of 14 physical qubits) as shown in Fig. 6B ("Non-fault-tolerant zero-state encoding"), and then a column of CNOT gates is executed on them, and one of the states (the lower half part of Fig. 6B) is measured to perform error detection ("Verification"). If an error is detected here, it is considered that the state preparation has failed and is restarted from the beginning. If no error is detected, it is successful and proceeds to the next step.
[0073] [Error detection for |+ θ 〉 Ｌ，２ using Steane's gadget] The logical state |+ θ 〉 Ｌ，２Errors are generally included in them. Errors in qubits are broadly classified into two types: X errors and Z errors. Steane's gadget, for example, reference 5 (Quantum Computation with Topological Codes: from qubit to topological fault-tolerance),<https: / / doi.org / 10.48550 / arXiv.1504.01444> Using the circuit disclosed in [document /
[0074] [Evaluation of Logical Errors] In the final performance evaluation, the completed (error-free) logical state |+ θ > Ｌ，２ Measurements are taken against the system, and the final error rate (logical error rate = the percentage of errors that occur in the state of a logical qubit) is evaluated.
[0075] Note that, for technical reasons, the logical state for a general rotation angle θ is |+ θ > Ｌ，２ The generation and evaluation of the above is difficult. This is due to technical constraints, as the above generation and evaluation require non-Clifford gate operations, making simulation on a classical computer difficult. Therefore, here we fix θ = 0 and obtain the logical state (|+ θ＝０ > Ｌ，２ =Rz(θ=0)|+〉 Ｌ，２ =|+〉 Ｌ，２ Performance evaluation is performed on the following: If an error remains, the logical state will be incorrectly set to logical state |-〉 Ｌ，２ This can sometimes result in a logical error. Therefore, the above procedure is attempted many times, and the logical state becomes |-〉 Ｌ，２ The percentage obtained is defined as the logical error rate. Increasing the physical error rate (described later) generally increases the logical error rate accordingly. Rather than the value of the logical error rate itself, the "logical error rate p Ｌ The "dependence of the physical error rate p" reflects the performance of the quantum error correction method. In the case of this method, p ＬTheoretically, it is suggested that there is a relationship of approximately p / 15, but in order to confirm this with numerical simulation, we will examine the logical error rate p for several physical error rate p values (described later). Ｌ It is calculating...
[0076] (Supplementary information on experimental conditions) In this simulation, it is assumed that an error rate of probability p (= 0.00001, ..., 0.0001) occurs in all processes of various operations on the physical qubit. This probability is called the "physical error rate". The breakdown of various operations on the physical qubit (in which errors occur) is as follows:
[0077] (1) |0> state generation (At the start of the calculation, all physical qubits used are reset to the |0> state, but this also fails with a certain probability, so this is treated as an error) (2) 1, 2 qubit gate operations (H, CNOT, etc.) (3) Measurement (Reading out the state of the qubits as 0 or 1 at the end of the calculation) (4) Idling (Errors are also generated for unused qubits, depending on the length of their waiting time)
[0078] Generally, the circuit is executed many times, and the number of errors that occur is counted. This number of circuit executions is called the number of shots, and in simulations, it is 10 ５ ~10 ７ It is usually done in a few shots. Repeating it many times is done because if the number of trials is small, the variability of the logical error rate value becomes large, resulting in a statistically unreliable value.
[0079] Figure 9A shows the |+ used in this simulation. θ > Ｌ This is an encoding circuit. In the diagram, "DEP" represents noise. In Figure 9A, "DEP1" represents noise applied individually to one qubit, and "DEP2" represents noise applied simultaneously to two qubits. When executing a two-qubit gate such as a CNOT gate or a CZ gate, it is necessary to consider the noise applied simultaneously to two qubits, so DEP2 is used. The noise generated by "DEP1" and "DEP2" is treated as a model in which errors (for example, bit inversion) are probabilistically introduced. In the diagram, R represents a reset to the |0> state, and H represents an Adamard gate. Figure 9B is an overall diagram of the quantum circuit used in this simulation. Figures 9C, 9D, 9E, 9F, 9G, 9H, 9I, and 9J are enlarged views of different parts of the quantum circuit shown in Figure 9B. In Figure 9J, "M" represents a measurement related to the Z basis. The quantum circuit shown in Figure 9B is |+ θ > Ｌ Encoding circuit and |+0〉 Ｌ The encoding circuit is comprised of a measurement section for error detection and logic error rate evaluation using Steane's gadget.
[0080] Furthermore, the technology disclosed herein is not limited to the embodiments described above, and various modifications and applications are possible without departing from the spirit of this invention.
[0081] For example, in the above embodiment, the case of converting the [[4,1,2]] code, which is an example of a first quantum error detection code, to the Steane code, which is an example of a second quantum error detection code, was explained as an example, but it is not limited to this. A quantum error detection code can be represented by the required number of physical qubits n, the number of logical qubits k, and the code distance d. Specifically, a quantum error detection code can be represented by [[required number of physical qubits n, createable number of logical qubits k, code distance d]]. The [[4,1,2]] code has a required number of physical qubits n=4, createable number of logical qubits k=1, and code distance d=2. The Steane code has a required number of physical qubits n=7, createable number of logical qubits k=1, and code distance d=3. For this reason, the Steane code is also called the [[7,1,3]] code. The required number of physical qubits in the first quantum error detection code is n １ Let the number of logical qubits be k. １ Let the code distance d be １ In this case, the first quantum error detection code is [[n １ ,k １ d １ This is denoted as the ]] code. Also, the number of physical qubits required in the second quantum error detection code is n. ２ Let the number of logical qubits be k. ２ Let the code distance d be ２ In this case, the second quantum error detection code is [[n ２ ,k ２ d ２ It is written as the symbol ]]. ２ >n １ If the code satisfies the following relationship, then it is the first quantum error detection code [[n １ ,k １ d １ The code is the [[n] code and the second quantum error detection code is the [[n] code. ２ ,k ２ d ２ The symbol can be any symbol.
[0082] In the above case, the control device 121 performs the execution of the quantum circuit, n １A quantum error detection code that represents one logical qubit using several physical qubits, and has a code distance d １ The logical state of the first quantum error detection code, which is the quantum error detection code |+〉 Ｌ，１ Next, the control device 121 generates the logic state |+〉 of the first quantum error detection code by executing the quantum circuit. Ｌ，１ By performing a logic Rz rotation gate operation on the first quantum error detection code, the logic state of the first quantum error detection code |+ θ > Ｌ，１ Next, the control device 121 generates the logical state of the first quantum error detection code |+ θ > Ｌ，１ By performing operations on a sequence of unitary quantum gates (e.g., a sequence of CNOT gates) on the first quantum error detection code, the logical state of the first quantum error detection code |+ θ > Ｌ，１ n ２ Logical state of a second quantum error detection code that represents one logical qubit using multiple physical qubits |+ θ > Ｌ，２ Convert to |+. Then, the control device 121 sets the logic state of the second quantum error detection code to |+ θ > Ｌ，２ Get the error syndrome.
[0083] For example, the following modifications can be made. <Modification 1> In the above embodiment, the case in which the first quantum error detection code is the [[4,1,2]] code was described as an example, but it is not limited to this. In place of the [[4,1,2]] code, another quantum error detection code can be used as the first quantum error detection code ([[n １ ,k １ d １ It may also be used as a first quantum error detection code ([[n １ ,k １ d １ The available codes as ]] codes are n １ (n ２ >n １Therefore, any code that can be represented is acceptable. For example, the Iceberg code disclosed in reference 6 (Self, CN, Benedetti, M. & Amaro, D. Protecting expressive circuits with a quantum error detection code. Nat. Phys. 20, 219-224 (2024). <https: / / doi.org / 10.1038 / s41567-023-02282-2>) can be used as the first quantum error detection code. The Iceberg code has a code distance d １ Since the code is equal to 2, it is possible to detect a 1-qubit error. Also, the code distance d １ Signs such that ≠ 2 (for example, d １ =3) can also be used as the first quantum error detection code. For example, code distance d １ If the code =3 is adopted as the first quantum error detection code, it is also possible to perform an Rzzz rotation (an operation that rotates all three physical qubits in a Z direction at once) after generating the code state of the first quantum error detection code. <Modification 2> In the above embodiment, the case in which the second quantum error detection code is a Steane code ([[7,1,3]] code) was explained as an example, but it is not limited to this. In place of the Steane code, other quantum error detection codes can be used as the second quantum error detection code ([[n ２ ,k ２ d ２ It may also be used as a second quantum error detection code ([[n ２ ,k ２ d ２ The available codes as ]] codes are n ２ (n ２ >n １Therefore, any code that can be represented is acceptable. For example, the second quantum error detection code may be the [[23,1,7]] code. The [[23,1,7]] code is also called the Golay code. As mentioned above, the quantum error detection code is represented by n, k, and d. When representing a code using n, k, and d, it is possible to represent the code as [[required number of physical qubits n, createable number of logical qubits k, code distance d]]. For this reason, the [[23,1,7]] code is represented as [[required number of physical qubits n = n ２ =23, number of logical qubits that can be created k=k2=1, code distance d=d ２ =7]]. Figure 10A shows the logical state |+ when the second quantum error detection code is the [[23,1,7]] code. θ > Ｌ，２ This is an example of a quantum circuit for generating. Figures 10B, 10C, 10D, and 10E are enlarged views of different parts of the quantum circuit shown in Figure 10A. By using the circuit in Figure 10A, the logic state of the [[23,1,7]] code |+ θ > Ｌ，２ This can be generated. Specifically, by using the circuit in Figure 10A, the logic state of the [[4,1,2]] code |+ θ > Ｌ，１ Generates a logical state of the [[23,1,7]] code |+ θ > Ｌ，２ It can be converted to [this format].
[0084] <Modification 3> In the above embodiment, the logical state of the second quantum error detection code is |+ θ > Ｌ，２ The explanation used the circuit shown in Figure 5 as an example for generating the logic state of the second quantum error detection code |+ θ > Ｌ，２This can generate the following. Figure 11A is a diagram of the same circuit as in Figure 5, but drawn in a different way. In the diagram, "R" represents a reset to the |0> state, "H" represents an Adamard gate, and "Rzz" represents an Rzz rotation gate. Here, the qubits q0 to q6 in Figure 11A appear different from the |+> and |0> in Figure 5, but they are equivalent. This is because the R operation resets each qubit to the |0> state, and then some of the qubits become the |+> state due to the Adamard gate. The circuits shown in Figures 11B and 11C are equivalent to the circuit in Figure 11A. Specifically, the circuit in Figure 11B is the same as the circuit in Figure 11A with the CNOT gate replaced. The circuit in Figure 11C is the same as the circuit in Figure 11A with the CNOT gate replaced by a CZ gate (the gate with black dots at both ends in Figure 11C) and an H gate. Figures 12 to 14 illustrate equivalent gates. The combination of CNOT gates shown in Figure 12 is interchangeable. Furthermore, as shown in Figure 13, one CNOT gate can be replaced with a CZ gate and an H gate. Also, as shown in Figure 14, connecting two H gates in series can be equivalent to performing no operation. These substitution rules are described, for example, in reference 7 (Salehi, T., Zomorodi, M., Plawiak, P. et al. An optimizing method for performance and resource utilization in quantum machine learning circuits. Sci Rep 12, 16949 (2022)).<https: / / doi.org / 10.1038 / s41598-022-20375-5> ) is disclosed in <Modification 4> Figure 15A shows the logic state of the second quantum error detection code |+, similar to the circuit in Figure 11. θ > Ｌ，２This is a diagram of an example of a quantum circuit for generating [the specified error]. Figures 15B, 15C, and 15D are quantum circuit diagrams obtained by transforming the configuration of the quantum circuit shown in Figure 15A based on the substitution rules shown in Figures 12 to 14. <Modification 5> In the above embodiment, the case in which the error detection circuit for acquiring the error syndrome is Steane's gadget was described as an example, but it is not limited to this. For example, other error detection circuits such as the DiVincenzo-Shor's gadget and Knill's gadget may be used. The error detection circuit can be any circuit that is capable of acquiring the error syndrome. For example, various error detection circuits are disclosed in the above-mentioned document 5.
[0085] Furthermore, in the above embodiment, the transmission and reception of information between the classical computer 110 and the quantum computer 120 may be carried out in any manner. For example, the transmission and reception of quantum circuit parameters and measurement results between the classical computer 110 and the quantum computer 120 may be performed sequentially each time a predetermined calculation is completed, or it may be performed after all calculations have been completed.
[0086] Furthermore, although the above embodiment describes an example in which calculation target information is transmitted from the user terminal 130 to the classical computer 110 and the classical computer 110 performs calculations according to the calculation target information, the invention is not limited to this. The user terminal 130 may transmit the calculation target information to the classical computer 110 or to a storage medium or memory device accessible by the classical computer 110 via a computer network such as an IP network, or it may store the calculation target information in a storage medium or memory device and hand it over to the operator of the classical computer 110, who then inputs the calculation target information into the classical computer 110 using the storage medium or memory device.
[0087] Furthermore, although the above embodiment describes a case in which a quantum circuit is executed by irradiation with electromagnetic waves, it is not limited to this, and quantum circuits may be executed by different methods.
[0088] Furthermore, although the above embodiment describes the case in which the quantum computer 120 performs quantum computation, it is not limited to this. For example, quantum computation may be performed by a classical computer that simulates the behavior of a quantum computer.
[0089] Furthermore, while the above embodiment assumes that the classical computer 110 and the quantum computer 120 are managed by different organizations, the classical computer 110 and the quantum computer 120 may be managed as a single unit by the same organization. In this case, the transmission of quantum computation information from the classical computer 110 to the quantum computer 120 and the transmission of measurement results from the quantum computer 120 to the classical computer 110 become unnecessary. In this case, the control device 121 of the quantum computer 120 may assume the role of the classical computer 110 as described above.
[0090] In the embodiments described above, please note that unless the word "only" is used, such as in "based only on XX," "according only to XX," or "in the case of XX only," it is assumed in this specification that additional information may also be considered. For example, the statement "do b in the case of a" does not necessarily mean "always do b in the case of a" unless explicitly stated otherwise.
[0091] Furthermore, in the embodiments described above, when expressions such as "optimize" or "optimized parameters" are used, it should be noted that these expressions of "optimization" mean approaching the optimal state. Therefore, when attempting to obtain parameters that minimize a certain function, it should be noted that the parameters obtained by optimizing the function may not be the global solution that minimizes the function, but rather a local solution.
[0092] Furthermore, even if there are aspects of a method, program, terminal, device, server, or system (hereinafter referred to as "method, etc.") that perform operations different from those described herein, each aspect of the disclosed technology is intended to cover the same operations as any of those described herein, and the existence of operations different from those described herein does not mean that such method, etc. is outside the scope of each aspect of the disclosed technology.
[0093] Furthermore, although the present specification describes an embodiment in which the program is pre-installed, it is also possible to provide the program stored on a computer-readable recording medium.
[0094] In addition, the processing that the CPU reads and executes in the above embodiment may be executed by various processors other than the CPU. Examples of such processors include PLDs (Programmable Logic Devices) such as FPGAs (Field-Programmable Gate Arrays) whose circuit configuration can be changed after manufacturing, and dedicated electrical circuits that are processors with circuit configurations specifically designed to execute specific processing, such as ASICs (Application Specific Integrated Circuits). Furthermore, each processing may be executed by one of these various processors, or by a combination of two or more processors of the same or different types (for example, multiple FPGAs, and a combination of a CPU and an FPGA). More specifically, the hardware structure of these various processors is an electrical circuit that combines circuit elements such as semiconductor elements.
[0095] Furthermore, while the above embodiments describe a configuration in which the program is pre-stored (installed) on storage, the invention is not limited to this. The program may be provided in a form stored on a non-transitory storage medium such as a CD-ROM (Compact Disk Read Only Memory), DVD-ROM (Digital Versatile Disk Read Only Memory), or USB (Universal Serial Bus) memory. Alternatively, the program may be downloaded from an external device via a network.
[0096] Furthermore, each process in this embodiment may be configured by a computer or server equipped with a general-purpose processing unit and storage device, and each process may be executed by a program. This program is stored in the storage device and can be recorded on a recording medium such as a magnetic disk, optical disk, or semiconductor memory, or provided over a network. Of course, none of the other components have to be implemented by a single computer or server; they may be implemented in a distributed manner across multiple computers connected by a network.
[0097] Furthermore, each component of the hybrid system in this embodiment does not have to be implemented by a single computer or server, but may be implemented in a distributed manner across multiple computers connected by a network.
[0098] For example, the processing performed by the classical computer in the above embodiment may be distributed and processed by multiple classical computers connected by a network. Alternatively, for example, the processing performed by the quantum computer in each of the above embodiments may be distributed and processed by multiple quantum computers connected by a network. In this case, a hybrid system is configured with at least one classical computer and at least one quantum computer.
[0099] All documents, patent applications, and technical standards described herein are incorporated by reference to the same extent as if each individual document, patent application, and technical standard were specifically and individually noted to be incorporated by reference.
[0100] (Note) The following is a note regarding the nature of this disclosure.
[0101] (Note 1) n １ A quantum error detection code that represents one logical qubit using several physical qubits, and has a code distance d １ The logical state of the first quantum error detection code, which is the quantum error detection code |+〉 Ｌ，１ Generates the logical state of the first quantum error detection code |+〉 Ｌ，１ By performing a logic Rz rotation gate operation on the first quantum error detection code, the logic state of the first quantum error detection code |+ θ > Ｌ，１ Generates the logical state of the first quantum error detection code |+ θ > Ｌ，１ By performing a sequence of unitary quantum gate operations on the first quantum error detection code, the logical state |+ θ > Ｌ，１ n ２ pieces (n ２ >n １ The logical state of the second quantum error detection code, which represents one logical qubit using physical qubits, |+ θ > Ｌ，２ Convert to the logical state of the second quantum error detection code |+ θ > Ｌ，２ A quantum error detection method in which a computer performs a process to acquire the error syndrome. (Note 2) d １ = 2, the quantum error detection method described in Appendix 1. (Appendix 3) n １ = 4, the quantum error detection method described in Appendix 2. (Appendix 4) n ２ = 7, the quantum error detection method described in any one of the appendices 1 to 3. (Appendix 5) The quantum error detection method described in any one of the appendices 1 to 3, wherein the second quantum error detection code is a quantum error correction code. (Appendix 6) n１ = 4, d １ = 2, and the first quantum error detection code is a [[4,1,2]] code, the quantum error detection method described in any one of the appendices 1 to 5. (Appendix 7) n ２ = 7, and the second quantum error detection code is a Steane code, as described in Appendix 6 for the quantum error detection method. (Appendix 8) n ２ The quantum error detection method according to Appendix 6, wherein = 23, and the second quantum error detection code is the [[23,1,7]] code. (Appendix 9) The quantum error detection method according to any one of Appendix 1 to Appendix 8, wherein the error detection circuit for acquiring the error syndrome is an error detection circuit that performs at least one post-selection of Steane's gadget method, DiVincenzo-Shor's gadget method, and Knill's gadget method. (Appendix 10) The quantum error detection method according to any one of Appendix 1 to Appendix 8, comprising a processor, wherein the processor is n １ A quantum error detection code that represents one logical qubit using several physical qubits, and has a code distance d １ The logical state of the first quantum error detection code, which is the quantum error detection code |+〉 Ｌ，１ Generates the logical state of the first quantum error detection code |+〉 Ｌ，１ By performing a logic Rz rotation gate operation on the first quantum error detection code, the logic state of the first quantum error detection code |+ θ > Ｌ，１ Generates the logical state of the first quantum error detection code |+ θ > Ｌ，１ By performing a sequence of unitary quantum gate operations on the first quantum error detection code, the logical state |+ θ > Ｌ，１ n ２ n physical qubits ２ >n １ The logical state of the second quantum error detection code that represents one logical qubit by |+ θ > Ｌ，２ Convert to the logical state of the second quantum error detection code |+ θ > Ｌ，２A quantum error detection device that acquires the error syndrome. (Note 11) n １ A quantum error detection code that represents one logical qubit using several physical qubits, and has a code distance d １ The logical state of the first quantum error detection code, which is the quantum error detection code |+〉 Ｌ，１ Generates the logical state of the first quantum error detection code |+〉 Ｌ，１ By performing a logic Rz rotation gate operation on the first quantum error detection code, the logic state of the first quantum error detection code |+ θ > Ｌ，１ Generates the logical state of the first quantum error detection code |+ θ > Ｌ，１ By performing a sequence of unitary quantum gate operations on the first quantum error detection code, the logical state |+ θ > Ｌ，１ n ２ The logical state of the second quantum error detection code, which represents one logical qubit using several physical qubits |+ θ > Ｌ，２ Convert to the logical state of the second quantum error detection code |+ θ > Ｌ，２ A quantum error detection program that causes a computer to perform a process to acquire the error syndrome.
Claims
1. An １ error-detecting quantum code that represents one logical qubit with n １ physical qubits, and has a code distance d Ｌ，１ generates the logical state |+〉 of the first error-detecting quantum code, and Ｌ，１ performs a logical Rz rotation gate operation on the logical state |+〉 of the first error-detecting quantum code to generate the logical state |+ θ 〉 Ｌ，１ of the first error-detecting quantum code, and θ 〉 Ｌ，１ performs a sequence of unitary quantum gate operations on the logical state |+ θ 〉 Ｌ，１ of the first error-detecting quantum code to convert the logical state |+ ２ 〉 of the first error-detecting quantum code to the logical state |+ ２ 〉 of a second error-detecting quantum code that represents one logical qubit with n １ (n θ > n Ｌ，２ θ 〉 of the second error-detecting quantum code, and 〉 Ｌ，２ [[ID=3Gets the error syndrome of the logical state |+〉 of the second error-detecting quantum code. A quantum error-detecting method executed by a computer.
2. d １ The quantum error detection method according to claim 1, wherein the value is 2.
3. n １ The quantum error detection method according to claim 2, wherein the result is 4.
4. n ２ The quantum error detection method according to claim 3, wherein the result is 7.
5. The quantum error detection method according to claim 1 or claim 2, wherein the second quantum error detection code is a quantum error correction code.
6. n １ = 4, d １ The quantum error detection method according to claim 1 or claim 2, wherein = 2, and the first quantum error detection code is a [[4,1,2]] code.
7. n ２ The quantum error detection method according to claim 6, wherein the second quantum error detection code is a Steane code, and the value of the second quantum error detection code is 7.
8. n ２ The quantum error detection method according to claim 6, wherein = 23, and the second quantum error detection code is the [[23,1,7]] code.
9. The quantum error detection method according to claim 1 or 2, wherein the error detection circuit for acquiring the error syndrome is an error detection circuit that performs at least one post-selection of the Steane's gadget method, the DiVincenzo-Shor's gadget method, and the Knill's gadget method.
10. A processor comprising n １ A quantum error detection code that represents one logical qubit using several physical qubits, and has a code distance d １ The logical state of the first quantum error detection code, which is the quantum error detection code |+〉 Ｌ，１ Generates the logical state of the first quantum error detection code |+〉 Ｌ，１ By performing a logic Rz rotation gate operation on the first quantum error detection code, the logic state of the first quantum error detection code |+ θ > Ｌ，１ Generates the logical state of the first quantum error detection code |+ θ > Ｌ，１ By performing a sequence of unitary quantum gate operations on the first quantum error detection code, the logical state |+ θ > Ｌ，１ n ２ pieces (n ２ >n １ The logical state of the second quantum error detection code, which represents one logical qubit using physical qubits, |+ θ > Ｌ，２ Convert to the logical state of the second quantum error detection code |+ θ > Ｌ，２ A quantum error detection device that acquires error syndromes.
11. n １ A quantum error detection code that represents one logical qubit using several physical qubits, and has a code distance d １ The logical state of the first quantum error detection code, which is the quantum error detection code |+〉 Ｌ，１ Generates the logical state of the first quantum error detection code |+〉 Ｌ，１ By performing a logic Rz rotation gate operation on the first quantum error detection code, the logic state of the first quantum error detection code |+ θ > Ｌ，１ Generates the logical state of the first quantum error detection code |+ θ > Ｌ，１ By performing a sequence of unitary quantum gate operations on the first quantum error detection code, the logical state |+ θ > Ｌ，１ n ２ pieces (n ２ >n １ The logical state of the second quantum error detection code, which represents one logical qubit using physical qubits, |+ θ > Ｌ，２ Convert to the logical state of the second quantum error detection code |+ θ > Ｌ，２ A quantum error detection program that causes a computer to perform a process to acquire the error syndrome.