Semiconductor integrated circuit device

Abstract

An inverter cell (C2) having a logical function and a filler cell (C3) having no logical function are arranged across cell strings (CR1, CR2). The inverter cell (C2) is provided with an active region (2P2) and an active region (2N3) formed above the active region (2P2). The filler cell (C3) is provided with an active region (2P3) and an active region (2N3) formed above the active region (2P3). The active regions (2P2, 2P3) are formed across the cell string boundary and have the same width and position in a second direction.

Description

Semiconductor integrated circuit device

[0001] The present disclosure relates to a semiconductor integrated circuit device including a standard cell (hereinafter, also simply referred to as a cell for convenience) including a CFET (Complementary FET).

[0002] As a method of forming a semiconductor integrated circuit on a semiconductor substrate, a standard cell method is known. The standard cell method is a method of designing an LSI chip by previously preparing basic units having specific logic functions (for example, inverters, latches, flip - flops, full - adders, etc.) as standard cells, arranging a plurality of standard cells on a semiconductor substrate, and connecting these standard cells with wiring.

[0003] Also, transistors, which are basic components of LSIs, have achieved improved integration density, reduced operating voltage, and improved operating speed by reducing the gate length (scaling). However, in recent years, the off - current due to excessive scaling and the resulting significant increase in power consumption have become problems. To solve this problem, three - dimensional structure transistors in which the transistor structure is changed from a conventional planar type to a three - dimensional type have been actively studied. Among them, nanosheet FETs have attracted attention as one type of three - dimensional structure transistors.

[0004] Patent Document 1 discloses the structure of a semiconductor integrated circuit device in which a normal cell and a double - height cell having a cell height twice that of the normal cell are mixed in a circuit block composed of standard cells using CFETs.

[0005] Patent Document 2 discloses the structure of a filler cell, which is a cell having no logic function, arranged adjacent to a cell having a logic function in a circuit block composed of standard cells using CFETs.

[0006] U.S. Patent Application Publication No. 2020 / 0328201, International Publication No. 2020 / 137660

[0007] In the semiconductor integrated circuit device described in Patent Document 1, standard cells with different active region widths are arranged adjacent to each other. However, when adjacent active region widths differ, the manufacturing precision of the semiconductor integrated circuit device decreases, making it impossible to obtain the desired performance. Furthermore, because the distance from the active region located at the cell edge to the active region of the adjacent cell differs, the accuracy of the transistor performance estimation decreases.

[0008] This disclosure aims to provide a semiconductor integrated circuit layout that improves the manufacturing precision of semiconductor integrated circuit devices and the accuracy of transistor performance estimation, with respect to filler cells using CFETs.

[0009] In aspects of the present disclosure, a semiconductor integrated circuit device comprises a plurality of cell rows, each having a plurality of standard cells aligned in a first direction, the plurality of cell rows being arranged in a second direction perpendicular to the first direction, the first cell row having a first standard cell having logic function, the first cell row and the second cell row adjacent to the first cell row in the second direction having a second standard cell having logic function arranged across the cell row boundary which is the boundary between the first cell row and the second cell row, and a third standard cell not having logic function arranged across the cell row boundary which is the boundary between the first cell row and the second cell row, the first standard cell constituting the channel, source, and drain of a first transistor of a first conductivity type, the channel comprising a first active region including a first nanosheet extending in the first direction, and a second transistor of a second conductivity type formed above the first active region in the depth direction and overlapping with the first active region in a plan view The third standard cell comprises a channel, source, and drain, the channel comprising a second active region including a second nanosheet extending in the first direction, the second standard cell is formed in the same layer as the first active region in the depth direction and comprises a channel, source, and drain of a third transistor of the first conductivity type, the channel comprising a third active region including a third nanosheet extending in the first direction, the channel comprising a fourth active region formed in the same layer as the second active region in the depth direction and comprising a fourth active region including a fourth nanosheet extending in the first direction, the channel comprising a fifth active region formed in the same layer as the first active region in the depth direction and a sixth active region formed in the same layer as the second active region in the depth direction, the third and fifth active regions are formed across the cell column boundary and have the same width and position in the second direction.

[0010] According to this disclosure, the third active region in the second standard cell and the fifth active region in the third standard cell have the same width and position in the second direction. This improves the manufacturing precision of semiconductor integrated circuit devices and improves the accuracy of transistor performance estimation.

[0011] According to this disclosure, with respect to filler cells using CFETs, it is possible to improve the manufacturing precision of semiconductor integrated circuit devices and to improve the accuracy of transistor performance estimation.

[0012] A plan view showing an example of the layout of a circuit block in a semiconductor integrated circuit device according to an embodiment. A plan view of part A1 in Figure 1. A cross-sectional view in Figure 2. A cross-sectional view in Figure 2. Circuit diagram of an inverter cell. A plan view showing an example of the layout of a circuit block in a semiconductor integrated circuit device according to a modified example.

[0013] The embodiments will be described below with reference to the drawings. In the following embodiments, the semiconductor integrated circuit device comprises a plurality of standard cells. At least some of these standard cells are equipped with nanosheet FETs, and furthermore, they are equipped with a CFET structure in which transistors with different conductivity types (in this embodiment, the lower part of the cell is P-conducting and the upper part of the cell is N-conducting) are stacked.

[0014] Furthermore, in this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. Also, in this specification, expressions meaning that widths, etc., are the same, such as "same wiring width," include a range of manufacturing variations.

[0015] (Embodiment) (Circuit Block Configuration) Figure 1 is a plan view showing an example of the layout of a circuit block in a semiconductor integrated circuit device according to an embodiment. In Figure 1, only the power supply wiring formed on the back wiring layer provided on the back of the semiconductor chip on which the transistors are formed is shown, and everything else is omitted from the illustration.

[0016] The circuit block layout in Figure 1 is constructed by arranging standard cells. In this embodiment, power supply wiring is formed on the BM0 (Backside Metal 0) wiring layer, which is a wiring layer (back wiring layer) provided on the back of the semiconductor chip on which the transistor is formed, and on the M0 wiring layer, which is a metal wiring layer above the transistor.

[0017] In the following explanation, in plan views such as Figure 1, the horizontal direction of the drawing is referred to as the X direction (corresponding to the first direction), the vertical direction of the drawing as the Y direction (corresponding to the second direction), and the direction perpendicular to the substrate surface as the Z direction (corresponding to the depth direction). Also, in the following explanation, the same symbols refer to the same thing, and explanations may be omitted.

[0018] Furthermore, in plan views such as Figure 1, the solid lines surrounding the cells indicate the cell frame (outer edge of the standard cell) of the standard cell. Standard cells are arranged so that their cell frames touch the cell frames of adjacent cells in the X or Y direction.

[0019] In the layout shown in Figure 1, multiple cells aligned in the X direction constitute a cell column CR (in this case, 6 columns). These cells include cells with logic functions such as inverters, NAND gates, and NOR gates. The cells also include inverter cells C1 and C2 and filler cell C3, which have logic functions. A "filler cell" is a cell that does not have logic functions, does not contribute to the logic function of the circuit block, and is placed between logic cells.

[0020] In the layout shown in Figure 1, cell rows CR1 and CR2 are arranged adjacent to each other in the Y direction. Cell row CR1 contains inverter cell C1 (C1a). Cell row CR2 contains inverter cell C1 (C1b).

[0021] Inverter cell C2 and filler cell C3 are double-height cells. Inverter cell C2 and filler cell C3 are located in cell rows CR1 and CR2. Specifically, inverter cell C2 and filler cell C3 are located across the cell row boundary of cell rows CR1 and CR2. Filler cell C3 is located between inverter cells C1 (C1a, C1b) and C2.

[0022] Each cell has power wiring formed in the center of the Y direction in the BM0 wiring layer and the M0 wiring layer. Specifically, the BM0 wiring layer has power wiring (power wiring 11, described later) that supplies the power supply voltage VDD, and the M0 wiring layer has power wiring (power wiring 51, described later) that supplies the power supply voltage VSS. Through this power wiring, each cell receives the power supply voltages VDD and VSS from the outside. In other words, in the block layout of Figure 1, power wiring that is continuous in the X direction is formed in the BM0 wiring layer and the M0 wiring layer of cell row CR.

[0023] In the following explanation, the inverter cell C1 located in cell row CR1 may be referred to as inverter cell C1a, and the inverter cell C1 located in cell row CR2 may be referred to as inverter cell C1b. Also, the power supply wirings 11 and 51 formed in cell row CR1 may be referred to as power supply wirings 11a and 51a, respectively, and the power supply wirings 11 and 51 formed in cell row CR2 may be referred to as power supply wirings 11b and 51b.

[0024] (Configuration of Inverter Cell C1) Figure 2 is a plan view of part A1 in Figure 1, Figures 3 and 4 are cross-sectional views in Figure 2, and Figure 5 is a circuit diagram of the inverter cell. Specifically, Figure 2(a) shows the lower part of the cell, Figure 2(b) shows the upper part of the cell, Figure 3(a) is a cross-section along line X1-X1' in Figure 2, Figure 3(b) is a cross-section along line Y1-Y1' in Figure 2, Figure 4(a) is a cross-section along line Y2-Y2' in Figure 2, and Figure 4(b) is a cross-section along line Y3-Y3' in Figure 2.

[0025] Furthermore, in the following explanation, the dashed lines running vertically and horizontally in plan views such as Figure 2, and the dashed lines running vertically in cross-sectional views such as Figure 2, indicate a grid used for arranging components during the design phase. The grid is arranged at equal intervals in the X direction and at equal intervals in the Y direction. Note that the grid spacing may be the same or different in the X and Y directions. Also, the grid spacing may differ from layer to layer. Moreover, each component does not necessarily have to be placed on the grid.

[0026] As shown in Figure 2(a), a power supply wiring 11 extending in the X direction is formed in the BM0 wiring layer at the center of the cell in the Y direction. The power supply wiring 11 supplies the power supply voltage VDD.

[0027] In the P-type transistor region at the bottom of the cell, active regions constituting the channel, source, and drain of the P-type transistor are formed. Specifically, an active region 2P1 is formed in the P-type transistor region. In a plan view, the active region 2P1 overlaps with the power supply wiring 11.

[0028] A P-type transistor P1 is formed in the P-type transistor region. Transistor P1, as a channel, consists of three overlapping sheet structures in a plan view (not shown) and has a nanosheet 21 extending in the X direction. In the active region 2P1, the source portion of transistor P1 is connected to the power supply wiring 11 via vias 61 and local wiring 41.

[0029] As shown in Figure 2(b), the active regions constituting the channel, source, and drain of the N-type transistor are formed in the N-type transistor region at the top of the cell. Specifically, an active region 2N1 is formed in the N-type transistor region. Active region 2N1 is located above active region 2P1 in the Z direction. Active region 2N1 overlaps with active region 2P1 in a plan view.

[0030] An N-type transistor N1 is formed in the N-type transistor region. Transistor N1, as a channel, consists of three overlapping sheet structures in a plan view (not shown) and has a nanosheet 22 extending in the X direction.

[0031] Regarding the active region, the source and drain portions on both sides of the nanosheet are formed, for example, by epitaxial growth from the nanosheet.

[0032] In the X-direction of the cell, a gate wiring 31 is formed in the center of the diagram, extending in the Y-direction and extending in the Z-direction from the top to the bottom of the cell. The nanosheets 21 and 22 overlap with the gate wiring 31 in a plan view. The gate wiring 31 corresponds to the gates of transistors P1 and N1.

[0033] Dummy gate wiring 32 and 33 are formed on the cell frames on both sides in the X direction, extending in the Y and Z directions. Dummy gate wiring 32 is shared with other cells located on the left side of the drawing. Dummy gate wiring 33 is shared with other cells located on the right side of the drawing (filler cell C3 in Figure 1).

[0034] The dummy gate wiring 32, gate wiring 31, and dummy gate wiring 33 are arranged at the same pitch in the X direction. Furthermore, gate wiring 31 and dummy gate wirings 32 and 33 are formed with the same width in the X direction.

[0035] As shown in Figure 2(a), local interconnects (LI) 41 and 42 extending in the Y direction are formed at the bottom of the cell. Local interconnect 41 is connected to the source portion of transistor P1 in the active region 2P1. Local interconnect 42 is connected to the drain portion of transistor P1 in the active region 2P1.

[0036] As shown in Figure 2(b), local wirings 43 and 44 extending in the Y direction are formed on the upper part of the cell. Local wiring 43 is connected to the source portion of transistor N1 in the active region 2N1. Local wiring 44 is connected to the drain portion of transistor N1 in the active region 2N1.

[0037] In the M0 wiring layer, which is a metal wiring layer located above the active region 2N1, power supply wiring 51 and wirings 52 and 53 extending in the X direction are formed. Power supply wiring 51 supplies the power supply voltage VSS. Wiring 52 corresponds to input A, and wiring 53 corresponds to output Y.

[0038] The power supply wiring 51 is formed in the center of the cell in the Y direction. In a plan view, the power supply wiring 51 overlaps with the active region 2N1. The power supply wiring 51 is connected to the source portion of transistor N1 in the active region 2N1 via via 62 and local wiring 43.

[0039] The wiring 52 is located on the lower side of the cell in the Y direction. The wiring 52 is connected to the gate wiring 31 via a via 63. The via 63 is formed in the region where the wiring 52 and the gate wiring 31 overlap in a plan view.

[0040] Wiring 53 is located on the upper side of the cell in the Y direction. Wiring 53 is connected to the drain portion of transistor P1 and the drain portion of transistor N1 via vias 64, 65 and local wires 42, 44.

[0041] As described above, the inverter cell C1 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit with input A and output Y. In other words, the inverter cell C1 is a standard cell with logic functionality.

[0042] As shown in Figures 2(a) and 2(b), the active regions 2P1 and 2N1 in the inverter cell C1 have a width w1 in the Y direction when viewed from above.

[0043] (Configuration of Inverter Cell C2) The inverter cell C2 has substantially the same configuration as the inverter cell C1. Specifically, the inverter cell C2 has a P-type transistor P1 and an N-type transistor N1, and realizes an inverter circuit for input A and output Y. That is, the inverter cell C2 is a standard cell having a logical function.

[0044] The inverter cell C2 is a double-height cell and is arranged across the cell column boundaries of the cell columns CR1 and CR2.

[0045] As shown in Fig. 2(a), power supply wirings 11a and 11b extending in the X direction are formed in the BM0 wiring layer. The power supply wiring 11a is formed at the upper part of the cell in the Y direction of the drawing, and the power supply wiring 11b is formed at the lower part of the cell in the Y direction of the drawing. The power supply wirings 11a and 11b supply the power supply voltage VDD.

[0046] An active region 2P2 is formed in the P-type transistor region at the lower part of the cell. The active region 2P2 overlaps the power supply wirings 11a and 11b in plan view.

[0047] A transistor P1 is formed in the active region 2P2. The transistor P1 has a nanosheet 23 extending in the X direction. The portion serving as the source of the transistor P1 in the active region 2P2 is connected to the power supply wiring 11a via a via 66 and a local wiring 45, and is connected to the power supply wiring 11b via a via 67 and a local wiring 45.

[0048] As shown in Fig. 2(b), an active region 2N2 is formed in the N-type transistor region at the upper part of the cell. The active region 2N2 overlaps the power supply wirings 51a and 51b in plan view. A transistor N1 is formed in the active region 2N2. The transistor N1 has a nanosheet 24 extending in the X direction.

[0049] A gate wiring 34 extending in the Y and Z directions is formed. The nanosheets 23 and 24 overlap the gate wiring 34 in plan view. The gate wiring 34 corresponds to the gates of the transistors P1 and N1.

[0050] Dummy gate wiring 35 and 36 are formed on the cell frames on both sides in the X direction, extending in the Y and Z directions. Dummy gate wiring 35 is shared with another cell located on the left side of the drawing (filler cell C3 in Figure 2). Dummy gate wiring 36 is shared with another cell located on the right side of the drawing.

[0051] The dummy gate wiring 35, gate wiring 34, and dummy gate wiring 36 are arranged at the same pitch in the X direction. Furthermore, gate wiring 34 and dummy gate wirings 35 and 36 are formed with the same width in the X direction.

[0052] As shown in Figure 2(a), local wirings 45 and 46 extending in the Y direction are formed at the bottom of the cell. Local wiring 45 is connected to the source portion of transistor P1 in the active region 2P2. Local wiring 46 is connected to the drain portion of transistor P1 in the active region 2P2.

[0053] As shown in Figure 2(b), local wirings 47 and 48 extending in the Y direction are formed on the upper part of the cell. Local wiring 47 is connected to the source portion of transistor N1 in the active region 2N2. Local wiring 48 is connected to the drain portion of transistor N1 in the active region 2N2.

[0054] Power supply wirings 51a and 51b extending in the X direction are formed in the M0 wiring layer. Power supply wiring 51a is formed in the upper part of the cell in the Y direction, and power supply wiring 51b is formed in the lower part of the cell in the Y direction. Power supply wirings 51a and 51b supply the power supply voltage VSS. The active region 2N2 overlaps with the power supply wirings 51a and 51b in a plan view.

[0055] Power supply wiring 51a is connected via via 68 and local wiring 47 to the source portion of transistor N1 in the active region 2N2. Power supply wiring 51b is connected via via 69 and local wiring 47 to the source portion of transistor N1 in the active region 2N2.

[0056] As shown in Figures 2(a) and (b), the inverter cell C2 has active regions 2P2 and 2N2. The active regions 2P2 and 2N2 have a width w2 in the Y direction. w2 is greater than twice w1 (w2 > w1 × 2). That is, the drive capacity of inverter cell C2 is greater than the drive capacity of inverter cell C1. Furthermore, the active regions 2P2 and 2N2 are formed spanning the cell column boundaries of cell columns CR1 and CR2.

[0057] (Configuration of filler cell C3) As shown in Figure 1, filler cell C3 is located between inverter cells C1 (C1a, C1b) and C2. Filler cell C3 is a double-height cell and is located across the cell column boundary of cell columns CR1 and CR2.

[0058] As shown in Figure 2(a), the BM0 wiring layer has power supply wiring 11a, 11b and wiring 111-114 extending in the X direction. Power supply wiring 11a is formed at the top of the cell in the Y direction, and power supply wiring 11b is formed at the bottom of the cell in the Y direction. Power supply wiring 11a and 11b supply the power supply voltage VDD. Wiring 111 and 112 are formed at the top and bottom of the power supply wiring 11a in the Y direction, respectively. Wiring 113 and 114 are formed at the top and bottom of the power supply wiring 11b in the Y direction, respectively.

[0059] An active region 2P3 is formed in the P-type transistor region at the bottom of the cell. In a plan view, the active region 2P3 overlaps with the power supply wiring 11a and 11b.

[0060] A P-type dummy transistor DP1 is formed in the active region 2P3. The dummy transistor DP1 has a channel consisting of three overlapping sheet structures in a plan view and a nanosheet 121 extending in the X direction.

[0061] As shown in Figure 2(b), an active region 2N3 is formed in the N-type transistor region at the top of the cell. The active region 2N3 overlaps with the active region 2P3 in a plan view. The active region 2N3 overlaps with the power supply wiring 51a and 51b in a plan view.

[0062] An N-type dummy transistor DN1 is formed in the active region 2N3. The dummy transistor DN1 has a channel consisting of three overlapping sheet structures in a plan view and a nanosheet 122 extending in the X direction.

[0063] Dummy gate wiring 131 is formed extending in the Y and Z directions. Nanosheets 121 and 122 overlap with the dummy gate wiring 131 in a plan view. The dummy gate wiring 131 corresponds to the gates of dummy transistors DP1 and DN1.

[0064] As shown in Figure 2(a), local wirings 141 and 142 extending in the Y direction are formed at the bottom of the cell. Local wiring 141 is connected to the source portion of the dummy transistor DP1 in the active region 2P3. Local wiring 142 is connected to the drain portion of the dummy transistor DP1 in the active region 2P3.

[0065] As shown in Figure 2(b), local wirings 143 and 144 extending in the Y direction are formed on the upper part of the cell. Local wiring 143 is connected to the source portion of dummy transistor DN1 in the active region 2N3. Local wiring 144 is connected to the drain portion of dummy transistor DN1 in the active region 2N3.

[0066] The M0 wiring layer has power supply wiring 51a, 51b and wiring 151-154 extending in the X direction. Power supply wiring 51a is formed at the top of the cell in the Y direction, and power supply wiring 51b is formed at the bottom of the cell in the Y direction. Power supply wiring 51a and 51b supply the power supply voltage VDD. Wiring 151 and 152 are formed at the top and bottom of the power supply wiring 51a in the Y direction, respectively. Wiring 153 and 154 are formed at the top and bottom of the power supply wiring 51b in the Y direction, respectively.

[0067] In filler cell C3 shown in Figure 2, unlike inverter cells C1 and C2, the dummy gate wiring 131 and local wiring 141-144 are not connected to any other wiring. In other words, filler cell C3 is a standard cell that does not have logic functionality.

[0068] As shown in Figures 2(a) and 2(b), the active regions 2P3 and 2N3 of filler cell C3 have a width of w2 in the Y direction. The active regions 2P3 and 2N3 are formed across the cell column boundaries of cell columns CR1 and CR2.

[0069] Furthermore, the dummy gate wiring 131 in filler cell C3 is formed at the same position in the Y direction as the gate wiring 34 and dummy gate wirings 35 and 36 of inverter cell C2, and is formed to the same length. Also, the dummy gate wiring 131, dummy gate wiring 35, gate wiring 34, and dummy gate wiring 35 are arranged at the same pitch in the X direction, and the positions of both ends in the Y direction coincide.

[0070] Furthermore, the local wiring 141 and 142 in filler cell C3 have the same positions at both ends in the Y direction as the local wiring 45 and 46 in inverter cell C2. The local wiring 141, 142, 45, and 46 are arranged at the same pitch in the X direction. The local wiring 143 and 144 in filler cell C3 have the same positions at both ends in the Y direction as the local wiring 47 and 48 in inverter cell C2. The local wiring 143, 144, 47, and 48 are arranged at the same pitch in the X direction.

[0071] With the above configuration, in cell rows CR1 and CR2, an inverter cell C2 having logic functionality and a filler cell C3 without logic functionality are arranged adjacent to each other in the X direction. The nanosheets 121 (122) of the filler cell C3 have the same width and position in the Y direction as the nanosheets 23 (24) of the inverter cell C2. This makes it possible to suppress variations in the finished shape of the layout pattern of the semiconductor integrated circuit device, thereby suppressing manufacturing variations in the semiconductor integrated circuit device, improving yield, and improving reliability.

[0072] Furthermore, the active region 2P2 (2N2) in the inverter cell C2 and the active region 2P3 (2N3) in the filler cell C3 have the same width w2 in the Y direction and are located at the same position in the Y direction. This improves the manufacturing precision of semiconductor integrated circuit devices and also improves the accuracy of transistor performance estimation.

[0073] Furthermore, the Y-direction width of the active region 2P1 (2N1) in inverter cell C1 is w1, which is smaller than the Y-direction width w2 of the active region 2P3 (2N3) in filler cell C3. The upper edge of the drawing in the Y-direction of the active region 2P1 (2N1) of inverter cell C1a and the upper edge of the drawing in the Y-direction of the active region 2P3 (2N3) of filler cell C3 are at the same position in the Y-direction. The lower edge of the drawing in the Y-direction of the active region 2P1 (2N1) of inverter cell C1b and the lower edge of the drawing in the Y-direction of the active region 2P3 (2N3) of filler cell C3 are at the same position in the Y-direction. As a result, the active region 2P3 (2N3) of filler cell C3 is positioned close to the active region 2P1 (2N1) of inverter cell C1, so that the distance from the active region of inverter cell C1 to the active region of the adjacent filler cell C3 can be kept constant, and the accuracy of transistor performance estimation can be improved.

[0074] Furthermore, the dummy gate wiring 32, gate wiring 31, and dummy gate wiring 33 in inverter cell C1, the dummy gate wiring 131 in filler cell C3, and the dummy gate wiring 35, gate wiring 34, and dummy gate wiring 36 in inverter cell C2 are arranged at the same pitch in the X direction. As a result, the gate wiring (including dummy gate wiring) in inverter cells C1, C2, and filler cell C3 is arranged regularly, which helps to suppress manufacturing variations in semiconductor integrated circuit devices and improve yield.

[0075] Furthermore, the local wiring 41 and 42 in inverter cell C1, the local wiring 141 and 142 in filler cell C3, and the local wiring 45 and 46 in inverter cell C2 are arranged at the same pitch in the X direction. The local wiring 43 and 44 in inverter cell C1, the local wiring 143 and 144 in filler cell C3, and the local wiring 47 and 48 in inverter cell C2 are also arranged at the same pitch in the X direction. As a result, the local wiring in inverter cells C1 and C2 and filler cell C3 is arranged regularly at the top and bottom of the cells, respectively, which helps to suppress manufacturing variations in semiconductor integrated circuit equipment and improve yield.

[0076] In this embodiment, the filler cell C3 is provided with local wiring 141-144 and wiring 111-114, 151-154, but some or all of these may not be provided.

[0077] (Modified Version) Figure 6 is a plan view showing an example of the layout of a circuit block in a semiconductor integrated circuit device according to a modified version. Specifically, Figure 6(a) shows the lower part of the cell, and Figure 6(b) shows the upper part of the cell. In Figure 6, compared to Figure 2, the size of the filler cell C3 in the X direction is 4 grids, and the filler cell C3 is further provided with active regions 2P4, 2P5, 2N4, 2N5, dummy gate wiring 132, 133, and local wiring 145-148.

[0078] As shown in Figure 6(a), active regions 2P4 and 2P5 are formed in the P-type transistor region at the bottom of the cell. In a plan view, the active regions 2P4 and 2P5 overlap with the power supply wiring 11a and 11b, respectively.

[0079] In the active regions 2P4 and 2P5, p-type dummy transistors DP2 and DP3 are formed, respectively. The dummy transistors DP2 and DP3 have nanosheets 123 and 124 extending in the X direction as channels.

[0080] As shown in Figure 6(b), active regions 2N4 and 2N5 are formed in the N-type transistor region at the top of the cell. Active regions 2N4 and 2N5 overlap with active regions 2P4 and 2N5 in a plan view. Active regions 2N4 and 2N5 also overlap with power supply wiring 51a and 51b in a plan view.

[0081] In the active regions 2N4 and 2N5, N-type dummy transistors DN2 and DN3 are formed. The dummy transistors DN2 and DN3 have nanosheets 125 and 126 extending in the X direction as channels.

[0082] Dummy gate wirings 132 and 133 extending in the Y and Z directions are formed. Nanosheets 123 to 126 overlap with the dummy gate wirings 132 in a plan view. The dummy gate wirings 132 correspond to the gates of dummy transistors DP2, DP3, DN2, and DN3.

[0083] As shown in Figure 6(a), local wirings 145 and 146 extending in the Y direction are formed at the bottom of the cell. Local wiring 145 is connected to the source portion of dummy transistor DP2 in active region 2P4 and to the source portion of dummy transistor DP3 in active region 2P5, respectively. Local wiring 146 is connected to the drain portion of dummy transistor DP2 in active region 2P4 and to the drain portion of dummy transistor DP3 in active region 2P5.

[0084] As shown in Figure 6(b), local wirings 147 and 148 extending in the Y direction are formed on the upper part of the cell. Local wiring 147 is connected to the source portion of dummy transistor DN2 in the active region 2N4 and to the source portion of dummy transistor DN3 in the active region 2N5, respectively. Local wiring 148 is connected to the drain portion of dummy transistor DN2 in the active region 2N4 and to the drain portion of dummy transistor DN3 in the active region 2N5.

[0085] In Figure 6, the active region 2P4 (2N4) is located adjacent to the active region 2P1 (2N1) of inverter cell C1a in the upper left part of the cell diagram. The active region 2P5 (2N5) is located adjacent to the active region 2P1 (2N1) of inverter cell C1b in the lower left part of the cell diagram. The active regions 2P4, 2P5, 2N4, and 2N5 have a width w1 in the Y direction.

[0086] Furthermore, the dummy gate wirings 131-133 in the filler cell C3 are formed at the same position in the Y direction as the gate wiring 34 and dummy gate wirings 35 and 36 of the inverter cell C2, and are formed to the same length. In addition, the dummy gate wirings 131-133, dummy gate wiring 35, gate wiring 34, and dummy gate wiring 36 are arranged at the same pitch in the X direction, and the positions of both ends in the Y direction coincide.

[0087] Furthermore, the local wirings 141, 142, 145, and 146 in filler cell C3 have the same positions at both ends in the Y direction as the local wirings 45 and 46 in inverter cell C2. The local wirings 145, 146, 141, 142, 45, and 46 are arranged at the same pitch in the X direction. The local wirings 143, 144, 147, and 148 in filler cell C3 have the same positions at both ends in the Y direction as the local wirings 47 and 48 in inverter cell C2. The local wirings 147, 148, 143, 144, 47, and 48 are arranged at the same pitch in the X direction.

[0088] In the configuration shown in Figure 6, the nanosheet 123 (125) of filler cell C3 has the same width and position in the Y direction as the nanosheet 21 (22) of inverter cell C1a. The nanosheet 124 (126) of filler cell C3 has the same width and position in the Y direction as the nanosheet 21 (22) of inverter cell C1b. This makes it possible to suppress variations in the finished shape of the layout pattern of the semiconductor integrated circuit device, thereby reducing manufacturing variations in the semiconductor integrated circuit device, improving yield, and improving reliability.

[0089] Furthermore, the active region 2P1 (2N1) in inverter cell C1a and the active region 2P4 (2N4) in filler cell C3 have the same width w1 in the Y direction and are located in the same position in the Y direction. The active region 2P1 (2N1) in inverter cell C1b and the active region 2P5 (2N5) in filler cell C3 have the same width w1 in the Y direction and are located in the same position in the Y direction. This improves the manufacturing precision of semiconductor integrated circuit devices and improves the accuracy of transistor performance estimation.

[0090] Furthermore, the dummy gate wiring 32, gate wiring 31, and dummy gate wiring 33 in inverter cell C1, the dummy gate wirings 132, 133, and 131 in filler cell C3, and the dummy gate wiring 35, gate wiring 34, and dummy gate wiring 36 in inverter cell C2 are arranged at the same pitch in the X direction. As a result, the gate wiring (including dummy gate wiring) in inverter cells C1, C2, and filler cell C3 is arranged regularly, which can suppress manufacturing variations in semiconductor integrated circuit equipment and improve yield.

[0091] Furthermore, the local wiring 41 and 42 in inverter cell C1, the local wiring 145, 146, 141, and 142 in filler cell C3, and the local wiring 45 and 46 in inverter cell C2 are arranged at the same pitch in the X direction. The local wiring 43 and 44 in inverter cell C1, the local wiring 147, 148, 143, and 144 in filler cell C3, and the local wiring 47 and 48 in inverter cell C2 are also arranged at the same pitch in the X direction. As a result, the local wiring in inverter cells C1, C2 and filler cell C3 is regularly arranged in the upper and lower parts of the cells, respectively, which can suppress manufacturing variations in semiconductor integrated circuit equipment and improve yield.

[0092] In this modified example, the filler cell C3 is assumed to include local wiring 141-148 and wiring 111-114 and 151-154, but some or all of these may not be included.

[0093] In the embodiments and modifications described above, each transistor is provided with three nanosheets, but some or all of the transistors may be provided with one, two, or four or more nanosheets.

[0094] Furthermore, while the cross-sectional shape of the nanosheet is rectangular in each of the embodiments and modifications described above, it is not limited to this. For example, it may be square, circular, elliptical, or the like.

[0095] Furthermore, in the embodiments and modifications described above, a P-type transistor is formed at the bottom of the cell and an N-type transistor at the top of the cell, but the invention is not limited to this, and a P-type transistor may be formed at the top of the cell and an N-type transistor at the bottom of the cell.

[0096] Furthermore, although the above-described embodiments and modifications were explained using the case where the standard cell having logic functionality is an inverter cell as an example, the standard cell having logic functionality may be other cells (NAND, NOR, flip-flop, etc.).

[0097] Furthermore, in the above-described embodiment, the power supply wiring for VDD is formed on the BM0 layer and the power supply wiring for VSS is formed on the M0 layer, but the wiring layers on which the power supply wiring is formed are not limited to these. For example, both the power supply wiring for VDD and the power supply wiring for VSS may be formed on the wiring layer on the back side of the transistor. Also, the arrangement position of the power supply wiring in the Y direction is not limited to that shown in the above-described embodiment and drawings. In addition, the power supply wiring may be formed on multiple wiring layers.

[0098] Furthermore, the width and position of the active area in the Y direction at the top and bottom of the cell may be the same or different.

[0099] Furthermore, while the transistors in the embodiments described above are nanosheet FETs, the invention is not limited to them. For example, fin FETs or other types of transistors may also be used.

[0100] This disclosure describes how a filler cell using a CFET can improve the manufacturing precision of semiconductor integrated circuit devices and improve the accuracy of transistor performance estimation.

[0101] 11 (11a, 11b), 51 (51a, 51b) Power supply wiring 21-24, 121-126 Nanosheet 31, 34 Gate wiring 32, 33, 35, 36, 131-133 Dummy gate wiring 41-48, 141-148 Local wiring 2P1-2P5, 2N1-2N5 Active region P1, N1 Transistors DP1-DP3, DN1-DN3 Dummy transistors C1 (C1a, C1b), C2 Inverter cell C3 Filler cell CR (CR1, CR2) Cell row

Claims

1. A semiconductor integrated circuit device comprising a plurality of cell rows, each having a plurality of standard cells arranged in a first direction, wherein the plurality of cell rows are arranged in a second direction perpendicular to the first direction, the first cell row of the plurality of cell rows comprises a first standard cell having a logic function, the first cell row and the second cell row adjacent to the first cell row in the second direction of the plurality of cell rows are arranged across the cell row boundary which is the boundary between the first cell row and the second cell row and comprise a second standard cell having a logic function, and a third standard cell arranged across the cell row boundary which is the boundary between the first cell row and the second cell row and does not have a logic function, wherein the first standard cell constitutes the channel, source and drain of a first transistor of a first conductivity type, and the channel comprises a first active region including a first nanosheet extending in the first direction, The second standard cell comprises a second active region formed above the first active region in the depth direction, overlapping with the first active region in a plan view, and constituting the channel, source, and drain of a second transistor of the second conductivity type, wherein the channel includes a second nanosheet extending in the first direction; the second standard cell comprises a third active region formed in the same layer as the first active region in the depth direction, constituting the channel, source, and drain of a third transistor of the first conductivity type, wherein the channel includes a third nanosheet extending in the first direction; the fourth active region formed in the same layer as the second active region in the depth direction, constituting the channel, source, and drain of a fourth transistor of the second conductivity type, wherein the channel includes a fourth nanosheet extending in the first direction; the third standard cell comprises a fifth active region formed in the same layer as the first active region in the depth direction, and a sixth active region formed in the same layer as the second active region in the depth direction.The third and fifth active regions are formed across the cell column boundary and have the same width and position in the second direction in a semiconductor integrated circuit device.

2. A semiconductor integrated circuit apparatus according to claim 1, wherein the fourth and sixth active regions are formed across the cell column boundary and have the same width and position in the second direction.

3. A semiconductor integrated circuit apparatus according to claim 1, wherein the width of the fifth active region in the second direction is greater than the width of the first active region in the second direction, and one end of the fifth active region in the second direction and one end of the first active region in the second direction are at the same position in the second direction.

4. A semiconductor integrated circuit apparatus according to claim 1, wherein the third standard cell further comprises a seventh active region formed in the same layer as the first active region in the depth direction, and an eighth active region formed in the same layer as the second active region in the depth direction, wherein the first and seventh active regions have the same width and position in the second direction.

5. A semiconductor integrated circuit apparatus according to claim 4, wherein the second and eighth active regions have the same width and position in the second direction.

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