Method and device for connectivity check of integrated circuit
The method optimizes metal integration and verification in semiconductor circuits by using grid-based routing and BFS error checking, addressing inefficiencies in conventional methods, achieving faster and more accurate verification.
WO2026141750A1PCT designated stage Publication Date: 2026-07-02INDUSTRY UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY
Patent Information
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- INDUSTRY UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY
- Filing Date
- 2024-12-27
- Publication Date
- 2026-07-02
Smart Images
Figure KR2024021349_02072026_PF_FP_ABST
Abstract
A method for a connectivity check for an integrated circuit performed by a computing device, according to one embodiment, may comprise: a metal vector information extraction step for extracting metal vector information about metals on a layout; a merged metal vector information generation step for generating a merged metal by merging the metals according to a preset method on the basis of the metal vector information, and then generating merged metal vector information about the merged metal; and a connectivity check graph generation step for generating a connectivity check graph on the basis of via information and the merged metal information.
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