Circuit board and semiconductor package

Abstract

This circuit board comprises: a core layer including a hole penetrating through the upper and lower surfaces thereof; a seed layer provided on at least one of the upper and lower surfaces of the core layer; a core via electrode provided in the hole; and a filling portion which is arranged on the inner wall of the hole and surrounds the core via electrode, wherein the seed layer vertically overlaps the core via electrode and the filling portion.

Description

Circuit boards and semiconductor packages

[0001] The present embodiment relates to a circuit board and a semiconductor package.

[0002]

[0003] Recently, technologies related to electronic products such as AI and servers have been progressing toward multi-functionality and high speed. To respond to this trend, high-layer and large-area circuit board technologies are also developing rapidly to keep pace with the fast-advancing semiconductor chip manufacturing technology.

[0004] In particular, as the density of transistors and wiring within semiconductor chips increases, the number of I / O terminals on the chips is growing. To meet this trend, not only are the wiring densities, lengths, and widths of circuit boards becoming finer, but there is also a trend toward high-layer, large-area designs.

[0005] Furthermore, from the perspective of miniaturizing finished electronic products, the thickness of the applied circuit boards is also decreasing, and technologies related to multilayer circuit boards, which configure more circuit layers within a circuit board of the same thickness, are being actively researched. In addition, as the pitch of semiconductor chips narrows and the size of chips increases, chiplet technology for separating semiconductor chips by function is being researched. Moreover, technologies for connecting separated chiplets on circuit boards are being actively researched. Furthermore, by connecting semiconductor chips with different functions on circuit boards, technologies regarding the connection relationship between circuit boards and semiconductor chips are being actively researched, such as the circuit board connecting semiconductor chips to each other, which was previously considered only from the perspective of conventional semiconductor packaging.

[0006] A circuit board is a device in which circuit line patterns are arranged using a conductive material, such as copper, on an electrically insulating substrate; it is a general term for the package board immediately before mounting electronic components. To densely mount many different types of electronic components on a flat surface, the mounting positions of each component are determined, and circuit patterns connecting the components are printed and fixed onto the surface.

[0007] A circuit board includes a core layer and a build-up structure disposed on the surface of the core layer. The core layer and the build-up structure each include one or more insulating layers, and a wiring layer and a via electrode connecting different wiring layers in a vertical direction are disposed on each insulating layer. The via electrode is disposed within a via hole penetrating the insulating layer.

[0008] In the case of via electrodes placed in the core layer, the width may be greater than that of via electrodes placed in the build-up structure. However, when the width of the via hole for placing the via electrode is increased, defects in plating solution deposition occur due to differences in internal current density by region within the via hole and the occurrence of voids, making it difficult to ensure the quality of the via electrode.

[0009] In addition, the core layer includes a resin and glass fibers disposed within the resin as reinforcing materials. In this case, there is a problem in that the electrical signal transmission efficiency through the via electrode is reduced due to interference and migration between the glass fibers protruding through the inner wall of the via hole and the via electrode.

[0010]

[0011] The present invention provides a circuit board and a semiconductor package in which the process of forming via electrodes within a core layer can be performed more easily, and the electrical signal transmission efficiency and reliability are improved due to the improvement in the quality of the core electrodes.

[0012]

[0013] A circuit board according to the present embodiment includes a core layer having a hole penetrating an upper surface and a lower surface; a seed layer disposed on at least one of the upper surface or the lower surface of the core layer; a core via electrode disposed in the hole; and a filling portion disposed on the inner wall of the hole and surrounding the core via electrode, wherein the seed layer is vertically superimposed on the core via electrode and the filling portion.

[0014] The above-mentioned filling part may be resin.

[0015] The vertical length of the filling portion and the vertical length of the core via electrode may each be equal to the vertical thickness of the core layer.

[0016] The upper and lower surfaces of the above-mentioned filling part can each form a plane identical to the upper and lower surfaces of the above-mentioned core layer.

[0017] The horizontal width of the above-mentioned filling portion may be shorter than the horizontal width of the above-mentioned core via electrode.

[0018] The wiring portion is disposed on the upper or lower surface of the core layer and connected to the core via electrode, and the wiring portion may include a region having a crystal grain smaller than the crystal grain of the core via electrode.

[0019] A region having grains smaller than the grains of the core via electrode can be placed on the surface of the seed layer.

[0020] The horizontal width of the seed layer may be larger than the horizontal width of the core via electrode.

[0021] The core layer may include polished surfaces disposed on the upper and lower surfaces of the core layer where the seed layer is disposed.

[0022] A semiconductor package according to the present embodiment comprises: a core layer including a hole penetrating an upper surface and a lower surface; a first build-up structure disposed on the upper surface of the core layer; a second build-up structure disposed on the lower surface of the core layer; a semiconductor chip disposed on the first build-up structure or the second build-up structure; a seed layer disposed on at least one of the upper surface or the lower surface of the core layer; a core via electrode disposed in the hole; and a filling portion disposed on the inner wall of the hole and surrounding the core via electrode, wherein the seed layer is vertically superimposed on the core via electrode and the filling portion.

[0023]

[0024] In this embodiment, the core via electrode is implemented by a metal pin coupling method rather than a plating method, thereby improving the reliability of the electrical connection of the circuit board compared to the conventional method.

[0025] In addition, compared to the structure of forming a core via electrode by an electrochemical plating method, the process time for forming the core via electrode can be shortened.

[0026] In addition, as the pitch between multiple core via electrodes is reduced, there is an advantage that a fine pattern between multiple core via electrodes can be implemented.

[0027] In addition, electrical performance degradation such as migration caused by interference between the glass fibers of the core layer and the core via electrodes can be prevented.

[0028]

[0029] FIG. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention.

[0030] FIG. 2 is an enlarged view illustrating the arrangement structure of a core via electrode within a core layer according to an embodiment of the present invention.

[0031] FIG. 3 is a diagram illustrating the arrangement structure of a core via electrode together with glass fibers within a core layer according to an embodiment of the present invention.

[0032] FIGS. 4 to 8 are drawings for explaining the process of forming a core via electrode according to an embodiment of the present invention.

[0033] FIG. 9 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.

[0034]

[0035] The present invention is susceptible to various modifications and may have various embodiments, and specific embodiments are illustrated and described in the drawings. However, this does not specify the present invention.

[0036] It should be understood that the embodiments are not intended to be limited and include all modifications, equivalents, and substitutions that fall within the spirit and scope of the invention.

[0037] However, the technical concept of the present invention is not limited to some of the described embodiments but can be implemented in various different forms, and within the scope of the technical concept of the present invention, one or more of the components among the embodiments may be selectively combined or substituted.

[0038] In addition, terms used in the embodiments of the present invention (including technical and scientific terms) shall be interpreted in a meaning generally understood by those skilled in the art to which the present invention pertains, unless explicitly and specifically defined otherwise. Commonly used terms, such as those defined in a dictionary, shall be interpreted in consideration of their contextual meaning as described in the present invention. If a commonly used term defined in a dictionary does not match the meaning it has in the context of the description of the present invention, it shall be interpreted in accordance with the meaning it has in the context of the description of the present invention. Furthermore, even if not explicitly defined in this application, it shall not be interpreted in an ideal or overly formal sense based on the description of the present invention.

[0039] Furthermore, the terms used in the embodiments of the present invention are for describing the embodiments and are not intended to limit the present invention. In this specification, the singular form may include the plural form unless specifically stated otherwise in the text.

[0040] Terms containing ordinal numbers, such as "first," "second," etc., may be used to describe various components, but the meaning of the components is not limited by the ordinal numbers. Terms containing ordinal numbers are used solely for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the second component may be named the first component, and similarly, the first component may be named the second component. Furthermore, if the meaning of the component does not depart from the scope of the present invention even without ordinal numbers such as "first" and "second," the component may be referred to by excluding the ordinal number.

[0041] The term "and / or" includes a combination of multiple related listed items or any of the multiple related listed items. Such a term is used merely to distinguish a component from other components and is not limited by the nature, order, sequence, etc. of the component.

[0042] In this application, terms such as “comprising,” “provided,” and “having” are intended to specify the existence of the features, numbers, steps, actions, components, parts, or combinations thereof described in the specification, and should be understood as not excluding in advance the existence or addition of one or more other features, numbers, steps, actions, components, parts, or combinations thereof.

[0043] When referring to directions, vertical and horizontal directions are used for convenience of explanation. Additionally, the horizontal direction may include a first horizontal direction perpendicular to the vertical direction, and a second horizontal direction perpendicular to the first horizontal direction and the vertical direction. Furthermore, if the vertical and horizontal directions follow a Cartesian coordinate system, they may correspond to the first horizontal direction (X-axis), the second horizontal direction (Y-axis), and the vertical direction (Z-axis), respectively; if they follow a cylindrical coordinate system, the first horizontal direction may refer to the azimuth (Φ) direction (or circumferential direction), and the second horizontal direction may refer to the radius (ρ) direction (or centrifugal direction) separated from a specific configuration; and if they follow a spherical coordinate system, the first horizontal direction may refer to the azimuth (Φ) direction (or circumferential direction), and the second horizontal direction may refer to the radius (r) direction (or centrifugal direction) separated from a specific configuration. In particular, the vertical direction may refer to the polar angle (θ) direction formed by the second horizontal direction and the Z-axis. For convenience of explanation, the first horizontal direction, the second horizontal direction, and the vertical direction may be used by combining the Cartesian coordinate system, the cylindrical coordinate system, and the spherical coordinate system described above. However, unless otherwise specified, the vertical direction refers to the Z-axis according to the Cartesian coordinate system, and the horizontal direction refers to any direction that can be defined on the XY plane; when referring to the first horizontal direction and the second horizontal direction perpendicular to the first horizontal direction, the first horizontal direction refers to the X-axis and the second horizontal direction refers to the Y-axis.

[0044] Furthermore, when described as being formed or placed "above or below" each component, "above" or "below" includes not only cases where two components are in direct contact with each other, but also cases where one or more other components are formed or placed between the two components. Additionally, when expressed as "above or below," it may include the meaning of a downward direction as well as an upward direction relative to a single component.

[0045] Furthermore, the meaning that Configuration A is positioned between Configuration B and Configuration C may include the meaning that Configuration A is positioned such that at least a portion of it overlaps with Configurations B and C in the horizontal and / or vertical directions. Unless otherwise noted, even if Configuration C is located between a virtual line extending vertically and / or horizontally from Configuration A and a virtual line extending vertically and / or horizontally from Configuration B, the meaning may include that Configuration C is positioned between Configuration A and Configuration B.

[0046] Furthermore, the statement that Configuration A is exposed from Configuration B should be understood as meaning that Configuration A is exposed from Configuration B, not that Configuration A is exposed from the entire product; and unless there are special circumstances, it should not be understood as meaning that the entirety of Configuration A is covered by Configuration B. In other words, when Configuration A is stated to be exposed from Configuration B, it should be understood to mean that Configuration C, in addition to Configurations A and B, covers Configuration A exposed from Configuration B.

[0047] Additionally, where it is stated that a component is 'connected,' 'combined,' 'connected,' or 'contacted' with another component, this may include not only cases where the component is directly connected, combined, or connected to the other component, but also cases where it is 'connected,' 'combined,' or 'connected' due to another component located between the component and the other component. Accordingly, if component A is to be understood only as being directly 'connected,' 'combined,' 'connected,' or 'contacted' with component B, it is described as being 'directly connected,' 'directly combined,' 'directly connected,' or 'directly contacted.'

[0048] In addition, when it is stated that configuration A is 'fixed' to configuration B, it should be understood that configuration A is indirectly fixed to configuration B through configuration C and / or configuration D, etc., unless otherwise specifically mentioned, considering the function and purpose to be solved, and in cases where configuration A is to be understood only as being 'directly fixed' to configuration B, it is stated as being 'directly fixed'.

[0049] In addition, when described as “flat” or “located on the same plane,” it should not be interpreted according to the dictionary definition, but rather understood by a person with ordinary knowledge in the relevant technical field to the extent that process deviations are taken into account.

[0050] FIG. 1 is a cross-sectional view of a circuit board according to an embodiment of the present invention, FIG. 2 is an enlarged view showing the arrangement structure of a core via electrode within a core layer according to an embodiment of the present invention, and FIG. 3 is a view showing the arrangement structure of a core via electrode together with glass fibers within a core layer according to an embodiment of the present invention.

[0051] Referring to FIGS. 1 to 3, a circuit board (10) according to an embodiment of the present invention may include a core layer (100), a first build-up structure (200), a second build-up structure (300), and a protective layer (410, 420).

[0052] The circuit board (10) may include a core layer (100). The core layer (100) may be a component forming the base of the circuit board (10). Based on the vertical direction, the core layer (100) may be positioned in the center of the circuit board (10). The material of the core layer (100) may include at least one selected from the group consisting of glass, resin, plastic, and metal.

[0053] The core layer (100) may include a resin and glass fibers (102, see FIG. 3) disposed within the resin as a reinforcing material. The glass fibers (102) may be provided in multiple numbers and may be arranged along a vertical direction within the core layer (100). The glass fibers (102) may have a longitudinal direction in a horizontal direction within the resin, and in this case, the glass fibers (102) may have a separated region in a horizontal direction in the hole (110) forming region to be described later.

[0054] However, this is not limited to glass fiber (102), and it may be implemented as a single layer.

[0055] In order to suppress warpage of the circuit board (10), the vertical thickness of the core layer (100) may be greater than the vertical thickness of the first build-up structure (200) or the second build-up structure (300) to be described later. However, depending on the area of ​​the circuit board (10) and the design of the circuit, the thickness of the core layer (100) may be freely provided without being limited thereto.

[0056] The first build-up structure (200) may be disposed on one side of the core layer (100). The first build-up structure (200) may be disposed on the upper surface of the core layer (100). The second build-up structure (300) may be disposed on the other side of the core layer (100). The second build-up structure (300) may be disposed on the lower surface of the core layer (100). The first build-up structure (100) and the second build-up structure (300) may be disposed facing each other in a vertical direction with respect to the core layer (100). The first build-up structure (200) and the second build-up structure (300) may each include a plurality of insulating layers disposed in a vertical direction. The number of insulating layers of the first build-up structure (200) and the number of insulating layers of the second build-up structure (300) may be the same. Accordingly, the occurrence of bending of the circuit board (10) based on the core layer (100) can be minimized. However, this is not limited to the number of insulating layers in the first build-up structure (200) and the number of insulating layers in the second build-up structure (300) may differ from each other.

[0057] The first build-up structure (200) may include a plurality of first insulating layers (210) arranged in a vertical direction, a plurality of wiring portions (220) each arranged in a plurality of first insulating layers (210), and a plurality of via portions (230) arranged to penetrate at least a portion of each of the plurality of first insulating layers (210) and electrically connecting the plurality of wiring portions (220) arranged in a vertical direction.

[0058] The second build-up structure (300) may include a plurality of second insulating layers (310) arranged in a vertical direction, a plurality of wiring portions (320) each arranged in the plurality of second insulating layers (310), and a plurality of via portions (330) arranged to penetrate at least a portion of each of the plurality of second insulating layers (310) and electrically connecting the plurality of wiring portions (320) arranged in a vertical direction.

[0059] The number of insulating layers constituting the first build-up structure (200) and the number of insulating layers constituting the second build-up structure (300) shown in FIG. 1 are exemplary, and the circuit board (10) may have a greater number of insulating layers stacked vertically to form the first build-up structure (200) and the second build-up structure (300), respectively.

[0060] Additionally, the number of insulating layers in the first build-up structure (200) and the number of insulating layers in the second build-up structure (300) may be the same. Accordingly, the occurrence of bending of the circuit board (10) based on the core layer (100) can be minimized. However, this is not limited to this, and the number of insulating layers in the first build-up structure (200) and the number of insulating layers in the second build-up structure (300) may be different from each other.

[0061] The insulating layer of the first build-up structure (200) and the insulating layer of the second build-up structure (300) may each be any insulating material, such as a photocurable and / or thermosetting material. As a thermosetting insulating material, an insulating material in which inorganic and / or organic fillers are dispersed within a resin, such as ABF (Ajinomoto Build-up Film), a product released by Ajinomoto Corporation, may be used, and a prepreg (PPG) containing glass fibers within a resin may be used. Additionally, the resin described above may be, for example, an epoxy resin, a bismaleimide triazine resin (BT resin), a phenolic resin, etc., and the inorganic and / or organic fillers may be provided with materials such as silica or plastic. At least one insulating layer among the insulating layer of the first build-up structure (200) and the insulating layer of the second build-up structure (300) may be a photocurable insulating layer, and if it is a photocurable insulating layer, at least one insulating layer among the insulating layer of the first build-up structure (200) and the insulating layer of the second build-up structure (300) may be a PID (Photo Imageable Dielectric).

[0062] The circuit board (10) may include a protective layer (410, 420). The protective layer (410, 420) may include a first protective layer (410) disposed on the surface of a first build-up structure (200) and a second protective layer (420) disposed on the surface of a second build-up structure (300). When a semiconductor device is disposed on the surface of the circuit board (10) using a material such as solder, the first protective layer (410) and the second protective layer (420) can perform the function of preventing short circuits between solders due to low wettability with the solder, and can prevent the problem of external contaminants penetrating into the build-up structure and reducing reliability. The first protective layer (410) and the second protective layer (420) may each utilize a photocurable insulating material. Accordingly, the first protective layer (410) and the second protective layer (420) are provided with a solder resist other than the aforementioned ABF, PPG, BT resin, and PID. However, they are not limited thereto and may be provided with various materials capable of performing low wettability with solder and thus preventing short circuits between solders as described above.

[0063] The first protective layer (410) may include a hole for exposing upward a wiring portion (220) disposed on the surface of the first build-up structure (200). The second protective layer (420) may include a hole for exposing downward a wiring portion (320) disposed on the surface of the second build-up structure (300) to the circuit board (10).

[0064] Below, we will explain the arrangement structure of the core via electrodes within the core layer (100).

[0065] A first wiring section (120) may be disposed on one side of the core layer (100). The first wiring section (120) may be disposed on the upper surface of the core layer (100) where the first build-up structure (200) is disposed. The first wiring section (120) may be electrically connected to the wiring section (220) and via section (230) of the first build-up structure (200).

[0066] A second wiring section (130) may be disposed on the other side of the core layer (100). The second wiring section (130) may be disposed on the lower side of the core layer (100) where the second build-up structure (300) is disposed. The second wiring section (130) may be electrically connected to the wiring section (320) and via section (330) of the second build-up structure (300).

[0067] The core layer (100) may include a hole (110) penetrating from the upper surface of the core layer (100) to the lower surface of the core layer (100). The hole (110) may be provided in multiple numbers and arranged along the horizontal direction of the core layer (100). A core via electrode (150) may be arranged within the hole (110). The cross-sectional area of ​​the hole (110) may be larger than the cross-sectional area of ​​the core via electrode (150). As shown in FIG. 2, the horizontal width of the hole (110) may be larger than the horizontal width (w3) of the core via electrode (150).

[0068] The horizontal width of the hole (110) of the core layer (100) may be greater than the horizontal width of each of the plurality of via portions arranged in the first build-up structure (200) or the second build-up structure (300). In an embodiment, the horizontal width of the hole (110) of the core layer (100) may be 50 µm or more. When processing the hole (110) for forming the core via electrode (150) within the core layer (100) due to the vertical length of the core layer (100) itself, if the width of the hole (110) is less than 50 µm, there is a problem of reduced productivity due to the difficulty of the hole processing operation. In addition, in a structure that connects a plurality of wiring portions in the vertical direction, if the width of the hole (110) is less than 50 µm, the bonding force with the wiring layer may not be sufficient.

[0069] The vertical length of the hole (110) may be equal to the vertical thickness of the core layer (100).

[0070] The circuit board (10) may include a core via electrode (150). The core via electrode (150) may be positioned to penetrate at least a portion of the core layer (100). The core via electrode (150) may be positioned to penetrate at least a portion of the filling portion (160) to be described later. The core via electrode (150) may be positioned to overlap the core layer (100) in a horizontal direction. The first wiring portion (120) and the second wiring portion (130) may be electrically connected through the core via electrode (150). The core via electrode (150) may be provided in a plurality and may be positioned along the horizontal direction of the core layer (100) in each of the plurality of holes (110).

[0071] The core via electrode (150) can be placed inside the hole (110).

[0072] In the embodiment, the core via electrode (150) may be a metal pin. The core via electrode (150) may be a pin made of copper (Cu). The core via electrode (150) may have a rod shape with a cross-sectional shape of a circle or a triangle or larger. Therefore, since the core via electrode (150) is implemented by a method of joining the hole (110) of a pre-fabricated metal pin rather than a plating method within the hole (110) of the core layer (100), there is an advantage that core via electrodes (150) of various shapes and sizes can be formed.

[0073] According to the prior art, the formation of core via electrodes within a core layer is achieved by an electroplating method through a seed layer placed on the inner wall of a hole within the core layer. However, during the process of forming a hole within the core layer, plating deviations occur due to glass fibers of the core layer protruding through the inner wall of the hole, and voids are generated, resulting in problems such as short circuits in electrical connections through the core via electrodes or reduced plating quality.

[0074] According to the embodiment, since the core via electrode (150) is implemented by a metal pin coupling method rather than a plating method, it has superior quality compared to a core via electrode according to the prior art, so the reliability of the electrical connection of the circuit board (10) in the vertical direction can be improved.

[0075] In addition, compared to the electrochemical plating method, the pin bonding method can shorten the process time for forming the core via electrode.

[0076] In addition, compared to the electrochemical plating method, as the pitch between multiple core via electrodes is reduced, there is an advantage that a fine pattern can be realized between multiple core via electrodes (150).

[0077] A filling portion (160) may be disposed in a hole (110) within the core layer (100). The filling portion (160) may be disposed on the inner wall of the hole (110). The filling portion (160) may be disposed between the inner surface of the hole (110) and the outer surface of the core via electrode (150). The core via electrode (150) may be disposed to penetrate the filling portion (160). The filling portion (160) may be made of a resin material. Accordingly, the core via electrode (150) within the hole (110) may be fixed by the curing of the filling portion (160).

[0078] In the process of forming a hole (110) for the placement of a core via electrode (150) within a core layer (100), when interference occurs between the core via electrode (150) and the glass fiber (102, see FIG. 3) protruding through the inner wall of the hole (110), the signal transmission efficiency through the core via electrode (150) decreases, and problems such as migration occur. Accordingly, according to the embodiment, by placing a filling portion (160) between the inner wall of the hole (110) and the core via electrode (150), migration is prevented, and the prevention of electrical performance degradation of the core via electrode (150) due to friction with the glass fiber (102) can be minimized.

[0079] Meanwhile, as illustrated in FIG. 3, at least a portion of the glass fiber (102) within the core layer (100) may protrude through the inner wall of the hole (110). The protruding portion (102a) of the glass fiber (102) may be spaced horizontally apart from the core via electrode (150) through the filling portion (160). During the formation process of the filling portion (160) within the hole (110), at least a portion of the filling portion (160) may be positioned to surround the protruding portion (102a) of the glass fiber (102). That is, a groove to which the protruding portion (102a) of the glass fiber (102) is joined may be arranged on the outer surface of the filling portion (160). Accordingly, the bonding strength between the core layer (100) and the filling portion (160) may be increased.

[0080] In a modified example, the core layer (100) may be a glass core made of glass material. In this case, when a core via electrode is formed by plating on the inner wall of the hole (110) within the core layer (100), there is a risk of a short circuit occurring within the core via electrode due to the alkaline component of the core layer (100) itself. According to the modified example, even if the material of the core layer (100) is formed of glass, a filling portion (160) is disposed between the inner wall of the hole (110) and the core via electrode (150), so a short circuit of the core via electrode (150) can be prevented.

[0081] The core via electrode (150) may be positioned at the center of the filling portion (160). In this case, as shown in FIG. 2, the horizontal width (w1) of the filling portion (160) positioned on one side relative to the core via electrode (150) and the horizontal width (w2) of the filling portion (160) positioned on the other side opposite to the one side may be the same.

[0082] However, this is not limited to the core via electrode (150), and the core via electrode (150) may be positioned offset from the center of the filling portion (160). In this case, the horizontal width (w1) of the filling portion (160) positioned on one side relative to the core via electrode (150) and the horizontal width (w2) of the filling portion (160) positioned on the other side opposite to the one side may be different. That is, according to the embodiment, the degree of freedom of the positioning area of ​​the core via electrode (150) may be increased in the range where there is a spaced-away area from the inner wall of the hole (110) through the filling portion (160).

[0083] The horizontal width (W1+W2) of the filling portion (160) may be shorter than the horizontal width (W3) of the core via electrode (150). The horizontal width of the core via electrode (150) may be greater than half the horizontal width (W1+W2+W3) of the hole (110). Accordingly, by securing the horizontal thickness of the core via electrode (150) within the hole (110), the reduction in signal transmission efficiency of the circuit board (10) through the core via electrode (150) can be minimized.

[0084] As described above, a first wiring section (120) and a second wiring section (130) connected to a core via electrode (150) may be respectively disposed on one side and the other side of the core layer (100). The horizontal width of each of the first wiring section (120) and the second wiring section (130) may be greater than the horizontal width of the hole (110).

[0085] The first wiring section (120) may include a first section (122) disposed on the core layer (100) and a second section (126) disposed on the first section (122). The vertical thickness of the first section (122) may be shorter than the vertical thickness of the second section (126). The size of the crystal grains constituting the first section (122) may be larger than the size of the crystal grains constituting the second section (126). The size of the crystal grains of the second section (126) may be smaller than the size of the crystal grains of the core via electrode (150). The first section (122) may be a seed layer for forming the second section (126). Accordingly, after the first section (122) is formed on the core layer (100), the second section (126) may be implemented on the surface of the first section (122) by an electroplating method. This will be described later.

[0086] The first wiring section (120) may be vertically superimposed on the upper surface of the core via electrode (150) and the filling section (160). The lower surface of the first section (122) within the first wiring section (120) may be in contact with the upper surface of the core via electrode (150) and the upper surface of the filling section (160). The polished surface (190) in FIG. 2 is merely for indicating a polished area and does not indicate that a specific configuration is placed between the lower surface of the first section (122) and the upper surface of the core via electrode (150) and the upper surface of the filling section (160).

[0087] The second wiring section (130) may include a third section (132) disposed on the lower surface of the core layer (100) and a fourth section (136) disposed on the lower surface of the third section (132). The vertical thickness of the third section (132) may be shorter than the vertical thickness of the fourth section (136). The size of the crystal grains constituting the third section (132) may be larger than the size of the crystal grains constituting the fourth section (126). The size of the crystal grains of the fourth section (126) may be smaller than the size of the crystal grains of the core via electrode (150). The third section (132) may be a seed layer for forming the fourth section (136). Accordingly, after the third section (132) is formed on the lower surface of the core layer (100), the fourth section (136) may be implemented on the surface of the third section (132) by an electroplating method. This will be discussed later.

[0088] The second wiring section (130) may be vertically superimposed on the lower surface of the core via electrode (150) and the filling section (160). The upper surface of the third section (132) within the second wiring section (130) may be in contact with the lower surface of the core via electrode (150) and the lower surface of the filling section (160). Likewise, the polished surface (190) is merely for indicating a polished area and does not indicate that a specific configuration is placed between the upper surface of the third section (132) and the lower surface of the core via electrode (150) and the lower surface of the filling section (160).

[0089] Meanwhile, in this embodiment, the core via electrode (150) and the filling portion (160) are each formed with a vertical length equal to the vertical length of the hole (110) or the core layer (100), so that the upper surface of the core via electrode (150) and the upper surface of the filling portion (160) form a plane identical to the upper surface of the core layer (100), and the lower surface of the core via electrode (150) and the lower surface of the filling portion (160) form a plane identical to the lower surface of the core layer (100).

[0090] However, this is not limited to at least one of the upper or lower surface of the filling portion (160) may be positioned vertically stepped relative to the upper or lower surface of the core layer (100). In this case, the vertical length of the filling portion (160) may be shorter than the vertical length of the core layer (100) or the hole (110). For example, the upper surface of the filling portion (160) may be positioned stepped downward relative to the upper surface of the core layer (100). As another example, the lower surface of the filling portion (160) may be positioned stepped upward relative to the lower surface of the core layer (100). In this case, at least a portion of the first portion (122) or the third portion (132), which is the seed layer, includes a protruding area toward the hole (110), and the protruding area may be positioned to overlap horizontally with the core layer (100) or the core via electrode (150). Accordingly, the upper or lower portion of the core via electrode (150) may have a structure joined to the first portion (122) or the third portion (132) on multiple sides through the protruding portion of the first portion (122) or the third portion (132), which are seed layers, respectively. For example, when the protruding portion is formed in the first portion (122), the upper surface and part of the side of the core via electrode (150) may be covered by the lower surface and the protruding portion of the first portion (122). When the protruding portion is formed in the third portion (132), the lower surface and part of the side of the core via electrode (150) may be covered by the upper surface and the protruding portion of the third portion (132).

[0091] FIGS. 4 to 8 are drawings for explaining the process of forming a core via electrode according to an embodiment of the present invention.

[0092] Referring to FIG. 4, the process of forming a core via electrode (150) may include the step of forming a hole (110) within a core layer (100). The hole (110) may be provided in multiple numbers corresponding to the number of core via electrodes (150) and arranged along the horizontal direction within the core layer (100). After forming the hole (110), a film (800) may be placed on one side of the core layer (100). Through the film (800), one side of the hole (110) may be covered. The film (800) may function as a cover for a filling material for forming a filling portion (160).

[0093] Referring to FIG. 5, a filling material (160a) can be injected to form a filling portion (160) within a hole (110). The amount of filling material (160a) injected can be determined by considering the volume of the hole (110) and the size of the core via electrode (150). When the amount of filling material (160a) injected is low, as described above, one side or the other side of the filling portion (160) can be positioned vertically stepped with respect to one side or the other side of the core layer (100).

[0094] Referring to FIG. 6, a core via electrode (150) can be realized as a metal pin is inserted into a hole (110) into which a filling material (160a) is injected. After insertion of the core via electrode (150), a filling portion (160) is formed by the hardening of the filling material (160a), and the core via electrode (150) and the inner wall of the hole (110) can be separated horizontally through the filling portion (160).

[0095] As illustrated in FIG. 7, the film (800) is removed from the core layer (100), and the upper and lower surfaces of the core layer (100) can be polished. Accordingly, a stable bond can be formed with a seed layer for forming a wiring portion disposed on the surface of the core layer (100). By polishing the surface of the core layer (100), polished surfaces (190) can be disposed on the upper and lower surfaces of the core layer (100) where the wiring portion is disposed. By the polished surfaces (190), the upper and lower surfaces of the core layer (100) and the upper and lower surfaces of the filling portion (160), and the upper and lower surfaces of the core layer (100) and the upper and lower surfaces of the via electrode (150) can be disposed to form a plane with respect to each other.

[0096] As illustrated in FIG. 8, a seed layer for forming a wiring portion may be formed on the upper and lower surfaces of the core layer (100), respectively. The seed layer may consist of a first portion (122) disposed on the aforementioned core layer (100) and a third portion (132) disposed on the lower surface of the core layer (100). At least a portion of each of the first portion (122) and the third portion (132) may be disposed so as to overlap vertically with the core via electrode (150) or the filling portion (160). A wiring portion may be realized by forming a second portion (126) and a fourth portion (136) on the surfaces of the first portion (122) and the third portion (132) by a plating method. A portion of the seed layer excluding the area where the wiring portion is disposed may be removed by etching.

[0097] FIG. 9 is a cross-sectional view of a semiconductor package according to an embodiment of the present invention.

[0098] Referring to FIG. 9, a semiconductor package according to an embodiment of the present invention may include a first semiconductor chip (1000) disposed on a circuit board (10) and a second semiconductor chip (2000), wherein the first semiconductor chip (1000) is bonded to a first build-up structure (200) through a first bonding part (1100), and the second semiconductor chip (2000) is bonded to a second build-up structure (300) through a second bonding part (2100). Here, the first bonding part (1100) and the second bonding part (2100) may each be solder balls.

[0099] In the foregoing, although all components constituting an embodiment of the present invention have been described as being combined or operating in combination, the present invention is not necessarily limited to such embodiments. That is, within the scope of the purpose of the present invention, all components may be selectively combined in one or more ways to operate. Furthermore, terms such as "include," "constitute," or "have" described above, unless specifically stated otherwise, mean that the relevant component may be inherent; thus, they should be interpreted as allowing for the inclusion of additional components rather than excluding other components. All terms, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which the present invention pertains, unless otherwise defined. Terms commonly used, such as those defined in advance, should be interpreted in accordance with their meaning in the context of the relevant technology and should not be interpreted in an ideal or overly formal sense unless explicitly defined in the present invention.

[0100] The foregoing description is merely an illustrative explanation of the technical concept of the present invention, and those skilled in the art to which the present invention pertains will be able to make various modifications and variations within the scope of the essential characteristics of the present invention. Accordingly, the embodiments disclosed in the present invention are intended to explain, not limit, the technical concept of the present invention, and the scope of the technical concept of the present invention is not limited by such embodiments. The scope of protection of the present invention shall be interpreted by the claims below, and all technical concepts within an equivalent scope shall be interpreted as being included within the scope of rights of the present invention.

[0101] Meanwhile, when a circuit board having the features of the invention described above is used in IT devices or home appliances such as smartphones, server computers, and TVs, it can stably perform functions such as signal transmission or power supply. For example, when a circuit board having the features of the invention performs a semiconductor package function, it can safely protect the semiconductor chip from external moisture or contaminants, and can resolve issues such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. In addition, when it is responsible for signal transmission, it can resolve noise issues. Through this, the circuit board having the features of the invention described above enables the stable operation of IT devices or home appliances, thereby allowing the entire product and the circuit board to which the invention is applied to achieve functional integration or technical interoperability.

[0102] When a circuit board having the features of the invention described above is used in a transportation device such as a vehicle, it can resolve the problem of signal distortion transmitted to the transportation device, or safely protect a semiconductor chip controlling the transportation device from the outside, and further improve the stability of the transportation device by resolving problems such as leakage current, electrical short circuits between terminals, or electrical open circuits of terminals supplying power to the semiconductor chip. Accordingly, the transportation device and the circuit board to which the present invention is applied can achieve functional integration or technical interoperability with each other.

Claims

1. A core layer including a hole penetrating the upper and lower surfaces; A seed layer disposed on at least one of the upper or lower surface of the core layer; A core via electrode disposed in the above hole; and It includes a filling portion disposed on the inner wall of the above hole and surrounding the core via electrode, and The above seed layer is a circuit board vertically superimposed on the core via electrode and the filling portion.

2. In Paragraph 1, The above-mentioned filling part is a circuit board made of resin.

3. In Paragraph 1, A circuit board in which the vertical length of the filling portion and the vertical length of the core via electrode are each equal to the vertical thickness of the core layer.

4. In Paragraph 1, A circuit board in which the upper and lower surfaces of the above-mentioned filling portion each form the same plane as the upper and lower surfaces of the above-mentioned core layer.

5. In Paragraph 1, A circuit board in which the horizontal width of the filling portion is shorter than the horizontal width of the core via electrode.

6. In Paragraph 1, It includes a wiring portion disposed on the upper or lower surface of the core layer and connected to the core via electrode, The above wiring portion is a circuit board including a region having crystal grains smaller in size than the crystal grains of the core via electrode.

7. In Paragraph 6, A circuit board having a region having a grain size smaller than that of the core via electrode, disposed on the surface of the seed layer.

8. In Paragraph 1, A circuit board in which the horizontal width of the seed layer is larger than the horizontal width of the core via electrode.

9. In Paragraph 1, The above core layer is a circuit board comprising polished surfaces disposed on the upper and lower surfaces of the core layer on which the above seed layer is disposed.

10. A core layer including a hole penetrating the upper and lower surfaces; A first build-up structure disposed on the upper surface of the above-mentioned core layer; A second build-up structure disposed on the lower surface of the above-mentioned core layer; A semiconductor chip disposed on the first build-up structure or the second build-up structure; A seed layer disposed on at least one of the upper or lower surface of the core layer; A core via electrode disposed in the above hole; and It includes a filling portion disposed on the inner wall of the above hole and surrounding the core via electrode, and The above seed layer is a semiconductor package vertically superimposed on the core via electrode and the filling portion.

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