Multi-configuration stacked die dynamic random access devices

Abstract

The embodiments herein are directed to technologies multi-configuration stacked die DRAM devices. DRAM devices may include a first semiconductor die, a second semiconductor die, and a plurality of input / output (I / O) pins. The DRAM device can be configured in a first mode of operation by connecting a first die and a second die to a first set of the plurality of I / O pins. The DRAM device can be configured in second mode of operation, the first semiconductor die is configured to connect to the first set of the plurality of I / O pins and the second semiconductor die is configured to connect to a second set of the plurality of I / O pins.

Description

Attorney Docket No.: 27170.1093 (L1044PCT)MULTI-CONFIGURATION STACKED DIE DYNAMIC RANDOM ACCESS DEVICESBACKGROUND

[0001] Computing system memory generally includes one or more dynamic random access memory (DRAM) integrated circuits, referred to herein as DRAM devices, which are connected to one or more processors. There are different types of memory modules, for example, Double Data Rate Types one through five (DDR1-DDR5). Advancements in DDR technology have lowered power consumption, increased prefetching performance, enhanced error correction, and enabled larger capacity support. As each successive DDR technology has been released, structure and use requirements for the DDR modules are adjusted.

[0002] In particular, DDR5 modules have improved performance over earlier modules by utilizing a dual-channel architecture. The dual-channel architecture allows for double prefetch capabilities by utilizing half of the DRAM die for a first channel processing and the other half of the DRAM die for a second channel processing. Future iterations of DDR technologies may implement dual-channel or more channel architecture in a single package. Reduction in module area to increase server memory bandwidth and capacity under these improvements results in the need for multi-die stacking. Multi-die stacks can be configured in several ways, however, due to limitations in die configurability, existing stacks require specific DRAM packages to be produced per multi-die configuration. Therefore, there is a need for modifications to DRAM package structures that can allow for multi-configuration stacked die DRAM devices.BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings.

[0004] FIG. 1 is a block diagram illustrating an example system architecture for a host and a memory module in accordance with some embodiments of the present disclosure.

[0005] FIG. 2 is a block diagram illustrating a multi-configuration stacked die DRAM in a first mode and the multi-configuration stacked die DRAM in a second mode in accordance with some embodiments of the present disclosure.

[0006] FIG. 3 is a block diagram illustrating a block diagram of a multi-configuration die, in accordance with some embodiments of the present disclosure.Attorney Docket No.: 27170.1093 (L1044PCT)

[0007] FIG. 4 is a block diagram illustrating multi-configuration stacked die DRAM device, in accordance with some embodiments of the present disclosure.

[0008] FIG. 5 is a block diagram illustrating a four die multi-configuration stacked die DRAM device, in accordance with some embodiments of the present disclosure.

[0009] FIG. 6 is a block diagram illustrating a configurable server multi-configuration stacked die DRAM device, in accordance with some embodiments of the present disclosure.

[0010] FIG. 7 is an example method for configuring a multi-stacked die DRAM device, in accordance with some embodiments of the present disclosure.DETAILED DESCRIPTION

[0011] Many electronic devices (e.g., cell phones, tablets, set-top boxes, etc.) use integrated circuits that have one or more integrated circuit dies in a semiconductor package. As described above, advancements in technology have led to adjustments in semiconductor packages. However, stacked die architectures can be configured in multiple ways for different use cases. Traditionally, each configuration must be selected prior to fabrication and is designed specifically for each particular implementation. As such, the configuration is permanently devoted to a single purpose.

[0012] Specific design for die architectures within modules can be costly and can limit the use of the modules. As such, there is an increased need to allow for adjustability to utilize stacked die architectures to provide configurability of the semiconductor packages. Specifically, a single stacked die architecture that can serve to enable multiple channel configurations can limit costs by allowing a single stacked die created for multiple purposes, limiting production costs.

[0013] Additionally, in previous architectures the number of single die DRAM packages attached to a module and their connectivity dictated the configuration of the memory module. Utilizing a stacked die with a configurable architecture allows the creation of a memory module that can be used in multiple module configurations. For example, a module may be made more useful by allowing its DRAM to operate in one of two width configurations while total module capacity remains constant.

[0014] Traditional DRAM architectures can include two dies stacked that are configured as a dual die package (DDP) architecture, where each die represents one of two ranks and one die is actively transmitting or receiving data on DQ data pins shared between dies.Alternatively, two dies can be stacked in a two slice (2S) architecture, where each die concurrently transmits or receives data corresponding to different portions (slices) of aAttorney Docket No.: 27170.1093 (L1044PCT)common cache line. Either configuration can utilize four DQ data pins (x4), eight DQ data pins (x8), or more. A die for a stacked die architecture can include a first channel connected to a first set of pins, and a second channel connected to a second set of pins. The first channel may receive inputs from one or more pins, for example, from a first command array (CA) pin, and the second channel may receive inputs from the one or more pins, for example from a second CA pin. The die may be configured to provide a synchronization signal to data strobe, or DQS, pin. In some embodiments, a DQS pin may be a differential pair utilizing two or more pins per DQS signal. It should be understood that a “DQS pin” as described within may be a differential pair.

[0015] For a DDP architecture, the x4 multi-channel DRAM device (x4 DRAM) can comprise two identical device dies with two channels per device die. The first set of pins for the first die and the first set of pins for the second die can be common pins. In some embodiments, the first set of pins and the second set of pins can each be four pins, two pins per channel. Similarly, the second set of pins for the first die and the second set of pins for the second die can be common pins. The DQS pins for the first die and second die may be one or more common pins. As such, only four data I / O pins and two DQS pins are required for a x4 DRAM.

[0016] For a 2S architecture, two x4 DRAMs can be utilized together in a x8 mode of operation. However, in a 2S architecture, the first set of pins for the first die and the first set of pins for the second die are not common, and instead utilize four input / output (VO) pins. Similarly, in a 2S architecture, the second set of pins for the first die and the second set of pins for the second die are not common. Rather the second sets use four I / O pins for the two second channels, two I / O pins utilized per channel. Additionally, the DQS pins are not common, requiring two DQS pins for the DRAM. The total number of data VO pins is at least 8 and the total number of DQS pins is at least 2 for a x8 mode of operation.

[0017] Aspects of the present disclosure utilize a die configuration for each die within a stacked die architecture that can be customized between a DDP configuration and a 2S configuration at boot time, or at manufacturing of a module in which the stacked die is placed. In some embodiments, a dynamic random-access memory (DRAM) device comprises a first semiconductor die, a second semiconductor die, and a plurality of input / output (I / O) pins. The first semiconductor die and the second semiconductor die may be configurable into a first mode of operation and a second mode of operation. The first mode of operation can correspond to a DDP configuration. When in the first mode of operation, the first channel of the first die and the first channel of the second die can beAttorney Docket No.: 27170.1093 (L1044PCT)electrically tied to a first set of common pins. Also, in the first mode of operation, the second channel of the first die and the second channel of the second die can be electrically tied to a second set of common pins. The second mode of operation can correspond to a 2S configuration. When in the second mode of operation, the first channel of the first die can be electrically tied to a first set of I / O pins and the first channel of the second die can be electrically tied to a second set of I / O pins. Also, in the second mode of operation, the second channel of the first die can be electrically tied to a third set of I / O pins and the second channel of the second die can be electrically tied to a fourth set of I / O pins.

[0018] In one or more embodiments, the first semiconductor device and / or the second semiconductor device can comprise one or more selector devices. In some embodiments, the selector device can be a switch that causes electrical connections to be changed from one or more I / O pins to one or more other I / O pins. For example, in a first selector position, the DRAM device may be oriented in a DDP configuration, or in the first mode. The first selector position of the one or more selector devices, can enable connections to tie the first channel of the first device and the first channel of the second device to the common pins. In the second selector position, the DRAM device may be oriented in a 2S configuration, or in the second mode. The second selector position of the one or more selector devices, can enable each channel in each device to be electrically tied to a separate set of pins.

[0019] In one or more embodiments, the plurality of I / O pins can be DQ pins. Additional pins can be included that are DQS pins. In some embodiments, in the first mode, the first die and the second die can be electrically connected to a first set of DQS pin and in the second mode, the first die can be electrically connected to the first DQS pin and the second die can be electrically connected to a second set of DQS pin. In some embodiments, the first channel of the first die and the first channel of the second die can be connected to an I / O pin and the second channel of the first die and the second channel of the second die can be connected to a second I / O pin.

[0020] FIG. 1 is a block diagram illustrating an example system architecture 100 for a host 102 and a memory module 120 in accordance with some embodiments of the present disclosure The memory module 120, in some embodiments can be a dual inline memory module (DIMM) that includes multiple DRAM devices 124. In particular, the multiple DRAM devices 124 can be single die DRAM devices, stacked die DRAM devices, and / or multi-configuration stacked die DRAM devices as described in FIGs. 2-7. The memory module 120 can include a register 122thatcanbeusedtobufferthe memory commands. The CA signal can be provided at a CA interface such as one or more CA pins. In someAttorney Docket No.: 27170.1093 (L1044PCT)embodiments, selector signals that are utilized by the multi-configuration stacked DRAM devices can be provided to configure the DRAM devices 124 according to a desired stacked configuration. In some embodiments, the memory module 120 can include a plurality of I / O pins 110 for communicating and receiving signals to and from the memory module 120. For example, the I / O pins may connect the memory module 120 to a motherboard. In some embodiments, the I / O pins 110 can be utilized by the DRAM devices 124 to output data and or receive data. In some embodiments, the I / O pins 110 can be used to attach the memory module 120 to power or ground, access addresses, connect to a clock, and / or the like.

[0021] In some embodiments, the memory module 120 can connect to a host 102. The host can be part of the architecture 100 or can be an external device. The host can include a CPU 103 that can control the memory functionality of the memory module. In some embodiments, the CPU 103 can provide the selector signals or selector signal instructions to the memory module 120 to direct the configuration of the DRAM devices 124. For example, the CPU 103 can identify a certain configuration and send the signal to enable the configuration. In some embodiments, the CPU 103 can identify certain data output requirements needed from the DRAM devices 124 to generate the selector signals. The host 102 can further comprise a host memory controller 105 and a cache memory 104 for utilizing the memory module 120 data.

[0022] FIG. 2 is a block diagram illustrating a multi-configuration stacked die DRAM 200 in a first mode 202 and the multi-configuration stacked die DRAM in a second mode 204 in accordance with some embodiments of the present disclosure. Within the memory module 120 of FIG. 1 , the DRAM devices 124 can be configured as a stacked die architecture. The first mode 202 can comprise a first die 206, for example of a rank 0, and a second die 208, for example of a rank 1. The first die 206 and the second die 208 can respectively output four data bits on four commonly connected I / O pins. Because of the common pins, the first die and the second die are ranked separately thus allowing the memory module 120 to utilize data from both the first die 206, with the rank of 0, and the second die 208, with the rank of one. The second mode 204 can comprise a first die 210 and a second die 212 that can respectively output four data bits each onto eight connected VO pins, four for the first die 210 and four for the second die 212. Because the outputs from the first die 210 and the second die 212 are not connected to common I / O pins, there is no need for ranks for the memory module 120 to use to collect data from the DRAM device 200 in the second mode 204. In some embodiments, the first dies 206 and 210 are the same die utilized in a die package set to a first mode 202 or second mode 204 with a selector device of the first dies 206 and 210 inAttorney Docket No.: 27170.1093 (L1044PCT)first position. In some embodiments, the second dies 208 and 212 are the same die utilized in a die package set to a first mode 202 or second mode 204 with the selector device in a second position in the second mode 204.

[0023] In some embodiments, to configure the selector devices for the DRAM device 200 in the first mode 202 or the second mode 204, the selector signal is conveyed by a buffer on the module or by the host 102. The mode selection canbe performed, in some embodiments, by tying a pin on the DRAM package high or low, for example on the module PCB. In some embodiments, mode selection canbe performed by blowing a fuse after the DRAM has been packaged (e.g., at the time o module creation). The utilization of the first mode 202 and the second mode 204 can allow the DRAM device 200 to provide DRAM vendors the ability to carry one SKU instead of two SKUs, one for each mode 202 and 204.

[0024] FIG. 3 is a block diagram illustrating a multi-configuration die 300, in accordance with some embodiments of the present disclosure. In some embodiments, a first die and / or a second die of a stacked die configuration as shown in FIG. 2, can be configured as the multiconfiguration die 300. The multi-configuration die 300 can include one or more input pins 306. The input pins can be input / output pins that provide CA instructions to a first channel 302 and a second channel 304. The first channel 302 and the second channel 304 can receive a same or separate signals from the input pins 306.

[0025] In some embodiments, the first channel 302 can be configured to electrically connect to a plurality of VO pins 308, for example DQ0-DQ3. The first channel 302, in some embodiments may implement two signals that may be provided to the plurality of I / O pins 308 via one or more selector devices 310. Based on an orientation of the selector device 310a, a first output of the first channel 302 may be provided to a first I / O pin, for example DQ0, of the I / O pins 308, ora second I / O pin, for example DQ2, of the I / O pins 308. Based on the orientation of the selector device 310b, a second output of the first channel 302 may be provided to a first I / O pin, for example DQ1, of the I / O pins 308, or a second I / O pin, for example DQ3, of the I / O pins 308.

[0026] In some embodiments, the second channel 304 can be configured to electrically connect to a plurality of I / O pins 308, for example DQ4-DQ7. The second channel 304, in some embodiments may output two signals that may be provided to the plurality of I / O pins 308 via one or more selector devices 310. Based on an orientation of the selector device 310c, a first output of the second channel 304 maybe provided to a first I / O pin, for example DQ4, of the I / O pins 308, ora second I / O pin, for example DQ6, of the I / O pins 308. Based on the orientation of the selector device 3 lOd, a second output of the second channel 304 mayAttorney Docket No.: 27170.1093 (L1044PCT)be provided to a first I / O pin, for example DQ5, of the I / O pins 308, or a second I / O pin, for example DQ7, of the I / O pins 308. In some embodiments, the selector devices 310 can be configured as multiplexors. In some embodiments, the selector signals are preset according to device widths.

[0027] The data signals of the first channel 302 and the data signals of the second channel 304 may pass through the selector device 310, each devoted to one output of a channel, a common selector device for the outputs of each channel respectively, or a common selector device for all outputs of the channels. The orientation of the selector device 310 can be, in some embodiments, setusingan input signal 312 to the selector device 310. In some embodiments, the input signal 312 can control a single or multiple selector devices 310 of the one or more selector devices 310 of the multi-configuration die 300. Depending on the input signal 312, the selector device 310 can orient the multi-configuration die 300 into a first configuration, for example for use in a DDP multi-die DRAM architecture, or a second configuration, for example for use in a two slice (2S) multi-die DRAM architecture.

[0028] In some embodiments, the multi-configuration die 300 can include a selector device 3 lOe to orient a DQS output to a first DQS I / O pin DQS0, or a second DQS I / O pin DQS1, depending on the desired configuration. In some embodiments, the selector devices 310 may not be required for a first die in a stacked die configuration. In such cases, the selector devices may be non-adjustable. In such cases, the first and second output from the first channel 302 can be directly connected to a first and second I / O pin 308, for example I / O pinsDQO andDQl. The first and second output from the second channel 304 can be directly connected to a third and fourth I / O pin 308, for example, DQ4 and DQ5.

[0029] FIG. 4 is a block diagram illustrating multi-configuration stacked die DRAM device 400, in accordance with some embodiments of the present disclosure. The multiconfiguration stacked die DRAM device 400 can include a first multi-configuration die 406 and a second multi-configuration die 408. The first multi-configuration die 406 and the second multi-configuration die 408 can be configured, for example, as the multiconfiguration die 300 of FIG. 300. While shown side by side, the first multi-configuration die 406 and the second multi-configuration die 408 can be oriented such that one is stacked upon the other.

[0030] The multi-configuration stacked die DRAM device 400 can be configured in a first mode or a second mode. In some embodiments, the configuration is set via selector signals 412 and 414 at the selector devices 310 of the first multi-configuration die 406 and the second multi-configuration die 408. In some embodiments the selector device 310 of theAttorney Docket No.: 27170.1093 (L1044PCT)first multi-configuration die 406 and the selector device 310 of the second multiconfiguration die 408 are set to be in the DDP selector configuration such that it creates a multi-configuration stacked die DRAM device 400 operating in a DDP mode. For the DRAM device 400 to begin operating in the DDP mode, in some embodiments, the first multi-configuration die 406 may remain connected in a first mode of operation at the selector device 310 and the selector device 310 of the second multi-configuration die 408 can orient the second multi-configuration die 408 into a first mode of operation based on a selector signal 412 causing the selector device 310 and the second multi-configuration die 408 to be in a DDP selector configuration. As shown in FIG. 4, the DDP selector configuration electrical connections 402 enabled in the first mode of operation can enable electrical connections for the multi-configuration dies 406 and 408 to be tied to a same set of I / O pins 418, for example I / O pins DQ0-DQ1 and DQ4-DQ5, resulting in the multi-configuration stacked die DRAM device 400 operating in the DDP mode of operation. In some embodiments, in the DDP mode of operation, electrical connections 404, for example wire bonds, may not be utilized. As shown in FIG. 3, the first multi-configuration die 406 and the second multi-configuration die 408 each include localized input pins 306 and VO pins 308 that are utilized only by that die. The multi-configuration stacked die DRAM device 400 has corresponding, input pins 416 and I / O pins 418 that are common for and connected to the corresponding pins of each die and are utilized according to the mode of operation. For FIG.4-6, signals directed through input pins 306 and I / O pins 308 are assumed to be directed to the corresponding input pins 416 and I / O pins 418 of the multi-configuration stacked die DRAM device 400. For example, in some embodiments, a wire bond for an I / O pin 308 from a first die 300 may be connected to a common package pad, and subsequently package I / O pin 418, to which a second wire bond for an I / O pin 308 from a second die 300 is connected.

[0031] In some embodiments, the selector device of the second multi-configuration die 408 can orient the second multi-configuration die 408 in a second mode of operation based on the selector signal 412 to be in a 2S configuration. As shown in FIG. 4, the 2S configuration electrical connections 404 enabled in the second mode of operation can enable electrical connections for the multi-configuration dies 406 and 408 to be provided to independent pins of the multi-configuration stacked die DRAM device 400 resulting in the device operating in the 2S mode of operation. In some embodiments, in the 2S mode of operation, electrical connections 402, for example wire bonds, may not be utilized. In some embodiments, the first multi-configuration die 406 can utilize example I / O pins DQ0-DQ1 and DQ4-DQ5, and the second multi-configuration die 408 can utilize example I / O pinsAttorney Docket No.: 27170.1093 (L1044PCT)DQ2-DQ3 and DQ6-DQ7. In some embodiments, though not shown, selector signal 312 can toggle the electrical connections to the I / O pins 418 according to similar methods. In some embodiments, a signal may be used to adjust a DQS signal of either the first multiconfiguration die 408 or the second multi-configuration die 408 as described above.

[0032] In some embodiments, the selector signals 412 and 414 can be utilized to select the mode of operation upon assembly of the module in which the multi-configuration stacked die DRAM device 400 is input, or upon each initialization of the multi-configuration stacked die DRAM device 400 device within the module. In some embodiments, the first or second mode may be elected atthe time of manufacture, for example by setting selector signal 312 of one or more die in the multi-configuration stacked die DRAM device 400 to a constant value using a wire bond and / or a fuse, or the first or second mode may be elected after manufacturing by, for example, configuration of a register in one or more die 300 of the multi-configuration stacked die DRAM device 400.

[0033] FIG. 5 is a block diagram illustrating a four die multi-configuration stacked die DRAM device 500, in accordance with some embodiments of the present disclosure. In some embodiments, a four die multi-configuration stacked die DRAM device 500 can be created by replicating twice the configuration of the die and connectivity from multiconfiguration stacked die DRAM device 400 as shown in FIG. 4 within a single package. A four die architecture can be used to output bits that utilize both ranks and slices as shown in FIG. 2 using the first mode and the second mode as described in FIG. 4.

[0034] The four die multi-configuration stacked die DRAM device 500 can be configured as a two slice DDP DRAM or a four slice DRAM. In a two slice DDP DRAM, the DRAM device utilizes four device die split into two pairs of dies. The first pair is configured as a DDP DRAM, or the first mode 202, as shown in FIG. 2, in which there are two die that make up a first slice, such as slice 0, with two ranks, utilizing four I / O pins total. The second pair is architecturally the same as the first pair, however within the two slice DDP DRAM, the second pair constitutes a second slice, for example slice 1 , with two ranks, utilizing four I / O pins total. The resulting two slice DDP DRAM utilizes eight I / O pins, spilt over two slices, each slice with two ranks.

[0035] In a four slice DRAM, the DRAM device utilizes four device die, each device die configured as a separate slice. The four slice DRAM, like the second mode 204, of FIG. 2, can include four dies, each with its own slice, slices 0-3, and a single rank, rank 0. Each die utilizes four I / O pins, for a total of 16 I / O pins utilized by the four slices.Attorney Docket No.: 27170.1093 (L1044PCT)

[0036] In some embodiments, a first stacked die assembly 502 can be configured, for example, as a multi-configuration stacked die DRAM device 400. As described above, the first stacked die assembly 502 can be configured in a first mode of operation or a second mode of operation. The first stacked die assembly 502 can be configured to electrically connect to a first and second input pin 416 and a first plurality of the I / O pins 418, for example, I / O pins DQ0-DQ3 and DQ8-DQ11. Depending on the mode of operation, the first stacked die assembly 502 can utilize some or all of the first plurality of the I / O pins 418. The mode of operation can be set by the selector signals 412 and 414 received at the selector devices 310 of the first stacked die assembly 502.

[0037] In some embodiments, a second stacked die assembly 504 of the four die multiconfiguration stacked die DRAM device 500 can be configured, for example, as a multiconfiguration stacked die DRAM device 400. As described above, the second stacked die assembly 504 can be configured in a first mode of operation or a second mode of operation. The second stacked die assembly 504 can be configured to electrically connect to a first and second input pin 416 and a second plurality of the I / O pins 418, for example, I / O pins DQ4-DQ7 and DQ12-DQ15. Depending on the mode of operation, the second stacked die assembly 504 can utilize some or all of the second plurality of the I / O pins 418. The mode of operation can be set by the selector signals 512 and 514 received at the selector devices 310 of the second stacked die assembly 504.

[0038] In some embodiments, the mode of operation for the first stacked die assembly 502 may be the same or different from the mode of operation for the second stacked die assembly 504. In one example, the first stacked die assembly 502 may be in the first mode and the second stacked die assembly 504 may also be in the first mode. For example, the selector signals 412 and 414 may place the first stacked die assembly 502 in the first mode of operation, such as a DDP operation. The first stacked die assembly 502, may then output four bits of data using ranks assigned to the channels of the dies 406 and 408 within the first stacked die assembly 502. In the first mode of operation, I / O pins DQ0-DQ1 and DQ8-DQ9 may be used and DQ2-DQ3 and DQ10-DQ11 may not receive signals. The selector signals 512 and 514 may place the second stacked die assembly 504 in the first mode of operation, such as a DDP operation. The second stacked die assembly 504, may then output four bits of data using ranks assigned to the channels of the dies 406 and 408 within the second stacked die assembly 504. In the first mode of operation, I / O pins DQ4-DQ5 and DQ12-DQ13 may be used and DQ6-DQ7 andDQ14-DQ15 may not receive signals. In some embodiments, the first stacked die assembly 502 and the second stacked die assembly 504 each in the firstAttorney Docket No.: 27170.1093 (L1044PCT)mode of operation may make the output of the four die multi-configuration stacked die DRAM device 500 utilize two slices, a first slice with a first rank and a second rank for the first stacked die assembly 502 and a second slice with a first rank and a second rank for the second stacked die assembly 504, ultimately outputting eight bits of data total using two slices.

[0039] In some embodiments, the selector signals 412 and 414 may place the first stacked die assembly 502 in the second mode of operation, such as a 2S operation. The second mode of operation would cause the first stacked die assembly 502 to send signals to all of the I / O pins 418 of the first plurality of the I / O pins 418. The selector signals 512 and 514 may orient the second stacked die assembly 504 in the second mode of operation, such as a 2S operation. The second mode of operation would cause the second stacked die assembly 504 to send signals to all of the I / O pins 418 of the second plurality of the I / O pins 418. In some embodiments, the first stacked die assembly 502 and the second stacked die assembly 504 each in the second mode of operation can cause the four die multi-configuration stacked die DRAM device 500 to output eight bits of data from the first stacked die assembly 502 and eight bits of data from the second stacked die assembly 504, ultimately outputting 16 bits of data total using four dies. The 16 bits of data can be generated using only two inputs 306.

[0040] In some embodiments, either the selector signals 412 and 414 or the selector signals 512 and 514 can configure the first stacked die assembly 502 or the second stacked die assembly 504 in the first mode and the alternate in the second mode. For example, if the first stacked die assembly 502 is in the first mode, the second stacked die assembly 504 could be in the second mode or vice versa. Utilizing one of each mode of operation, the four die multi-configuration stacked die DRAM device 500 can utilize both slices and ranks to generate four bits of output from one die 502 or 504 and eight bits of output from the other die 502 or 504. This would eliminate the need for having two separate DRAM devices, like those described in FIG. 4. Without two distinct DRAM devices, the module would not be as crowded with electrical connections to input pins, power pins, alert pins, and the like. Rather, the four die multi-configuration stacked die DRAM device 500 can allow for more compact design that can be further customized at module creation or during use.

[0041] FIG. 6 is a block diagram illustrating a configurable multi-configuration stacked die DRAM device 600, in accordance with some embodiments of the present disclosure. The configurable server multi-configuration stacked die DRAM device 600 may include the addition of inverse selector devices 610 to provide modal configuration between x4 and x8 modes to the multi-configuration stacked die DRAM device 400 of FIG. 4. Compared to x4Attorney Docket No.: 27170.1093 (L1044PCT)mode, in x8 mode a DRAM die outputs twice the data using twice the I / O (DQ) pins resulting in fewer total die contributing to a cache line of data. Using the inverse selector devices 610, the configurable server multi-configuration stacked die DRAM device 600 may support a first mode of operation that is, for example a x8 DDP mode and a second mode of operation that is, for example, a x42S mode. All I / O signals for x4 and x8 modes of operation are connected from each DRAM die to a common set of DRAM package pins, for example using double bonded wire bonds, but not all modes of operation utilize all I / O signals from each die.

[0042] FIG. 6 shows an example of logic that utilizes the inverse selector devices 610 to allow for configurations that transitions between x4 and x8 modes. In the illustrated example, the first die 602 of the configurable server multi-configuration stacked die DRAM device 600 can comprise a first channel 302 and a second channel 304 that provide multiple outputs to, for example, selector devices 310 and inverse selector devices 610. A first and a second output signal may be provided to the selectors 310. The selector devices 310 may provide the first and second output signals to I / O pins of the plurality of I / O pins 418. The selector devices 310 can be controlled by a selector signal 412 that set the selector devices 310 in a first setting to configure a first mode, or a second setting to configure a second mode. The first setting may pass the first and second output signals directly to I / O pins. In channel 1302 of the first die 602, for example, the first mode of the selector device 310 can provide the first and second signals to I / O pins DQ0 and DQ1. In channel 2304 of the first die 602, for example, the first mode of the selector device 310 can provide the first and second signals to I / O pins DQ4 and DQ5. The second setting of selector devices 310 may provide the first and second output signals to inverse selector devices 610. The inverse selector devices 610 maybe controlled by an inverse selector signal 606. Depending on the inverse selector signal 606, the inverse selector device 610 of the first die 602 may provide the first and the second signals to the I / O pins 418 or may provide a third and fourth signal to the I / O pins418. In channel 1 302, for example, the first mode of the inverse selector device 610 can provide the first and second signals to I / O pins DQ2 and DQ3 and the second mode of the inverse selector device 610 can provide the third and fourth signals to the I / O pins DQ2 and DQ3. In channel 2304, for example, the first mode of the inverse selector device 610 can provide the first and second signals to I / O pins DQ6 and DQ7 and the second mode of the inverse selector device 610 can provide the third and fourth signals to the I / O pins DQ6 and DQ7.Attorney Docket No.: 27170.1093 (L1044PCT)

[0043] Unlike the first die 406 of FIG. 4, the inclusion of the inverse selector devices 610 can enable each channel 302 and 304 the first die 602 ofFIG. 6 to provide signals to all four I / O pins simultaneously, allowing each channel 302 and 304 of the first die 602 to support interface widths of two bits and four bits of data, resulting in either x4 or x8 mode for the first die 602 and the multi-configuration stacked die DRAM device 600. For example, if the selector signal 412 directs the first and second output to a first set of I / O pins, and the inverse selector signal 606 directs the third and fourth I / O pins to a second set of pins, all four pins electrically connect to the first channel 302 of the first die 602. Similarly, inclusion of the inverse selector devices 610 in the second die 604 can cause an increase and / or variability of data output over the second die 408 of FIG. 4.

[0044] The second die 604 of the configurable server multi-configuration stacked die DRAM device 600 can comprise a first channel 302 and a second channel 304 that provide multiple outputs to selector devices 310 and inverse selector devices 610. A first and a second output signal may be provided to the selectors 310. The selector devices 310 may provide the first and second output signals to VO pins of the plurality of I / O pins 418. The selector devices 310 can be controlled by a selector signal 414 that set the selector devices 310 in a first setting to configure a first mode, or a second setting to configure a second mode. The first setting may pass the first and second output signals directly to I / O pins. In channel 1 302 of the second die 604, for example, the first mode of the selector device 310 can provide the first and second signals to I / O pins DQ0 and DQ1. In channel 2 304 of the second die 604, for example, the first mode of the selector device 310 can provide the first and second signals to I / O pins DQ4 and DQ5. The second setting of selector devices 310 may the first and second output signals to inverse selector devices 610. The inverse selector devices 610 may be controlledby an inverse selector signal 608. Depending on the inverse selector signal 608, the inverse selector device 610 of the second die 604 may provide the first and the second signals to the I / O pins 418 or may provide a third and fourth signal to the I / O pins 418. In channel 1 302, for example, the first mode of the inverse selector device 610 can provide the first and second signals to I / O pins DQ2 and DQ3 and the second mode of the inverse selector device 610 can provide the third and fourth signals to the I / O pins DQ2 and DQ3. In channel 2304, for example, the first mode of the inverse selector device 610 can provide the first and second signals to VO pins DQ6 and DQ7 and the second mode of the inverse selector device 610 can provide the third and fourth signals to the I / O pins DQ6 and DQ7.Attorney Docket No.: 27170.1093 (L1044PCT)

[0045] The selector signals 412 and 414 may be the same or different such that the selector devices 310 of the first die 602 and the second die 604 may be configured both in the first mode, both in the second mode, or one the first mode and one in the second mode. Similarly, the inverse selector signals 606 and 608 may be the same or different such that the inverse selector devices610 of the first die 602 and the second die 604 may be configured both in the first mode, both in the second mode, or one the first mode and one in the second mode.

[0046] Using all eight I / O pins 418 for each device die 602 and 604, the configurable server multi-configuration stacked die DRAM device 600 can be configurable as a 2S x4 DRAM device or a DDP x8 DRAM device depending on the settings of the selectors. A 2S x4 DRAM may be utilized when memory slices need to be configured separately, but the configuration of the module in which the DRAM device resides only has need for, or availability for, x4 memory output bits.

[0047] As a 2S x4 DRAM device, the configurable server multi-configuration stacked die DRAM device 600 utilizes the first die 602 as a first slice of a cache line and the second die 604 as a second slice. Each slice outputs 4 data bits. The selector signal 412 for a 2S x4 DRAM device may be a first setting, causing the selector device 310 to be configured in the first mode. The inverse selector signal 606 for a 2S x4 DRAM device may be a first setting, causing the inverse selector device 610 to be in a first mode. The selector device 310, could then provide the first and second signals to the first set of pins, for example pins DQ0 and DQ1, but as the first and second signals are not being passed to the inverse selector device 610, no signal would be passed to the second set of pins. In some embodiments, transceivers within the first die 602 can be utilized to interrupt the signal transmissions based on the mode of the selectors and inverse selectors. Thus, the first channel 302 of the first die 602 would only utilize two I / O pins. The selector signal 412 and the inverse selector signal 606 would cause the same output number, for example at VO pinsDQ4 and DQ5, to be output from the second channel 304 of the first die 602, thusthe first die 602 would only output four bits of data.

[0048] To complete the 2S x4 DRAM configuration, the selector signal 414 for the selector device 310 of the second die 604 may be a second setting, causing the selector device 310 to pass the first and second signals to the inverse selector device 610. The inverse selector signal 608, may then be configured in the first setting such that the first and second signals are provided to a set of pins, for example pinsDQ2 andDQ3. The selector signal 414 and the inverse selector signal 608 would cause the same output number, for example at I / OAttorney Docket No.: 27170.1093 (L1044PCT)pins DQ6 and DQ7, to be output from the second channel 304 of the second die 604, thus the second die 604 would only output four bits of data.

[0049] In a DDPx8 configuration, the first die 602 may output data to all eight I / O pins 418 and at a rank of 0. The second die 604 may output data to all eight I / O pins 418 at a rank of 1, by which the output data from the second die 604 may be accessed following the output data from rank 0 or may not be used. The selector signal for a DDP x8 device may be in a first setting, causing the selector device 310 to be configured in the first mode. The inverse selector signal 606 for a DDP x8 device may be in the second setting, causing the inverse selector device 610 to be in a second mode. The selector device 310 could then provide the first and second signals to the first set of pins, for example pins DQ0 and DQ1, and the inverse selector device 610 can provide the third and fourth signals to the second set of pins, for example DQ2 andDQ3. Thus, the first channel 302 of the first die 602 would send and receive data using four I / O pins 418. The selector signal 412 and the inverse selector signal 606 would cause the same input / output number, for example at I / O pins DQ4-DQ7, to be output from the second channel 304 of the first die 602, thus the first die 602 would output eight bits of data.

[0050] To complete the DDP x8 DRAM configuration, the selector signal 414 for the selector device 310 of the second die 604 maybe in a first setting, causing the selector device 310 to be configured in a first mode. The inverse selector signal 606 for a DDP x8 device may be in the second setting, causing the inverse selector device 610 to be in a second mode. The selector device 310 could then provide the first and second signals to the first set of pins, for example pins DQ0 and DQ1, and the inverse selector device 610 can provide the third and fourth signals to the second set of pins, for example DQ2 and DQ3. Thus, the second channel 304 of the second die 604 would send and receive data using four I / O pins 418. The selector signal 414 and the inverse selector signal 608 would cause the same input / output number, for example at I / O pins DQ4-DQ7, to be output from the second channel 304 of the second die 604, thus the second die 604 would output eight bits of data. In the x8 DDP configuration, both the first die 602 and the second die 604 are electrically connected to the same DRAM I / O pins 418, for example DQ0-DQ7, and thus the die operate as ranks and are not concurrently accessed.

[0051] The selector devices 310 and the inverse selector devices 610 can be configured such that the configurable server multi-configuration stacked die DRAM device 600 can provide the same functionality as the multi-configuration stacked die DRAM device 400 of FIG. 4. For example, the configurable server multi-configuration stacked die DRAM deviceAttorney Docket No.: 27170.1093 (L1044PCT)600 can be configured in a x4 DDP configuration. As described for the multi-configuration stacked die DRAM device 400 of FIG. 4, configuration of the multi-configuration stacked die DRAM device 600 in the first or second mode may be elected at the time of manufacture and configuration of a register of the multi-configuration stacked die DRAM device 400 and may utilize a wire bond and / or a fuse. For example, at boot time, the multi-configuration stacked die DRAM device 600 may be provided selector signals 412 and inverse selector signals 606 that would orient the first die 602 and the second die 604 such that the multi-configuration stacked die DRAM device 600 is operating in a first mode or a second mode. At a subsequent boot time, the multi-configuration stacked die DRAM device 600 may be directed by the selector signals 412 and inverse selector signals 606 to operate in a mode different than the mode selected at the previous boot time.

[0052] In some embodiments, the DRAM device 600 can be utilized within a module to operate in a 2Sx4 mode or a x8 mode. Without the use of the DRAM device 600, previous modules would be required to use four die or eight die to get designated bit outputs.Therefore, a module would specifically need to be created for one of the modes, but could not support both without substantial increase in space to house all required die. Alternatively, to achieve either mode with a set number of die, the module would be required to be formatted to facilitate the 2Sx4 mode orthex8 mode, but could not maintain the same format for both.

[0053] Using the DRAM device 600, in some embodiments, a module can support the 2S x4 mode and the x8 mode with a single module SKU. For example, the module may include four DRAM devices 600 per sub-channel each with two die. The utilization of the DRAM devices 600 eliminates the need for alternative die configurations and module formats to achieve both modes.

[0054] FIG. 7 is an example method 700 for configuring a multi-stacked die DRAM device 400, in accordance with some embodiments of the present disclosure. The method begins atblock 702 where a first semiconductor die, for example die 406, can receive a first selector signal. As explained above, the first selector signal, such as selector signal 412, can control the selector devices of the first die 406, to configure the die in a mode of operation. The method continues atblock 704 where a second semiconductor die, for example die 408, can receive a second selector signal. As explained above, the second selector signal, such as selector signal 414, can control the selector devices of the second die 408, to configure the die in a mode of operation.

[0055] The method continues at block 706, where the multi-stacked die DRAM device 400 can, configure, based on the first selector signal, a first selector device, such as selectorAttorney Docket No.: 27170.1093 (L1044PCT)device 310 of the first channel 302 or the second channel 304, of the first semiconductor die. The first selector device can electrically connect the first semiconductor die to at least one of a first set of input / output (I / O) pins or a second set of I / O pins. In some embodiments, the first set of I / O pins are the pins that are used by the first channel 302 of the first die 406 and the first channel 302 of the second die 406. In some embodiments, the second set of I / O pins are the pins that are used by the second channel 304 of the first die 406 and the second channel 304 of the second die 406. The configuration of the first die 406 using the first selector device 310 can configure the first die 406 into either a DDP selector configuration or a 2S configuration, depending on the configuration of the second die 408.

[0056] The method continues at block 708. The multi-configuration stacked DRAM device 400 can configure, based on the second selector signal, a second selector device. The second selector device for the second die 408 can be, for example selector device 310 of the first channel 302 or the second channel 304 . The second selector device can connect the second semiconductor die to at least one of the first set of I / O pins or the second set of I / O pins. In some embodiments, the first set of I / O pins are the pins that are used by the first channel 302 of the second die 406 and the first channel 302 of the second die 406. In some embodiments, the second set of I / O pins are the pins that are used by the second channel 304 of the first die 406 and the second channel 304 of the second die 406. The configuration of the second die 408 using the second selector device 310 can configure the second die 408 into either a DDP selector configuration or a 2S configuration, depending on the configuration of the second die 408. In some embodiments, the combination of the configuration of the first die 406 in one mode of operation set by the first selector signal and the configuration of the second die 408 in one mode of operation set by the second selector signal, can cause the multi-configuration stacked DRAM device 400 to output data in a DDP selector configuration or a 2S configuration.

[0057] In the above description, numerous details are set forth. It will be apparent, however, to one of ordinary skill in the art having the benefit of this disclosure, that embodiments of the present disclosure may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the description.

[0058] The words “example” or “exemplary” are used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as “example’ or “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the words “example” or “exemplary” is intended to presentAttorney Docket No.: 27170.1093 (L1044PCT)concepts in a concrete fashion. As used in this disclosure, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless specified otherwise, or clear from context, “X includes A or B” is intended to mean any of the natural inclusive permutations. That is, if X includes A; X includes B; or X includes both A and B, then “X includes A orB” is satisfied under any of the foregoing instances. In addition, the articles “a” and “an” as used in this disclosure and the appended claims should generally be construed to mean “one or more” unless specified otherwise or clear from context to be directed to a singular form. Moreover, use of the term “an embodiment” or “one embodiment” or “an implementation” or “one implementation” throughout is not intended to mean the same embodiment or implementation unless described as such.

[0059] The above description sets forth numerous specific details such as examples of specific systems, components, methods, and so forth, in order to provide a good understanding of several embodiments of the present disclosure. It will be apparent to one skilled in the art, however, that at least some embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known components or methods are not describedin detail or are presentedin simple block diagram format in order to avoid unnecessarily obscuring the present disclosure. Thus, the specific details set forth above are merely exemplary. Particular implementations may vary from these exemplary details and still be contemplated to be within the scope of the present disclosure.

[0060] The description above includes specific terminology and drawing symbols to provide a thorough understanding of the present disclosure. In some instances, the terminology and symbols may imply specific details that are not required to practice the disclosure. For example, any of the specific numbers of bits, signal path widths, signaling or operating frequencies, component circuits or devices and the like may be different from those described above in alternative embodiments. Also, the interconnection between circuit elements or circuit blocks shown or described as multi-conductor signal links may alternatively be single-conductor signal links, and single conductor signal links may alternatively be multiconductor signal links. Signals and signaling paths shown or described as being single-ended may also be differential, and vice-versa. Similarly, signals described or depicted as having active-high or active-low logic levels may have opposite logic levels in alternative embodiments. Component circuitry within integrated circuit devices may be implemented using metal oxide semiconductor (MOS) technology, bipolar technology, or any other technology in which logical and analog circuits may be implemented. With respect to terminology, a signal is said to be “asserted” when the signal is driven to a low or high logicAttorney Docket No.: 27170.1093 (L1044PCT)state (or charged to a high logic state or discharged to a low logic state) to indicate a particular condition. Conversely, a signal is said to be “de-asserted” to indicate that the signal is driven (or charged or discharged) to a state other than the asserted state (including a high or low logic state, or the floating state that may occur when the signal driving circuit is transitioned to a high impedance condition, such as an open drain or open collector condition). A signal driving circuit is said to “output” a signal to a signal receiving circuit when the signal driving circuit asserts (or de-asserts, if explicitly stated or indicated by context) the signal on a signal line coupled between the signal driving and signal receiving circuits. A signal line is said to be “activated” when a signal is asserted on the signal line, and “deactivated” when the signal is de-asserted. Additionally, the prefix symbol “ / ” attached to signal names indicates that the signal is an active low signal (i.e., the asserted state is a logic low state). A line over a signal name (e.g.,< s’™a'name> ’) js aiso usec[ t0indicate an active low signal. The term “coupled” is used herein to express a direct connection as well as a connection through one or more intervening circuits or structures. Integrated circuit device “programming” may include, for example and without limitation, loading a control value into a register or other storage circuit within the device in response to a host instruction and thus controlling an operational aspect of the device, establishing a device configuration or controlling an operational aspect of the device through a one-time programming operation (e.g., blowing fuses within a configuration circuit during device production), and / or connecting one or more selected pins or other contact structures of the device to reference voltage lines (also referred to as strapping) to establish a particular device configuration or operation aspect of the device. The term “exemplary” is used to express an example, not a preference or requirement. While the disclosure has been described with reference to specific embodiments thereof, it will be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the disclosure. For example, features or aspects of any of the embodiments may be applied, at least where practicable, in combination with any other of the embodiments or in place of counterpart features or aspects thereof. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

[0061] It is to be understood that the above description is intended to be illustrative and not restrictive. Many other embodiments will be apparent to those of skill in the art upon reading and understanding the above description. The scope of the disclosure should,Attorney Docket No.: 27170.1093 (L1044PCT)therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

[0062] While the invention has been described with reference to specific embodiments thereof, it will be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. For example, features or aspects of any of the embodiments maybe applied, at least where practicable, in combination with any other of the embodiments or in place of counterpart features or aspects thereof. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

Attorney Docket No.: 27170.1093 (L1044PCT)CLAIMS1. A dynamic random-access memory (DRAM) device, the DRAM device comprising:a first semiconductor die;a second semiconductor die; anda plurality of input / output (I / O) pins, wherein when the DRAM device is configured in a first mode of operation, the first semiconductor die and the second semiconductor die are each configured to connect to a first set of the plurality of I / O pins, and wherein when the DRAM device is configured in a second mode of operation, the first semiconductor die is configured to connect to the first set of the plurality of I / O pins and the second semiconductor die is configured to connect to a second set of the plurality of I / O pins.

2. The DRAM device of claim 1, wherein the second semiconductor die further comprises a selector device.

3. The DRAM device of claim 2, wherein the selector device is to electrically connect the second semiconductor die to the first set of the plurality of I / O pins when the DRAM device is configured in the first mode of operation and to the second set of the plurality of I / O pins when the DRAM device is configured in the second mode of operation.

4. The DRAM device of claim 1, wherein the plurality of I / O pins comprises data queue pins.

5. The DRAM device of claim 1, wherein the first mode of operation comprises a dual die package mode, and wherein the second mode of operation comprises a two slice mode.

6. The DRAM device of claim 1, wherein the first semiconductor die and the second semiconductor die are each connected to a first command address interface and to a second command address interface.

7. A dynamic random-access memory (DRAM) device, the DRAM device comprising:a first semiconductor die, the first semiconductor die comprising:a first channel configured to output one or more signals at a first set of a first plurality of input / output (I / O) pins; andAttorney Docket No.: 27170.1093 (L1044PCT)a second channel configured to output one or more signals to a first set of a second plurality of I / O pins; anda second semiconductor die, the second semiconductor die comprising:a third channel communicatively coupled to the first plurality of I / O pins and to a first selector device, the third channel configured to output one or more signals to the first set of the first plurality of I / O pins when the DRAM device is configured in a first mode of operation or to a second set of the first plurality of I / O pins when the DRAM device is configured in a second mode of operation according to a setting of the first selector device; anda fourth channel communicatively coupled to the second plurality of I / O pins and to a second selector device, the fourth channel configured to output one or more signals to the first set of the second plurality of I / O pins when the DRAM device is configured in the first mode of operation or to a second set of the second plurality of I / O pins when the DRAM device is configured in the second mode of operation according to a setting of the second selector device.

8. The DRAM device of claim 7, wherein the first selector device and the second selector device are controlled by a selector signal.

9. The DRAM device of claim 8, wherein the selector signal is received prior to boot time.

10. The DRAM device of claim 7, wherein the first plurality of I / O pins and the second plurality of I / O pins comprise data queue pins.

11. The DRAM device of claim 7, wherein the first mode is a dual die package mode and wherein the second mode is a two slice mode.

12. The DRAM device of claim 7, wherein the first semiconductor die and the second semiconductor die are each connected to a first command address interface and to a second command address interface.Attorney Docket No.: 27170.1093 (L1044PCT)13. The DRAM device of claim 12, wherein the first channel and the third channel are connected to the first command address pin and the second channel and the fourth channel are connected to the second command address pin.

14. A method of operation of a memory device, the method comprising:receiving, at a first semiconductor die of the memory device, a first selector signal; receiving, at a second semiconductor die of the memory device, a second selector signal;configuring, based on the first selector signal, a first selector device of the first semiconductor die, wherein the first selector device is to electrically connect the first semiconductor die to at least one of a first set of input / output (I / O) pins or a second set of I / O pins; andconfiguring, based on the second selector signal, a second selector device of the second semiconductor die, wherein the second selector device is to electrically connect the second semiconductor die to at least one of the first set of I / O pins or the second set of I / O pins.

15. The method of claim 14, wherein the first selector signal and the second selector signal are received from an external device.

16. The method of claim 14, wherein the first semiconductor die and the second semiconductor die comprise a first channel and a second channel.

17. The method of claim 16, wherein the first channel is electrically connected to a first input pin and the second channel is electrically connected to a second input pin.

18. The method of claim 17, wherein first input pin and the second input pin are command address pins.

19. The method of claim 17, wherein the selector comprises a multiplexor.

20. The method of claim 14, wherein the first set of I / O pins and the second set of I / O pins comprise data queue pins.

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