Methods for improving oxidation and nitridation resistance of low resistivity conductive materials

Abstract

The present technology includes methods and systems for forming semiconductor structures, and devices therefrom. Methods include depositing a low resistivity conductive material and depositing a protective alloying material. Methods include forming an alloy of the low resistivity conductive material and the protective alloying material over a semiconductor structure. Methods include where the alloy includes less than or about 40 at.% of the protective alloying material.

Description

Atorney Docket No.: 080042-1540075-44025010W001METHODS FOR IMPROVING OXIDATION AND NITRIDATION RESISTANCE OF LOW RESISTIVITY CONDUCTIVE MATERIALSCROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims the benefit of and priority to U.S. Provisional Application No. 63 / 738,332, filed on December 23, 2024, and titled “METHODS FOR IMPROVING OXIDATION AND NITRIDATION RESISTANCE OF LOW RESISTIVITY CONDUCTIVE MATERIALS,” the content of which is herein incorporated by reference in its entirety for all purposes.TECHNICAL FIELD

[0002] This disclosure generally describes designs for advanced memory devices, logic devices, and other semiconductor structures, including as 4F2dynamic random-access memory (DRAM) arrays, 6F2DRAM arrays, 3D DRAM, 3D NAND, junction-less SONOS memory, floating body cell memory, oxide semiconductor memory, ferroelectric memory, and other advanced memory devices, as well as back end of line structures include interconnects, and low resistivity metal interconnects in subtractive schemes. More specifically, this disclosure describes low resistivity materials suitable for use in semiconductor structures with enhanced resistance to oxidation and nitridation.BACKGROUND

[0003] Integrated circuits are made possible by processes which produce intricately patterned material layers on substrate surfaces. Producing patterned material on a substrate requires controlled methods for forming and removing material. Material characteristics may affect how the device operates and may also affect how the films are removed relative to one another. Deposition processes produce films having certain characteristics. Many films that are formed require additional processing to adjust or enhance the material characteristics of the film in order to provide suitable properties.

[0004] Thus, there is a need for improved systems and methods that can be used to produce high quality devices and structures. These and other needs are addressed by the present technology.BRIEF SUMMARY

[0005] The present technology is generally directed to methods of forming semiconductor devices. Methods include depositing a low resistivity conductive material, depositing a protective alloying material, and forming an alloy of the low resistivity conductive material and the protective alloying material over a semiconductor structure. Methods include where the alloy includes less than or about 40 at.% of the protective alloying material.Atorney Docket No.: 080042-1540075-44025010W001

[0006] In embodiments, depositing the low resistivity conductive material or the protective alloying material includes depositing a layer of the low resistivity conductive material or the protective alloying material over the semiconductor structure. Moreover, in embodiments, depositing the protective alloying material or the low resistivity conductive material includes depositing an alternating layer of the protective alloying material or the low resistivity conductive material over the layer of low resistivity conductive material or the protective alloying material. In further embodiments, methods include depositing a further alternating layer of the low resistivity conductive material or the protective alloying material over the respective layer of low resistivity conductive material or protective alloying material. In yet more embodiments, forming the alloy includes a thermal anneal drive process with a temperature of greater than or about 400 °C to about 1100 °C. Embodiments include where depositing the low resistivity conductive material and the protective alloying material include co-sputtering the low resistivity conductive material and the protective alloying material. In embodiments, depositing the low resistivity conductive material and the protective alloying material include sputtering a mixture of the low resistivity conductive material and the protective alloying material. Additionally or alternatively, embodiments include subjecting the semiconductor device to one or more high thermal budget processes.

[0007] Furthermore, in embodiments, methods include annealing the semiconductor device, recovering the low resistivity conductive material. In more embodiments, the low resistivity conductive material includes titanium nitride, titanium silicon nitride, polycrystalline silicon, molybdenum nitride, molybdenum silicide, titanium, tantalum, ruthenium, tungsten, molybdenum, platinum, nickel, cobalt, tantalum nitride, tungsten nitride, niobium nitride, titanium aluminide, titanium aluminum nitride, titanium silicide, titanium silicon nitride, tantalum silicide, tantalum silicon nitride, ruthenium titanium nitride, nickel silicide, cobalt silicide, iridium oxide, ruthenium oxide or a combination thereof, and combinations thereof. Embodiments include where the low resistivity conductive material includes molybdenum. In embodiments, the protective alloying material includes silicon, carbon, boron, or a combination thereof. In yet more embodiments, the protective alloying material includes silicon. In embodiments, the alloy includes MoSiy.

[0008] The present technology is also generally directed to semiconductor processing systems for forming semiconductor devices. Systems include a system controller configured to deposit a low resistivity conductive material, deposit a protective alloying material, and form an alloy of the low resistivity conductive material and the protective alloying material over a semiconductor structure. Systems include where the alloy contains less than or about 40 at.% of the protective alloying material, and at least a portion of the deposition occurs in a first processing chamber.Atorney Docket No.: 080042-1540075-44025010W001

[0009] In embodiments, a second processing chamber, a third processing chamber, and an optional fourth processing chamber, are contained within a cluster tool having a shared vacuum environment. In further embodiments, systems include a second processing chamber, where the system is configured to perform one or more operations in the second processing chamber.Moreover, in embodiments, a layer of the low resistivity conductive material and a layer of the protective alloying material are deposited in the first processing chamber. In embodiments, a layer of the low resistivity conductive material and a layer of the protective alloying material are deposited in different processing chambers. Furthermore, in embodiments, the system is further configured to anneal the semiconductor device after one or more high thermal budget processes.

[0010] Such technology may provide numerous benefits over conventional systems and techniques. For example, the processes and systems may allow the use of low resistivity materials in devices that subject such low resistivity materials to oxidation and nitridation during processing. Additionally, the processes and systems may significantly improve electrical properties of the low resistivity materials, as oxide and / or nitride formation over the low resistivity material may be reduced or eliminated. These and other embodiments, along with many of their advantages and features, are described in more detail in conjunction with the below description and attached figures.BRIEF DESCRIPTION OF THE DRAWINGS

[0011] A further understanding of the nature and advantages of the disclosed technology may be realized by reference to the remaining portions of the specification and the drawings.

[0012] FIG. 1 A shows a top plan view of an exemplary processing chamber according to embodiments of the present technology.

[0013] FIG. IB illustrates a top view of a conventional 4F2memory array.

[0014] FIG. 1C illustrates a perspective view of a conventional 4F2memory array.

[0015] FIG. ID illustrates a perspective view of a conventional 6F2memory array.

[0016] FIG. 2 shows selected operations in a formation method according to embodiments of the present technology.

[0017] FIG. 3 A shows a schematic view of a semiconductor structure according to embodiments of the present technology.

[0018] FIG. 3B shows a schematic view of a semiconductor structure according to embodiments of the present technology.Atorney Docket No.: 080042-1540075-44025010W001

[0019] FIG. 3C shows a schematic view of a semiconductor structure according to embodiments of the present technology.

[0020] FIG. 3D shows a schematic view of a semiconductor structure according to embodiments of the present technology

[0021] FIG. 4A shows a schematic view of a semiconductor structure according to embodiments of the present technology.

[0022] FIG. 4B shows a schematic view of a semiconductor structure according to embodiments of the present technology.

[0023] FIG. 5 shows a schematic view of a semiconductor structure according to embodiments of the present technology.

[0024] Several of the figures are included as schematics. It is to be understood that the figures are for illustrative purposes and are not to be considered of scale unless specifically stated to be of scale. Additionally, as schematics, the figures are provided to aid comprehension and may not include all aspects or information compared to realistic representations and may include exaggerated material for illustrative purposes.

[0025] In the appended figures, similar components and / or features may have the same reference label. Further, various components of the same type may be distinguished by following the reference label by a letter that distinguishes among the similar components. If only the first reference label is used in the specification, the description is applicable to any one of the similar components having the same first reference label irrespective of the letter.DETAILED DESCRIPTION

[0026] Advanced semiconductor devices, including vertical cell structures such as 4F2DRAM, 6F2DRAM, 3D NAND, 3D DRAM, junction-less SONOS memory, floating body cell memory, oxide semiconductor memory, ferroelectric memory, logic devices and other devices having complex features and a desire for lower resistivity materials, such as back end of line structures include interconnects, and low resistivity metal interconnects in subtractive schemes as examples, come with their own challenges. For instance, there is a desire to utilize low resistivity conductive materials in semiconductor devices, such as for forming signal or power lines as well as interconnects, which may also be in the form of sheets or thin films. However, low resistivity conductive materials, such as molybdenum, ruthenium, tungsten, titanium, titanium nitride, iridium, rhodium, and the like easily undergo oxidation and / or nitridation when left exposed, or adjacent to a nitride or oxygen containing materials or exposed to high temperatures duringAtorney Docket No.: 080042-1540075-44025010W001processing. In addition, such low resistivity conductive materials are easily damaged during processing. One of the reasons is that common low resistivity conductive materials often have low bond energies, allowing non-self-limiting oxidation or nitridation processes to proceed. These difficulties are further compounded by the fact that suitable isolation materials often cannot handle thermal processing that occurs during semiconductor processing, such as dielectric or metal depositions, silicide formation, and junction activation, as examples. This is problematic, as oxidation and nitridation increase the resistance of the material, impacting the electrical properties.

[0027] Attempts have been made to protect low resistivity materials using passivating agents, such as by formation of a silicon cap using a silicon containing precursor gas. However, such processes are difficult to control, and result in variations is depth of the passivation material as well as high levels of silicon, such as greater than 40 at.% silicon in the modified low resistivity material film. This is problematic, as high levels of the passivating agent, such as silicon, also increases the resistance of the low resistivity conductive material. Attempts have been made to remove the passivating material after processing, but such a procedure is not suitable for use with all semiconductor structures, as the necessary thermal annealing processing requires a prohibitively high thermal budget for many semiconductor structures. Thus, existing processes have failed to provide methods of improving the resistance to oxidation and nitridation of low resistivity materials, without impacting the electrical properties of the material.

[0028] The present technology overcomes these and other problems by utilizing an alloying process that deposits a film of an alloying material over the low resistivity conductive material, and drives in the alloying material, to improve the stability of the low resistivity conductive material. Namely, the present technology has surprisingly found that by utilizing a solid phase process, a carefully tailored amount of the alloying element may be incorporated into the low resistivity material layer. This allows for enhanced resistance to oxidation and nitridation of the low resistivity material without the impact to electrical properties previously exhibited by attempts that utilized large percentages of a passivating element. In addition, by forming an alloy of the low resistivity material, such as by utilizing a thermal drive operation, the alloy of the low resistivity material may be protected throughout an entirety of the layer, allowing for etching and other processing of the layer without exposure of the unmodified low resistivity material. Furthermore, as the alloy may be formed simultaneously with or just after formation of the low resistivity material, no recovery of the low resistivity material may be needed.

[0029] Although the remaining disclosure will routinely identify specific deposition and etch processes utilized for forming vertical cell access array transistors (VCAATs), such as aAtorney Docket No.: 080042-1540075-44025010W0014F2DRAM device, it will be readily understood that the systems and methods are equally applicable to other memory and logic devices, including 4F2DRAM, 6F2DRAM, 3D NAND, 3D DRAM, junction-less SONOS memory, floating body cell memory, oxide semiconductor memory, ferroelectric memory, and logic devices having complex features and a desire for lower resistivity materials, such as back end of line structures include interconnects, and low resistivity metal interconnects in subtractive schemes as examples, as well as processes for forming such devices. Accordingly, the technology should not be considered to be so limited as for use with these specific devices or systems alone. The disclosure will discuss one possible semiconductor device that may include one or more components, utilizing one or more power lines and / or signal lines according to embodiments of the present technology before additional variations and adjustments to this apparatus according to embodiments of the present technology are described.

[0030] FIG. 1 A illustrates a top plan view of a multi-chamber processing system 100, which may be specifically configured to implement aspects or operations according to some embodiments of the present technology. The multi-chamber processing system 100 may be configured to perform one or more fabrication processes on individual substrates, such as any number of semiconductor substrates, for forming semiconductor devices. The multi-chamber processing system 100 may include some or all of a transfer chamber 106, a buffer chamber 108, single wafer load locks 110 and 112, although dual load locks may also be included, processing chambers 114, 116, 118, 120, 122, and 124, preheating chambers 123 and 125, and robots 126 and 128. The single wafer load locks 110 and 112 may include heating elements 113 and may be attached to the buffer chamber 108. The processing chambers 114, 116, 118, and 120 may be attached to the transfer chamber 106. The processing chambers 122 and 124 may be attached to the buffer chamber 108. Two substrate transfer platforms 102 and 104 may be disposed between transfer chamber 106 and buffer chamber 108 and may facilitate transfer between robots 126 and 128. The platforms 102, 104 can be open to the transfer chamber and buffer chamber, or the platforms may be selectively isolated or sealed from the chamber to allow different operational pressures to be maintained between the transfer chamber 106 and the buffer chamber 108. Transfer platforms 102 and 104 may each include one or more tools 105, such as for orientation or measurement operations.

[0031] The operation of the multi-chamber processing system 100 may be controlled by a computer system 130. The computer system 130 may include any device or combination of devices configured to implement the operations described below. Accordingly, the computer system 130 may be a controller or array of controllers and / or a general-purpose computer configured with software stored on a non-transitory, computer-readable medium that, whenAtorney Docket No.: 080042-1540075-44025010W001executed, may perform the operations described in relation to methods according to embodiments of the present technology. Each of the processing chambers 114, 116, 118, 120, 122, and 124 may be configured to perform one or more process steps in the fabrication of a semiconductor structure. More specifically, the processing chambers 114, 116, 118, 120, 122, and 124 may be outfitted to perform a number of substrate processing operations including dry etch processes, cyclical layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etch, pre-clean, degas, orientation, among any number of other substrate processes.

[0032] FIGS. IB and 1C illustrate top and perspective views of a conventional 4F2memory array 150. The memory array 150 may include a plurality of word lines 152 that are arranged in a first layer over a substrate. The word lines 152 may be conductive traces that are used to select a word line of memory cells in the memory array 150. The memory array 150 may also include a plurality of bit lines 154 arranged in a second layer over a substrate. The plurality of bit lines may be conductive traces that are used to select a bit line of memory cells in the memory array 150. Activating one of the plurality of bit lines 154 and one of the plurality of word lines 152 may select an individual cell in the memory array 150. The first layer and the second layer may include different metal layers formed at different times during manufacturing process. For example, the first layer with the word lines 152 may be formed above the second layer with the bit lines 154 such that the two layers do not intersect.

[0033] A plurality of vertical memory cells may be arranged over intersections between the plurality of word lines 152 and the plurality of bit lines 154. Each of the plurality of vertical memory cells may include a vertical transistor, which may be referred to as a vertical pillar transistor or vertical column transistor. A channel material for the transistor may be formed from a single-crystalline silicon, poly-crystalline silicon, amorphous silicon, silicon carbide, silicon germanium, germanium, an oxide semiconductor, including indium gallium zinc oxide, 2D materials including molybdenum disulfide, gallium nitride, carbon nanotubes, graphene, boron arsenide, combinations thereof, or any other substrates discussed in greater detail herein.Furthermore, dopants may be introduced based upon the device need, for any one or more of the materials discussed herein. This silicon channel may be formed by etching the substrate, as shown in the illustrated embodiments, or may be deposited onto the substrate, depending upon the desired device. Each of the plurality of vertical memory cells may also include a vertical capacitor 156. The vertical memory cell may operate by storing a charge on the vertical capacitors 156 to indicate a saved memory state. However, while FIGS. IB and 1C illustrate the arrangement of the vertical transistors and capacitors in a rectangular generally orthogonal grid pattern (where “generally orthogonal” may be within about 10° from orthogonal, such as less than or about 7.5°, such as lessAtorney Docket No.: 080042-1540075-44025010W001than or about 5°, such as less than or about 2.5°, such as less than or about 1° from orthogonal, or any ranges or values therebetween, where “generally” may be utilized to similarly vary “vertical”, “horizontal” and the like), it should be understood that other orientations are contemplated for use with the present technology. For instance, in embodiments, the capacitors and vertical transistors may be spaced in alternating rows that are offset by one half the distance between the vertical transistors. Namely, a first row of memory cells may be regularly spaced apart in a line in a first direction, and a second row of memory cells may also be regularly spaced apart in a line also in the first direction, but the second row of memory cells may be offset from the first row of memory cells, such as aligned approximately halfway between the vertical transistors and capacitors of the first row, in embodiments. Such a pattern may be referred to as a “honeycomb” or “hexagonal pattern” as compared to the square pattern illustrated in FIGS. IB and 1C. Thus, it should be understood that any suitable orientation may be utilized with the present technology.

[0034] It is useful to characterize the dimensions of the unit cell area 166 for this conventional 4F2memory array for comparison to the simple memory array described below. For example, a capacitor footprint 158 may be defined as a circular area around each vertical capacitor 156. The capacitor footprint 158 may include the horizontal cross-sectional area of the capacitor expanded out until the cross-sectional area contacts a capacitor area from a neighboring memory cell.Assuming that the word line pitch 162 for the plurality of word lines 152 and the bit line pitch 164 for the plurality of bit lines 154 may be defined as 2F. This leads to an overall cross-sectional area of 4F2for a unit cell area 166.

[0035] FIGS. ID may illustrate further example structures that may utilize a low conductivity resistive material discussed herein. FIG. ID illustrates a perspective view of a 6F2DRAM cell layout 10. The word line 12, bit line contact 13, bit line 14, storage node post 15, and storage node contact 16 are arranged in a 6F2layout. As discussed above, it should be clear that other structures may benefit from the low resistivity conductive material discussed herein. However, as examples only, FIGS. 1B-1D have been discussed. For instance, the methods and materials discussed herein may be well suited for 4F2devices, 6F2devices and back end of line structures, as the methods and materials allow for tailored drive-in temperatures based upon device requirements. Namely, a low drive in temperature may be utilized for structures such as 4F2devices and backend of line structures that require low temperatures due to device and thermal budget constraints, but also be suitable for high temperature drive-in structures such as 6F2, where higher temperatures may be possible, or needed due to device requirements, as examples only, which will be discussed in greater detail below. Thus, in embodiments, the systems and materials discussed herein may be utilized for forming one or more structures or features in one or more semiconductor devices fromAtorney Docket No.: 080042-1540075-44025010W001a low resistivity conductive material, such as bit lines in a 4F2and 6F2device, or metal interconnects in one or more logic devices, as examples only.

[0036] FIG. 2 shows exemplary operations in a method 200 according to some embodiments of the present technology. The method may be performed in a variety of processing chambers, including processing chamber 100 described above. Method 200 may include a number of optional operations, which may or may not be specifically associated with some embodiments of methods according to the present technology. For example, many of the operations are described in order to provide a broader scope of the structural formation, but are not critical to the technology, or may be performed by alternative methodology as would be readily appreciated. In addition, while the method may describe the formation method vertically, it should be understood that the other orientation from bit line to word line side may be utilized, as well as other orientations for nonvertical cell transistors.

[0037] Method 200 may include additional operations prior to initiation of the listed operations. For example, additional processing operations may include forming structures on a semiconductor substrate, which may include both forming and removing material. Prior processing operations may be performed in the chamber in which method 200 may be performed, or processing may be performed in one or more other processing chambers prior to delivering the substrate into the semiconductor processing chamber in which method 200 may be performed. Regardless, method 200 may optionally include delivering a semiconductor substrate to a processing region of a semiconductor processing chamber, such as processing chamber 100 described above, or other chambers that may include components as described above. The substrate may be deposited on a substrate support / transfer platform, which may be a pedestal such as substrate support 104, and which may reside in a processing region of the chamber, such as processing region of processing chamber 120 described above. Method 200 describes operations shown schematically in the Figures, the illustrations of which will be described in conjunction with the operations of method 200. It is to be understood that the Figures illustrate only partial schematic views, and a semiconductor substrate may include further components as illustrated in the figures, as well as alternative components, of any size or configuration that may still benefit from aspects of the present technology.

[0038] Method 200 may or may not involve optional operations to develop the semiconductor structure to a particular fabrication operation. It is to be understood that method 200 may be performed on any number of semiconductor devices 300 as illustrated in the Figures, including exemplary structures on which a selective deposition material may be formed. The films and layersAtorney Docket No.: 080042-1540075-44025010W001discussed herein may be illustrated as being formed directly over the semiconductor structure(s) 301, but it should be clear that one or more intervening materials may be present, as would be known in the art.

[0039] Moreover, while various deposition and fill processes will be described, it should be understood that, in embodiments, the semiconductor structure may be transferred to and between one or more process chambers 114, 116, 118, 120, 122, and 124 configured for deposition and / or fill processes, including chambers for: chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), thermally enhanced chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), plasma enhanced atomic layer deposition (PEALD), or the like. Thus, unless specified, it should be understood that any one or more of the above methods may be utilized as known in the art. Similarly, the semiconductor structure may be transferred to and between one or more process chambers 114, 116, 118, 120, 122, and 124 configured for etching, such as one or more of inductively coupled plasma (ICP) etching, reactive ion etching (RIE), capacitively coupled plasma (CCP) etching, or the like, as well as other etching processes as known in the art.

[0040] In embodiments, the substrate may include bulk substrates, epitaxially grown substrates, silicon, silicon germanium (SiGe), silicon on insulator (SOI), silicon germanium on insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, and / or gallium arsenide, as well as any one or more substrate materials discussed above, on insulator wafer. As used herein, the term “semiconductor substrate” refers to a substrate in which the entirety of the substrate is comprised of a semiconductor material. The semiconductor substrate may include any suitable semiconducting material and / or combinations of semiconducting materials for forming a semiconductor structure. For example, the semiconducting layer may comprise one or more materials such as crystalline silicon (e.g., Si<100>or Si<l 11>), silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafers, patterned or non-patterned wafers, doped silicon, germanium, gallium arsenide, or other suitable semiconducting materials. In embodiments, the semiconductor material is silicon (Si). In one or more embodiments, the semiconductor substrate includes a semiconductor material, e.g., silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), germanium tin (GeSn), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate includes one or more of silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), or phosphorus (P). Although a few examples of materials from which the substrate may be formed are described herein, any material that may serve as a foundation upon which passive and active electronic devices (e.g., transistors, memories, capacitors, inductors, resistors, switches, integratedAtorney Docket No.: 080042-1540075-44025010W001circuits, amplifiers, optoelectronic devices, or any other electronic devices) may be built falls within the spirit and scope of the present disclosure.

[0041] In embodiments, the semiconductor material may be a doped material, such as n-doped silicon (n-Si), or p-doped silicon (p-Si). In embodiments, the substrate may be doped using any suitable process such as an ion implantation process. As used herein, the term “n-type” refers to semiconductors that are created by doping an intrinsic semiconductor with an electron donor element during manufacture. The term n-type comes from the negative charge of the electron. In n-type semiconductors, electrons are the majority carriers and holes are the minority carriers. As used herein, the term “p-type” refers to the positive charge of a well (or hole). As opposed to n-type semiconductors, p-type semiconductors have a larger hole concentration than electron concentration. In p-type semiconductors, holes are the majority carriers and electrons are the minority carriers.

[0042] As illustrated in FIG. 3A, device 300 is provided that may include a semiconductor structure 301. The semiconductor structure may include a substrate formed from one or more substrate materials discussed above or dielectric materials, as examples only. In embodiments, a dielectric material may include one or more layers of a SiO gate oxide, a SiO-SiN-SiO stack, a SiON layer, a high k material, or combinations thereof. However, in embodiments, the semiconductor structure 301 may be or include one or more device components, such as one or more capacitors, one or more transistors, one or more bitlines, one or more metal and interconnection layers, one or more control circuits, one or more storage devices, one or more logic devices, or the like. It should be clear that the one or more completed device components may be completed or partially completed, such as may utilize a low resistivity conductive material discussed herein. Thus, it should be understood that, while the semiconductor structure 301 is illustrated as a generally horizontal surface, semiconductor structure 301 may be in the form of one or more features of trenches, including a plurality of such features or trenches arranged in an adjacent spaced apart relationship. For instance, in embodiments, the semiconductor structure 301 may be in the form of one or more word line or bit line trenches, or one or more features or trenches for a back end of line interconnects, as discussed above.

[0043] As illustrated, in embodiments, a low resistivity conductive material 302 may be deposited over the semiconductor structure 301. In embodiments, the low resistivity conductive material 302 may be formed, such as by one or more deposition processes, directly over the semiconductor structure 301 or a component thereof. Thus, it should be understood that, while the low resistivity conductive material 302 is illustrated as a generally horizontal surface, lowAtorney Docket No.: 080042-1540075-44025010W001resistivity conductive material 302 may be in the form of a line or sheet, such as one or more of the bit lines or word lines or back end of line interconnects discussed above, as well as a plurality of such structures disposed in an adjacent relationship. In embodiments, the low resistivity conductive material 302 may be a metallic signal or power line, such as a wordline and / or bitline material in embodiments or a metal material suitable for forming one or more interconnects.

[0044] In embodiments, the low resistivity conductive material may be deposited at a thickness of greater than or about 1 nm, such as greater than or about 2 nm, greater than or about 3 nm, greater than or about 3.5 nm, greater than or about 4 nm, greater than or about 4.5 nm, greater than or about 5 nm, greater than or about 5.5 nm, greater than or about 6 nm, greater than or about 6.5 nm, such as greater than or about 7 nm, such as less than or about 14 nm, less than or about 12 nm, less than or about 10 nm, or any ranges or values therebetween.

[0045] In embodiments, low resistivity conductive materials (“M”) may include any one or more low conductive materials having a low resistivity. In embodiments, low resistivity conductive materials may include titanium nitride, titanium silicon nitride, polycrystalline silicon, molybdenum nitride, molybdenum silicide, titanium, tantalum, ruthenium, tungsten, molybdenum, platinum, nickel, cobalt, tantalum nitride, tungsten nitride, niobium nitride, titanium aluminide, titanium aluminum nitride, titanium silicide, titanium silicon nitride, tantalum silicide, tantalum silicon nitride, ruthenium titanium nitride, nickel silicide, cobalt silicide, iridium oxide, ruthenium oxide or a combination thereof, and combinations thereof. The conductive materials listed above may also contain certain dopants to improve electrical, physical or chemical properties. The dopant can be boron, phosphorus, carbon, germanium, and the like, as well as combinations thereof. In embodiments, conductive materials may include one or more metals, such as titanium nitride, molybdenum nitride, molybdenum silicide, titanium, tantalum, ruthenium, tungsten, molybdenum, platinum, nickel, cobalt, tantalum nitride, tungsten nitride, niobium nitride, titanium aluminide, titanium aluminum nitride, titanium silicide, titanium silicon nitride, tantalum silicide, tantalum silicon nitride, ruthenium titanium nitride, nickel silicide, cobalt silicide, iridium oxide, ruthenium oxide or a combination thereof, and combinations thereof. Furthermore, in embodiments, the conductive material may include titanium nitride, molybdenum nitride, titanium, tantalum, ruthenium, tungsten, molybdenum, platinum, nickel, cobalt, tantalum nitride, tungsten nitride, niobium nitride, titanium aluminide, or a combination thereof, and combinations thereof. In further embodiments, the conductive material may include titanium nitride, titanium, tantalum, ruthenium, tungsten, molybdenum, platinum, nickel, cobalt, tungsten nitride, or a combination thereof, and combinations thereof. Moreover, in embodiments, the conductive material includes molybdenum, ruthenium, tungsten, titanium nitride, titanium, or a combination thereof.Atorney Docket No.: 080042-1540075-44025010W001

[0046] The low resistivity conductive material may be deposited using any one or more of the deposition methods discussed above. In embodiments, the deposition may include deposition utilizing one or more processes as known in the art, such as by utilizing a PVD, ALD, or CVD processes, as well as other selective and non-selective deposition processes discussed herein. Namely, one or more precursors or targets of the selected low resistivity conductive material may be flowed alone or co-flowed with one or more carrier and / or inert gasses and / or one or more pure metals or mixtures or alloys of the desired metal alone or in the presence of one or more additives, into the chamber. For instance, when utilizing molybdenum as the conductive material, suitable precursors may include molybdenum fluoride, molybdenum chloride, molybdenum oxychloride, a molybdenum-based metal organic compound, or combinations thereof. However, it should be clear that other precursors may be utilized based upon the conductive material selected.

[0047] Either before or after deposition of the low resistivity conductive material 302 during operation 201, the semiconductor device 300 may optionally undergo one or more cleaning operations, such as an oxide removal and / or an oxide conversion operation. One or more cleaning operations may be utilized to remove any oxides formed prior to deposition of the low resistivity conductive material 302. However, it should be understood that, in embodiments, no cleaning operation(s) may be necessary. For instance, in embodiments, some or all of the operations discussed herein may be conducted in the same cluster tool without breaking a vacuum environment. Additionally or alternatively, as the protective alloying material may be deposited in the same chamber or cluster tool as the low resistivity conductive material, little to no recovery of the low resistivity conducive material and / or pre-cleaning may be necessary.

[0048] Regardless of whether any cleaning is conducted, the deposition of the low resistivity conductive material may be conducted at a temperature of greater than or about 20 °C, such as greater than or about 50 °C, such as greater than or about 100 °C, such as greater than or about 150 °C, such as greater than or about 200 °C, such as greater than or about 210 °C, such as greater than or about 220 °C, such as greater than or about 230 °C, such as greater than or about 240 °C, such as greater than or about 250 °C, such as greater than or about 260 °C, such as greater than or about 270 °C, such as greater than or about 280 °C, such as greater than or about 290 °C, such as greater than or about 300 °C, such as greater than or about 310 °C, such as greater than or about 320 °C, such as greater than or about 330 °C, such as greater than or about 340 °C, such as greater than or about 350 °C, such as greater than or about 360 °C, such as greater than or about 370 °C, such as greater than or about 380 °C, such as greater than or about 390 °C, such as greater than or about 400 °C, such as greater than or about 410 °C, such as greater than or about 420 °C, such as greater than or about 430 °C, such as greater than or about 440 °C, such as greater than or about 450 °C,Atorney Docket No.: 080042-1540075-44025010W001such as greater than or about 460 °C, such as greater than or about 470 °C, such as greater than or about 480 °C, such as greater than or about 490 °C, such as greater than or about 500 °C, such as greater than or about 510 °C, such as greater than or about 520 °C, such as greater than or about 530 °C, such as greater than or about 540 °C, such as greater than or about 550 °C, such as greater than or about 560 °C, such as greater than or about 570 °C, such as greater than or about 580 °C, such as greater than or about 590 °C, such as greater than or about 600 °C, such as greater than or about 610 °C, such as greater than or about 620 °C, such as greater than or about 630 °C, such as greater than or about 640 °C, such as greater than or about 650 °C, such as greater than or about 660 °C, such as greater than or about 670 °C, such as greater than or about 680 °C, such as greater than or about 690 °C, such as up to about 700 °C or greater, or any ranges or values therebetween. Furthermore, it should be understood that the temperature or other chamber process conditions may be selected based upon the precursor(s) selected and / or the desired conductive material.

[0049] Furthermore, in embodiments, the conductive material may be deposited at a chamber pressure of greater than or about 50 millitorr, such as greater than or about 500 millitorr, such as greater than or about 1 torr, such as greater than or about 5 torr, such as greater than or about 10 torr, such as greater than or about 15 torr, such as greater than or about 20 torr, such as greater than or about 25 torr, such as greater than or about 30 torr, such as greater than or about 35 torr, such as greater than or about 40 torr, such as greater than or about 45 torr, such as greater than or about 50 torr, such as greater than or about 75 torr, such as greater than or about 100 torr, such as greater than or about 150 torr, such as greater than or about 200 torr, such as greater than or about 250 torr, such as greater than or about 300 torr, such as greater than or about 350 torr, such as greater than or about 400 torr, such as greater than or about 450 torr, such as greater than or about 500 torr, such as greater than or about 550 torr, such a greater than or about 600 torr, such as greater than or about 650 torr, such as greater than or about 700 torr, up to about 760 torr, or any ranges or values therebetween.

[0050] Regardless of the process conditions utilized, as illustrated in FIG. 3B, in embodiments, a protective alloying material 304 is applied over the low resistivity conductive material 302. In embodiments, protective alloying materials (“A”) may include silicon, boron, carbon, and combinations thereof. The protective alloying material 304 may be deposited using any one or more of the physical or chemical deposition methods discussed above. In embodiments, the deposition may include deposition utilizing one or more processes as known in the art, such as PVD, ALD, or CVD processes, as well as other selective and non-selective deposition processes discussed herein. Namely, one or more precursors of the selected protective alloying material 304 may be flowed alone or co-flowed with one or more carrier and / or inert gasses, into the chamber,Atorney Docket No.: 080042-1540075-44025010W001forming a film or layer over the low resistivity conductive material 302. While illustrated as being applied as a generally horizontal layer, it should be understood that the protective alloying material may be applied to any one or more sides of the low resistivity conductive material 302. For instance, the protective alloying material 304 may be formed over or applied over one or more top surfaces, side surfaces, bottom surfaces, or a combination thereof, of the low resistivity conductive material. For instance, in embodiments, the protective alloying material may be formed over any one or more exposed surfaces of the low resistivity conductive material.

[0051] Notwithstanding the protective alloying material(s) selected, the present technology has found that by utilizing a deposition process that deposits a film, as compared to gas treatment of the underlying material, a carefully controlled amount of the protective alloying material may be incorporated into or onto the low resistivity conductivity material. Namely, previous attempts utilized soaking processes that were difficult to control, and thus exhibited variations in depth uniformity and also resulted in large quantities of the passivating material being incorporated into the existing layers in as little as 1-2 seconds. Thus, the process may be considered difficult to control, and may result in materials with increased resistivity due to high levels of the passivating agent. Conversely, the processes and systems discussed herein allow for formation of carefully controlled layers, such as one or more protective alloying material layers having a thickness of greater than or about 0.1 nm, greater than or about 0.5 nm, greater than or about 1 nm, greater than or about 1.5 nm, as greater than or about 2 nm, greater than or about 2.5 nm, greater than or about 3 nm, greater than or about 3.5 nm, greater than or about 4 nm, greater than or about 4.5 nm, greater than or about 5 nm, or such as less than or about 10 nm, less than or about 9 nm, less than or about 8 nm, less than or about 7 nm, less than or about 6 nm, less than or about 5 nm, or any ranges or values therebetween.

[0052] However, in embodiments, the atomic percentage of the protective alloying material in the alloy may be dependent upon the initial thickness of the low resistivity conductive material. Thus, in embodiments, any thickness of the low resistivity conductive material and / or protective alloying material may be utilized, such that the protective alloying material forms less than or about 40 at.% of the alloy material, such as less than or about 37.5 at.%, less than or about 35 at.%, less than or about 32 at.%, less than or about 30 at.%, less than or about 27.5 at.%, less than or about 25 at.%, less than or about 22.5 at.%, less than or about 20 at.%, less than or about 17.5 at.%, less than or about 15 at.%, less than or about 12.5 at.%, less than or about 10 at.%, less than or about 7.5 at.%, less than or about 5 at.%, less than or about 2.5 at.%, less than or about 1 at.%, or any ranges or values therebetween.Atorney Docket No.: 080042-1540075-44025010W001

[0053] After deposition of the protective alloying material(s), a thermal drive operation may be utilized to form an alloy of the low resistivity conductive material “M” and the protective alloying material “A”, MxAy, finalizing operation 201 as illustrated in FIG. 3C. For instance, in embodiments, where the low resistivity conductive material is molybdenum, the protective alloying material may be silicon, forming an alloy MoSiy, as a nonlimiting example only. As illustrated, advantageously, the methods discussed herein form a layer of the alloy 306 of the low resistivity conductive material and the protective alloying material, such that the low resistivity conductive material is modified throughout an entirety of the layer (e.g. through a thickness of the layer extending form an exposed surface 305 to the semiconductor structure 301). Whereas prior attempts would only protect an exposed surface of the material. This is beneficial, as one or more features, vias, or other shapes may be etched or otherwise formed in the alloy 306 of the low resistivity conductive material and the protective alloying material without exposing an unmodified surface of the low resistivity conductive material to oxidation or nitridation. Thus, the alloy 306 of the low resistivity conductive material and the protective alloying material may exhibit an enhanced or increased resistance to oxidation and nitridation (e.g. the alloy is more resistant to oxidation and / or nitridation than the underlying low resistivity conductive material).

[0054] In embodiments, the thermal drive operation may be conducted at a temperature of greater than or about 100 °C, such as greater than or about 150 °C, such as greater than or about 200 °C, such as greater than or about 250 °C, such as greater than or about 300 °C, such as greater than or about 350 °C, such as greater than or about 400 °C, such as greater than or about 410 °C, such as greater than or about 420 °C, such as greater than or about 430 °C, such as greater than or about 440 °C, such as greater than or about 450 °C, such as greater than or about 460 °C, such as greater than or about 470 °C, such as greater than or about 480 °C, such as greater than or about 490 °C, such as greater than or about 500 °C, such as greater than or about 510 °C, such as greater than or about 520 °C, such as greater than or about 530 °C, such as greater than or about 540 °C, such as greater than or about 550 °C, such as greater than or about 560 °C, such as greater than or about 570 °C, such as greater than or about 580 °C, such as greater than or about 590 °C, such as greater than or about 600 °C, such as greater than or about 610 °C, such as greater than or about 620 °C, such as greater than or about 630 °C, such as greater than or about 640 °C, such as greater than or about 650 °C, such as greater than or about 660 °C, such as greater than or about 670 °C, such as greater than or about 680 °C, such as greater than or about 690 °C, such as greater than or about 700 °C, such as greater than or about 710 °C, such as greater than or about 720 °C, such as greater than or about 730 °C, such as greater than or about 740 °C, such as greater than or about 750 °C, such as greater than or about 760 °C, such as greater than or about 770 °C, such as greaterAtorney Docket No.: 080042-1540075-44025010W001than or about 780 °C, such as greater than or about 790 °C, such as greater than or about 800 °C, such as greater than or about 810 °C, such as greater than or about 820 °C, such as greater than or about 830 °C, such as greater than or about 840 °C, such as greater than or about 850 °C, such as greater than or about 860 °C, such as greater than or about 870 °C, such as greater than or about 880 °C, such as greater than or about 890 °C, such as greater than or about 900 °C, such as greater than or about 910 °C, such as greater than or about 920 °C, such as greater than or about 930 °C, such as greater than or about 940 °C, such as greater than or about 950 °C, such as greater than or about 960 °C, such as greater than or about 970 °C, such as greater than or about 980 °C, such as greater than or about 990 °C, such as greater than or about 1000 °C, such as greater than or about 1010 °C, such as greater than or about 1020 °C, such as greater than or about 1030 °C, such as greater than or about 1040 °C, such as greater than or about 1050 °C, such as greater than or about 1060 °C, such as greater than or about 1070 °C, such as greater than or about 1080 °C, such as greater than or about 1090 °C such as up to about 1100 °C or greater, or any ranges or values therebetween. Furthermore, it should be understood that the temperature or other chamber process conditions may be selected based upon the low resistivity conductive material, the protective alloying material, and / or the thermal constraints of the device.

[0055] Thus far, formation of the metal alloy has been discussed as utilizing a layer of the protective alloying material over a layer of the low resistivity conductive material. However, it should be clear that other methods of forming the alloy layer are contemplated herein, so long as the relative weight ratios of the low resistivity conductive material and protective alloying material are maintained at the levels discussed above.

[0056] For instance, referring to FIG. 4, in embodiments, alternating layers of the low resistivity conductive material and the protective alloying material may be utilized. While only three layers are shown, it should be clear that greater than three layers, such as four or more, five or more, six or more, seven or more, eight or more, nine or more, ten or more, or any ranges or values therebetween, may be utilized. Furthermore, in the illustrated figure, the low resistivity conductive material 302 is deposited over the semiconductor structure 301 followed by subsequent layer(s) of protective alloying material 304 and low resistivity conductive material 302, but it should be clear that, in embodiments, the protective alloying material 304 may be formed first, followed by subsequent layers of the low resistivity protective material. Such an orientation is also contemplated in regards to FIGS. 3A-3C.

[0057] As a further benefit, depending upon the thickness of the layers, little to no thermal drive operation may be needed to form the alloy 306 of the low resistivity conductive material and theAtorney Docket No.: 080042-1540075-44025010W001protective alloying material, particularly when utilizing alternating layers of the low resistivity conductive material and the protective alloying material. Namely, when multiple thin layers are utilized, little to no drive in may be necessary. Nonetheless, in embodiments, a thermal drive operation may be utilized to form the alloy 306 of the low resistivity conductive material and the protective alloying material, illustrated in FIG. 4B.

[0058] Moreover, in embodiments, the alloy 306 of the low resistivity conductive material and the protective alloying material may be formed directly over semiconductor structure 301, as illustrated in FIG. 5. In embodiments, such a layer may be achieved by one or more co-sputtering processes, that allow for multiple materials to be sputtered simultaneously or sequentially to one or more targets or cathodes. Each cathode can have a DC / Pulse DC or RF target and an associated magnetron. In such embodiments, the low resistivity material target and / or protective alloying material target may be sputtered sequentially or simultaneously, allowing for formation of the alloy 306 of the low resistivity conductive material and the protective alloying material.Additionally or alternatively, in embodiments, the low resistivity conductive material and protective alloying material may be pre-mixed at the desired atomic ratios, such as one or more of the weight ratios discussed above, and sputtered to a common target. In such embodiments, a PVD process may be utilized to deposit the alloy layer(s) 306, however, one or more of the processes discussed herein may be utilized. In embodiments, no thermal drive may be necessary when sputtering or co-sputtering, as the alloy forms during deposition. However, a thermal drive may still be utilized to form a uniform layer of the alloy 306 of the low resistivity conductive material and the protective alloying material. Nonetheless, it should be clear that the one or more layers illustrated in FIG. 5 may also be formed utilizing one or more of the CVD / ALD processes discussed above in regards to FIGS. 3A-3C discussed above. Namely, a multi-layer or multicomponent CVD and / or ALD process may be utilized to flow or co-flow one or more precursors, forming one or more alloy layer(s) 306.

[0059] Nevertheless, after formation of the alloy 306 of the low resistivity conductive material and the protective alloying material, one or more semiconductor processing operations 202 may be performed, such as etching, deposition, thermal or plasma treatment, and the like. For instance, referring to FIG. 3D, one or more power lines, signal lines, and / or interconnects 305 may be etched or otherwise formed in the alloy 306 of the low resistivity conductive material and the protective alloying material, as an example only. In embodiments, one or more of the semiconductor processing operations may include a high thermal budget operation.Advantageously, the alloy 306 of the low resistivity conductive material and the protectiveAtorney Docket No.: 080042-1540075-44025010W001alloying material may exhibit increased resistance to oxidation or nitridation, allowing for protection of the low resistivity conductive material during subsequent processing.

[0060] In embodiments an optional second anneal operation 203 may be conducted to drive the protective alloying material 304 out of the low resistivity conductive material 302, recovering the low resistivity conductive material. When utilized, the optional anneal process may be performed for between about 10 second and about 3600 seconds, at a temperature of between about 100 °C and about 650 °C, and at a pressure of between about 1 Torr and 760 Torr. However, as discussed above, in embodiments, due to the increased control over the formed alloy and the weight percentage of the protective alloying material, no recovery of the low resistivity conductive material may be necessary, as little to no effect on the electrical properties of the low resistivity conductive material is exhibited due to the carefully controlled amount of the alloying material(s).

[0061] As used herein, the terms “about” or “approximately” or “substantially” may be interpreted as being within a range that would be expected by one having ordinary skill in the art in light of the specification, namely may be used to modify a value, indicates that the value can be raised or lowered by 10% and remain within the disclosed aspect, such as 7.5%, such as 5%, such as 4%, such as 3%, such as 2%, such as 1 %, or any ranges or values therebetween. Moreover, the term “substantially free of’ is not to be limited to entirely or completely free of and may correspond to a lack of any appreciable or detectable amount of the recited substance in the material, such as less than the precision of an industry-accepted instrument or test for measuring the amount of the substance in the material. For instance, in embodiments, a material may be “substantially free of’ a substance when the amount of the substance in the material is less than 10%, less than 9%, less than 8%, less than 7%, less than 6%, less than 5%, less than 4%, less than 3%, less than 2%, less than 1 %, less than 0.5%, or less than 0.1 % by weight of the material.

[0062] In the foregoing description, for the purposes of explanation, numerous specific details were set forth in order to provide a thorough understanding of various embodiments. It will be apparent, however, that some embodiments may be practiced without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form.

[0063] The foregoing description provides exemplary embodiments only, and is not intended to limit the scope, applicability, or configuration of the disclosure. Rather, the foregoing description of various embodiments will provide an enabling disclosure for implementing at least one embodiment. It should be understood that various changes may be made in the function and arrangement of elements without departing from the spirit and scope of some embodiments as set forth in the appended claims.Atorney Docket No.: 080042-1540075-44025010W001

[0064] Specific details are given in the foregoing description to provide a thorough understanding of the embodiments. However, it will be understood that the embodiments may be practiced without these specific details. For example, circuits, systems, networks, processes, and other components may have been shown as components in block diagram form in order not to obscure the embodiments in unnecessary detail. In other instances, well-known circuits, processes, algorithms, structures, and techniques may have been shown without unnecessary detail in order to avoid obscuring the embodiments.

[0065] Also, it is noted that individual embodiments may have beeen described as a process which is depicted as a flowchart, a flow diagram, a data flow diagram, a structure diagram, or a block diagram. Although a flowchart may have described the operations as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be re-arranged. A process is terminated when its operations are completed, but could have additional steps not included in a figure. A process may correspond to a method, a function, a procedure, a subroutine, a subprogram, etc. When a process corresponds to a function, its termination can correspond to a return of the function to the calling function or the main function.

[0066] The term “computer-readable medium” includes, but is not limited to portable or fixed storage devices, optical storage devices, wireless channels and various other mediums capable of storing, containing, or carrying instruction(s) and / or data. A code segment or machine-executable instructions may represent a procedure, a function, a subprogram, a program, a routine, a subroutine, a module, a software package, a class, or any combination of instructions, data structures, or program statements. A code segment may be coupled to another code segment or a hardware circuit by passing and / or receiving information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc., may be passed, forwarded, or transmitted via any suitable means including memory sharing, message passing, token passing, network transmission, etc.

[0067] Furthermore, embodiments may be implemented by hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. When implemented in software, firmware, middleware or microcode, the program code or code segments to perform the necessary tasks may be stored in a machine readable medium. A processor(s) may perform the necessary tasks.

[0068] In the foregoing specification, features are described with reference to specific embodiments thereof, but it should be recognized that not all embodiments are limited thereto.Attorney Docket No.: 080042-1540075-44025010W001Various features and aspects of some embodiments may be used individually or jointly. Further, embodiments can be utilized in any number of environments and applications beyond those described herein without departing from the broader spirit and scope of the specification. The specification and drawings are, accordingly, to be regarded as illustrative rather than restrictive.

[0069] Additionally, for the purposes of illustration, methods were described in a particular order. It should be appreciated that in alternate embodiments, the methods may be performed in a different order than that described. It should also be appreciated that the methods described above may be performed by hardware components or may be embodied in sequences of machineexecutable instructions, which may be used to cause a machine, such as a general-purpose or special-purpose processor or logic circuits programmed with the instructions to perform the methods. These machine-executable instructions may be stored on one or more machine readable mediums, such as CD-ROMs or other type of optical disks, floppy diskettes, ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, flash memory, or other types of machine-readable mediums suitable for storing electronic instructions. Alternatively, the methods may be performed by a combination of hardware and software.

Claims

Attorney Docket No.: 080042-1540075-44025010W001WHAT IS CLAIMED IS:

1. A method of forming semiconductor device, comprising:depositing a layer of a low resistivity conductive material;depositing a layer of a protective alloying material; andforming, from the layer of the low resistivity conductive material and the layer of the protective alloying material, an alloy of the low resistivity conductive material and the protective alloying material over a semiconductor structure,wherein the alloy comprises less than or about 40 at.% of the protective alloying material.

2. The method of claim 1, wherein depositing the low resistivity conductive material or the protective alloying material comprises depositing layer of the low resistivity conductive material or the protective alloying material over the semiconductor structure.

3. The method of claim 2, wherein depositing the protective alloying material or the low resistivity conductive material comprises depositing an alternating layer of the protective alloying material or the low resistivity conductive material over the layer of low resistivity conductive material or the protective alloying material.

4. The method of claim 3, further comprising depositing a further alternating layer of the low resistivity conductive material or the protective alloying material over the respective layer of low resistivity conductive material or protective alloying material.

5. The method of claim 1, wherein forming the alloy comprises a thermal anneal drive process with a temperature of greater than or about 400 °C to about 1100 °C.

6. The method of claim 1, further comprising subjecting the semiconductor device to one or more high thermal budget processes.

7. The method of claim 6, further comprising annealing the semiconductor device, recovering the low resistivity conductive material.

8. The method of claim 1, wherein the low resistivity conductive material comprises titanium nitride, titanium silicon nitride, polycrystalline silicon, molybdenum nitride, molybdenum silicide, titanium, tantalum, ruthenium, tungsten, molybdenum, platinum, nickel, cobalt, tantalum nitride, tungsten nitride, niobium nitride, titanium aluminide, titanium aluminum nitride, titanium silicide, titanium silicon nitride, tantalum silicide, tantalum silicon nitride,Attorney Docket No.: 080042-1540075-44025010W001ruthenium titanium nitride, nickel silicide, cobalt silicide, iridium oxide, ruthenium oxide or a combination thereof, and combinations thereof.

9. The method of claim 1, wherein the protective alloying material comprises silicon, carbon, boron, or a combination thereof.

10. The method of claim 1, wherein the alloy comprises MoSiy.

11. The method of claim 1 , wherein depositing the layer of low resistivity conductive material and depositing the layer of protective alloying material occurs without vacuum break.

12. The method of claim 1, wherein the alloy forms one or more structures in a memory device or a back end of line structure.

13. The method of claim 12, wherein the alloy forms a signal line, a power line, or a back end of line interconnect.

14. A method of forming semiconductor device, comprising:sputter depositing an alloy of a low resistivity conductive material and a protective alloying material;wherein the alloy comprises less than or about 20 at.% of the protective alloying material.

15. The method of claim 14, wherein depositing the low resistivity conductive material and the protective alloying material comprises co-sputtering the low resistivity conductive material and the protective alloying material.

16. The method of claim 14, wherein depositing the low resistivity conductive material and the protective alloying material comprises sputtering a mixture of the low resistivity conductive material and the protective alloying material.

17. The method of claim 14, wherein the alloy comprises MoSiy.

18. The method of claim 14, wherein the alloy forms a signal line, a power line, or a back end of line interconnect.Attorney Docket No.: 080042-1540075-44025010W00119. A semiconductor processing system for forming a semiconductor device, comprising:a system controller configured todeposit a layer of a low resistivity conductive material;deposit a layer of a protective alloying material; andform, from the layer of the low resistivity conductive material and the layer of the protective alloying material, an alloy of the low resistivity conductive material and the protective alloying material over a semiconductor structure,wherein the alloy comprises less than or about 40 at.% of the protective alloying material.

20. The semiconductor processing system of claim 19, wherein a layer of the low resistivity conductive material and a layer of the protective alloying material are deposited in a first processing chamber.

21. The semiconductor processing system of claim 19, the system further comprising at least a first processing chamber and a second processing chamber, wherein a layer of the low resistivity conductive material and a layer of the protective alloying material are deposited in different processing chambers.

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