Semiconductor device and manufacturing method therefor, and electronic apparatus

Abstract

The present application relates to the technical field of semiconductors, and provides a semiconductor device and a manufacturing method therefor, and an electronic apparatus. The semiconductor device comprises a substrate and an epitaxial layer provided on the substrate, wherein the epitaxial layer comprises a channel layer and a barrier layer, and a gate is provided on the barrier layer. In addition, the semiconductor device further comprises a first passivation composite layer provided on the epitaxial layer, and / or a second passivation composite layer located on the gate, wherein the first passivation composite layer comprises at least two passivation layers, and the absolute value of the stress of the two passivation layers decreases in a direction away from the substrate; and the second passivation composite layer comprises at least two passivation layers, and the absolute value of the stress of the two passivation layers decreases in the direction away from the substrate. By providing a plurality of passivation layers having varying stress, the present application can reduce lattice defects on passivation surfaces, reduce leakage current, and reduce off-state power consumption, and can suppress the current collapse effect of the device.

Description

Semiconductor devices and their fabrication methods, electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202411994033.2, filed with the State Intellectual Property Office of China on December 30, 2024, entitled "Semiconductor Device and Preparation Method Thereof, Electronic Device", the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of semiconductor technology, and more particularly to a semiconductor device, an electronic device including the semiconductor device, and a method for fabricating the semiconductor device. Background Technology

[0003] With the development of communication technology, the field of radio frequency communication has put forward the requirements for semiconductor devices to have higher frequency, higher voltage, higher output power and higher efficiency.

[0004] Semiconductor devices based on compound semiconductor materials, such as gallium nitride (GaN)-based high electron mobility transistors (HEMTs), are increasingly being used in high-power radio frequency devices and high-voltage switching devices due to their excellent physical properties, including wide bandgap, high electron drift velocity, radiation resistance, and high-temperature resistance. They are widely applied in systems such as radar, wireless communication, navigation, satellite communication, and electronic warfare equipment. In HEMT devices, the use of a passivation layer can enhance the areal density of the two-dimensional electron gas in the channel region, thereby increasing the device's output power density.

[0005] As the performance requirements for devices increase, it is also necessary to suppress the current collapse effect and prevent the passivation layer from generating excessive stress on the device. However, in some related technologies, it is difficult to simultaneously suppress the current collapse effect and prevent excessive stress. For example, while the current collapse effect can be effectively suppressed, it may generate significant stress. This significant stress can lead to defects such as lattice discontinuities on the device surface, introducing large surface leakage current and increasing the device's power consumption in the off-state. Summary of the Invention

[0006] This application provides a semiconductor device, an electronic device including the semiconductor device, and a method for fabricating the semiconductor device. The main objective is to optimize the passivation surface, reduce lattice defects on the passivation surface, reduce leakage current, and lower off-state power consumption.

[0007] To achieve the above objectives, the embodiments of this application adopt the following technical solutions:

[0008] In one aspect, this application provides a semiconductor device, such as a high electron mobility transistor (HEMT).

[0009] The semiconductor device includes a substrate, a channel layer formed on the substrate, and a barrier layer formed on the channel layer; in addition, the barrier layer has a first passivation composite layer on the side opposite to the channel layer, and / or the semiconductor device further includes a gate formed on the barrier layer, and the gate has a second passivation composite layer.

[0010] The stress directions of the first passivation composite layer and the second passivation composite layer in this application can both be the same as the stress direction of the barrier layer. For example, if the stress of the barrier layer is normal stress, then both the first passivation composite layer and the second passivation composite layer are normal stress. Or, if the stress of the barrier layer is tensile stress, then both the first passivation composite layer and the second passivation composite layer are tensile stress.

[0011] In one implementation, the current collapse effect of the device can be suppressed by increasing the thickness of the passivation layer. Therefore, this application can increase the passivation composite layer, such as increasing the thickness of the first passivation composite layer or increasing the thickness of the second passivation composite layer, to achieve the purpose of suppressing the current collapse effect of the device.

[0012] In addition, in this application, the first passivation composite layer includes a first passivation layer and a second passivation layer, and the second passivation composite layer includes a third passivation layer and a fourth passivation layer; the first passivation layer and the second passivation layer are stacked in the direction from the channel layer to the barrier layer, and the third passivation layer and the fourth passivation layer are stacked in the same way; that is, the passivation layer (such as the first passivation composite layer or the second passivation composite layer) in the example of this application includes multiple layers, rather than a single layer structure.

[0013] Furthermore, in the first passivation composite layer, the absolute stress value of the first passivation layer is greater than that of the second passivation layer, and / or the density of the first passivation layer is greater than that of the second passivation layer. In the second passivation composite layer, the absolute stress value of the third passivation layer is greater than that of the fourth passivation layer, and / or the density of the third passivation layer is greater than that of the fourth passivation layer. This can be understood as follows: along the direction away from the barrier layer, the absolute stress value of the multiple passivation layers gradually decreases, i.e., the stress is designed with a stress gradient. In this example, the second and fourth passivation layers can be understood as stress-adjusting layers. Thus, even if the passivation composite layer including multiple passivation layers is relatively thick, compared to a single thick passivation layer, this application can reduce some phenomena that degrade device performance caused by excessive stress. For example, it can reduce lattice defects on the passivation surface, reduce leakage current, and reduce off-state power consumption.

[0014] Furthermore, in this application, the thickness of the first passivation layer is less than the thickness of the second passivation layer. Thus, even if the absolute value of the stress in the first passivation layer is greater than the absolute value of the stress in the second passivation layer, the stress will not be very large because the first passivation layer is relatively thin, and it will basically not cause lattice defects on the device surface, thereby reducing leakage current.

[0015] Therefore, the semiconductor device provided in this application can not only suppress the device current collapse effect, but also reduce stress, weaken the passivation surface lattice defects, reduce leakage current, and reduce off-state power consumption, thereby improving the working performance of the device.

[0016] Furthermore, since this application employs a multilayer passivation layer with varying stress gradients, stress accumulation can be avoided, thereby reducing the likelihood of substrate warping or even cracking caused by stress concentration.

[0017] In one feasible approach, the thickness of the third passivation layer is greater than the thickness of the fourth passivation layer.

[0018] Since the third passivation layer and the fourth passivation layer are disposed on the gate, the third passivation layer is closer to the gate than the fourth passivation layer. Furthermore, the third passivation layer in this application is thicker than the fourth passivation layer. That is, by using a thicker third passivation layer, the gate parasitic capacitance or parasitic resistance can be reduced, thereby further optimizing the device performance.

[0019] In one possible implementation, the semiconductor device includes a first passivation composite layer, a gate, and a second passivation composite layer; at least a portion of the second passivation composite layer is located on the first passivation composite layer.

[0020] In other words, the device surface has a stacked first passivation layer, a second passivation layer, a third passivation layer, and a fourth passivation layer. Because these stacked passivation layers have stress gradients, even if the overall thickness is large, the stress will not be very large in suppressing the current collapse effect of the device, and it will basically not cause surface lattice defects. Thus, leakage current is reduced, off-state power consumption is reduced, and the operating performance of the device is improved.

[0021] In one possible implementation, at least a portion of the sidewalls of the gate and at least a portion of the surface away from the barrier layer are covered by a second passivation composite layer, and the second passivation composite layer covering the gate extends onto the first passivation composite layer.

[0022] In this application example, since a second passivation composite layer is present on at least a portion of the surface and at least a portion of the side of the gate, the area of ​​the second passivation composite layer can be increased, thereby further suppressing the gate parasitic resistance or parasitic capacitance.

[0023] Furthermore, the second passivation composite layer on the gate extends onto the first passivation composite layer. From a manufacturing process perspective, after the gate and the first passivation composite layer are fabricated, the second passivation composite layer can be fabricated simultaneously on both the gate and the first passivation composite layer. The fabrication process is simple and does not require additional process steps.

[0024] In one possible implementation, a first passivation composite layer is present between the gate and the barrier layer.

[0025] This first passivation composite layer can suppress the parasitic capacitance and resistance of the gate, thereby optimizing device performance.

[0026] In one feasible approach, the thickness of the third passivation layer is greater than the thickness of the second passivation layer.

[0027] In some structures, when the device surface has a first passivation layer, a second passivation layer, a third passivation layer, and a fourth passivation layer, the third passivation layer can be understood as a stress adjustment layer. The third passivation layer is thicker than the second passivation layer, and it will not produce a large stress concentration phenomenon.

[0028] In one feasible approach, the thickness of the third passivation layer is S3, the thickness of the second passivation layer is S2, and S3 / S2 ≥ 2.

[0029] For example, S3 / S2≥2.5; or S3 / S2≥3.

[0030] In one feasible approach, the thickness of the fourth passivation layer is greater than the thickness of the first passivation layer.

[0031] In one possible implementation, the thickness of the fourth passivation layer is S4, the thickness of the first passivation layer is S1, and S4 / S1 ≥ 2.

[0032] For example, S3 / S2≥2.5; or S3 / S2≥3.

[0033] In one feasible manner, the absolute stress value of the first passivation layer is greater than the absolute stress value of the third passivation layer.

[0034] Since the absolute stress value of the first passivation layer is greater than that of the second passivation layer, and the absolute stress value of the first passivation layer is also greater than that of the third passivation layer, the absolute stress value of the first passivation layer near the device surface is larger, while the stress of the other passivation layers is smaller. As a stress adjustment layer, it will not cause the entire passivation layer to generate a large stress on the device surface, thus reducing the risk of lattice defects on the device surface.

[0035] In one possible implementation, the absolute stress value F1 of the first passivation layer and the absolute stress value F3 of the third passivation layer, F1 / F3 ≥ 1.2. For example, F1 / F3 ≥ 1.5. In another possible implementation, the absolute stress value of the second passivation layer is greater than or equal to the absolute stress value of the fourth passivation layer.

[0036] In one possible implementation, the absolute stress value F2 of the second passivation layer and the absolute stress value F4 of the fourth passivation layer are such that F2 / F4 ≥ 1.2. For example, F2 / F4 ≥ 1.5. In another possible implementation, the thickness S1 of the first passivation layer and the thickness S2 of the second passivation layer are such that 1 < S2 / S1 ≤ 10; for example, 1 < S2 / S1 ≤ 5. For example, 1 < S2 / S1 ≤ 3. And yet another example, 2 < S2 / S1 ≤ 3.

[0037] The rule 1 < S2 / S1 ≤ 10 ensures that the thickness of the second passivation layer cannot be too thick, thus avoiding the large stress caused by a thicker second passivation layer.

[0038] In one possible implementation, the thickness of the third passivation layer S3 and the thickness of the fourth passivation layer S4 are such that 1 < S3 / S4 ≤ 5.

[0039] For example, 1 < S3 / S4 ≤ 3. Another example is 2 < S3 / S4 ≤ 3.

[0040] The formula 1 < S3 / S4 ≤ 5 ensures that the thickness of the fourth passivation layer cannot be too thin, thus preventing a thinner fourth passivation layer from failing to play a stress-regulating role.

[0041] In one feasible manner, the refractive index of the first passivation layer is greater than that of the second passivation layer, and the refractive index of the third passivation layer is greater than that of the fourth passivation layer.

[0042] Since the refractive index of the first passivation layer is greater than that of the second passivation layer, the stress of the first passivation layer can be greater than that of the second passivation layer, thus ensuring the force on the barrier layer, enhancing the surface density of the two-dimensional electron gas in the device channel region, and improving the output power density of the device.

[0043] Since the refractive index of the third passivation layer is greater than that of the fourth passivation layer, the stress in the third passivation layer can be greater than that in the fourth passivation layer. This can also ensure the force on the barrier layer, enhance the surface density of the two-dimensional electron gas in the device channel region, and improve the output power density of the device.

[0044] In one feasible approach, the refractive index of the third passivation layer is less than that of the first passivation layer, and the refractive index of the fourth passivation layer is greater than that of the second passivation layer.

[0045] In one possible implementation, the stress direction of the second passivation layer is either opposite to or the same as the stress direction of the first passivation layer.

[0046] For example, the stress in the barrier layer is normal stress, and the stress in the second passivation layer and the stress in the first passivation layer can both be normal stress, or the stress in the first passivation layer is normal stress and the stress in the second passivation layer is tensile stress.

[0047] For example, the stress in the barrier layer is tensile stress, and the stress in the second passivation layer and the stress in the first passivation layer can both be tensile stress, or the stress in the first passivation layer is tensile stress and the stress in the second passivation layer is normal stress.

[0048] In some other examples, the stress in the second passivation layer can be close to zero.

[0049] In one feasible approach, the refractive index of the first passivation layer is greater than that of the second passivation layer, and the stress direction of the second passivation layer is the same as that of the first passivation layer.

[0050] In one feasible approach, the refractive index of the third passivation layer is greater than that of the fourth passivation layer, and the stress direction of the third passivation layer is the same as that of the fourth passivation layer.

[0051] In one possible implementation, either the first passivation layer or the second passivation layer is a single-layer structure, or either the first passivation layer or the second passivation layer comprises a stacked multilayer structure in which the absolute stress values ​​of adjacent layers are the same.

[0052] In one possible implementation, either the third or fourth passivation layer is a single-layer structure, or either the third or fourth passivation layer comprises a stacked multilayer structure in which the absolute stress values ​​of adjacent layers are the same.

[0053] For example, a single passivated structure can be obtained by using the same equipment and adjusting the growth program in one step, or by using different equipment or different programs to grow multiple passivated structures.

[0054] In one possible implementation, the materials of the first passivation layer and the second passivation layer are the same; and / or, the materials of the third passivation layer and the fourth passivation layer are the same.

[0055] The materials of the first passivation layer and the second passivation layer can be the same, and the materials of the third passivation layer and the fourth passivation layer can be the same. Selecting the same passivation material can simplify the manufacturing process. Also, if the density of the first passivation layer is greater than that of the second passivation layer, the absolute stress value of the first passivation layer can be greater than that of the second passivation layer. If the density of the third passivation layer is greater than that of the fourth passivation layer, the absolute stress value of the third passivation layer can be greater than that of the fourth passivation layer.

[0056] In one possible implementation, the semiconductor device further includes a source and a drain, as well as a source metal layer and a drain metal layer; the source extends through the barrier layer into the channel layer, and the drain extends through the barrier layer into the channel layer; a portion of the source metal layer is located in a second passivation layer and a portion penetrates the first passivation layer to contact the source; a portion of the drain metal layer is located in the second passivation layer and a portion penetrates the first passivation layer to contact the drain.

[0057] In fabricating the above structure, after the channel layer and barrier layer are fabricated, the source and drain are fabricated. Then, a first passivation layer is fabricated on the device surface above the barrier layer, followed by the source metal layer and the drain metal layer. Then, a second passivation layer is fabricated, which covers the source metal layer and the drain metal layer. In this way, the second passivation layer can be used to protect the source metal layer and the drain metal layer, avoiding contamination or damage to the source metal layer and the drain metal layer during subsequent gate etching.

[0058] Secondly, this application also provides an electronic device, which includes a radio frequency front-end circuit, the radio frequency front-end circuit including a power amplifier, and the power amplifier including a semiconductor device in any of the above implementations.

[0059] The electronic device provided in this application includes the aforementioned semiconductor device. The passivation layer of the semiconductor device adopts a multi-layer stacked structure with a stress gradient. In this way, even if the passivation composite layer including the multi-layer passivation layer is thicker, compared with a single thick passivation layer, this application can reduce some phenomena that degrade device performance caused by excessive stress. For example, it can reduce lattice defects on the passivation surface, reduce leakage current, and reduce off-state power consumption.

[0060] Thirdly, this application provides a method for fabricating a semiconductor device, the method comprising:

[0061] A channel layer and a barrier layer are fabricated on a substrate, with the channel layer located on the substrate and the barrier layer located on the channel layer.

[0062] The preparation method further includes: obtaining a first passivation layer and a second passivation layer, and / or obtaining a gate, a third passivation layer and a fourth passivation layer;

[0063] The thickness of the first passivation layer is less than the thickness of the second passivation layer. The first passivation layer is located on the barrier layer, and the second passivation layer is located on the first passivation layer. The absolute value of the stress in the first passivation layer is greater than the absolute value of the stress in the second passivation layer, and / or the density of the first passivation layer is greater than the density of the second passivation layer.

[0064] The gate is located on the barrier layer, at least a portion of the third passivation layer is located on the gate, the fourth passivation layer is located on the third passivation layer, the absolute stress value of the third passivation layer is greater than the absolute stress value of the fourth passivation layer, and / or the density of the third passivation layer is greater than the density of the fourth passivation layer.

[0065] In the semiconductor device fabricated by the above method, the passivation layer on the barrier layer includes at least two layers, and the passivation layer on the gate also includes at least two layers. One of the layers can serve as a stress adjustment layer to adjust the stress value of the entire passivation layer. In this way, even if the entire stacked passivation layer is relatively thick, it can effectively suppress the device current collapse effect without causing excessive stress. This can reduce lattice defects on the passivation surface, reduce leakage current, and lower off-state power consumption.

[0066] In one feasible manner, the third and fourth passivation layers are fabricated by:

[0067] A third passivation layer is formed on at least a portion of the side surface of the gate and at least a portion of the surface away from the barrier layer, and a third passivation layer is formed on the second passivation layer;

[0068] A fourth passivation layer is formed on the third passivation layer on the gate, and a fourth passivation layer is formed on the third passivation layer on the second passivation layer.

[0069] Not only is a second passivation composite layer disposed on the gate, but a second passivation composite layer is also disposed on the device epitaxial layer. That is, a first passivation composite layer and a second passivation composite layer are disposed on the device epitaxial layer. The stress of these multi-layer passivation layers is designed in a gradient manner. In this way, even if the passivation composite layer including the multi-layer passivation layer is relatively thick, compared with a single thick passivation layer, this application can reduce some phenomena that degrade device performance caused by excessive stress. For example, it can reduce lattice defects on the passivation surface, reduce leakage current, and reduce off-state power consumption.

[0070] In one possible implementation, the materials of the first passivation layer and the second passivation layer are the same; and / or, the materials of the third passivation layer and the fourth passivation layer are the same. Attached Figure Description

[0071] Figure 1 is a partial structural schematic diagram of a base station provided in an embodiment of this application;

[0072] Figure 2 is an exploded view of a portion of the structure of a mobile phone provided in an embodiment of this application;

[0073] Figure 3 is a partial circuit diagram of a mobile phone provided in an embodiment of this application;

[0074] Figure 4 is a circuit diagram of a radio frequency power amplifier provided in an embodiment of this application;

[0075] Figure 5 is a schematic diagram of the packaging structure of a semiconductor device provided in an embodiment of this application;

[0076] Figure 6 is a schematic diagram of the structure of a semiconductor device;

[0077] Figure 7 is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;

[0078] Figure 8 is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;

[0079] Figure 9 is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;

[0080] Figure 10 is a schematic diagram of the structure of a semiconductor device provided in an embodiment of this application;

[0081] Figure 11 is a flowchart of a method for fabricating a semiconductor device according to an embodiment of this application;

[0082] Figures 12 to 20 are schematic diagrams of the process structure after each step in the fabrication method of a semiconductor device provided in the embodiments of this application.

[0083] Reference numerals: 100-Circuit board; 200-Second electrical connection structure; 300-Semiconductor device; 400-Substrate; 500-First electrical connection structure; 11-Middle frame; 12-Back cover; 13-Display screen; 110-Bezel; 111-Carrier plate; 301-Substrate; 302-Buffer layer; 303-Channel layer; 304-Insertion layer; 305-Barrier layer; 306-Cap layer; 307-Passivation layer; 308-Source; 309-Drain; 310-Gate; 311-First passivation composite layer; 3111-First passivation layer; 3112-Second passivation layer; 312-Second passivation composite layer; 3121-Third passivation layer; 3122-Fourth passivation layer; 313-Source metal layer; 314-Drain metal layer; 315-Gate dielectric layer. Detailed Implementation

[0084] The solutions involved in the embodiments of this application will be described below with reference to the accompanying drawings.

[0085] This application provides an electronic device that may include communication devices (e.g., base stations, mobile phones), wireless charging devices, medical devices, radar, navigation devices, radio frequency (RF) plasma lighting devices, RF induction and microwave heating devices, etc. This application does not impose any special limitations on the specific form of the aforementioned electronic device.

[0086] The aforementioned electronic devices generally include radio frequency (RF) semiconductor devices, such as power amplifiers (PAs). The main function of a PA is to amplify RF signals. Taking a base station as an example, Figure 1 shows a simplified structural diagram of a base station. This base station includes a control unit, which comprises a radio transceiver, antennas, and related signal processing circuits. The control unit mainly consists of four components: a cell controller, a voice channel controller, a signaling channel controller, and a multiplexer interface for expansion. The base station control unit typically controls several base station transceivers. Through remote commands from the transceivers and mobile stations, the base station control unit is responsible for managing all mobile communication interfaces, primarily the allocation, release, and management of radio channels.

[0087] Referring back to Figure 1, the base station also includes a transmission unit, which is connected to the core network. Control signaling, voice calls, or data service information from the core network side are sent to the base station's control unit through the transmission unit, and these services are processed by the control unit.

[0088] Referring to Figure 1, the base station also includes a baseband unit and a radio frequency (RF) unit. The baseband unit mainly performs functions such as baseband modulation and demodulation, allocation of radio resources, call processing, power control, and soft handover. The RF unit mainly performs the conversion between the air radio frequency channel and the baseband digital channel, then amplifies the signal through a power amplifier (PA), and then sends it to the antenna for transmission via the RF feeder. Terminal devices, such as mobile phones and tablets, receive the radio waves transmitted by the antenna through the wireless channel and then demodulate their own signal.

[0089] Referring to Figure 1, the base station also includes a power supply unit, which can be used to supply power to structures such as the transmission unit, baseband unit, and control unit.

[0090] Figure 2 shows a structural diagram of another electronic device, taking a mobile phone as an example. The mobile phone may include a mid-frame 11, a back cover 12, and a display screen 13. The mid-frame 11 includes a support plate 111 for supporting the display screen 13, and a frame 110 around the support plate 111.

[0091] Figure 3 illustrates an exemplary circuit diagram of an electronic device. This example includes a transceiver and an RF front-end circuit, with the transceiver coupled to an antenna via the RF front-end circuit. The RF front-end circuit includes a power amplifier; for example, the power amplifier can be coupled to the antenna via a switch and a filter, or, for another example, via a duplexer and a switch. In other examples, other electronic components can be added to the circuit of Figure 3. Figure 4 is an exemplary circuit diagram of a power amplifier provided in this application. In this circuit, the power amplifier (e.g., a GaN HEMT semiconductor device unit) serves as the main component, and during operation, it needs to work with RF signal input / output matching, bias circuits, and electronic components such as capacitors and inductors to form a microwave monolithic integrated circuit.

[0092] With the development of mobile communication technology, the functional requirements for the aforementioned semiconductor devices are becoming increasingly higher, such as higher frequency, higher voltage, higher output power, and higher efficiency.

[0093] Among the available semiconductor materials, gallium nitride (GaN) has become a key material for fabricating radio frequency semiconductor devices due to its high thermal conductivity, high breakdown field strength, and high saturation electron mobility. For example, high electron mobility transistors (HEMTs) based on gallium nitride (GaN) are fabricated from GaN epitaxial single-crystal thin films grown on single-crystal substrates. The single-crystal substrate is typically made of materials such as sapphire, silicon carbide (SiC), or silicon (Si). For instance, when the substrate is made of silicon single-crystal material, the resulting HEMT can be called a gallium nitride-on-silicon (GaN-on-Si) HEMT device.

[0094] As shown in Figure 5, the HEMT device 300 in the above-mentioned device is disposed on the substrate 400, and the HEMT device 300 is disposed on the substrate 400 through a first electrical connection structure (e.g., a metal layer) 500 so that the HEMT device 300 can be interconnected with other electronic devices on the substrate 400.

[0095] The substrate 400 is then disposed on the circuit board 100 via the second electrical connection structure 200. For example, the circuit board 100 can be a printed circuit board (PCB), and the second electrical connection structure 200 can be a ball grid array (BGA) or other electrical connection structures.

[0096] The HEMT device 300 shown in Figure 5 can be the structure shown in Figure 6. Figure 6 is a structural diagram of an HEMT device 300, which can be referred to as a semiconductor device. The semiconductor device may include: a substrate 301, a channel layer 303 disposed on the substrate 301, and a barrier layer 305 disposed on the channel layer 303.

[0097] The transistor also includes a gate 310, a source 308, and a drain 309. The source 308 and the drain 309 can both be in ohmic contact with the channel layer 303. For example, the source 308 and the drain 309 pass through the barrier layer 305 and are both in ohmic contact with the channel layer 303.

[0098] In one possible implementation, the substrate 301 may be silicon, silicon carbide, aluminum oxide, GaN, or a composite substrate formed based on the above substrates, and the silicon substrate may be a high-resistivity silicon substrate.

[0099] The channel layer 303 comprises gallium nitride (GaN) material. The barrier layer 305 comprises aluminum gallium nitride (AlGaN) material. For example, a group IIIA nitride barrier layer is disposed on top of the group IIIA nitride channel layer. The group IIIA nitride barrier layer 305 is used to cooperate with the group IIIA nitride channel layer 303 to generate a two-dimensional electron gas (2DEG) through polarization in the region where the group IIIA nitride channel layer 303 and the group IIIA nitride barrier layer 305, thereby providing a channel for conducting current.

[0100] In some embodiments, as shown in FIG6, the transistor may further include a buffer layer 302, which is stacked between the substrate 301 and the channel layer 303. The buffer layer 302 may include a group IIIA nitride, such as AlN or AlGaN. The buffer layer 302 is used to buffer the stress between the substrate 301 and the channel layer 303 and improve the quality of the epitaxial growth of the channel layer 303.

[0101] Referring again to Figure 6, in some implementable embodiments, an insert layer 304 may be provided between the channel layer 303 and the barrier layer 305. In other examples, the insert layer 304 may not be provided between the channel layer 303 and the barrier layer 305.

[0102] In some structures, as shown in Figure 6, a cap layer 306 can also be provided on the barrier layer 305 to protect the device.

[0103] In the example of Figure 6, buffer layer 302, channel layer 303, insertion layer 304, barrier layer 305, and cap layer 306 can be referred to as epitaxial layers; in other examples, some film structures can be added, or some film structures in Figure 6 can be removed. In this semiconductor device, the surface of the epitaxial layer can be referred to as the device surface.

[0104] In this application example, the channel layer 303 is located on the substrate 301, which can be understood as: the channel layer 303 is attached to the surface of the substrate 301, or there are other film layer structures between the substrate 301 and the channel layer 303, such as a buffer layer 302 stacked between the substrate 301 and the channel layer 303. That is to say, the channel layer 303 is located on one side of the substrate 301 or above the substrate 301, that is, the channel layer 303 is located on the substrate 301.

[0105] In this example, the barrier layer 305 is located on the channel layer 303. This can be understood as the barrier layer 305 being attached to the surface of the channel layer 303, or, alternatively, other film structures exist between the barrier layer 305 and the channel layer 303, such as an insert layer 304 stacked between the barrier layer 305 and the channel layer 303. In other words, the barrier layer 305 is located on the side of the channel layer 303 away from the substrate 301, or above the channel layer 303, meaning the barrier layer 305 is located on the channel layer 303.

[0106] In this application example, one layer structure is located on another layer structure, which can be understood as: the other layer structure is directly attached to the surface of a layer structure, or there are other layer structures between the two layer structures.

[0107] Continuing with Figure 6, a passivation layer 307 can also be formed on the surface of the epitaxial layer, for example, by stacking the passivation layer 307 on the cap layer 306. The stress modulation technique using the surface passivation layer can effectively improve the electrical properties of the bulk material or epitaxial layer caused by the strain polarization layer. For example, the passivation layer 307 can effectively enhance the areal density of the two-dimensional electron gas 2DEG, thereby increasing the output power density of the device.

[0108] As the performance requirements for semiconductor devices increase, such as the need to suppress current collapse, some implementations can increase the thickness of the passivation layer 307 to suppress the current collapse effect. However, a thicker passivation layer 307 can cause other defects that affect device performance. For example, higher stress can cause defects such as lattice discontinuities on the device surface, leading to larger surface leakage current and increased power consumption in the off-state. Another example is that higher stress can cause the thinner substrate to warp.

[0109] In order to suppress the current collapse effect of the device without introducing large stress, this application presents some feasible structures, as shown below.

[0110] As shown in Figure 7, Figure 7 is a structural diagram of a semiconductor device according to an embodiment of this application.

[0111] In the example of Figure 7, a first passivation composite layer 311 is included. The first passivation composite layer 311 is located on the barrier layer 305. That is, the first passivation composite layer 311 can be attached to the surface of the barrier layer 305. Alternatively, in Figure 7, the first passivation composite layer 311 is located on the device epitaxial layer, such as being attached to the surface of the cap layer 306.

[0112] In order to effectively suppress the current collapse effect of the device, the thickness of the first passivation composite layer 311 can be increased. As shown in Figure 7, the size of the first passivation composite layer 311 in the Z direction can be increased. In some structures, the thickness of the first passivation composite layer 311 can be from 30 nm to 200 nm.

[0113] As shown in Figure 7, the first passivation composite layer 311 includes a first passivation layer 3111 and a second passivation layer 3112. The first passivation layer 3111 and the second passivation layer 3112 are stacked in the direction from the channel layer 303 to the barrier layer 305. That is, the first passivation layer 3111 is closer to the surface of the epitaxial layer than the second passivation layer 3112, and the second passivation layer 3112 is disposed on the first passivation layer 3111. In one example, the second passivation layer 3112 is attached to the surface of the first passivation layer 3111.

[0114] The stress direction of the first passivation composite layer 311 is the same as the stress direction of the barrier layer 305. For example, when the stress of the barrier layer 305 is normal stress, the stress of the first passivation composite layer 311 is also normal stress; or, for example, when the stress of the barrier layer 305 is tensile stress, the stress of the first passivation composite layer 311 is also tensile stress.

[0115] The stress (directed stress) of the first passivation composite layer 311 can be understood as the sum of the stress (directed stress) of the first passivation layer 3111 and the stress (directed stress) of the second passivation layer 3112.

[0116] In this example, the normal stress can be considered as the stress applied toward the barrier layer 305, and the tensile stress can be considered as the stress away from the barrier layer 305. Alternatively, it can be understood as: compressive stress tends to make the size of an object smaller, while tensile stress tends to make the size of an object larger.

[0117] When the stress direction of the first passivation composite layer 311 is the same as the stress direction of the barrier layer 305, the concentration of two-dimensional electron gas 2DEG can be enhanced, thereby increasing the output power density of the device.

[0118] In this example, the first passivation layer 3111 has stress, which can be from 200 MPa to 500 MPa, and 200 MPa or 500 MPa can be considered as normal stress. The second passivation layer 3112 has stress, which can be from -500 MPa to 400 MPa, where -500 MPa can be considered as tensile stress and 400 MPa can be considered as normal stress.

[0119] This can be understood as follows: the stress direction of the first passivation layer 3111 can be the same as the stress direction of the barrier layer 305; the stress direction of the second passivation layer 3112 can be the same as the stress direction of the barrier layer 305; the stress direction of the second passivation layer 3112 can be opposite to the stress direction of the barrier layer 305; and the stress of the second passivation layer 3112 can be zero. The stress direction of the second passivation layer 3112 can be the same as or opposite to the stress direction of the first passivation layer 3111.

[0120] In some examples, the absolute stress value of the first passivation layer 3111 is greater than that of the second passivation layer 3112. Since the first passivation layer 3111 is closer to the epitaxial layer surface than the second passivation layer 3112, the areal density of the 2DEG in the channel region can be effectively increased by using the first passivation layer 3111 with greater stress, thereby improving the output power density of the device.

[0121] In other examples, the density of the first passivation layer 3111 is greater than that of the second passivation layer 3112. Since the denser first passivation layer 3111 is closer to the epitaxial layer surface than the less dense second passivation layer 3112, the first passivation layer 3111 can generate greater stress. By using the first passivation layer 3111 with greater stress, the areal density of the 2DEG in the channel region can be effectively increased, thereby improving the output power density of the device.

[0122] In some other examples, the absolute stress value of the first passivation layer 3111 is greater than the absolute stress value of the second passivation layer 3112, and the density of the first passivation layer 3111 is greater than the density of the second passivation layer 3112. By using the first passivation layer 3111 with greater stress, the areal density of the 2DEG in the channel region can be further effectively increased, thereby improving the output power density of the device.

[0123] To effectively suppress the current collapse effect of the device, even if the thickness of the first passivation composite layer 311 is relatively large, because the first passivation composite layer of this application is not a single layer structure, but includes a stacked first passivation layer 3111 and a second passivation layer 3112. The second passivation layer 3112 can be a stress adjustment layer. During the preparation process, the first passivation layer 3111 with large stress can be adjusted, so that the stress of the entire passivation layer will not be too large, and thus dangling bonds will not be introduced on the surface of the epitaxial layer, weakening the lattice defects caused by the device surface and suppressing leakage current.

[0124] In addition, in this example, the thickness of the first passivation layer 3111 is less than the thickness of the second passivation layer 3112. Thus, even if the absolute value of the stress in the first passivation layer 3111 is greater than the absolute value of the stress in the second passivation layer 3112, the stress will not be very large because the first passivation layer 3111 is relatively thin, and it will basically not cause lattice defects on the device surface, thereby reducing leakage current.

[0125] Furthermore, since this application includes multiple stacked passivation layers with gradient stress, stress concentration can be avoided, reducing the risk of substrate warping or cracking caused by stress concentration.

[0126] In some examples, the thickness S1 of the first passivation layer 3111 can be from 5 nm to 50 nm. The thickness S2 of the second passivation layer 3112 can be from 30 nm to 150 nm. For example, the thickness S1 of the first passivation layer 3111 can be 30 nm, and the thickness S2 of the second passivation layer 3112 can be 80 nm.

[0127] To enhance the stress regulation effect of the second passivation layer 3112, 1 < S2 / S1 ≤ 10; for example, 1 < S2 / S1 ≤ 5, 1 < S2 / S1 ≤ 3, and 2 < S2 / S1 ≤ 3.

[0128] When the thickness S2 of the second passivation layer 3112 is larger than the thickness S1 of the first passivation layer 3111, the stress of the entire passivation composite layer will increase, thus deteriorating the device performance.

[0129] In some implementations, the material of the first passivation layer 3111 may include at least one of aluminum nitride (AlN), aluminum oxide (Al2O3), silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and aluminum oxynitride (AlON). The material of the second passivation layer 3112 may include at least one of aluminum nitride (AlN), aluminum oxide (Al2O3), silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and aluminum oxynitride (AlON).

[0130] The material of the first passivation layer 3111 can be the same as or different from the material of the second passivation layer 3112.

[0131] The density of the first passivation layer 3111 is greater than the density of the second passivation layer 3112. For example, if the materials of the first passivation layer 3111 and the second passivation layer 3112 are the same, the density of the first passivation layer 3111 can be greater than the density of the second passivation layer 3112. In this way, the absolute value of the stress in the first passivation layer 3111 can be greater than the absolute value of the stress in the second passivation layer 3112.

[0132] In some feasible structures, the refractive index of the first passivation layer 3111 is greater than the refractive index of the second passivation layer 3112. For example, the refractive index of the first passivation layer 3111 is 1.2 to 3.0, or it could be 1.2 to 2.0, or it could be 2.0 to 3.0. The refractive index of the second passivation layer 3112 is 1.0 to 3.0, or it could be 1.0 to 1.2, or it could be 1.0 to 2.0.

[0133] As shown in Figure 8, Figure 8 is a structural diagram of a semiconductor device according to an embodiment of this application.

[0134] In the example of Figure 8, the first passivation layer 3111 includes a stacked multi-layer structure, for example, in Figure 8, the first passivation layer 3111 includes a stacked two-layer structure.

[0135] When the first passivation layer 3111 includes stacked multilayer structures, the stress directions of these multilayer structures can be the same, the absolute values ​​of the stress can be the same, and the materials can be the same.

[0136] In the example of Figure 8, the second passivation layer 3112 includes a stacked multi-layer structure, for example, in Figure 8, the second passivation layer 3112 includes a stacked three-layer structure.

[0137] When the second passivation layer 3112 includes stacked multilayer structures, the stress directions of these multilayer structures can be the same, the absolute values ​​of the stress can be the same, and the materials can be the same.

[0138] In some other implementations, the number of layer structures in the first passivation layer 3111 and the number of layer structures in the second passivation layer 3112 can be the same or different.

[0139] The first passivation layer 3111 can be a single layer, and the second passivation layer 3112 can be multiple stacked layers. Alternatively, the first passivation layer 3111 can be multiple stacked layers, and the second passivation layer 3112 can be a single layer.

[0140] For example, a single passivated structure can be obtained by using the same equipment and adjusting the growth program in one step, or by using different equipment or different programs to grow multiple passivated structures.

[0141] In some fabrication processes, passivation layers can be grown using metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), physical vapor deposition (PVD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD).

[0142] As shown in Figure 9, Figure 9 is a structural diagram of another semiconductor device given in an embodiment of this application.

[0143] In this example, a second passivation composite layer 312 may be provided on the gate 310. The gate 310 has a surface facing away from the substrate 301 and a side surface connected to the surface.

[0144] The second passivation composite layer 312 can be formed on at least a portion of the surface of the gate 310 away from the substrate 301 (e.g., all or part of the surface); or, the second passivation composite layer 312 can be formed on at least a portion of the side surface of the gate 310 (e.g., all or part of the side surface); or, the second passivation composite layer 312 can be formed on at least a portion of the surface of the gate 310 away from the substrate 301 (e.g., all or part of the surface), and also on at least a portion of the side surface of the gate 310 (e.g., all or part of the side surface).

[0145] The stress direction of the second passivation composite layer 312 is the same as that of the barrier layer 305. For example, when the stress of the barrier layer 305 is normal stress, the stress of the second passivation composite layer 312 is also normal stress; or, for example, when the stress of the barrier layer 305 is tensile stress, the stress of the second passivation composite layer 312 is also tensile stress.

[0146] By setting a second passivation composite layer 312 in a semiconductor device and making the stress direction of the second passivation composite layer 312 the same as the stress direction of the barrier layer 305, the areal density of the two-dimensional electron gas 2DEG can be increased, thereby improving the output power density of the device.

[0147] As shown in Figure 9, the second passivation composite layer 312 includes a third passivation layer 3121 and a fourth passivation layer 3122. The third passivation layer 3121 and the fourth passivation layer 3122 are stacked in the direction from the channel layer 303 to the barrier layer 305. That is, the third passivation layer 3121 is closer to the surface of the epitaxial layer than the fourth passivation layer 3122, and the fourth passivation layer 3122 is disposed on the third passivation layer 3121. In one example, the fourth passivation layer 3122 is bonded to the surface of the third passivation layer 3121.

[0148] In this example, the stress direction of the third passivation layer 3121 can be the same as the stress direction of the barrier layer 305; the stress direction of the fourth passivation layer 3122 can be the same as the stress direction of the barrier layer 305; the stress direction of the fourth passivation layer 3122 can be opposite to the stress direction of the barrier layer 305; the stress of the fourth passivation layer 3122 can be zero; the stress direction of the fourth passivation layer 3122 can be the same as the stress direction of the third passivation layer 3121, or it can be opposite.

[0149] In some examples, the absolute stress value of the third passivation layer 3121 is greater than that of the fourth passivation layer 3122. Since the third passivation layer 3121 is closer to the epitaxial layer surface than the fourth passivation layer 3122, the areal density of the 2DEG in the channel region can be effectively increased by using the third passivation layer 3121 with greater stress, thereby improving the output power density of the device.

[0150] For example, the third passivation layer 3121 has stress, which can be from 200 MPa to 500 MPa. 200 MPa or 500 MPa can be regarded as normal stress. The fourth passivation layer 3122 has stress, which can be from -500 MPa to 400 MPa. -500 MPa can be regarded as tensile stress, and 400 MPa can be regarded as normal stress.

[0151] In other examples, the density of the third passivation layer 3121 is greater than that of the fourth passivation layer 3122. Since the denser third passivation layer 3121 is closer to the epitaxial layer surface than the less dense fourth passivation layer 3122, the third passivation layer 3121 can generate greater stress. By using the third passivation layer 3121 with greater stress, the areal density of the 2DEG in the channel region can be effectively increased, thereby improving the output power density of the device.

[0152] In some other examples, the absolute stress value of the third passivation layer 3121 is greater than the absolute stress value of the fourth passivation layer 3122, and the density of the third passivation layer 3121 is greater than the density of the fourth passivation layer 3122. By using the third passivation layer 3121 with greater stress, the areal density of the 2DEG in the channel region can be further effectively increased, thereby improving the output power density of the device.

[0153] In this example, the thickness of the third passivation layer 3121 is greater than the thickness of the fourth passivation layer 3122. Thus, the force exerted on the gate 310 by the thicker third passivation layer 3121 can suppress the parasitic capacitance and resistance of the gate 310, thereby optimizing device performance.

[0154] In some examples, the thickness S3 of the third passivation layer 3121 can be from 50 nm to 300 nm. The thickness S4 of the fourth passivation layer 3122 can be from 30 nm to 100 nm. For example, the thickness S3 of the third passivation layer 3121 can be 150 nm, and the thickness S4 of the fourth passivation layer 3122 can be 50 nm.

[0155] To enhance the parasitic capacitance suppression effect of the third passivation layer 3121 on the gate, 1 < S3 / S4 ≤ 5; for example, 1 < S3 / S4 ≤ 3, or 2 < S3 / S4 ≤ 3, or 2 < S3 / S4 ≤ 4.

[0156] When the thickness S3 of the third passivation layer 3121 is larger than the thickness S4 of the fourth passivation layer 3122, the suppression effect on gate parasitic capacitance and parasitic resistance will be increased or decreased.

[0157] In some implementations, the material of the third passivation layer 3121 may include at least one of: aluminum nitride (AlN), aluminum oxide (Al2O3), silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and aluminum oxynitride (AlON). The material of the fourth passivation layer 3122 may include at least one of: aluminum nitride (AlN), aluminum oxide (Al2O3), silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and aluminum oxynitride (AlON).

[0158] The material of the third passivation layer 3121 can be the same as or different from the material of the fourth passivation layer 3122.

[0159] The density of the third passivation layer 3121 is greater than the density of the fourth passivation layer 3122. For example, if the materials of the third passivation layer 3121 and the fourth passivation layer 3122 are the same, the density of the third passivation layer 3121 can be greater than the density of the fourth passivation layer 3122. In this way, the absolute value of the stress in the third passivation layer 3121 can be greater than the absolute value of the stress in the fourth passivation layer 3122.

[0160] In some feasible structures, the refractive index of the third passivation layer 3121 is greater than that of the fourth passivation layer 3122. For example, the refractive index of the third passivation layer 3121 is 1.2 to 3.0, or it could be 1.2 to 2.0, or it could be 2.0 to 3.0. The refractive index of the fourth passivation layer 3122 is 1.0 to 3.0, or it could be 1.0 to 1.2, or it could be 1.0 to 2.0.

[0161] In some examples, the third passivation layer 3121 can be a single layer or a stacked multilayer structure. When the third passivation layer 3121 includes a stacked multilayer structure, the stress directions of these multilayer structures can be the same, the absolute values ​​of the stress can be the same, and the materials can be the same.

[0162] Similarly, the fourth passivation layer 3122 can be a single layer or a stacked multilayer structure. When the fourth passivation layer 3122 includes a stacked multilayer structure, the stress directions of these multilayer structures can be the same, the absolute values ​​of the stress can be the same, and the materials can be the same.

[0163] Alternatively, the third passivation layer 3121 may include a stacked multilayer structure, and the fourth passivation layer 3122 may be a single-layer structure.

[0164] For example, a single passivated structure can be obtained by using the same equipment and adjusting the growth program in one step, or by using different equipment or different programs to grow multiple passivated structures.

[0165] In some examples, the embodiment shown in FIG9 may further include the first passivation composite layer 311 in the foregoing embodiments. Specifically, as shown in FIG9, a first passivation composite layer 311 is provided between the gate 310 and the barrier layer 305.

[0166] In feasible processes, a first passivation composite layer 311 can be formed on the surface of the epitaxial layer before forming the gate 310, so that the gate 310 has a first passivation composite layer 311 underneath. The first passivation composite layer 311 can suppress the parasitic capacitance and parasitic resistance of the gate 310 and optimize the device performance.

[0167] The semiconductor device in this application example may include only the first passivation composite layer 311, or only the second passivation composite layer 312, or both the first passivation composite layer 311 and the second passivation composite layer 312.

[0168] Continuing with Figure 9, when the semiconductor device includes a first passivation composite layer 311 and a second passivation composite layer 312, the second passivation composite layer 312 can be disposed on the gate 310, and the second passivation composite layer 312 can also extend to the first passivation composite layer 311.

[0169] Thus, the epitaxial layer not only has a first passivation composite layer 311, but also includes a second passivation composite layer 312 disposed on the first passivation composite layer 311. That is, the surface of the epitaxial layer has a first passivation layer 3111, a second passivation layer 3112, a third passivation layer 3121, and a fourth passivation layer 3122 stacked sequentially.

[0170] By stacking a first passivation composite layer 311 and a second passivation composite layer 312 on the epitaxial layer of a semiconductor device, and ensuring that the stress directions of the first passivation composite layer 311 and the second passivation composite layer 312 are the same as the stress direction of the barrier layer 305, the areal density of the two-dimensional electron gas 2DEG can be increased, thereby improving the output power density of the device.

[0171] The stress directions of the first passivation composite layer 311 and the second passivation composite layer 312 are the same as the stress direction of the barrier layer 305. This can be understood as follows: the sum of the stress (including direction) of the first passivation composite layer 311 and the stress (including direction) of the second passivation composite layer 312 is the same as the stress direction of the barrier layer 305.

[0172] When there are at least four passivation layers as illustrated in Figure 9 on the epitaxial layer, the stress of these passivation layers varies, including changes in stress direction or changes in the absolute value of stress.

[0173] For example, the absolute stress value of the first passivation layer 3111 is greater than the absolute stress value of the second passivation layer 3112, the absolute stress value of the third passivation layer 3121 is greater than the absolute stress value of the fourth passivation layer 3122, the absolute stress value of the first passivation layer 3111 is greater than the absolute stress value of the third passivation layer 3121, and the absolute stress value of the second passivation layer 3112 is greater than or equal to the absolute stress value of the fourth passivation layer 3122.

[0174] For example, the absolute stress value F1 of the first passivation layer 3111 and the absolute stress value F3 of the third passivation layer 3121, F1 / F3 ≥ 1.2. For example, F1 / F3 ≥ 1.5, or F1 / F3 ≥ 1.8, or F1 / F3 ≥ 2.

[0175] For another example, the absolute stress value F2 of the second passivation layer 3112 and the absolute stress value F4 of the fourth passivation layer 3122, F2 / F4 ≥ 1.2. For example, F2 / F4 ≥ 1.5, or F2 / F4 ≥ 1.6, or F2 / F4 ≥ 1.8.

[0176] The stress direction of the first passivation layer 3111 is opposite to the stress direction of the second passivation layer 3112, the stress direction of the third passivation layer 3121 is opposite to the stress direction of the second passivation layer 3112, and the stress direction of the fourth passivation layer 3122 is opposite to the stress direction of the third passivation layer 3121. That is, the stress directions of adjacent layers are opposite.

[0177] Because the stress (including direction or absolute value) of these passivation layers varies, even if the sum of the at least four passivation layers is designed to be relatively thick, in order to suppress the device current collapse effect, the stress will not be large, thus weakening the lattice defects on the passivation surface, reducing leakage current, reducing off-state power consumption, and improving the operating performance of the device.

[0178] In the example shown in Figure 9, the thickness of the third passivation layer 3121 is greater than the thickness of the second passivation layer 3112, and the thickness of the fourth passivation layer 3122 is greater than the thickness of the first passivation layer. For example, the second passivation layer 3112 is under tensile stress, and the third passivation layer 3121 is under normal stress. By using two adjacent passivation layers with varying thicknesses, a significant stress concentration phenomenon is unlikely to occur.

[0179] For example, the thickness S3 of the third passivation layer 3121 and the thickness S2 of the second passivation layer 3112 are such that S3 / S2 ≥ 2. For example, S3 / S2 ≥ 2.2, or S3 / S2 ≥ 2.5.

[0180] For another example, the thickness S4 of the fourth passivation layer 3122 and the thickness S1 of the first passivation layer 3111 are such that S4 / S1 ≥ 2. For example, S4 / S1 ≥ 2.2, or S4 / S1 ≥ 2.5, or S4 / S1 ≥ 3.

[0181] As shown in the example in Figure 9, the multilayer passivation layer stacked on the epitaxial layer is designed with varying stress direction, varying absolute stress value, varying thickness, and varying refractive index. This can effectively enhance the areal density of the 2DEG in the channel region of the HEMT device, improve the output power density of the device, and the thicker passivation layer can effectively suppress the current collapse effect of the device. It will basically not cause lattice (dangling bond) defects on the surface of the passivation layer and the epitaxial layer, reduce interface leakage current, reduce off-state power consumption, and also basically not cause stress accumulation, which will cause warping or even cracking of the thinner substrate.

[0182] For example, in some examples, the first passivation layer 3111 is a monolayer silicon nitride (SiNx) layer, grown by plasma-enhanced chemical vapor deposition (PECVD), with a thickness of 30 nm, a refractive index of 2.0, and a stress of 400 MPa; the second passivation layer 3112 is a monolayer silicon nitride (SiNx) layer, grown by PECVD, with a thickness of 80 nm, a refractive index of 1.2, and a stress of 100 MPa; the third passivation layer 3121 is a monolayer silicon nitride (SiNx) layer, grown by PECVD, with a thickness of 150 nm, a refractive index of 2.5, and a stress of 300 MPa; and the fourth passivation layer 3122 is a monolayer silicon nitride (SiNx) layer, grown by PECVD, with a thickness of 50 nm, a refractive index of 1.5, and a stress of -100 MPa. In this example, nm stands for nanometer, and MPa stands for megapascal.

[0183] Referring again to Figure 9, the semiconductor device in this example also includes: a source metal layer 313 and a drain metal layer 314; the source metal layer 313 is electrically connected to the source 308, and the drain metal layer 314 is electrically connected to the drain 309.

[0184] Among them, part of the source metal layer 313 is located in the second passivation layer 3112, and part of it passes through the first passivation layer 3111 and contacts the source 308; part of the drain metal layer 314 is located in the second passivation layer 3112, and part of it passes through the first passivation layer 3111 and contacts the drain 309.

[0185] That is, in Figure 9, the surface and part of the side of the source metal layer 313 facing away from the substrate are covered by the second passivation layer 3112, and the surface and part of the side of the drain metal layer 314 facing away from the substrate are covered by the second passivation layer 3112.

[0186] In some feasible fabrication processes, a first passivation layer 3111 can be formed on the epitaxial layer first, then a source metal layer 313 and a drain metal layer 314 can be formed, and then a second passivation layer 3112 can be formed. In this way, the second passivation layer 3112 can cover the source metal layer 313 and the drain metal layer 314. Thus, when the gate is subsequently etched, the source metal layer 313 and the drain metal layer 314 can be prevented from being contaminated because they are covered and protected by the second passivation layer 3112.

[0187] The structure shown in Figure 9 can be a schematic diagram of the fabrication process. In some semiconductor device fabrication processes, cutting can be performed along the deep groove shown in Figure 9 to obtain a semiconductor device containing active devices, as shown in the dashed box structure in Figure 9.

[0188] In some semiconductor devices, as shown in Figure 10, which is a structural diagram of another semiconductor device according to an example of this application, the semiconductor device includes not only an active device region but also a passive device region. In the active device region, transistors can be integrated, and in the passive device region, electronic devices such as resistors, inductors, or capacitors can be integrated.

[0189] As shown in Figure 10, the first passivation layer 3111, the second passivation layer 3112, the third passivation layer 3121, and the fourth passivation layer 3122 can be disposed in the active device region or the passive device region. For example, disposing of them on a resistor in the passive device region can reduce the parasitic resistance of the resistor, or disposing of them on a capacitor can reduce the parasitic capacitance of the capacitor.

[0190] This application also provides a method for fabricating a semiconductor device, as shown in Figure 11, which is a flowchart of the process for fabricating a semiconductor device.

[0191] S1: A channel layer and a barrier layer are fabricated on a substrate, with the channel layer located on the substrate and the barrier layer located on the channel layer.

[0192] In some processes, a buffer layer can be fabricated on the substrate, and then a channel layer can be fabricated on the buffer layer.

[0193] Before the barrier layer is fabricated, an insertion layer can be fabricated on the channel layer, and then the barrier layer and cap layer can be fabricated sequentially on the insertion layer.

[0194] S21: A first passivation layer and a second passivation layer are formed, wherein the thickness of the first passivation layer is less than the thickness of the second passivation layer, the first passivation layer is located on the barrier layer, the second passivation layer is located on the first passivation layer, the absolute stress value of the first passivation layer is greater than the absolute stress value of the second passivation layer, and / or the density of the first passivation layer is greater than the density of the second passivation layer.

[0195] In some processes, as shown in Figure 11, the preparation method may also include:

[0196] S22: A gate is formed, which is located on the barrier layer; a third passivation layer and a fourth passivation layer are formed, at least a portion of the third passivation layer is located on the gate, the fourth passivation layer is located on the third passivation layer, the absolute stress value of the third passivation layer is greater than the absolute stress value of the fourth passivation layer, and / or the density of the third passivation layer is greater than the density of the fourth passivation layer.

[0197] S21 and S22 can both be included in the fabrication of semiconductor devices, or only one of them can be included.

[0198] When fabricating a semiconductor device, which includes steps S21 and S22, step S21 can be executed first, followed by step S22.

[0199] Based on the above process steps, it can be seen that when preparing a passivation layer on the surface of the epitaxial layer, multiple passivation layers can be prepared by multiple processes. For example, a first passivation layer and a second passivation layer can be prepared by stacking them. The stress and thickness of the multi-layered passivation layers vary. In order to effectively suppress the current collapse effect of the device, even if the thickness of the multi-layered passivation layers is very large, it will not generate large stress, thus reducing stress concentration.

[0200] In addition, by fabricating multiple stacked passivation layers on the gate, the stress of these multi-layered passivation layers varies. This not only effectively suppresses the device current collapse effect, but also reduces the gate parasitic resistance or parasitic capacitance, thereby optimizing device performance.

[0201] Figures 12 to 20 exemplarily illustrate the process structure diagrams after each step of fabricating a semiconductor device is completed.

[0202] As shown in Figure 12, a buffer layer 302, a channel layer 303, an insertion layer 304, a barrier layer 305, and a cap layer 306 can be sequentially fabricated on a substrate 301.

[0203] The buffer layer 302, the channel layer 303, the insertion layer 304, the barrier layer 305, and the cap layer 306 can be referred to as epitaxial layers.

[0204] In some examples, marker etching can be performed on the epitaxial layer to identify active and passive device regions.

[0205] During marking and etching, etching can be performed up to the trench layer 303.

[0206] As shown in Figure 13, a groove is formed in the epitaxial layer. This groove is used for the epitaxial growth of the source electrode 308 and the drain electrode 309. The epitaxial growth of the source electrode 308 and the drain electrode 309 can be referred to as secondary epitaxial growth.

[0207] The source electrode 308 extends to the channel layer 303 and is in ohmic contact with the channel layer 303; the drain electrode 309 extends to the channel layer 303 and is in ohmic contact with the channel layer 303.

[0208] As shown in Figure 14, a first passivation layer 3111 is formed on the surface of the epitaxial layer. For example, the first passivation layer 3111 covers the cap layer 306, the source 308 and the drain 309; or, the first passivation layer 3111 covers the passive devices in the passive device region.

[0209] The stress direction of the first passivation layer 3111 is the same as the stress direction of the barrier layer 305. For example, if the barrier layer 305 is under normal stress, then the first passivation layer 3111 is under normal stress.

[0210] In some processes, a first passivation layer 3111 can be prepared using PECVD technology. The first passivation layer 3111 has a thickness of 30 nm, a refractive index of 2, and a stress of 400 MPa.

[0211] As shown in Figure 15, a source metal layer 313 and a drain metal layer 314 are fabricated. The source metal layer 313 passes through the first passivation layer 3111 and contacts the source 308. The drain metal layer 314 passes through the first passivation layer 3111 and contacts the drain 309.

[0212] As shown in Figure 16, a second passivation layer 3112 is formed on the first passivation layer 3111. The second passivation layer 3112 covers the source metal layer 313 and drain metal layer 314 formed above.

[0213] In some processes, the second passivation layer 3112 can be made using the same material as the first passivation layer 3111, for example, SiN.

[0214] The stress direction of the second passivation layer 3112 can be the same as or opposite to the stress direction of the first passivation layer 3111.

[0215] In some processes, a second passivation layer 3112 can be prepared using PECVD technology. The second passivation layer 3112 has a thickness of 80 nm, a refractive index of 1.2, and a stress of 100 MPa.

[0216] As shown in Figure 17, a gate trench is etched to accommodate the gate.

[0217] A gate trench is etched between the source metal layer 313 and the drain metal layer 314. The gate trench can extend through the second passivation layer 3112 and the first passivation layer 3111 to the surface of the epitaxial layer. For example, the gate trench can extend to the surface of the cap layer, or it can extend to the barrier layer.

[0218] As shown in Figure 18, the gate 310 is fabricated in the gate trench.

[0219] In some feasible processes, as shown in Figure 18, the gate dielectric layer 315 can be formed first, and then the gate 310 can be fabricated.

[0220] As shown in Figure 19, the third passivation layer 3121 is prepared.

[0221] The third passivation layer 3121 covers the side and surface of the gate 310, and the third passivation layer 3121 covers the second passivation layer 3112. Thus, the first passivation layer 3111, the second passivation layer 3112 and the third passivation layer 3121 are stacked on the epitaxial layer, and the gate 310 has the third passivation layer 3121.

[0222] Since the third passivation layer 3121 is fabricated in a single process, the third passivation layer 3121 covering the epitaxial layer and the third passivation layer 3121 on the gate 310 are integrally formed structures.

[0223] The stress direction of the third passivation layer 3121 is the same as the stress direction of the barrier layer 305. For example, if the barrier layer 305 is under normal stress, then the first passivation layer 3111 is under normal stress.

[0224] In some processes, a third passivation layer 3121 can be prepared using PECVD technology. This third passivation layer 3121 has a thickness of 150 nm, a refractive index of 2.5, and a stress of 300 MPa.

[0225] As shown in Figure 20, a fourth passivation layer 3122 is formed on the third passivation layer 3121.

[0226] The stress direction of the fourth passivation layer 3122 can be opposite to or the same as the stress direction of the third passivation layer 3121.

[0227] In some processes, a fourth passivation layer 3122 can be prepared using PECVD technology. This fourth passivation layer 3122 has a thickness of 50 nm, a refractive index of 1.5, and a stress of -100 MPa.

[0228] After obtaining the structure shown in Figure 20, the source and drain can be brought out using a front-mount back-side process, that is, an electrical connection structure is set on the back side of the substrate to bring out the source and drain. Alternatively, the source and drain can be brought out using a flip-chip back-end process, that is, interconnect lines are set on the front side of the substrate to bring out the source and drain.

[0229] The semiconductor devices fabricated using Figures 12 to 20 contain multiple passivation layers with varying absolute stress values, which optimizes lattice defects on the device surface and reduces stress concentration.

[0230] In the description of this specification, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0231] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: Substrate; The channel layer is located on the substrate; A barrier layer is located on the channel layer; as well as The semiconductor device further includes a first passivation composite layer, and / or the semiconductor device further includes a gate and a second passivation composite layer; Wherein, the first passivation composite layer is located on the barrier layer, and the first passivation composite layer includes: a first passivation layer and a second passivation layer; from the channel layer to the barrier layer, the first passivation layer and the second passivation layer are stacked, and the thickness of the first passivation layer is less than the thickness of the second passivation layer. The absolute stress value of the first passivation layer is greater than the absolute stress value of the second passivation layer, and / or the density of the first passivation layer is greater than the density of the second passivation layer; At least a portion of the second passivation composite layer is located on the gate, and the second passivation composite layer includes: a third passivation layer and a fourth passivation layer; the third passivation layer and the fourth passivation layer are stacked in a direction from the channel layer to the barrier layer; The absolute stress value of the third passivation layer is greater than the absolute stress value of the fourth passivation layer, and / or the density of the third passivation layer is greater than the density of the fourth passivation layer.

2. The semiconductor device according to claim 1, characterized in that, The thickness of the third passivation layer is greater than the thickness of the fourth passivation layer.

3. The semiconductor device according to claim 1 or 2, characterized in that, In the case where the semiconductor device includes the first passivation composite layer, the gate, and the second passivation composite layer; At least a portion of the second passivation composite layer is located on the first passivation composite layer.

4. The semiconductor device according to claim 3, characterized in that, At least a portion of the sidewalls of the gate and at least a portion of the surface facing away from the barrier layer are covered by the second passivation composite layer, and the second passivation composite layer covering the gate extends onto the first passivation composite layer.

5. The semiconductor device according to claim 3 or 4, characterized in that, The first passivation composite layer is present between the gate and the barrier layer.

6. The semiconductor device according to any one of claims 3-5, characterized in that, The thickness of the third passivation layer is greater than the thickness of the second passivation layer.

7. The semiconductor device according to claim 6, characterized in that, The thickness of the third passivation layer is S3, the thickness of the second passivation layer is S2, and S3 / S2≥2.

8. The semiconductor device according to any one of claims 3-7, characterized in that, The thickness of the fourth passivation layer is greater than the thickness of the first passivation layer.

9. The semiconductor device according to claim 8, characterized in that, The thickness of the fourth passivation layer is S4, the thickness of the first passivation layer is S1, and S4 / S1≥2.

10. The semiconductor device according to any one of claims 3-9, characterized in that, The absolute stress value of the first passivation layer is greater than the absolute stress value of the third passivation layer.

11. The semiconductor device according to claim 10, characterized in that, The absolute stress value of the first passivation layer is F1, the absolute stress value of the third passivation layer is F3, and F1 / F3 ≥ 1.

2.

12. The semiconductor device according to any one of claims 3-11, characterized in that, The absolute stress value of the second passivation layer is greater than or equal to the absolute stress value of the fourth passivation layer.

13. The semiconductor device according to claim 12, characterized in that, The absolute stress value of the second passivation layer is F2, the absolute stress value of the fourth passivation layer is F4, and F2 / F4 ≥ 1.

2.

14. The semiconductor device according to any one of claims 1-13, characterized in that, The thickness of the first passivation layer is S1, the thickness of the second passivation layer is S2, and 1 < S2 / S1 ≤ 10.

15. The semiconductor device according to any one of claims 1-14, characterized in that, The thickness of the third passivation layer is S3, the thickness of the fourth passivation layer is S4, and 1 < S3 / S4 ≤ 5.

16. The semiconductor device according to any one of claims 1-15, characterized in that, The first passivation layer, the second passivation layer, the third passivation layer, or the fourth passivation layer are all single-layer structures, or... The first passivation layer, the second passivation layer, the third passivation layer, or the fourth passivation layer comprises a stacked multilayer structure, wherein the absolute stress values ​​of adjacent layers in the multilayer structure are the same, and the materials of the multilayer structure are the same.

17. The semiconductor device according to any one of claims 1-16, characterized in that, The material of the first passivation layer is the same as the material of the second passivation layer; and / or The material of the third passivation layer is the same as that of the fourth passivation layer.

18. The semiconductor device according to any one of claims 1-17, characterized in that, The semiconductor device further includes: Source and drain; Source metal layer and drain metal layer; The source electrode penetrates the barrier layer and extends into the channel layer, and the drain electrode penetrates the barrier layer and extends into the channel layer; A portion of the source metal layer is located in the second passivation layer, and a portion passes through the first passivation layer to contact the source electrode; A portion of the drain metal layer is located in the second passivation layer, and a portion extends through the first passivation layer to contact the drain electrode.

19. An electronic device, characterized in that, include: Radio frequency front-end circuit, the radio frequency front-end circuit including a power amplifier; The power amplifier includes a semiconductor device as described in any one of claims 1-18.

20. A method for fabricating a semiconductor device, characterized in that, The preparation method includes: A channel layer and a barrier layer are fabricated on a substrate, wherein the channel layer is located on the substrate and the barrier layer is located on the channel layer; and The preparation method further includes: obtaining a first passivation layer and a second passivation layer, and / or obtaining a gate, a third passivation layer, and a fourth passivation layer. The thickness of the first passivation layer is less than the thickness of the second passivation layer, and the first passivation layer is located on the barrier layer. The second passivation layer is located on the first passivation layer, the absolute stress value of the first passivation layer is greater than the absolute stress value of the second passivation layer, and / or the density of the first passivation layer is greater than the density of the second passivation layer; The gate is located on the barrier layer, at least a portion of the third passivation layer is located on the gate, the fourth passivation layer is located on the third passivation layer, the absolute stress value of the third passivation layer is greater than the absolute stress value of the fourth passivation layer, and / or the density of the third passivation layer is greater than the density of the fourth passivation layer.

21. The preparation method according to claim 20, characterized in that, The preparation of the third passivation layer and the fourth passivation layer includes: The third passivation layer is formed on at least a portion of the side surface of the gate and at least a portion of the surface facing away from the barrier layer, and the third passivation layer is formed on the second passivation layer; The fourth passivation layer is formed on the third passivation layer on the gate, and the fourth passivation layer is formed on the third passivation layer on the second passivation layer.

22. The preparation method according to claim 20 or 21, characterized in that, The material of the first passivation layer is the same as the material of the second passivation layer; and / or The material of the third passivation layer is the same as that of the fourth passivation layer.

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