Chip packaging structure, radio frequency front-end module and electronic device

Abstract

The present application relates to the technical field of packaging, and in particular to a chip packaging structure. By providing a first connection point in a first region of an isolation layer (40) adjacent to a first gap, and setting the relationship between a length D of a first line segment formed by extending the first connection point at a 45-degree direction to intersect two points on a contour line of the first region of the isolation layer (40) and a height Hg1 of the first gap, the effect of the isolation layer (40) on cavity formation is more directly reflected. In addition, with respect to a thickness parameter of the isolation layer (40), the reliability, miniaturization, and costs of the entire packaging structure can be more accurately optimized and adjusted.

Description

A chip packaging structure, a radio frequency front-end module, and an electronic device.

[0001] This application is based on and claims priority to Chinese Patent Application No. 2024119952984, filed on December 31, 2024, entitled "A Chip Packaging Structure, Radio Frequency Front-End Module and Electronic Device". Technical Field

[0002] This application belongs to the field of packaging technology, and in particular relates to a chip packaging structure, a radio frequency front-end module, and an electronic device. Background Technology

[0003] With the rapid development of information technology, the technical requirements of the semiconductor industry are increasing. As the core of this technology, the importance of chips is becoming increasingly prominent. In the packaging process of certain special-function chips, a cavity structure needs to be formed between the chip and the substrate to meet functional, performance, or special requirements. Examples include surface acoustic wave (SAW) filter chips and bulk acoustic wave (BAW) filter chips. These filter chips play a crucial role in the radio frequency (RF) field. For users, the demands for integration and miniaturization are constantly challenging product design and layout, especially in the mobile terminal field. Particularly in the 5G era, the demand for filter chips in the RF front-end of mobile terminals has increased dramatically. Therefore, ensuring the reliability of these increasingly demanding chips in packaging design has become an urgent problem to be solved.

[0004] Application content

[0005] This application solves the technical problem of low chip reliability in the prior art and provides a chip packaging structure and method.

[0006] In a first aspect, embodiments of this application provide a chip packaging structure, including:

[0007] The substrate has a first pad on its first surface;

[0008] A protective layer is disposed on the first surface of the substrate;

[0009] A first packaged chip is disposed on a first surface of the substrate, and a first gap is formed between the bottom surface of the first packaged chip and the protective layer, with the bottom surface of the first packaged chip facing the first surface.

[0010] A first interconnect bump is disposed on the bottom surface of the first packaged chip, and the first interconnect bump is connected to the first pad.

[0011] An isolation layer covers the first packaged chip and the protective layer. The isolation layer includes a first region adjacent to the first gap. A first connection point exists within the first region. A first line segment is formed by two points extending from the first connection point at a 45-degree angle to the outline of the first region of the isolation layer. The length D of the first line segment is equal to the height H of the first gap. g1 The following relationship must be satisfied: D≥H g1 .

[0012] Secondly, embodiments of this application provide a chip packaging structure, including:

[0013] The substrate has a first pad on its first surface;

[0014] A protective layer is disposed on the first surface of the substrate;

[0015] A first packaged chip is disposed on a first surface of the substrate, and a first gap is formed between the bottom surface of the first packaged chip and the protective layer, with the bottom surface of the first packaged chip facing the first surface.

[0016] A first interconnect bump is disposed on the bottom surface of the first packaged chip. The first interconnect bump is connected to the first pad. The first interconnect bump forms a first projection pattern on the substrate along the longitudinal direction. In the first projection pattern, the longest line segment that passes through the center point of the first projection pattern and extends to both sides of the first projection pattern is greater than the height of the first interconnect bump.

[0017] An isolation layer covers the first packaged chip and the protective layer.

[0018] Thirdly, embodiments of this application provide a radio frequency front-end module, including:

[0019] The substrate has a first pad disposed on its first surface;

[0020] A protective layer is disposed on the first surface of the substrate;

[0021] A first packaged chip is disposed on a first surface of the substrate, and a first gap is formed between the bottom surface of the first packaged chip and the protective layer, with the bottom surface of the first packaged chip facing the first surface.

[0022] A first interconnect bump is disposed on the bottom surface of the first packaged chip, and the first interconnect bump is connected to the first pad.

[0023] An isolation layer covers the first packaged chip and the protective layer. The isolation layer includes a first portion disposed on the protective layer. A first point and a second point are present on the bottom side of the first packaged chip. The thickness of the first portion corresponding to the first point is less than the height of the first gap, and the thickness of the first portion corresponding to the second point is greater than the height of the first gap.

[0024] Fourthly, embodiments of this application provide a radio frequency front-end module, including:

[0025] The substrate has a first pad and a second pad on its first surface.

[0026] A protective layer is disposed on the first surface of the substrate;

[0027] A first packaged chip is disposed on a first surface of the substrate, and a first interconnect bump is disposed on the bottom surface of the first packaged chip. The first interconnect bump is connected to the first pad. A first gap is formed between the bottom surface of the first packaged chip and the protective layer. The bottom surface of the first packaged chip is opposite to the first surface.

[0028] A second packaged chip is disposed on the first surface of the substrate, and a second interconnection bump is disposed on the bottom surface of the second packaged chip. The second interconnection bump is connected to the second pad. A second gap is formed between the bottom surface of the second packaged chip and the first surface of the substrate. The bottom surface of the second packaged chip is opposite to the first surface.

[0029] An isolation layer covers the first packaged chip, the protective layer, and part of the second packaged chip;

[0030] The first interconnect bump forms a first projection pattern on the substrate along the longitudinal direction. In the first projection pattern, the longest line segment that passes through the center point of the first projection pattern and extends to both sides of the first projection pattern is greater than the height of the first interconnect bump. The height of the first interconnect bump is less than the height of the second interconnect bump.

[0031] A sealing layer covers the protective layer, the first packaged chip, and the second packaged chip, and at least partially fills the second gap.

[0032] Fifthly, embodiments of this application provide a radio frequency front-end module, including:

[0033] The substrate has a first pad and a second pad on its first surface.

[0034] A protective layer is disposed on the first surface of the substrate;

[0035] A first packaged chip is disposed on a first surface of the substrate, and a first interconnect bump is disposed on the bottom surface of the first packaged chip. The first interconnect bump is connected to the first pad. A first gap is formed between the bottom surface of the packaged chip and the protective layer. The bottom surface of the packaged chip is opposite to the first surface.

[0036] A second packaged chip is disposed on the first surface of the substrate, and a second interconnection bump is disposed on the bottom surface of the second packaged chip. The second interconnection bump is connected to the second pad. A second gap is formed between the bottom surface of the packaged chip and the first surface of the substrate. The bottom surface of the second packaged chip is opposite to the first surface.

[0037] The first interconnect bump forms a first projection pattern on the substrate along the longitudinal direction, and the second interconnect bump forms a second projection pattern on the substrate along the longitudinal direction. The area of ​​the first projection pattern is larger than the area of ​​the second projection pattern, and the height of the first interconnect bump is smaller than the height of the second interconnect bump.

[0038] An isolation layer covers the first packaged chip, the first surface of the substrate, and a portion of the second packaged chip;

[0039] A sealing layer covers the protective layer, the first packaged chip, and the second packaged chip, and at least partially fills the space between the second packaged chip and the substrate.

[0040] Sixthly, embodiments of this application provide a radio frequency front-end module, including:

[0041] The substrate has a first pad and a second pad on its first surface.

[0042] A protective layer is disposed on the first surface of the substrate;

[0043] A first packaged chip is disposed on a first surface of the substrate, and a first interconnect bump is disposed on the bottom surface of the first packaged chip. The first interconnect bump is connected to the first pad. A first gap is formed between the bottom surface of the packaged chip and the protective layer. The bottom surface of the packaged chip is opposite to the first surface.

[0044] A second packaged chip is disposed on the first surface of the substrate, and a second interconnection bump is disposed on the bottom surface of the second packaged chip. The second interconnection bump is connected to the second pad. A second gap is formed between the bottom surface of the packaged chip and the first surface of the substrate. The bottom surface of the second packaged chip is opposite to the first surface.

[0045] An isolation layer covers the first packaged chip and the first surface of the substrate;

[0046] A sealing layer covers the protective layer, the first packaged chip, and the second packaged chip;

[0047] The isolation layer also covers the second packaged chip and has openings formed on at least two and at most three sides of the second packaged chip, so that the sealing layer at least partially fills the space between the second packaged chip and the substrate.

[0048] Seventhly, embodiments of this application provide a radio frequency front-end module, including:

[0049] The substrate has a first pad, a second pad, and a third pad disposed on its first surface;

[0050] A protective layer is disposed on the first surface of the substrate;

[0051] A first packaged chip is disposed on a first surface of the substrate, and a first interconnect bump is disposed on the bottom surface of the first packaged chip. The first interconnect bump is connected to the first pad. A first gap is formed between the bottom surface of the packaged chip and the protective layer. The bottom surface of the first packaged chip is opposite to the first surface.

[0052] A second packaged chip is disposed on the first surface of the substrate, and a second interconnection bump is disposed on the bottom surface of the second packaged chip. The second interconnection bump is connected to the second pad. A second gap is formed between the bottom surface of the packaged chip and the first surface of the substrate. The bottom surface of the second packaged chip is opposite to the first surface.

[0053] A third packaged chip is disposed on the first surface of the substrate, and a third interconnection bump is disposed on the bottom surface of the third packaged chip. The third interconnection bump is connected to the third pad. A third gap is formed between the bottom surface of the packaged chip and the protective layer. The bottom surface of the third packaged chip is opposite to the first surface.

[0054] An isolation layer covers the first packaged chip, the third packaged chip, and a portion of the second packaged chip. The isolation layer includes a first portion disposed on a protective layer near the first packaged chip and a fourth portion disposed on a protective layer near the third packaged chip. The thickness of the first portion is less than the height of the first gap, and the thickness of the fourth portion is greater than the height of the third gap.

[0055] Eighthly, embodiments of this application provide an electronic device, including the above-described chip packaging structure, or including the above-described radio frequency front-end module.

[0056] In the chip packaging structure, RF front-end module, and electronic device provided in this application embodiment, by setting a first region, the length D of the first line segment and the height H of the first gap are formed by two points extending from the first connection point at a 45-degree angle to the outline of the first region of the isolation layer. g1 Relationship ， It more directly reflects the influence of the isolation layer on cavity formation, and compared with the thickness parameter of the isolation layer, it can more accurately optimize and adjust the reliability, miniaturization and cost of the overall packaging structure. Attached Figure Description

[0057] The present application will be further described below with reference to the accompanying drawings and embodiments.

[0058] Figure 1 is a schematic diagram of the chip packaging structure or radio frequency front-end module in one embodiment of this application;

[0059] Figure 2 is a schematic diagram of the chip packaging structure or radio frequency front-end module in another embodiment of this application;

[0060] Figure 3 is a schematic diagram of the chip packaging structure or radio frequency front-end module in another embodiment of this application;

[0061] Figure 4 is a schematic diagram of the chip packaging structure or radio frequency front-end module in another embodiment of this application;

[0062] Figure 5 is a schematic diagram of the chip packaging structure or radio frequency front-end module in another embodiment of this application;

[0063] Figure 6 is a schematic diagram of the chip packaging structure or radio frequency front-end module in another embodiment of this application;

[0064] Figure 7 is a schematic diagram of the chip packaging structure or radio frequency front-end module in another embodiment of this application;

[0065] Figure 8 is a schematic diagram of the chip packaging structure or radio frequency front-end module in another embodiment of this application;

[0066] Figure 9 is a schematic diagram of the chip packaging structure or radio frequency front-end module in another embodiment of this application;

[0067] Figure 10 is a schematic diagram of the chip packaging structure or radio frequency front-end module in another embodiment of this application;

[0068] Figure 11 is a schematic diagram of the chip packaging structure or radio frequency front-end module in another embodiment of this application;

[0069] Figure 12 is a schematic diagram of the chip packaging structure or radio frequency front-end module in another embodiment of this application;

[0070] The reference numerals in the drawings in the specification are as follows: 10, substrate; 11, first surface; 12, first pad; 13, second pad; 14, third pad; 20, protective layer; 30, first package chip; 31, first connection bump; 32, first functional area; 40, isolation layer; 50, sealing layer; 60, second package chip; 61, second interconnect bump; 70, third package chip; 71, third interconnect bump. Detailed Implementation

[0071] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0072] It should be understood that this application can be implemented in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of this application to those skilled in the art. In the drawings, for clarity, the dimensions of layers and regions, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0073] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this application, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0074] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0075] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0076] To fully understand this application, detailed structures and steps will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0077] One embodiment of this application provides a chip packaging structure, including:

[0078] The substrate has a first pad on its first surface;

[0079] A protective layer is disposed on the first surface of the substrate;

[0080] A first packaged chip is disposed on a first surface of the substrate, and a first gap is formed between the bottom surface of the first packaged chip and the protective layer, with the bottom surface of the first packaged chip facing the first surface.

[0081] A first interconnect bump is disposed on the bottom surface of the first packaged chip, and the first interconnect bump is connected to the first pad.

[0082] An isolation layer covers the first packaged chip and the protective layer. The isolation layer includes a first region adjacent to the first gap. A first connection point exists within the first region. A first line segment is formed by two points extending from the first connection point at a 45-degree angle to the outline of the first region of the isolation layer. The length D of the first line segment is equal to the height H of the first gap. g1 The following relationship must be satisfied: D≥H g1 .

[0083] In this embodiment, as shown in Figures 1 and 2, a first pad 12 is provided on the first surface 11 of the substrate 10. The first pad 12 on the first surface 11 can be disposed on the first surface 11 of the substrate (i.e., protruding from the first surface 11), or the first pad 12 can be embedded in the first surface (as shown in Figure 1), or the first pad 12 can be partially embedded in the first surface and another part protruding from the first surface 11 (as shown in Figure 2), or other feasible pad placement methods, which are not specifically limited here. Figure 1 shows an example of the first pad 12 being embedded in the first surface 11.

[0084] In at least one embodiment, the number of the first pads 12 is two or more. Optionally, the number of the first pads 12 is the same as the number of the first interconnect bumps 31. Exemplarily, the bottom surface of the first package chip 30 includes a plurality of first interconnect bumps 31, wherein each first interconnect bump 31 is connected to a first pad 12 on the first surface of the substrate 10.

[0085] A protective layer 20 is formed on a first surface of the substrate 10. In at least one embodiment, the protective layer 20 is formed using a dielectric material. In one embodiment, the protective layer 20 may also be a solder resist layer, which may be formed using a solder resist material. In this embodiment, the protective layer 20 is a solder resist layer formed on the first surface 11 of the substrate 10. By using a solder resist layer on the substrate as the protective layer, the formation of additional layers is reduced, thus reducing the consumption of additional materials and processes.

[0086] Understandably, the protective layer 20 is provided with an opening. For example, an opening is provided at the corresponding position of the first pad 12 to allow interconnection between the first interconnect bump 31 of the first package chip 30 and the first pad 12.

[0087] In at least one embodiment, the protective layer 20 has a first opening, and the first packaged chip 30 forms a third projected pattern on the substrate along the longitudinal direction. The main body of the third projected pattern is located in the first opening, and the outer periphery of the third projected pattern overlaps with the longitudinal projection of the protective layer 20. Understandably, in this embodiment, the first interconnect bump 31 also forms a first projected pattern on the substrate along the longitudinal direction, which is also located in the first opening. Understandably, the longitudinal direction in this application embodiment is a relative concept; it does not mean absolutely vertical or overhanging, and a slightly inclined direction is also permissible. Taking Figure 1 as an example, the longitudinal direction here can refer to the thickness direction in the chip package structure (e.g., the thickness direction of the substrate).

[0088] In at least one embodiment, the protective layer 20 is provided with a second opening, and the first interconnect bump 31 forms a first projected pattern on the substrate along the longitudinal direction, the first projected pattern being located in the second opening. It is understood that the number of second openings can be the same as the number of first interconnect bumps, so that the first projected pattern formed by each first interconnect bump is located in one second opening.

[0089] The first packaged chip 30 is disposed on the first surface 11 of the substrate 10, and the bottom surface of the first packaged chip 30 forms a first gap with the protective layer 20, with the bottom surface of the first packaged chip 30 facing the first surface 11.

[0090] A first interconnect bump 31 is disposed on the bottom surface of the first package chip 30, and the first interconnect bump 31 is connected to the first pad 12. It is understood that the bottom surface of the first package chip 30 includes at least two first interconnect bumps 31. In at least one embodiment, each first interconnect bump 31 may be connected to a first pad 12 on the first surface of the substrate.

[0091] In at least one embodiment, the first packaged chip further includes a first functional area, as shown in Figures 1 and 2. The first packaged chip 30 includes a first functional area 32, in which wiring patterns, devices, etc., of the first packaged chip are disposed. For example, if the first packaged chip is a SAW filter chip, the first functional area is provided with electrode finger patterns, wiring patterns, etc., of the SAW filter. A fifth projection pattern is formed on the substrate along the longitudinal direction of the first functional area. Optionally, the fifth projection pattern is located in the first opening. Optionally, the fifth projection pattern at least partially overlaps with the protective layer.

[0092] An isolation layer 40 covers the first packaged chip 30 and the protective layer 20. The isolation layer is a dielectric material. Optionally, the material of the isolation layer 40 can be an epoxy resin film, or a dry film, or other polymer films or other resin materials. In at least one embodiment, the isolation layer 40 can be a material that has a certain degree of ductility at high temperatures but poor fluidity and does not become liquid at high temperatures, so that the isolation layer 40 can better cover surfaces of various shapes and play a better barrier role.

[0093] The thickness of the isolation layer 40 can be greater than 20 micrometers, for example, the thickness of the isolation layer 40 can be 40 micrometers, 70 micrometers, 80 micrometers, 100 micrometers, etc., or the thickness of the isolation layer can be greater than or equal to 40 micrometers, 70 micrometers, 80 micrometers, 100 micrometers, etc.; it can also be less than or equal to 20 micrometers, for example, the thickness of the isolation layer 40 can be 18 micrometers, 15 micrometers, 10 micrometers, etc., or the thickness of the isolation layer can be less than or equal to 18 micrometers, 15 micrometers, 10 micrometers, etc.

[0094] In at least one embodiment, the isolation layer includes a first region adjacent to the first gap, the first region having a first connection point, and a first line segment formed by two points of the first connection point extending at a 45-degree angle to the outline of the first region of the isolation layer, the first connection point causing the trajectory line of the isolation layer on the side away from the first gap to intersect the first line segment at only one point.

[0095] Wherein, the length D of the first line segment and the height H of the first gap g1 The following relationship must be satisfied: D≥H g1 .

[0096] The first region is a region of the isolation layer near the first gap. For example, the first region can be the portion of the isolation layer within a rectangle formed by extending a certain distance horizontally away from the first gap from the bottom edge of the first gap and extending a certain distance vertically away from the first gap from the bottom edge of the first gap. Optionally, this first distance can be 10µm, 20µm, 30µm, 40µm, etc. As shown in Figure 3, in the first region of the isolation layer near the first gap, there is a first connection point, such that two points extending at a 45-degree angle from the first connection point intersect with the outline of the first region of the isolation layer to form a first line segment L. x Understandably, among the nodes outside the first connection point of the first region, there may be more than two or fewer than two intersection points extending at a 45-degree angle with the outline of the first region of the isolation layer.

[0097] In related technologies, an isolation layer is used to prevent subsequent sealing layers from entering the space / gap between the first packaged chip and the first surface of the substrate, thus forming a cavity in the first packaged chip. However, in actual manufacturing processes, improper control of the isolation layer thickness can lead to its cracking if it is too thin, failing to prevent subsequent sealing layers from entering the space / gap between the first packaged chip and the first surface of the substrate. Conversely, an excessively thick isolation layer can hinder the miniaturization of the overall package structure and increase costs.

[0098] The applicant discovered that related technologies primarily adjust the thickness of the isolation layer. However, in actual manufacturing processes, the thickness of the isolation layer changes due to compression, and different parts of the isolation layer also have different thicknesses. Therefore, setting the thickness parameter of the isolation layer cannot directly and effectively improve the formation of the cavity. Thus, this application's embodiment limits the relevant parameters of the first region of the isolation layer adjacent to the first gap. Specifically, it sets the length D of the first line segment formed by the intersection of two points extending at a 45-degree angle from the first connection point with the outline of the first region of the isolation layer, and the height H of the first gap. g1 Relationship ， It more directly reflects the influence of the isolation layer on cavity formation, and compared with the thickness parameter of the isolation layer, it can more accurately optimize and adjust the reliability, miniaturization and cost of the overall packaging structure.

[0099] In at least one embodiment, the isolation layer includes a first portion disposed on the protective layer, and a first point and a second point are located on the bottom side of the first packaged chip. The thickness of the first portion corresponding to the location of the first point is less than the height of the first gap, and the thickness of the first portion corresponding to the location of the second point is greater than the height of the first gap. By limiting the different thicknesses of the first point and the second point on the bottom side of the first packaged chip, the reliability of the chip package structure is better ensured.

[0100] In this embodiment, the isolation layer includes a first portion disposed on the protective layer. A first point and a second point are present on the bottom side of the first packaged chip 30, exemplarily, as shown in FIG. 4, a first point A and a second point B are located on the bottom side of the first packaged chip 30. It is understood that the first point A and the second point B may be on the same side of the first packaged chip 30 or on different sides of the first packaged chip 30. In at least one embodiment, the first point and the second point are disposed on adjacent sides of the first packaged chip, exemplarily, as shown in FIG. 4, a first point A and a second point B are disposed on adjacent sides of the first packaged chip. In at least one embodiment, the first point and the second point are disposed on opposite sides of the first packaged chip. In at least one embodiment, the first point and the second point are disposed on the same side of the first packaged chip.

[0101] Figure 5 shows a cross-sectional view of the first point A. As shown in Figure 5, the thickness H of the first portion corresponding to the first point A is... p1 The height H is less than the height of the first gap. g1 The isolation layer includes a first portion disposed on the protective layer. Understandably, the first portion can be a portion of the isolation layer extending horizontally along the protective layer. Optionally, the horizontal direction can be perpendicular to the longitudinal direction. Optionally, the thickness of the first portion corresponding to position A can be obtained by averaging the thickness values ​​taken from different positions within the first portion corresponding to position A, i.e., the thickness of the first portion is the average thickness. Optionally, the thickness of the first portion corresponding to position A can be the average thickness of the first portion extending horizontally away from the first package chip from the first point. This certain distance can be 20µm, 30µm, 40µm, 50µm, or 60µm, etc. Specifically, a cross-sectional view can be taken at the first point A, and the average thickness of the first portion extending horizontally away from the first package chip from the first point A can be calculated.

[0102] Figure 6 shows a cross-sectional view of the second point B. As shown in Figure 6, the thickness H of the first portion corresponding to the first point B is... p2 The height H greater than the first gap g1The isolation layer includes a first portion disposed on the protective layer. Understandably, the first portion can be a portion of the isolation layer extending horizontally on the protective layer. The horizontal direction can be perpendicular to the longitudinal direction. Optionally, the thickness of the first portion can be obtained by averaging the thickness values ​​taken at different locations within the first portion, resulting in an average thickness for the entire first portion. Optionally, the thickness of the first portion can be the average thickness of the first portion extending horizontally away from the first package chip from a first point. This certain distance can be 20µm, 30µm, 40µm, 50µm, or 60µm, etc. Specifically, a cross-sectional view at a second point B can be taken, and the average thickness of the first portion extending horizontally away from the first package chip from the second point B can be calculated.

[0103] In at least one embodiment, a first device and a second device are further included. The first device is disposed adjacent to the side where the first point is located, and the second device is disposed adjacent to the side where the second point is located. The distance between the first device and the first packaged chip is smaller than the distance between the second device and the first packaged chip. The first point and the second point are disposed on the bottom of different sides of the first packaged chip.

[0104] The first device can be a chip or component, for example, a filter chip, an RF low-noise amplifier chip, an RF switch chip, an RF power amplifier chip, or an analog control chip, or a capacitor, inductor, or resistor. The second device can also be a chip or component, for example, a filter chip, an RF low-noise amplifier chip, an RF switch chip, an RF power amplifier chip, or an analog control chip, or a capacitor, inductor, or resistor. By adjusting the distance between the first device, the second device, and the first packaged chip, the thickness of the first portion corresponding to the first point is less than the height of the first gap, and the thickness of the first portion corresponding to the second point is greater than the height of the first gap, thus avoiding additional complex manufacturing processes.

[0105] In at least one embodiment, this application provides a radio frequency front-end module, including:

[0106] The substrate has a first pad disposed on its first surface;

[0107] A protective layer is disposed on the first surface of the substrate;

[0108] A first packaged chip is disposed on a first surface of the substrate, and a first gap is formed between the bottom surface of the first packaged chip and the protective layer, with the bottom surface of the first packaged chip facing the first surface.

[0109] A first interconnect bump is disposed on the bottom surface of the first packaged chip, and the first interconnect bump is connected to the first pad.

[0110] An isolation layer covers the first packaged chip and the protective layer. The isolation layer includes a first portion disposed on the protective layer. A first point and a second point are located on the bottom side of the first packaged chip. The first point and the second point are disposed on the bottom of different sides of the first packaged chip. The thickness of the first portion corresponding to the position of the first point is less than the thickness of the first portion corresponding to the position of the second point.

[0111] The first device is disposed on the side adjacent to the location of the first point;

[0112] The second device is disposed on the side adjacent to the second point, and the distance between the first device and the first packaged chip is less than the distance between the second device and the first packaged chip.

[0113] In this embodiment, by adjusting the distance between the first device, the second device, and the first packaged chip, the thickness of the first part corresponding to the first point position is less than the thickness of the first part corresponding to the second point position, thus ensuring overall reliability without the need for additional complex processes.

[0114] In at least one embodiment, in the first packaged chip, the number of first points whose thickness is less than the height of the first gap is at least three. Further, the spacing between each of the at least three first points is greater than 5 μm.

[0115] In at least one embodiment, in the first packaged chip, the thickness of the first portion corresponding to the side where the first point is located is less than the height of the first gap. In at least one embodiment, in the first packaged chip, the thickness of the first portion corresponding to the side where the second point is located is greater than the height of the first gap.

[0116] In at least one embodiment, in the first packaged chip, the number of second points corresponding to the thickness of the first portion being greater than the height of the first gap is at least three. Further, the spacing between each of the at least three second points is greater than 5 μm.

[0117] In at least one embodiment, the first interconnect bump forms a first projection pattern on the substrate along the longitudinal direction, wherein the longest line segment passing through the center point of the first projection pattern and extending to both sides of the first projection pattern is greater than the height of the first interconnect bump.

[0118] As shown in Figure 1, the longest line segment L1 of the first interconnecting bump 31 that passes through the center point of the first projected pattern and extends to both sides of the first projected pattern is greater than the height H of the first interconnecting bump. e .

[0119] Understandably, the first projected pattern formed by the first interconnect bump on the substrate can be of any form. It can be a regular pattern or an irregular pattern.

[0120] For example, as shown in FIG7, the first interconnect bump 31 forms a first projected pattern on the substrate, which is elliptical. In this first projected pattern, the longest line segment L1 passing through the center point of the first projected pattern and extending to both sides of the first projected pattern is greater than the height H of the first interconnect bump. e .

[0121] For example, as shown in FIG8, a first interconnect bump 31 forms a first projected pattern on the substrate. In the first projected pattern shown in FIG8, the longest line segment L1 passing through the center point of the first projected pattern and extending to both sides of the first projected pattern is greater than the height H of the first interconnect bump. e .

[0122] The height H of the first interconnect bump e H is the height of the first interconnect bump itself. The longitudinal distance between the top surface of the first pad and the first surface of the substrate is H. f Understandably, if the first pad 12 is disposed on the first surface 11 of the substrate (i.e., protruding from the first surface 11, as shown in Figure 2), then H f If the first pad is embedded in the first surface and its top surface is flush with the first surface, then H is a positive value. f It is 0.

[0123] In at least one embodiment, as shown in FIG2, the distance H between the bottom surface of the first packaged chip and the first surface of the substrate is... c equals H e With H f The sum of, i.e., H c =H e +H f .

[0124] In this embodiment, by limiting the longest line segment in the first projection pattern that passes through the center point of the first projection pattern and extends to both sides of the first projection pattern to be greater than the height of the first interconnecting bump, the reliability of the first interconnecting bump can be guaranteed, and the possibility of cracking of the first interconnecting bump due to the presence of cavities can be reduced.

[0125] In at least one embodiment, the longest line segment is greater than 1.5 times the height of the first interconnect bump. In at least one embodiment, the longest line segment is greater than 1.8 times the height of the first interconnect bump. In at least one embodiment, the longest line segment is greater than 2 times the height of the first interconnect bump.

[0126] In at least one embodiment, the longest line segment is less than four times the height of the first interconnect bump.

[0127] In at least one embodiment, the first interconnect bump forms a first projection pattern on the substrate, wherein the shortest line segment passing through the center point of the first projection pattern and extending to both sides of the first projection pattern is greater than the height of the first interconnect bump.

[0128] In at least one embodiment, the first interconnect bump forms a first projected pattern on the substrate. In the first projected pattern, a longest line segment L1 extends through the center point of the first projected pattern to both sides, and a shortest line segment L2 extends through the center point of the first projected pattern to both sides. The average value of the longest line segment L1 and the shortest line segment L2 is greater than the height of the first interconnect bump. By limiting the average value of the longest line segment L1 and the shortest line segment L2, the possibility of the first interconnect bump cracking due to the presence of cavities is better reduced.

[0129] In at least one embodiment, the average value of the longest line segment L1 and the shortest line segment L2 is greater than 1.3 times the height of the first interconnect bump. In at least one embodiment, the average value of the longest line segment L1 and the shortest line segment L2 is greater than 1.5 times the height of the first interconnect bump. In at least one embodiment, the average value of the longest line segment L1 and the shortest line segment L2 is greater than 1.8 times the height of the first interconnect bump. In at least one embodiment, the average value of the longest line segment L1 and the shortest line segment L2 is greater than 2 times the height of the first interconnect bump.

[0130] In at least one embodiment, the average value of the longest line segment L1 and the shortest line segment L2 is less than four times the height of the first interconnect bump.

[0131] In at least one embodiment, the length D of the first line segment and the height H of the first gap are... g1 The following relationship must be satisfied: D≤2H g1 .

[0132] In at least one embodiment, the length D of the first line segment and the height H of the first gap are... g1 The following relationship must be satisfied: D≤1.5H g1 .

[0133] By limiting the upper limit of the length of the first segment, reliability, miniaturization of the overall packaging structure, and cost can be balanced.

[0134] In at least one embodiment, in the first region, a first set of line segments is formed by two points extending from the first connection point in a [40, 50] degree direction and intersecting with the outline of the first region of the isolation layer. The length of each line segment in the first set of line segments is greater than the height H of the first gap. g1 .

[0135] A first set of line segments is formed by intersecting two points extending from the first connection point at an angle of [40, 50] degrees with the outline of the first region of the isolation layer. The length of each line segment in the first set of line segments is greater than the height H of the first gap. g1 This can better ensure the formation of the cavity.

[0136] In at least one embodiment, the first pad protrudes from the substrate, and the height H of the first gap is... g1 and the thickness H of the protective layer s Satisfy: 2H g1 <H s .

[0137] In this embodiment, as shown in FIG2, the first pad 12 protrudes from the substrate, that is, the longitudinal distance H between the top surface of the first pad and the first surface of the substrate is... f It is a positive value. In this embodiment, the height H of the first gap is set. g1 and the thickness H of the protective layer s Satisfy: 2H g1 <H s The thickness of the protective layer is set to be thicker than that of the first gap to avoid the height H of the first gap. g1 Too high a height is not conducive to the formation of cavities.

[0138] In at least one embodiment, the first pad is embedded in the substrate, and the height H of the first gap is... g1 and the thickness H of the protective layer s Satisfies: 1.5Hg1 <H s ≤2H g1 .

[0139] In this embodiment, the first pad is embedded in the substrate. Referring to FIG1 as an example, the top surface of the first pad is flush with the first surface. In this embodiment, the height H of the first gap is set... g1 and the thickness H of the protective layer s Satisfy: 1.5H g1 <H s ≤2H g1 This better ensures the stability of cavity formation.

[0140] In at least one embodiment, the first pad is embedded in the substrate, and the height H of the first gap is... g1 and the thickness H of the protective layer s Satisfy: 1.5H g1 <H s <2H g1 .

[0141] In at least one embodiment, the thickness H of the isolation layer p and the height H of the first gap g1 Satisfying the following relationship: 1um <H g1 -H p ≤10um.

[0142] In at least one embodiment, in the first projected pattern, the longest line segment passing through the center point of the first projected pattern and extending to both sides of the first projected pattern is greater than 80 μm. Optionally, the longest line segment passing through the center point of the first projected pattern and extending to both sides of the first projected pattern is less than 150 μm.

[0143] In at least one embodiment, in the first projected pattern, the shortest line segment passing through the center point of the first projected pattern and extending to both sides of the first projected pattern is greater than 70 μm. Optionally, the longest line segment passing through the center point of the first projected pattern and extending to both sides of the first projected pattern is less than 150 μm.

[0144] In at least one embodiment, the area of ​​the first projected pattern is greater than 900 μm. 2 By limiting the area of ​​the overall projected pattern, the reliability of the first interconnect bump is ensured, and the possibility of cracking of the first interconnect bump due to the presence of cavities is reduced.

[0145] In at least one embodiment, the chip package structure further includes a sealing layer that covers at least the protective layer and the isolation layer. As shown in FIG1, the chip package structure further includes a sealing layer 50. The sealing layer 50 covers the protective layer 20 and the isolation layer 40. In at least one embodiment, the sealing layer also covers a portion of the first surface of the substrate.

[0146] The sealing layer can be made of insulating resin material or other encapsulating material. Optionally, the sealing layer is a resin material containing particulate matter. This particulate matter can be silicon dioxide (SiO2) particles or aluminum oxide (Al2O3) particles; this embodiment is not limited thereto. Understandably, other materials capable of achieving a sealing function can also be used, which will not be elaborated upon here.

[0147] In at least one embodiment, the thickness of the isolation layer is less than the height of the first gap.

[0148] In this embodiment, the thickness of the isolation layer is less than the height of the first gap. Understandably, the thickness of the isolation layer may vary in different parts during the manufacturing process. In this embodiment, the thickness of the isolation layer can be obtained by averaging the thickness values ​​of different regions of the isolation layer as the overall thickness of the isolation layer.

[0149] In at least one embodiment, the isolation layer includes a first portion disposed on the protective layer, the thickness of the first portion being less than the height of the first gap.

[0150] As shown in Figure 1, the isolation layer includes a first portion disposed on the protective layer. It can be understood that the first portion is a portion of the isolation layer extending horizontally on the protective layer. The horizontal direction may be perpendicular to the longitudinal direction. The thickness of the first portion can be obtained by averaging the thickness values ​​taken at different locations within the first portion.

[0151] By setting the thickness of the first part to be less than the height of the first gap, the isolation layer can be set more easily, thus better ensuring the formation of the cavity.

[0152] In at least one embodiment, the isolation layer further includes a second portion disposed on the side of the first packaged chip and a third portion disposed on the top surface of the packaged chip;

[0153] The thickness of the second part is less than the thickness of the third part, and / or the thickness of the second part is less than the thickness of the first part.

[0154] In this embodiment, as shown in Figures 1-2, the isolation layer further includes a second portion disposed on the side of the first packaged chip and a third portion disposed on the top surface of the packaged chip. Understandably, the second portion extends longitudinally along the first packaged chip, and the third portion extends horizontally on the top surface of the packaged chip. The thickness of the second portion can be obtained by averaging the thickness values ​​taken at different locations within the second portion. Similarly, the thickness of the third portion can be obtained by averaging the thickness values ​​taken at different locations within the third portion.

[0155] In at least one embodiment, the thickness of the second portion is less than the height of the first gap. In some embodiments, simply setting the thickness of the second portion to be less than the height of the first gap can better ensure the formation of the cavity.

[0156] In at least one embodiment, the thickness of the third portion is less than the height of the first gap. In some embodiments, simply setting the thickness of the third portion to be less than the height of the first gap can better ensure the formation of the cavity.

[0157] In at least one embodiment, the storage modulus of the isolation layer at 150 degrees Celsius is greater than or equal to 3 MPa. Optionally, the storage modulus of the isolation layer at 150 degrees Celsius is greater than or equal to 4 MPa. Exemplarily, the isolation layer can be selected from materials such as epoxy resin, silicone grease, PI film, etc., that satisfy the above condition (storage modulus greater than or equal to 3 MPa at 150 degrees Celsius), and this condition can be satisfied by adjusting its specific parameters, materials, etc.

[0158] In at least one embodiment, the storage modulus of the isolation layer at 150 degrees Celsius is greater than or equal to 4 MPa, and the thickness of the isolation layer is less than or equal to 20 micrometers. Further, the thickness of the isolation layer 40 can be less than or equal to 18 micrometers, less than or equal to 15 micrometers, or less than or equal to 10 micrometers, etc.

[0159] In at least one embodiment, the first packaged chip is a surface acoustic wave filter chip.

[0160] In at least one embodiment, the isolation layer at least partially fills the first gap. Partially filling the first gap with the isolation layer better prevents the isolation layer from being punctured by subsequent sealing layers, thus improving the reliability of the overall packaging structure.

[0161] At least one embodiment of this application provides a chip packaging structure, including:

[0162] The substrate has a first pad on its first surface;

[0163] A protective layer is disposed on the first surface of the substrate;

[0164] A first packaged chip is disposed on a first surface of the substrate, and a first gap is formed between the bottom surface of the first packaged chip and the protective layer, with the bottom surface of the first packaged chip facing the first surface.

[0165] A first interconnect bump is disposed on the bottom surface of the first packaged chip. The first interconnect bump is connected to the first pad. The first interconnect bump forms a first projection pattern on the substrate along the longitudinal direction. In the first projection pattern, the longest line segment that passes through the center point of the first projection pattern and extends to both sides of the first projection pattern is greater than the height of the first interconnect bump.

[0166] An isolation layer covers the first packaged chip and the protective layer.

[0167] In this embodiment, by limiting the longest line segment that passes through the center point of the first projection pattern and extends to both sides of the first projection pattern to be greater than the height of the first interconnecting bump, the reliability of the first interconnecting bump can be guaranteed, and the possibility of cracking of the first interconnecting bump due to the presence of cavities can be reduced.

[0168] At least one embodiment of this application provides a chip packaging structure, including:

[0169] The substrate has a first pad on its first surface;

[0170] A protective layer is disposed on the first surface of the substrate;

[0171] A first packaged chip is disposed on a first surface of the substrate, and a first gap is formed between the bottom surface of the first packaged chip and the protective layer, with the bottom surface of the first packaged chip facing the first surface.

[0172] A first interconnect bump is disposed on the bottom surface of the first packaged chip, and the first interconnect bump is connected to the first pad.

[0173] An isolation layer covers the first packaged chip and the protective layer. The isolation layer includes a first portion disposed on the protective layer. A first point and a second point are present on the bottom side of the first packaged chip. The thickness of the first portion corresponding to the first point is less than the height of the first gap, and the thickness of the first portion corresponding to the second point is greater than the height of the first gap.

[0174] In this embodiment, by limiting the different thicknesses of the first point and the second point on the bottom side of the first packaged chip, the reliability of the chip package structure is better guaranteed.

[0175] At least one embodiment of this application provides a radio frequency front-end module, including:

[0176] The substrate has a first pad and a second pad on its first surface.

[0177] A protective layer is disposed on the first surface of the substrate;

[0178] A first packaged chip is disposed on a first surface of the substrate, and a first interconnect bump is disposed on the bottom surface of the first packaged chip. The first interconnect bump is connected to the first pad. A first gap is formed between the bottom surface of the first packaged chip and the protective layer. The bottom surface of the first packaged chip is opposite to the first surface.

[0179] A second packaged chip is disposed on the first surface of the substrate, and a second interconnection bump is disposed on the bottom surface of the second packaged chip. The second interconnection bump is connected to the second pad. A second gap is formed between the bottom surface of the second packaged chip and the first surface of the substrate. The bottom surface of the second packaged chip is opposite to the first surface.

[0180] An isolation layer covers the first packaged chip, the protective layer, and part of the second packaged chip;

[0181] The first interconnect bump forms a first projection pattern on the substrate along the longitudinal direction. In the first projection pattern, the longest line segment that passes through the center point of the first projection pattern and extends to both sides of the first projection pattern is greater than the height of the first interconnect bump. The height of the first interconnect bump is less than the height of the second interconnect bump.

[0182] A sealing layer covers the protective layer, the first packaged chip, and the second packaged chip, and at least partially fills the second gap.

[0183] In this embodiment, taking FIG9 as an example, the first surface 11 of the substrate 10 is provided with a first pad 12 and a second pad 13. The first pad 12 disposed on the first surface 11 can be disposed on the first surface 11 of the substrate (i.e., protruding from the first surface 11), or the first pad 12 can be embedded in the first surface (as shown in FIG9), or the first pad 12 can be partially embedded in the first surface and the other part protruding from the first surface 11, or other feasible pad placement methods, which are not specifically limited here. FIG4 shows an example of the first pad 12 being disposed on the first surface 11. The second pad 13 disposed on the first surface 11 can be disposed on the first surface 11 of the substrate (i.e., protruding from the first surface 11), or the second pad 13 can be embedded in the first surface (as shown in FIG9), or the second pad 13 can be partially embedded in the first surface and the other part protruding from the first surface 11, or other feasible pad placement methods, which are not specifically limited here. FIG9 shows an example of the second pad 13 being disposed on the first surface 11.

[0184] In at least one embodiment, the number of the first pads 12 is two or more. Optionally, the number of the first pads 12 is the same as the number of the first interconnect bumps 31. Exemplarily, the bottom surface of the first package chip 30 includes a plurality of first interconnect bumps 31, wherein each first interconnect bump 31 is connected to a first pad 12 on the first surface of the substrate 10.

[0185] In at least one embodiment, the number of the second pads 13 is two or more. Optionally, the number of the second pads 13 is the same as the number of the second interconnect bumps 61. Exemplarily, the bottom surface of the first package chip 30 includes a plurality of second interconnect bumps 61, wherein each second interconnect bump 61 is connected to a second pad 13 on the first surface of the substrate 10.

[0186] A protective layer 20 is formed on a first surface of the substrate 10. In at least one embodiment, the protective layer 20 is formed using a dielectric material. In one embodiment, the protective layer 20 may also be a solder resist layer, which may be formed using a solder resist material. In this embodiment, the protective layer 20 is a solder resist layer formed on the first surface 11 of the substrate 10. By using a solder resist layer on the substrate as the protective layer, the formation of additional layers is reduced, thus reducing the consumption of additional materials and processes.

[0187] Understandably, the protective layer 20 is provided with an opening. For example, an opening is provided at the corresponding position of the first pad 12 to allow interconnection between the first interconnect bump 31 of the first package chip 30 and the first pad 12.

[0188] In at least one embodiment, the protective layer 20 has a first opening, and the first packaged chip 30 forms a third projected pattern on the substrate along the longitudinal direction. The main body of the third projected pattern is located in the first opening, and the outer periphery of the third projected pattern overlaps with the protective layer 20. It can be understood that in this embodiment, the first interconnect bump forming the first projected pattern on the substrate along the longitudinal direction is also located in the first opening.

[0189] In at least one embodiment, the protective layer 20 is provided with a second opening, and the first interconnect bump forms a first projected pattern on the substrate along the longitudinal direction, the first projected pattern being located in the second opening. It is understood that the number of second openings can be the same as the number of first interconnect bumps, so that the first projected pattern formed by each first interconnect bump is located in one second opening.

[0190] In at least one embodiment, the protective layer 20 is provided with a third opening, and the second package chip 60 forms a fourth projected pattern on the substrate along the longitudinal direction, the fourth projected pattern being located within the first opening. It can be understood that in this embodiment, the second interconnect bump forming a second projected pattern on the substrate along the longitudinal direction is also located within the three openings.

[0191] In at least one embodiment, the protective layer 20 is provided with a fourth opening, and the second interconnect bump forms a second projection pattern on the substrate along the longitudinal direction, the second projection pattern being located in the fourth opening. It is understood that the number of fourth openings can be the same as the number of second interconnect bumps, so that the first projection pattern formed by each second interconnect bump is located in one fourth opening.

[0192] In at least one embodiment, the protective layer has a first opening and a third opening. In at least one embodiment, the protective layer has a first opening and a fourth opening. In at least one embodiment, the protective layer has a second opening and a third opening. In at least one embodiment, the protective layer has a second opening and a fourth opening.

[0193] As shown in Figure 9, a first packaged chip 30 is disposed on a first surface 11 of the substrate 10, and a first interconnect bump 31 is disposed on the bottom surface of the first packaged chip. The first interconnect bump 31 is connected to the first pad 12. A first gap is formed between the bottom surface of the first packaged chip and the protective layer. The bottom surface of the first packaged chip is opposite to the first surface.

[0194] In at least one embodiment, the first packaged chip 30 is a chip that requires a cavity to exist between itself and the first surface of the substrate. Exemplarily, the first packaged chip is a filter chip. Optionally, the first packaged chip is a SAW filter chip, or the first packaged chip is a BAW filter chip.

[0195] A second packaged chip is disposed on the first surface of the substrate, and a second interconnect bump is disposed on the bottom surface of the second packaged chip. The second interconnect bump is connected to the second pad. A second gap is formed between the bottom surface of the second packaged chip and the first surface of the substrate. The bottom surface of the second packaged chip is opposite to the first surface.

[0196] As shown in Figure 9, a second pad 13 is provided on the first surface 11 of the substrate 10. The second pad 13 provided on the first surface 11 can be provided on the first surface 11 of the substrate (i.e., protruding from the first surface 11), or the second pad 13 can be embedded in the first surface (as shown in Figure 4), or the second pad 13 can be partially embedded in the first surface and another part protruding from the first surface 11, or other feasible pad configurations, which are not specifically limited here. Figure 4 shows the second pad 13 embedded in the first surface as an example.

[0197] In at least one embodiment, the number of the second pads 13 is two or more. Optionally, the number of the second pads 13 is the same as the number of the second interconnect bumps 61. Exemplarily, the bottom surface of the second package chip 60 includes a plurality of second interconnect bumps 61, wherein each second interconnect bump 61 is connected to a second pad 13 on the first surface of the substrate 10.

[0198] A second gap is formed between the bottom surface of the second packaged chip and the first surface of the substrate, as shown in Figure 9. The second gap H g2 It is the straight-line distance between the bottom surface of the second packaged chip and the first surface of the substrate.

[0199] In at least one embodiment, the second packaged chip is a chip that does not require a cavity between itself and the first surface of the substrate. Exemplarily, the second packaged chip is a non-filter chip. Optionally, the second packaged chip may include at least one of a radio frequency low-noise amplifier, a radio frequency switch, a radio frequency power amplifier, or an analog control circuit. Optionally, the second packaged chip may be a radio frequency low-noise amplifier chip, a radio frequency switch chip, a radio frequency power amplifier chip, or an analog control chip.

[0200] In at least one embodiment, the height of the second interconnect bump is less than three times the height of the first interconnect bump. In at least one embodiment, the height of the second interconnect bump is less than 2.5 times the height of the first interconnect bump. In at least one embodiment, the height of the second interconnect bump is less than twice the height of the first interconnect bump.

[0201] The RF front-end module also includes an isolation layer, as shown in FIG9. The isolation layer 40 covers the first packaged chip 30, the protective layer 20, and a portion of the second packaged chip 60. Wherein, the isolation layer 40 covering a portion of the second packaged chip 60 means that the isolation layer 40 does not completely cover the second packaged chip 60 (exemplarily, having an opening), so that the subsequent sealing layer 50 or other materials can at least partially fill the space between the second packaged chip 60 and the first surface of the substrate.

[0202] Specifically, the isolation layer 40 may cover the top surface of the second packaged chip 60 (opposite to the bottom surface of the second packaged chip 60), and it is understood that the isolation layer 40 may cover at least a portion of the top surface of the second packaged chip 60. In at least one embodiment, the isolation layer 40 also covers at least a portion of the side surfaces of the second packaged chip 60.

[0203] In at least one embodiment, the isolation layer 40 may initially completely cover the second packaged chip 60, but in subsequent processes / flows, the sealing layer 50 may penetrate the isolation layer in some areas and at least partially fill the space / gap between the second packaged chip 60 and the first surface of the substrate. It is understood that additional processes / flows may also be used to create openings in some areas for the sealing layer 50 to at least partially fill the space / gap between the second packaged chip 60 and the first surface of the substrate.

[0204] The RF front-end module also includes a sealing layer 50, as shown in FIG9. The sealing layer 50 covers the protective layer 20, the first packaged chip 30 and the second packaged chip 60, and at least partially fills the second gap.

[0205] As shown in Figure 9, it can be understood that the sealing layer 50 can enter through a pre-drilled opening in the isolation layer near the second packaged chip and at least partially fill the second gap, or the sealing layer 50 can break through a portion of the isolation layer area near the second packaged chip during the process and enter through this broken area and at least partially fill the second gap.

[0206] In at least one embodiment, the first interconnect bump forms a first projected pattern on the substrate along the longitudinal direction. In the first projected pattern, the longest line segment passing through the center point of the first projected pattern and extending to both sides of the first projected pattern is greater than the height of the first interconnect bump, and the height of the first interconnect bump is less than the height of the second interconnect bump. In this embodiment, by setting the longest line segment in the first projected pattern to pass through the center point of the first projected pattern and extending to both sides of the first projected pattern to be greater than the height of the first interconnect bump, the first interconnect bump can have stronger reliability when there is a cavity in the first packaged chip, reducing the possibility of cracking of the first interconnect bump due to the presence of a cavity. Furthermore, setting the height of the first interconnect bump to be less than the height of the second interconnect bump further ensures that the sealing layer can better fill the space between the second packaged chip and the substrate, reducing the obstruction of the subsequent sealing layer by the second interconnect bump, and better filling the space between the second packaged chip and the substrate, reducing the presence of gaps.

[0207] In at least one embodiment, the first interconnect bump forms a first projected pattern on the substrate along the longitudinal direction, and the second interconnect bump forms a second projected pattern on the substrate along the longitudinal direction. The area of ​​the first projected pattern is larger than the area of ​​the second projected pattern, and the height of the first interconnect bump is smaller than the height of the second interconnect bump. Figure 10 shows an example of the first projected pattern of the first interconnect bump 31 and the second projected pattern of the second interconnect bump 61. The area of ​​the first projected pattern is larger than the area of ​​the second projected pattern. As shown in Figure 9, the height H of the first interconnect bump... h1 The height H of the second interconnect bump is less than h2 In this embodiment, by setting the area of ​​the first projected pattern to be larger than the area of ​​the second projected pattern, the reliability of the first packaged chip is further ensured and the possibility of subsequent cracking is reduced, especially when cavities exist in the first packaged chip. Furthermore, setting the height of the first interconnect bump to be smaller than the height of the second interconnect bump further ensures that the sealing layer can better fill the space between the second packaged chip and the substrate. Therefore, setting the area of ​​the second projected pattern to be smaller than the area of ​​the first projected pattern reduces the obstruction of the subsequent sealing layer by the second interconnect bump, allowing the sealing layer to better fill the space between the second packaged chip and the substrate, reducing the presence of gaps.

[0208] In at least one embodiment, the thickness of the isolation layer is less than the height of the first gap, and the height of the first gap is less than the height of the second gap.

[0209] In this embodiment, by limiting the thickness of the isolation layer to be less than the height of the first gap, and the height of the first gap to be less than the height of the second gap, the smaller isolation layer thickness can balance reliability and miniaturization.

[0210] In at least one embodiment, the vertical distance between the second packaged chip and the protective layer is H. a The lateral distance between at least one side of the second packaged chip and the protective layer is H. b And satisfy: H a >H b This design allows the subsequent sealing layer to more easily break through the isolation layer near the second packaged chip, thus filling the space between the second packaged chip and the substrate.

[0211] In at least one embodiment, the vertical distance between the second packaged chip and the protective layer is H. a The lateral distance between at least one side of the second packaged chip and the protective layer is H. b And satisfy: By setting This allows for a suitable spacing between the second package chip and the protective layer, including both longitudinal and lateral dimensions, thereby making it easier for the subsequent sealing layer to penetrate the isolation layer surrounding the second package chip, so as to better fill the second gap formed between the bottom surface of the second package chip and the first surface of the substrate.

[0212] In at least one embodiment, the straight-line distance between any point on the bottom side of the second packaged chip and the protective layer is H. d In the second packaged chip, at least 20% of the H content is located on the bottom side. d The height is greater than the height of the first gap. This is achieved by limiting at least 20% of H... d The height is greater than the first gap, which better ensures that the space between the second package chip and the substrate is filled and that gaps are less likely to be left.

[0213] In at least one embodiment, the straight-line distance between any point on the bottom side of the second packaged chip and the protective layer is H. d In the second packaged chip, at least 50% of the H is located on the bottom side. d It is greater than the height of the first gap.

[0214] In at least one embodiment, the first interconnect bump forms a first projection pattern on the substrate along the longitudinal direction, and the second interconnect bump forms a second projection pattern on the substrate along the longitudinal direction. The longest line segment passing through the center point of the first projection pattern and extending to both sides of the first projection pattern is greater than the longest line segment passing through the center point of the second projection pattern and extending to both sides of the second projection pattern.

[0215] In this embodiment, by setting the longest line segment that passes through the center point of the first projection pattern and extends to both sides of the first projection pattern to be greater than the longest line segment that passes through the center point of the second projection pattern and extends to both sides of the second projection pattern, both reliability and miniaturization of the overall packaging structure are taken into account when there is a cavity in the first packaged chip and the space between the second packaged chip and the substrate is filled by the sealing layer.

[0216] In at least one embodiment, the first interconnect bump forms a first projection pattern on the substrate along the longitudinal direction, and the second interconnect bump forms a second projection pattern on the substrate along the longitudinal direction. The shortest line segment passing through the center point of the first projection pattern and extending to both sides of the first projection pattern is greater than the shortest line segment passing through the center point of the second projection pattern and extending to both sides of the second projection pattern.

[0217] In this embodiment, by setting the shortest line segment passing through the center point of the first projection pattern and extending to both sides of the first projection pattern to be greater than the shortest line segment passing through the center point of the second projection pattern and extending to both sides of the second projection pattern, both reliability and miniaturization of the overall packaging structure are taken into account when there is a cavity in the first packaged chip and the space between the second packaged chip and the substrate is filled by the sealing layer.

[0218] In at least one embodiment, the first packaged chip is a filter chip, and the second packaged chip is a non-filter chip.

[0219] In at least one embodiment, the insulating layer covers the second packaged chip and has openings formed on at least two sides of the second packaged chip, so that the sealing layer at least partially fills the space between the second packaged chip and the substrate. By defining openings on at least two sides, it better ensures that the space between the second packaged chip and the substrate is filled, and gaps are less likely to be left.

[0220] In at least one embodiment, the insulating layer covers the second packaged chip and has openings formed on up to three sides of the second packaged chip, so that the sealing layer at least partially fills the space between the second packaged chip and the substrate. By limiting the openings to up to three sides, it better ensures that the space between the second packaged chip and the substrate is filled, making it less likely to leave gaps and avoiding overfilling, which would increase the risk of additional stress.

[0221] In at least one embodiment, the distance between the bottom surface of the second packaged chip and the substrate is greater than the distance between the bottom surface of the first packaged chip and the substrate, and the longitudinal distance between the bottom surface of the second packaged chip and the bottom surface of the first packaged chip is greater than 10 μm.

[0222] At least one embodiment of this application provides a radio frequency front-end module, including:

[0223] The substrate has a first pad and a second pad on its first surface.

[0224] A protective layer is disposed on the first surface of the substrate;

[0225] A first packaged chip is disposed on a first surface of the substrate, and a first interconnect bump is disposed on the bottom surface of the first packaged chip. The first interconnect bump is connected to the first pad. A first gap is formed between the bottom surface of the packaged chip and the protective layer. The bottom surface of the packaged chip is opposite to the first surface.

[0226] A second packaged chip is disposed on the first surface of the substrate, and a second interconnection bump is disposed on the bottom surface of the second packaged chip. The second interconnection bump is connected to the second pad. A second gap is formed between the bottom surface of the packaged chip and the first surface of the substrate. The bottom surface of the second packaged chip is opposite to the first surface.

[0227] The first interconnect bump forms a first projection pattern on the substrate, and the second interconnect bump forms a second projection pattern on the substrate. The area of ​​the first projection pattern is larger than the area of ​​the second projection pattern, and the height of the first interconnect bump is smaller than the height of the second interconnect bump.

[0228] An isolation layer covers the first packaged chip, the first surface of the substrate, and a portion of the second packaged chip;

[0229] A sealing layer covers the protective layer, the first packaged chip, and the second packaged chip, and at least partially fills the space between the second packaged chip and the substrate.

[0230] At least one embodiment of this application provides a radio frequency front-end module, including:

[0231] The substrate has a first pad and a second pad on its first surface.

[0232] A protective layer is disposed on the first surface of the substrate;

[0233] A first packaged chip is disposed on a first surface of the substrate, and a first interconnect bump is disposed on the bottom surface of the first packaged chip. The first interconnect bump is connected to the first pad. A first gap is formed between the bottom surface of the packaged chip and the protective layer. The bottom surface of the packaged chip is opposite to the first surface.

[0234] A second packaged chip is disposed on the first surface of the substrate, and a second interconnection bump is disposed on the bottom surface of the second packaged chip. The second interconnection bump is connected to the second pad. A second gap is formed between the bottom surface of the packaged chip and the first surface of the substrate. The bottom surface of the second packaged chip is opposite to the first surface.

[0235] An isolation layer covers the first packaged chip and the first surface of the substrate;

[0236] A sealing layer covers the protective layer, the first packaged chip, and the second packaged chip;

[0237] The isolation layer also covers the second packaged chip and has openings formed on at least two and at most three sides of the second packaged chip, so that the sealing layer at least partially fills the space between the second packaged chip and the substrate.

[0238] At least one embodiment of this application provides a radio frequency front-end module, including:

[0239] The substrate has a first pad, a second pad, and a third pad disposed on its first surface;

[0240] A protective layer is disposed on the first surface of the substrate;

[0241] A first packaged chip is disposed on a first surface of the substrate, and a first interconnect bump is disposed on the bottom surface of the first packaged chip. The first interconnect bump is connected to the first pad. A first gap is formed between the bottom surface of the packaged chip and the protective layer. The bottom surface of the first packaged chip is opposite to the first surface.

[0242] A second packaged chip is disposed on the first surface of the substrate, and a second interconnection bump is disposed on the bottom surface of the second packaged chip. The second interconnection bump is connected to the second pad. A second gap is formed between the bottom surface of the packaged chip and the first surface of the substrate. The bottom surface of the second packaged chip is opposite to the first surface.

[0243] A third packaged chip is disposed on the first surface of the substrate, and a third interconnection bump is disposed on the bottom surface of the third packaged chip. The third interconnection bump is connected to the third pad. A third gap is formed between the bottom surface of the packaged chip and the protective layer. The bottom surface of the third packaged chip is opposite to the first surface.

[0244] An isolation layer covers the first packaged chip, the third packaged chip, and a portion of the second packaged chip. The isolation layer includes a first portion disposed on a protective layer near the first packaged chip and a fourth portion disposed on a protective layer near the third packaged chip. The thickness of the first portion is less than the height of the first gap, and the thickness of the fourth portion is greater than the height of the third gap.

[0245] In this embodiment, taking FIG11 as an example, the first surface 11 of the substrate 10 is provided with a first pad 12, a second pad 13, and a third pad 14. The third pad 14 disposed on the first surface 11 can be disposed on the first surface 11 of the substrate (i.e., protruding from the first surface 11), or the third pad 14 can be embedded in the first surface (as shown in FIG11), or the third pad 14 can be partially embedded in the first surface and another part protruding from the first surface 11, or other feasible pad placement methods, which are not specifically limited here. FIG11 shows an example of the third pad 14 being embedded in the first surface 11.

[0246] In at least one embodiment, the number of third pads 14 is two or more. Optionally, the number of third pads 14 is the same as the number of third interconnect bumps 71. Exemplarily, the bottom surface of the first package chip 30 includes a plurality of third interconnect bumps 71, wherein each third interconnect bump 71 is connected to a third pad 14 on the first surface of the substrate 10.

[0247] Understandably, the protective layer 20 is provided with an opening, for example, an opening is provided at the corresponding position of the third pad 14 for interconnection between the third interconnect bump 71 of the first package chip 30 and the third pad 14.

[0248] In at least one embodiment, the protective layer 20 is provided with a fifth opening, and the third package chip 70 forms a sixth projected pattern on the substrate along the longitudinal direction. The main body of the sixth projected pattern is located in the fifth opening, and the outer periphery of the sixth projected pattern overlaps with the longitudinal projection of the protective layer 20. It can be understood that in this embodiment, the first interconnect bump 31 forming a sixth projected pattern on the substrate along the longitudinal direction is also located in the fifth opening. It can be understood that the longitudinal direction in this application embodiment is a relative concept; it does not mean that it must be absolutely vertical or suspended, and a slightly inclined direction is also permissible. Taking Figure 1 as an example, the longitudinal direction here can refer to the thickness direction in the chip package structure (e.g., the thickness direction of the substrate).

[0249] In at least one embodiment, the protective layer 20 is provided with a sixth opening, and the third interconnect bump 71 forms a first projection pattern on the substrate along the longitudinal direction, the first projection pattern being located in the sixth opening. It is understood that the number of sixth openings can be the same as the number of first interconnect bumps, so that the seventh projection pattern formed by each third interconnect bump is located in one sixth opening.

[0250] A third packaged chip 70 is disposed on the first surface 11 of the substrate 10. A third gap is formed between the bottom surface of the third packaged chip 70 and the protective layer 20, and the bottom surface of the third packaged chip 70 faces the first surface 11. In at least one embodiment, the third packaged chip 70 is a chip that requires a cavity between itself and the first surface of the substrate. Exemplarily, the third packaged chip 70 is a filter chip. Optionally, the third packaged chip 70 is a SAW filter chip, or a BAW filter chip.

[0251] A third interconnect bump 71 is disposed on the bottom surface of the first package chip 30, and the third interconnect bump 71 is connected to the third pad 14. It is understood that the bottom surface of the third package chip 70 includes at least two third interconnect bumps 71. In at least one embodiment, each third interconnect bump 71 may be connected to a third pad 14 on the first surface of the substrate.

[0252] In at least one embodiment, the third packaged chip further includes a second functional area, as shown in FIG11. The third packaged chip 70 includes a second functional area, in which wiring patterns, devices, etc., of the third packaged chip are disposed. For example, if the third packaged chip is a SAW filter chip, the second functional area is provided with electrode finger patterns, wiring patterns, etc., of the SAW filter. A fifth projection pattern is formed on the substrate along the longitudinal direction of the second functional area. Optionally, the fifth projection pattern is located in the fifth opening. Optionally, the fifth projection pattern at least partially overlaps with the protective layer.

[0253] In this embodiment, the isolation layer covers the first packaged chip, the third packaged chip, and a portion of the second packaged chip. The isolation layer includes a first portion disposed on a protective layer near the first packaged chip and a fourth portion disposed on a protective layer near the third packaged chip. The thickness of the first portion is less than the height of the first gap, and the thickness of the fourth portion is greater than the height of the third gap.

[0254] As shown in Figure 11, the isolation layer covers the first packaged chip 30, the third packaged chip 70, and a portion of the second packaged chip 60. It is understood that the relative positions of the first packaged chip 30, the second packaged chip 60, and the third packaged chip 70 in Figure 11 are merely an example and should not be construed as limiting the relative positions of these three components. Optionally, the first packaged chip and the third packaged chip are disposed adjacent to each other. Alternatively, the first packaged chip and the third packaged chip are disposed on different sides of the second packaged chip. In at least one embodiment, the first packaged chip is disposed adjacent to the second packaged chip relative to the third packaged chip. In at least one embodiment, the third packaged chip is disposed adjacent to the second packaged chip relative to the first packaged chip.

[0255] The thickness of the fourth part can be obtained by averaging the thickness values ​​taken at different locations in the fourth part as the overall thickness of the fourth part.

[0256] At least one embodiment of this application provides a radio frequency front-end module, including:

[0257] The substrate has a first pad and a third pad disposed on its first surface;

[0258] A protective layer is disposed on the first surface of the substrate;

[0259] A first packaged chip is disposed on a first surface of the substrate, and a first interconnect bump is disposed on the bottom surface of the first packaged chip. The first interconnect bump is connected to the first pad. A first gap is formed between the bottom surface of the packaged chip and the protective layer. The bottom surface of the first packaged chip is opposite to the first surface.

[0260] A third packaged chip is disposed on the first surface of the substrate, and a third interconnection bump is disposed on the bottom surface of the third packaged chip. The third interconnection bump is connected to the third pad. A third gap is formed between the bottom surface of the packaged chip and the protective layer. The bottom surface of the third packaged chip is opposite to the first surface.

[0261] An isolation layer covers the first packaged chip and the third packaged chip. The isolation layer includes a first portion disposed on a protective layer near the first packaged chip and a fourth portion disposed on a protective layer near the third packaged chip. The thickness of the first portion is less than the height of the first gap, and the thickness of the fourth portion is greater than the height of the third gap.

[0262] At least one embodiment of this application provides an electronic device, including a chip packaging structure as described in any of the foregoing embodiments / implementations, or including a radio frequency front-end module as described in any of the foregoing embodiments / implementations.

[0263] Understandably, to avoid redundancy, some details of the same or similar technical features in the above specification have not been described in some embodiments or implementations, but in fact these details are also applicable to different embodiments or implementations.

[0264] The above are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A chip packaging structure, wherein, include: The substrate has a first pad on its first surface; A protective layer is disposed on the first surface of the substrate; A first packaged chip is disposed on a first surface of the substrate, and a first gap is formed between the bottom surface of the first packaged chip and the protective layer, with the bottom surface of the first packaged chip facing the first surface. A first interconnect bump is disposed on the bottom surface of the first packaged chip, and the first interconnect bump is connected to the first pad. An isolation layer covers the first packaged chip and the protective layer. The isolation layer includes a first region adjacent to the first gap. A first connection point exists within the first region. A first line segment is formed by two points extending from the first connection point at a 45-degree angle to the outline of the first region of the isolation layer. The length D of the first line segment is equal to the height H of the first gap. g1 The following relationship must be satisfied: D≥H g1 。 2. The chip packaging structure according to claim 1, wherein, The length D of the first line segment and the height H of the first gap g1 The following relationship must be satisfied: D≤1.5H g1 .

3. The chip packaging structure according to claim 1, wherein, In the first region, a first set of line segments is formed by two points extending from the first connection point in a [40, 50] degree direction and intersecting with the outline of the first region of the isolation layer. The length of each line segment in the first set of line segments is greater than the height H of the first gap. g1 .

4. The chip packaging structure according to claim 1, wherein, The first pad protrudes from the substrate, and the height H of the first gap is... g1 and the thickness H of the protective layer s Satisfy: 2H g1 <H s .

5. The chip packaging structure according to claim 1, wherein, The first pad is embedded in the substrate, and the height H of the first gap is... g1 and the thickness H of the protective layer s Satisfies: 1.5H g1 <H s ≤2H g1 .

6. The chip packaging structure according to claim 1, wherein, The thickness H of the isolation layer p and the height H of the first gap g1 Satisfying the following relationship: 1um <H g1 -H p ≤10um.

7. The chip packaging structure according to claim 1, wherein, The first interconnect bump forms a first projection pattern on the substrate along the longitudinal direction, and the first projection pattern satisfies at least one of the following: In the first projected image, the longest line segment that passes through the center point of the first projected image and extends to both sides of the first projected image is greater than 80 μm. In the first projected image, the shortest line segment that passes through the center point of the first projected image and extends to both sides of the first projected image is greater than 60 μm; The area of ​​the first projected image is greater than 900πum 2 .

8. The chip packaging structure according to claim 1, wherein, It also includes a sealing layer that at least covers the protective layer and the first packaged chip.

9. The chip packaging structure according to claim 1, wherein, The thickness of the isolation layer is less than the height of the first gap.

10. The chip packaging structure according to claim 1, wherein, The isolation layer includes a first portion disposed on the protective layer, the thickness of the first portion being less than the height of the first gap.

11. The chip packaging structure according to claim 10, wherein, The isolation layer also includes a second portion disposed on the side of the first packaged chip and a third portion disposed on the top surface of the packaged chip; The thickness of the second part is less than the thickness of the third part, and / or the thickness of the second part is less than the thickness of the first part.

12. The chip packaging structure according to claim 1 or 9, wherein, The isolation layer has a storage modulus greater than 3 MPa at 150 degrees Celsius.

13. The chip packaging structure according to claim 1, wherein, The first packaged chip is a surface acoustic wave filter chip.

14. The chip packaging structure according to claim 1, wherein, The isolation layer at least partially fills the first gap.

15. A chip packaging structure, wherein, include: The substrate has a first pad on its first surface; A protective layer is disposed on the first surface of the substrate; A first packaged chip is disposed on a first surface of the substrate, and a first gap is formed between the bottom surface of the first packaged chip and the protective layer, with the bottom surface of the first packaged chip facing the first surface. A first interconnect bump is disposed on the bottom surface of the first packaged chip. The first interconnect bump is connected to the first pad. The first interconnect bump forms a first projection pattern on the substrate along the longitudinal direction. In the first projection pattern, the longest line segment that passes through the center point of the first projection pattern and extends to both sides of the first projection pattern is greater than the height of the first interconnect bump. An isolation layer covers the first packaged chip and the protective layer.

16. A radio frequency front-end module, wherein, include: The substrate has a first pad disposed on its first surface; A protective layer is disposed on the first surface of the substrate; A first packaged chip is disposed on a first surface of the substrate, and a first gap is formed between the bottom surface of the first packaged chip and the protective layer, with the bottom surface of the first packaged chip facing the first surface. A first interconnect bump is disposed on the bottom surface of the first packaged chip, and the first interconnect bump is connected to the first pad. An isolation layer covers the first packaged chip and the protective layer. The isolation layer includes a first portion disposed on the protective layer. A first point and a second point are present on the bottom side of the first packaged chip. The thickness of the first portion corresponding to the first point is less than the height of the first gap, and the thickness of the first portion corresponding to the second point is greater than the height of the first gap.

17. The radio frequency front-end module according to claim 16, wherein, It also includes a first device and a second device. The first device is disposed on the side adjacent to the first point, and the second device is disposed on the side adjacent to the second point. The distance between the first device and the first packaged chip is smaller than the distance between the second device and the first packaged chip. The first point and the second point are disposed on the bottom of different sides of the first packaged chip.

18. A radio frequency front-end module, wherein, include: The substrate has a first pad and a second pad on its first surface. A protective layer is disposed on the first surface of the substrate; A first packaged chip is disposed on a first surface of the substrate, and a first interconnect bump is disposed on the bottom surface of the first packaged chip. The first interconnect bump is connected to the first pad. A first gap is formed between the bottom surface of the first packaged chip and the protective layer. The bottom surface of the first packaged chip is opposite to the first surface. A second packaged chip is disposed on the first surface of the substrate, and a second interconnection bump is disposed on the bottom surface of the second packaged chip. The second interconnection bump is connected to the second pad. A second gap is formed between the bottom surface of the second packaged chip and the first surface of the substrate. The bottom surface of the second packaged chip is opposite to the first surface. An isolation layer covers the first packaged chip, the protective layer, and part of the second packaged chip; The first interconnect bump forms a first projection pattern on the substrate along the longitudinal direction. In the first projection pattern, the longest line segment that passes through the center point of the first projection pattern and extends to both sides of the first projection pattern is greater than the height of the first interconnect bump. The height of the first interconnect bump is less than the height of the second interconnect bump. A sealing layer covers the protective layer, the first packaged chip, and the second packaged chip, and at least partially fills the second gap.

19. The radio frequency front-end module according to claim 18, wherein, The thickness of the isolation layer is less than the height of the first gap, and the height of the first gap is less than the height of the second gap.

20. The radio frequency front-end module according to claim 18, wherein, The vertical distance between the second packaged chip and the protective layer is H. a The lateral distance between at least one side of the second packaged chip and the protective layer is H. b And satisfy: H a >H b .

21. The radio frequency front-end module according to claim 18, wherein, The vertical distance between the second packaged chip and the protective layer is H. a The lateral distance between at least one side of the second packaged chip and the protective layer is H. b And satisfy:

22. The radio frequency front-end module according to claim 18, wherein, The straight-line distance between any point on the bottom side of the second packaged chip and the protective layer is H. d In the second packaged chip, at least 20% of the H content is located on the bottom side. d It is greater than the height of the first gap.

23. The radio frequency front-end module according to claim 18, wherein, The first packaged chip is a filter chip, and the second packaged chip is a non-filter chip.

24. The radio frequency front-end module according to claim 18, wherein, The isolation layer covers the second packaged chip and has openings formed on at least two sides of the second packaged chip, so that the sealing layer at least partially fills the second gap formed between the bottom surface of the second packaged chip and the first surface of the substrate.

25. The radio frequency front-end module according to claim 18, wherein, The isolation layer covers the second packaged chip and has openings on up to three sides of the second packaged chip, such that the sealing layer at least partially fills the second gap formed between the bottom surface of the second packaged chip and the first surface of the substrate.

26. The radio frequency front-end module according to claim 18, wherein, The distance between the bottom surface of the second packaged chip and the substrate is greater than the distance between the bottom surface of the first packaged chip and the substrate, and the longitudinal distance between the bottom surface of the second packaged chip and the bottom surface of the first packaged chip is greater than 10 μm.

27. The radio frequency front-end module according to claim 18, wherein, The height of the second interconnect bump is less than three times the height of the first interconnect bump.

28. A radio frequency front-end module, wherein, include: The substrate has a first pad and a second pad on its first surface. A protective layer is disposed on the first surface of the substrate; A first packaged chip is disposed on a first surface of the substrate, and a first interconnect bump is disposed on the bottom surface of the first packaged chip. The first interconnect bump is connected to the first pad. A first gap is formed between the bottom surface of the packaged chip and the protective layer. The bottom surface of the packaged chip is opposite to the first surface. A second packaged chip is disposed on the first surface of the substrate, and a second interconnection bump is disposed on the bottom surface of the second packaged chip. The second interconnection bump is connected to the second pad. A second gap is formed between the bottom surface of the packaged chip and the first surface of the substrate. The bottom surface of the second packaged chip is opposite to the first surface. The first interconnect bump forms a first projection pattern on the substrate along the longitudinal direction, and the second interconnect bump forms a second projection pattern on the substrate along the longitudinal direction. The area of ​​the first projection pattern is larger than the area of ​​the second projection pattern, and the height of the first interconnect bump is smaller than the height of the second interconnect bump. An isolation layer covers the first packaged chip, the first surface of the substrate, and a portion of the second packaged chip; A sealing layer covers the protective layer, the first packaged chip, and the second packaged chip, and at least partially fills the space between the second packaged chip and the substrate.

29. A radio frequency front-end module, wherein, include: The substrate has a first pad and a second pad on its first surface. A protective layer is disposed on the first surface of the substrate; A first packaged chip is disposed on a first surface of the substrate, and a first interconnect bump is disposed on the bottom surface of the first packaged chip. The first interconnect bump is connected to the first pad. A first gap is formed between the bottom surface of the packaged chip and the protective layer. The bottom surface of the packaged chip is opposite to the first surface. A second packaged chip is disposed on the first surface of the substrate, and a second interconnection bump is disposed on the bottom surface of the second packaged chip. The second interconnection bump is connected to the second pad. A second gap is formed between the bottom surface of the packaged chip and the first surface of the substrate. The bottom surface of the second packaged chip is opposite to the first surface. An isolation layer covers the first packaged chip and the first surface of the substrate; A sealing layer covers the protective layer, the first packaged chip, and the second packaged chip; The isolation layer also covers the second packaged chip and has openings formed on at least two and at most three sides of the second packaged chip, so that the sealing layer at least partially fills the space between the second packaged chip and the substrate.

30. A radio frequency front-end module, wherein, include: The substrate has a first pad, a second pad, and a third pad disposed on its first surface; A protective layer is disposed on the first surface of the substrate; A first packaged chip is disposed on a first surface of the substrate, and a first interconnect bump is disposed on the bottom surface of the first packaged chip. The first interconnect bump is connected to the first pad. A first gap is formed between the bottom surface of the packaged chip and the protective layer. The bottom surface of the first packaged chip is opposite to the first surface. A second packaged chip is disposed on the first surface of the substrate, and a second interconnection bump is disposed on the bottom surface of the second packaged chip. The second interconnection bump is connected to the second pad. A second gap is formed between the bottom surface of the packaged chip and the first surface of the substrate. The bottom surface of the second packaged chip is opposite to the first surface. A third packaged chip is disposed on the first surface of the substrate, and a third interconnection bump is disposed on the bottom surface of the third packaged chip. The third interconnection bump is connected to the third pad. A third gap is formed between the bottom surface of the packaged chip and the protective layer. The bottom surface of the third packaged chip is opposite to the first surface. An isolation layer covers the first packaged chip, the third packaged chip, and a portion of the second packaged chip. The isolation layer includes a first portion disposed on a protective layer near the first packaged chip and a fourth portion disposed on a protective layer near the third packaged chip. The thickness of the first portion is less than the height of the first gap, and the thickness of the fourth portion is greater than the height of the third gap.

31. An electronic device, wherein, Includes the chip packaging structure as described in any one of claims 1-17, or includes the radio frequency front-end module as described in any one of claims 18-30.

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