Semiconductor device and manufacturing method therefor

Abstract

A semiconductor device and a manufacturing method therefor. The semiconductor device has an ohmic contact region, a Schottky contact region, and an intermediate region between the ohmic contact region and the Schottky contact region. The semiconductor device comprises: a substrate; a first epitaxial structure located on one side of the substrate; and a second epitaxial structure located on the side of the first epitaxial structure away from the substrate. The second epitaxial structure comprises a first epitaxial portion, a second epitaxial portion, and a third epitaxial portion; the first epitaxial portion is located in the ohmic contact region, the second epitaxial portion is located in the Schottky contact region, and the third epitaxial portion is located in the intermediate region; and the first epitaxial portion, the second epitaxial portion, and the third epitaxial portion are all separately disposed. The technical solution of embodiments of the present application can achieve differentiated setting of the second epitaxial structure, and improve the performance of the semiconductor device.

Description

A semiconductor device and its fabrication method Technical Field

[0001] This application relates to the field of microelectronics technology, and more particularly to a semiconductor device and its fabrication method.

[0002] Background of the Invention

[0003] High electron mobility transistors (HEPs) are field-effect transistors that utilize the physical properties of GaN, such as its wide bandgap, high electron mobility, and high critical breakdown electric field, and have great potential for high-frequency power applications.

[0004] Currently, the epitaxial structure in high electron mobility transistors is a single, integrated structure. Different regions of the epitaxial structure are configured in the same way, which makes it impossible to achieve differentiated configuration of the epitaxial structure and thus affects the performance of semiconductor devices. Summary of the Invention

[0005] In view of this, embodiments of this application provide a semiconductor device and a method for fabricating the same, so as to achieve differentiated settings of the second epitaxial structure and thereby improve the performance of the semiconductor device.

[0006] In a first aspect, embodiments of this application provide a semiconductor device having an ohmic contact region, a Schottky contact region, and an intermediate region between the ohmic contact region and the Schottky contact region;

[0007] The semiconductor device includes:

[0008] Substrate;

[0009] A first epitaxial structure located on one side of the substrate;

[0010] A second epitaxial structure is located on the side of the first epitaxial structure away from the substrate. The second epitaxial structure includes a first epitaxial portion, a second epitaxial portion, and a third epitaxial portion. The first epitaxial portion is located in the ohmic contact region, the second epitaxial portion is located in the Schottky contact region, and the third epitaxial portion is located in the intermediate region. The first epitaxial portion, the second epitaxial portion, and the third epitaxial portion are all independently configured.

[0011] Optionally, the first epitaxial portion includes a first channel portion and an ohmic contact enhancement structure stacked together; the ohmic contact enhancement structure is located on the side of the first channel portion away from the substrate;

[0012] The second epitaxial portion includes a second channel portion and a first barrier portion stacked together; the first barrier portion is located on the side of the second channel portion away from the substrate;

[0013] The third epitaxial portion includes a third channel portion and a second barrier portion stacked together; the second barrier portion is located on the side of the third channel portion away from the substrate;

[0014] The thickness of the first channel section is less than the thickness of the second channel section and less than the thickness of the third channel section.

[0015] Optionally, a first carrier layer is formed between the first barrier portion and the second channel portion, and a second carrier layer is formed between the second barrier portion and the third channel portion.

[0016] The distance between the surface of the ohmic contact enhancement structure closest to the substrate and the substrate is less than the distance between the first charge carrier layer and the second charge carrier layer and the substrate.

[0017] Optionally, the ohmic contact enhancement structure, the first barrier portion, and the second barrier portion are all independently configured and prepared in different processes;

[0018] The thickness of the first barrier portion is less than the thickness of the second barrier portion.

[0019] Optionally, the first channel segment, the second channel segment, and the third channel segment are each independently configured and prepared in different processes.

[0020] Optionally, the second and third channel sections can be integrated into one unit.

[0021] Optionally, the first epitaxial portion has a first side surface near the third epitaxial portion, the second epitaxial portion has a second side surface near the third epitaxial portion, and the third epitaxial portion has a third side surface near the first epitaxial portion and a fourth side surface near the second epitaxial portion.

[0022] The first side and the third side abut against each other, and the second side and the fourth side abut against each other.

[0023] Optionally, the first side surface includes a first sub-side surface and a second sub-side surface; the first sub-side surface is the surface of the first channel portion near the third channel portion; the second sub-side surface is the surface of the ohmic contact enhancement structure near the second barrier portion; the angle θ1 between the first sub-side surface and the plane of the substrate satisfies 85°≤θ1≤95°; the angle θ2 between the second sub-side surface and the plane of the substrate satisfies 85°≤θ2≤95°;

[0024] The second side surface includes a third sub-side surface and a fourth sub-side surface; the third sub-side surface is the surface of the second channel portion near the third channel portion; the fourth sub-side surface is the surface of the first barrier portion near the second barrier portion; the angle θ3 between the third sub-side surface and the plane where the substrate is located satisfies 85°≤θ3≤95°; the angle θ4 between the fourth sub-side surface and the plane where the substrate is located satisfies 85°≤θ4≤95°;

[0025] The third side surface includes a fifth sub-side surface and a sixth sub-side surface; the fifth sub-side surface is the surface of the third channel portion near the first channel portion; the sixth sub-side surface is the surface of the second barrier portion near the ohmic contact enhancement structure; the angle θ5 between the fifth sub-side surface and the plane where the substrate is located satisfies 85°≤θ5≤95°; the angle θ6 between the sixth sub-side surface and the plane where the substrate is located satisfies 85°≤θ6≤95°;

[0026] The fourth side surface includes a seventh sub-side surface and an eighth sub-side surface; the seventh sub-side surface is the surface of the third channel portion near the second channel portion; the eighth sub-side surface is the surface of the second barrier portion near the first barrier portion; the angle θ7 between the seventh sub-side surface and the plane where the substrate is located satisfies 85°≤θ7≤95°; the angle θ8 between the eighth sub-side surface and the plane where the substrate is located satisfies 85°≤θ8≤95°.

[0027] Optionally, the ohmic contact enhancement structure comprises n-type doped GaN, wherein the doping concentration N of the n-type doped GaN satisfies 1*10n. 18 / cm 3 ≤N≤1*10 21 / cm 3 .

[0028] Secondly, embodiments of this application also provide a method for fabricating a semiconductor device, comprising:

[0029] A substrate is provided, and a first epitaxial structure is fabricated on one side of the substrate;

[0030] A first epitaxial portion, a second epitaxial portion, and a third epitaxial portion are prepared in a time-division manner on the side of the first epitaxial structure away from the substrate to obtain a second epitaxial structure located on the side of the first epitaxial structure away from the substrate. The first epitaxial portion is located in the ohmic contact region of the semiconductor device, the second epitaxial portion is located in the Schottky contact region of the semiconductor device, and the third epitaxial portion is located in the intermediate region of the semiconductor device between the ohmic contact region and the Schottky contact region. The first epitaxial portion, the second epitaxial portion, and the third epitaxial portion are all independently configured.

[0031] Optionally, the first epitaxial portion, the second epitaxial portion, and the third epitaxial portion are prepared in different processes.

[0032] Optionally, the preparation of the first epitaxial portion includes:

[0033] A first mask layer is prepared on the side of the first epitaxial structure away from the substrate and in the Schottky contact region and the intermediate region, the first mask layer exposing the ohmic contact region;

[0034] A first channel portion and an ohmic contact reinforcement structure are sequentially formed on the side of the first epitaxial structure away from the substrate and in the ohmic contact region; the ohmic contact reinforcement structure is located on the side of the first channel portion away from the substrate.

[0035] Optionally, the second epitaxial portion is prepared, including:

[0036] A second mask layer is prepared on the side of the first epitaxial structure away from the substrate and in the ohmic contact region and the intermediate region, the second mask layer exposing the Schottky contact region;

[0037] A second channel portion and a first barrier portion are sequentially formed on the side of the first epitaxial structure away from the substrate and in the Schottky contact region; the first barrier portion is located on the side of the second channel portion away from the substrate.

[0038] Optionally, the preparation of the third epitaxial portion includes:

[0039] A third mask layer is prepared on the side of the first epitaxial structure away from the substrate and in the ohmic contact region and the Schottky contact region, the third mask layer exposing the intermediate region;

[0040] A third channel portion and a second barrier portion are sequentially formed on the side of the first epitaxial structure away from the substrate and in the middle region; the second barrier portion is located on the side of the third channel portion away from the substrate.

[0041] Optionally, the first epitaxial portion, the second epitaxial portion, and the third epitaxial portion are fabricated in a time-division manner on the side of the first epitaxial structure away from the substrate, including:

[0042] A fourth mask layer is prepared on the side of the first epitaxial structure away from the substrate and in the Schottky contact region and the intermediate region, the fourth mask layer exposing the ohmic contact region;

[0043] A first channel portion is formed on the side of the first epitaxial structure away from the substrate and in the ohmic contact region;

[0044] A fifth mask layer is prepared on the side of the first channel portion away from the substrate and on the side of the first epitaxial structure corresponding to the intermediate region away from the substrate, the fifth mask layer exposing the Schottky contact region;

[0045] A second channel portion is formed on the side of the first epitaxial structure away from the substrate and in the Schottky contact region;

[0046] A sixth mask layer is prepared on the side of the first communication portion and the second channel portion away from the substrate, the sixth mask layer exposing the intermediate region;

[0047] A third channel portion is formed on the side of the first epitaxial structure away from the substrate and in the middle region;

[0048] A seventh mask layer is prepared on the side of the second channel portion and the third channel portion away from the substrate, the seventh mask layer exposing the ohmic contact region;

[0049] An ohmic contact enhancement structure is prepared on the side of the first channel portion away from the substrate;

[0050] An eighth mask layer is prepared on the side of the ohmic contact enhancement structure and the third channel portion away from the substrate, the eighth mask layer exposing the Schottky contact region;

[0051] A first barrier portion is formed on the side of the second channel portion away from the substrate and in the Schottky contact region;

[0052] A ninth mask layer is prepared on the side of the ohmic contact enhancement structure and the first barrier portion away from the substrate, the ninth mask layer exposing the intermediate region;

[0053] A second barrier portion is formed on the side of the third channel portion away from the substrate and in the middle region.

[0054] The technical solution provided in this application embodiment includes a second epitaxial structure on the side of the first epitaxial structure away from the substrate, comprising a first epitaxial structure portion, a second epitaxial structure portion, and a third epitaxial structure portion. The first, second, and third epitaxial portions are all independently configured, which facilitates differentiated configuration of the epitaxial structures corresponding to the ohmic contact region, Schottky contact region, and intermediate region in the semiconductor device, thereby improving the performance of the semiconductor device. Furthermore, the first, second, and third epitaxial portions can be fabricated using different processes, enabling independent and precise control of the material, thickness, and doping concentration of each region, breaking through the design limitations of traditional monolithic epitaxy.

[0055] Brief description of the attached figures

[0056] Figure 1 is a cross-sectional structural diagram of a semiconductor device provided in an exemplary embodiment of this application.

[0057] Figure 2 is a cross-sectional schematic diagram of a semiconductor device provided in another exemplary embodiment of this application.

[0058] Figure 3 is a cross-sectional schematic diagram of a semiconductor device provided in another exemplary embodiment of this application.

[0059] Figure 4 is a schematic flowchart of a method for fabricating a semiconductor device provided in an exemplary embodiment of this application.

[0060] Figure 5 is a schematic flowchart of a method for fabricating a semiconductor device provided in another exemplary embodiment of this application.

[0061] Figure 6 is a process flow diagram of the semiconductor device fabrication method corresponding to Figure 5.

[0062] Figure 7 is a schematic flowchart of a method for fabricating a semiconductor device provided in another exemplary embodiment of this application.

[0063] Figure 8 is a process flow diagram of the semiconductor device fabrication method corresponding to Figure 7.

[0064] Figure 9 is a schematic flowchart of a method for fabricating a semiconductor device provided in another exemplary embodiment of this application.

[0065] Figure 10 is a process flow diagram of the semiconductor device fabrication method corresponding to Figure 9.

[0066] Figure 11 is a schematic flowchart of a method for fabricating a semiconductor device provided in another exemplary embodiment of this application.

[0067] Methods of implementing the present invention

[0068] The present application will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the application and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present application, not the entire structure.

[0069] Figure 1 is a cross-sectional structural schematic diagram of a semiconductor device provided in an exemplary embodiment of this application. As shown in Figure 1, the semiconductor device has an ohmic contact region 100, a Schottky contact region 200, and an intermediate region 300 between the ohmic contact region 100 and the Schottky contact region 200. The semiconductor device includes: a substrate 10; a first epitaxial structure 20 located on one side of the substrate 10; and a second epitaxial structure 30 located on the side of the first epitaxial structure 20 away from the substrate 10. The second epitaxial structure 30 includes a first epitaxial portion 301, a second epitaxial portion 302, and a third epitaxial portion 303. The first epitaxial portion 301 is located in the ohmic contact region 100, the second epitaxial portion 302 is located in the Schottky contact region 200, and the third epitaxial portion 303 is located in the intermediate region 300. The first epitaxial portion 301, the second epitaxial portion 302, and the third epitaxial portion 303 are all independently disposed. Furthermore, the first epitaxial portion 301, the second epitaxial portion 302, and the third epitaxial portion 303 can be prepared in different processes.

[0070] Specifically, the ohmic contact region 100 can be understood as a region where an ohmic electrode is disposed, that is, the ohmic contact region may include a source setting region and a drain setting region. The Schottky contact region 200 can be understood as a region where a Schottky electrode is disposed, that is, the Schottky contact region 200 may be a gate setting region. The intermediate region 300 is located between the ohmic contact region 100 and the Schottky contact region 200, and is used to ensure the integrity of the second epitaxial structure 30.

[0071] In this application, the term "first epitaxial portion, second epitaxial portion, and third epitaxial portion are all independently configured" means that the three epitaxial portions are prepared through independent and time-sequential process steps, thereby enabling them to be configured differently, for example, with different stacked structures, thicknesses, materials, and / or doping concentrations. This "independent configuration" can also be expressed as partial layers of two or more portions being formed continuously and integrally, but the entire portion, as a functional unit, is configured differently through independent processes.

[0072] Specifically, the substrate 10 can be one or more of gallium nitride, aluminum gallium nitride, indium gallium nitride, aluminum indium gallium nitride, indium phosphide, gallium arsenide, silicon carbide, diamond, sapphire, germanium, and silicon. The substrate 10 can also be any other material capable of growing group III nitrides.

[0073] Referring again to Figure 1, the first epitaxial structure 20 includes a nucleation layer 203 and a buffer layer 202 stacked together, with the buffer layer 202 located on the side of the nucleation layer 203 away from the substrate 10.

[0074] For example, continuing to refer to FIG1, the material of nucleation layer 203 may be aluminum nitride, located between substrate 10 and buffer layer 202, serving to bond the semiconductor material layer to be grown next.

[0075] For example, continuing to refer to FIG1, the buffer layer 202 is located on one side of the substrate 10. The material of the buffer layer 202 can be gallium nitride, and the buffer layer 202 can include iron atoms, which is beneficial to achieve the high resistance performance of the buffer layer 202, ensuring that it can block vertical leakage current and improve the pinch-off characteristics of semiconductor devices, specifically manifested as lower leakage current and pinch-off voltage.

[0076] Specifically, the second epitaxial structure 30 is located on the side of the first epitaxial structure 20 away from the substrate 10, that is, after the first epitaxial structure 20 is grown, the second epitaxial structure 30 continues to be grown on the upper surface of the first epitaxial structure 20. The second epitaxial structure 30 includes a first epitaxial portion 301, a second epitaxial portion 302, and a third epitaxial portion 303. The source 40 and drain 60 can form ohmic contacts with the first epitaxial portion, and the gate 50 can form a Schottky contact with the second epitaxial portion.

[0077] Specifically, the three epitaxial divisions are set up independently and have structures corresponding to their respective locations, which can realize personalized and differentiated settings of the second epitaxial structure, thereby improving the performance of semiconductor devices.

[0078] Specifically, the first epitaxial portion 301, the second epitaxial portion 302, and the third epitaxial portion 303 are all independently configured and fabricated in different processes. In other words, the first epitaxial portion 301, the second epitaxial portion 302, and the third epitaxial portion 303 are not a single integrated structure, but rather three separate independent structures. The first epitaxial portion 301, the second epitaxial portion 302, and the third epitaxial portion 303 can have different numbers of film layers, different film thicknesses, or different materials than other epitaxial portions based on their location, to match their location and ensure the performance of the semiconductor device. For example, the first epitaxial portion 301 can be configured to have a smaller contact resistance than the second epitaxial portion 302 and the third epitaxial portion 303, to ensure a smaller ohmic contact resistance between the ohmic electrode in that region and the first epitaxial portion 301. For another example, the second epitaxial portion 302 can be configured to have a different thickness than the third epitaxial portion 303. Since the second epitaxial portion 302 is located at the position where the gate is subsequently set, configuring the second epitaxial portion 302 to have a different thickness than the third epitaxial portion 303 can realize semiconductor devices with different gate control capabilities based on requirements.

[0079] Furthermore, the first epitaxial portion 301, the second epitaxial portion 302, and the third epitaxial portion 303 are all independently configured and fabricated in different processes. In other words, the first epitaxial portion 301, the second epitaxial portion 302, and the third epitaxial portion 303 are not fabricated integrally; that is, the three epitaxial portions are not fabricated using the same process step, but are grown independently, i.e., the three epitaxial portions are fabricated in a time-sharing manner. In other words, the epitaxial portions corresponding to the ohmic contact region 100, the Schottky contact region 200, and the intermediate region 300 are grown independently. As a comparison, in the prior art, after the epitaxial structure is fabricated integrally, an n-type doped GaN region is formed by etching the epitaxial structure to fabricate the source and drain electrodes above the n-type doped GaN region. However, the etching process can damage the epitaxial structure. However, in the embodiments of this application, the three epitaxial segments in the second epitaxial structure 30 are prepared at the same time. This eliminates the need to etch the epitaxial structure and allows n-type doped GaN to be grown directly in the first epitaxial segment, thus avoiding damage to the epitaxial structure and improving the performance of the semiconductor device.

[0080] The semiconductor device provided in this application includes a second epitaxial structure on the side of the first epitaxial structure away from the substrate, comprising a first epitaxial structure portion, a second epitaxial structure portion, and a third epitaxial structure portion. The first, second, and third epitaxial portions are all independently configured and fabricated in different processes. This facilitates differentiated configurations of the epitaxial structures corresponding to the ohmic contact region, Schottky contact region, and intermediate region in the semiconductor device, thereby enabling personalized and differentiated configurations of the second epitaxial structure and improving the performance of the semiconductor device.

[0081] Optionally, continuing to refer to FIG1, the first epitaxial portion 301 includes a first channel portion 3012 and an ohmic contact reinforcement structure 3011 stacked together; the ohmic contact reinforcement structure 3011 is located on the side of the first channel portion 3012 away from the substrate 10; the second epitaxial portion 302 includes a second channel portion 3022 and a first barrier portion 3021 stacked together; the first barrier portion 3021 is located on the side of the second channel portion 3022 away from the substrate 10; the third epitaxial portion 303 includes a third channel portion 3032 and a second barrier portion 3021 stacked together. 31; The second barrier portion 3031 is located on the side of the third channel portion 3032 away from the substrate 10; the thickness of the first channel portion 3012 is less than the thickness of the second channel portion 3022 and less than the thickness of the third channel portion 3032; a carrier layer is formed between the first barrier portion 3021 and the second channel portion 3022, and a carrier layer is formed between the second barrier portion 3031 and the third channel portion 3032; the distance between the surface of the ohmic contact enhancement structure 3011 on the side close to the substrate 10 and the substrate 10 is less than the distance between the carrier layer and the substrate 10.

[0082] Specifically, the carrier layer can be a two-dimensional electron gas (2DEG) or other carriers. This application's embodiments use a two-dimensional electron gas as an example.

[0083] Specifically, since the second epitaxial portion 302 is located in the Schottky contact region 200, the gate 50 can form a Schottky contact with the second epitaxial structure 302. The third epitaxial portion 303 connects the first epitaxial portion 301 and the second epitaxial portion 302, thereby ensuring the integrity of the second epitaxial structure 30.

[0084] Specifically, both the second epitaxial portion 302 and the third epitaxial portion 303 include a barrier portion and a channel portion, thus forming a carrier layer in both portions. The thickness of the first channel portion 3012 is less than the thickness of the second channel portion 3022 and less than the thickness of the third channel portion 3032. The distance between the surface of the ohmic contact reinforcement structure 3011 near the substrate 10 and the substrate 10 is less than the distance between the carrier layer and the substrate 10. Thus, in the first epitaxial portion 301, the lower surface of the ohmic contact reinforcement structure 3011 does not have a carrier layer, and the lower surface of the ohmic contact reinforcement structure 3011 is located below the carrier layers in the second epitaxial portion 302 and the third epitaxial portion 303, so that the ohmic electrode and the ohmic contact reinforcement structure 3011 form an ohmic contact.

[0085] For example, continuing to refer to Figure 1, the channel portion can be a group III nitride, such as Al. x Ga 1－x N, where 0 ≤ x < 1. For example, x = 0 indicates that the channel portion is GaN. The channel portion can also be other Group III nitrides, such as InGaN or AlInGaN. The channel portion can be undoped or unintentionally doped. The channel portion can also be a multilayer structure, such as a combination of superlattice, GaN, or AlGaN.

[0086] Optionally, referring to Figure 1, the ohmic contact reinforcement structure 3011, the first barrier portion 3021, and the second barrier portion 3031 are all independently configured and prepared in different processes; the thickness of the first barrier portion 3021 is less than the thickness of the second barrier portion 3031.

[0087] Specifically, the ohmic contact enhancement structure 3011, the first barrier portion 3021, and the second barrier portion 3031 are all independently set, not integrally set, and are fabricated in different processes. This enables personalized and differentiated settings for the second epitaxial structure, thereby improving the performance of the semiconductor device.

[0088] Specifically, by setting the thickness of the first barrier portion 3021 to be less than the thickness of the second barrier portion 3031, the two-dimensional electron gas concentration in the Schottky contact region 200 can be reduced, thereby improving the gate's ability to regulate the channel current.

[0089] Optionally, referring to Figure 1, the first channel segment 3012, the second channel segment 3022 and the third channel segment 3032 are all independently set and prepared in different processes.

[0090] Specifically, the first channel section 3012, the second channel section 3022, and the third channel section 3032 are all set independently, rather than as a single unit. This allows for personalized settings of the first channel section 3012, the second channel section 3022, and the third channel section 3032, which helps ensure that the thickness of the first channel section 3012 is smaller than the thickness of the second channel section 3022 and the third channel section 3032.

[0091] Optionally, referring to Figure 1, the first extension portion 301 includes a first side a1 near the third extension portion 303, the second extension portion 302 includes a second side a2 near the third extension portion 303, and the third extension portion 303 includes a third side a3 near the first extension portion 301 and a fourth side a4 near the second extension portion 302; the first side a1 and the third side a3 abut against each other, and the second side a2 and the fourth side a4 abut against each other.

[0092] Specifically, since the third extensional portion 303 is located in the middle of the first extensional portion 301 and the second extensional portion 302, the third side a3 of the third extensional structure 303 is adjacent to the first side a1 of the first extensional portion 301, and the fourth side a4 of the third extensional structure 303 is adjacent to the second side a2 of the second extensional portion 302.

[0093] Specifically, the first side a1 and the third side a3 abut against each other, and the second side a2 and the fourth side a4 abut against each other. This indicates that the second epitaxial structure 30 is independently set, which is beneficial to realize the differentiated setting of the epitaxial structure corresponding to the ohmic contact region, Schottky contact region and the intermediate region in the semiconductor device, thereby improving the performance of the semiconductor device.

[0094] Specifically, the mutual contact between the first side a1 and the third side a3 can be understood as follows: after the first epitaxial portion 301 is prepared, the third epitaxial portion 303 will continue to grow on the side closer to the first side a1, or after the third epitaxial portion 303 is prepared, the first epitaxial portion 301 will continue to grow on the side closer to the third side a3. After both the first epitaxial portion 301 and the third epitaxial portion 303 are prepared, the first side a1 and the third side a3 will come into contact with each other.

[0095] Specifically, the mutual contact between the second side a2 and the fourth side a4 can be understood as follows: after the second epitaxial portion 302 is prepared, the third epitaxial portion 303 will continue to grow on the side closer to the second side a2, or after the third epitaxial portion 303 is prepared, the second epitaxial portion 302 will continue to grow on the side closer to the fourth side a4. After both the second epitaxial portion 302 and the third epitaxial portion 303 are prepared, the second side a2 and the fourth side a4 will be in contact with each other.

[0096] Specifically, the first side a1 and the third side a3 abut against each other, and the second side a2 and the fourth side a4 abut against each other. This indicates that the first epitaxial portion 301, the second epitaxial portion 302, and the third epitaxial portion 303 are grown independently, rather than fabricated as a single unit. This eliminates the need for etching the epitaxial structure, avoids damage to the epitaxial structure, and thus improves the performance of the semiconductor device.

[0097] Optionally, referring to Figure 1, the first side surface a1 includes a first sub-side surface a11 and a second sub-side surface a12; the first sub-side surface a11 is the surface of the first channel portion 3012 near the third channel portion 3032; the second sub-side surface a12 is the surface of the ohmic contact reinforcement structure 3011 near the second barrier portion 3031; the angle θ1 between the first sub-side surface a11 and the plane of the substrate 10 satisfies 85°≤θ1≤95°; the angle θ2 between the second sub-side surface a12 and the plane of the substrate 10 satisfies 85°≤θ1≤95°. 5°≤θ2≤95°; the second side surface a2 includes a third sub-side surface a21 and a fourth sub-side surface a22; the third sub-side surface a21 is the surface of the second channel portion 3022 near the third channel portion 3032; the fourth sub-side surface a22 is the surface of the first barrier portion 3021 near the second barrier portion 3031; the angle θ3 between the third sub-side surface a21 and the plane containing the substrate 10 satisfies 85°≤θ2≤95°; the angle θ4 between the fourth sub-side surface a22 and the plane containing the substrate 10 satisfies 85°≤θ2≤95°. 4 ≤ 95°; the third side surface a3 includes a fifth sub-side surface a31 and a sixth sub-side surface a32; the fifth sub-side surface a31 is the surface of the third channel portion 3032 near the first channel portion 3012; the sixth sub-side surface a32 is the surface of the second barrier portion 3031 near the ohmic contact reinforcement structure 3011; the angle θ5 between the fifth sub-side surface a31 and the plane of the substrate 10 satisfies 85° ≤ θ5 ≤ 95°; the angle θ6 between the sixth sub-side surface a32 and the plane of the substrate 10 satisfies 85° ≤ θ6 ≤ 95°. 95°; the fourth side surface a4 includes the seventh sub-side surface a41 and the eighth sub-side surface a42; the seventh sub-side surface a41 is the surface of the third channel portion 3032 near the second channel portion 3022; the eighth sub-side surface a42 is the surface of the second barrier portion 3031 near the first barrier portion 3021; ​​the angle θ7 between the seventh sub-side surface a41 and the plane where the substrate 10 is located satisfies 85°≤θ7≤95°; the angle θ8 between the eighth sub-side surface a42 and the plane where the substrate 10 is located satisfies 85°≤θ8≤95°.

[0098] Specifically, 85°≤θ1≤95°, 85°≤θ2≤95°, 85°≤θ3≤95°, 85°≤θ4≤95°, 85°≤θ5≤95°, 85°≤θ6≤95°, 85°≤θ7≤95°, and 85°≤θ8≤95° indicate that the angles between the three epitaxial portions and the plane containing the substrate are moderate. This helps ensure that the first, second, and third epitaxial portions are located in their respective regions, thereby ensuring that the epitaxial portion corresponding to each region is relatively complete. It also prevents the epitaxial portions from covering or occupying other regions, which is beneficial to ensuring the performance of the semiconductor device.

[0099] Furthermore, in the prior art, during the etching process of the epitaxial structure, due to limitations in the etching process, the groove shape formed by etching in the epitaxial structure is similar to an "inverted trapezoid." Therefore, after filling the groove with material, the shape of the filling material is also similar to an "inverted trapezoid," and the angle between the filling material and the plane of the epitaxial structure and the substrate is not approximately perpendicular. In the embodiments of this application, the angles between the two sides of the third epitaxial portion 303, the first side abutting against the third epitaxial portion 303, and the plane of the substrate are all approximately perpendicular. This indicates that the side perpendicularity of the first epitaxial portion 301, the second epitaxial portion 302, and the third epitaxial portion 303 is good, meaning that the second epitaxial structure is not formed by an etching process but is prepared separately, thereby improving the performance of the semiconductor device.

[0100] Optionally, FIG2 is a cross-sectional schematic diagram of a semiconductor device provided in another exemplary embodiment of the present application. As shown in FIG2, the second channel portion 3022 and the third channel portion 3032 are integrally disposed.

[0101] Specifically, the second channel segment 3022 and the third channel segment 3032 are integrally formed. This means that the second channel segment 3022 and the third channel segment 3032 can be fabricated in the same process step, rather than being fabricated in separate time steps. This ensures a simpler fabrication process for the second channel segment 3022 and the third channel segment 3032, improving fabrication efficiency. It should be understood that although the second and third channel segments are formed integrally, the second epitaxial segment and the third epitaxial segment as a whole are still fabricated independently through a time-series process.

[0102] Optionally, FIG3 is a cross-sectional schematic diagram of a semiconductor device provided in another exemplary embodiment of the present application. As shown in FIG3, the second epitaxial structure 302 further includes a first spacing portion 3023 and a first cap layer portion 3024, and the third epitaxial structure 303 further includes a second spacing portion 3033 and a second cap layer portion 3034. The first spacing portion 3023 is located on the side of the first barrier portion 3021 close to the first epitaxial structure 20, and the first cap layer portion 3024 is located on the side of the first barrier portion 3021 away from the first epitaxial structure 20. The second spacing portion 3033 is located on the side of the second barrier portion 3031 close to the first epitaxial structure 20, and the second cap layer portion 3034 is located on the side of the second barrier portion 3031 away from the first epitaxial structure 20.

[0103] Specifically, in the second epitaxial portion 302, a first spacer layer 3023 is disposed between the first barrier portion 3021 and the first epitaxial structure 20. The material of the first spacer layer 3023 can be AlN, which can enhance the polarization effect and improve the electron density and mobility of two-dimensional electrons. The first cap layer portion 3024 is located on the side of the first barrier portion 3021 away from the first epitaxial structure 20. The first cap layer portion 3024 can reduce surface states, reduce surface leakage current of subsequent semiconductor devices, suppress current collapse, thereby improving the performance and reliability of the second epitaxial portion 302 and the semiconductor device.

[0104] Specifically, in the third epitaxial portion 303, a second spacer layer 3033 is disposed between the second barrier portion 3031 and the first epitaxial structure 20. The material of the second spacer layer 3033 can be AlN, which can enhance the polarization effect and improve the electron density and mobility of two-dimensional electrons. The second cap layer portion 3034 is located on the side of the second barrier portion 3031 away from the first epitaxial structure 20. The second cap layer portion 3034 can reduce surface states, reduce surface leakage current of subsequent semiconductor devices, and suppress current collapse, thereby improving the performance and reliability of the third epitaxial portion 303 and the semiconductor device.

[0105] Optionally, referring to Figure 1, the ohmic contact reinforcement structure 3011 includes n-type doped GaN, where the doping concentration N of the n-type doped GaN satisfies 1*10⁻⁶. 18 / cm 3 ≤N≤1*10 21 / cm 3 .

[0106] Specifically, the ohmic contact reinforcement structure 3011 includes n-type doped GaN, where the doping concentration N of the n-type doped GaN satisfies 1*10^2. 18 / cm 3 ≤N≤1*10 21 / cm 3 The high doping concentration of n-type GaN, which is heavily doped, helps ensure that the source 40 and drain 60 form an ohmic contact with the first epitaxial portion 301 when the source 40 and drain 60 are subsequently grown on the ohmic contact enhancement structure 3011. It also helps to reduce the ohmic contact resistance and thus improve the performance of the semiconductor device.

[0107] Optionally, continuing to refer to FIG1, the first epitaxial structure 20 includes a nucleation layer 203 and a buffer layer 202 stacked together, with the buffer layer 202 located on the side of the nucleation layer 203 away from the substrate 10.

[0108] Specifically, the first epitaxial structure 20 is required for the ohmic contact region 100, the Schottky contact region 200, and the intermediate region 300. Therefore, the nucleation layer 203 can be integrally formed, meaning that the nucleation layers 203 for the ohmic contact region 100, the Schottky contact region 200, and the intermediate region 300 are prepared simultaneously, not independently. Furthermore, the buffer layer 202 can also be integrally formed, meaning that the buffer layer 202 for the ohmic contact region 100, the Schottky contact region 200, and the intermediate region 300 are prepared simultaneously, not independently. This ensures consistent performance, structural stability, and a simple fabrication process for the first epitaxial structure 20.

[0109] Optionally, referring to FIG1, the semiconductor device further includes a source 40, a gate 50, and a drain 60; the source 40 and the drain 60 are located on the side of the first epitaxial portion 301 away from the substrate 10, and form ohmic contacts with the first epitaxial portion 301 respectively; the gate 50 is located on the side of the second epitaxial portion 302 away from the substrate 10, and forms a Schottky contact with the second epitaxial portion 302.

[0110] Specifically, both the source 40 and drain 60 can form ohmic contacts with the first epitaxial portion 301. For example, the source 40 can serve as the input terminal of the semiconductor device, and the drain 60 can serve as the output terminal. The gate 50 can serve as the control terminal of the semiconductor device, and the current flow between the source 40 and drain 60 can be controlled by adjusting the voltage of the gate 50. When a certain voltage is applied to the gate 50, a current is generated between the source 40 and drain 60, and the current between the source 40 and drain 60 can be controlled by changing the voltage of the gate 50.

[0111] In summary, the semiconductor device provided in this application embodiment has a first epitaxial portion, a second epitaxial portion, and a third epitaxial portion that are independently configured and fabricated in different processes. This facilitates the differentiation of the epitaxial structures corresponding to the ohmic contact region, the Schottky contact region, and the intermediate region in the semiconductor device, thereby improving the performance of the semiconductor device.

[0112] It should be understood that the embodiments of this application are based on the epitaxial structure design of semiconductor devices. The three epitaxial divisions are set independently and have structures corresponding to their respective positions. This can realize personalized and differentiated settings of the second epitaxial structure, thereby improving the performance of the semiconductor device. The semiconductor devices include, but are not limited to: high-power HEMTs operating in high-voltage, high-current environments; silicon-on-insulator (SOI) transistors; gallium arsenide (GaAs)-based transistors; and metal-oxide-semiconductor field-effect transistors (MOSFETs), metal-insulator-semiconductor field-effect transistors (MISFETs), double heterojunction field-effect transistors (DHFETs), junction field-effect transistors (JFETs), metal-semiconductor field-effect transistors (MESFETs), metal-insulator-semiconductor heterojunction field-effect transistors (MISHFETs), or other field-effect transistors. The semiconductor devices and manufacturing methods provided in this application can be widely used in the manufacturing of semiconductor devices such as radio frequency microwave and power electronics. They are particularly advantageous for gallium nitride electronic devices with large bandgap, high electron mobility, high breakdown field strength, and good thermal conductivity, and are better able to meet the high-performance requirements of rapidly developing fields such as electronic communications.

[0113] Based on the same concept, this application also provides a method for fabricating a semiconductor device. Figure 4 is a flowchart illustrating the method for fabricating a semiconductor device according to an exemplary embodiment of this application. As shown in Figure 4, the method for fabricating a semiconductor device according to this application includes:

[0114] S101, Provide a substrate and prepare a first epitaxial structure on one side of the substrate.

[0115] Specifically, a core layer, a buffer layer, and a channel layer are sequentially fabricated on one side of the substrate.

[0116] S102. The first epitaxial portion, the second epitaxial portion, and the third epitaxial portion are prepared in a time-division manner on the side of the first epitaxial structure away from the substrate to obtain a second epitaxial structure located on the side of the first epitaxial structure away from the substrate. The first epitaxial portion is located in the ohmic contact region of the semiconductor device, the second epitaxial portion is located in the Schottky contact region of the semiconductor device, and the third epitaxial portion is located in the middle region of the semiconductor device between the ohmic contact region and the Schottky contact region. The first epitaxial portion, the second epitaxial portion, and the third epitaxial portion are all independently set.

[0117] Furthermore, the first epitaxial portion, the second epitaxial portion, and the third epitaxial portion can be prepared in different processes.

[0118] Specifically, the first epitaxial portion, the second epitaxial portion, and the third epitaxial portion are fabricated sequentially on the side of the first epitaxial structure furthest from the substrate. In other words, the first, second, and third epitaxial portions are not fabricated simultaneously, but rather independently, time-divisionally. Put simply, the epitaxial portions corresponding to the ohmic contact region, the Schottky contact region, and the intermediate region are grown independently.

[0119] Specifically, referring to Figure 1, the ohmic contact region 100 can be understood as the region where an ohmic electrode is disposed, that is, the ohmic contact region may include a source setting region and a drain setting region. The Schottky contact region 200 can be understood as the region where a Schottky electrode is disposed, that is, the Schottky contact region 200 may be a gate setting region. The intermediate region 300 is located between the ohmic contact region 100 and the Schottky contact region 200.

[0120] Specifically, the first epitaxial portion 301, the second epitaxial portion 302, and the third epitaxial portion 303 are all independently configured and fabricated in different processes. In other words, the first epitaxial portion 301, the second epitaxial portion 302, and the third epitaxial portion 303 are not fabricated as a single unit; that is, the three epitaxial portions are not fabricated using the same process step, but are grown independently, i.e., they are fabricated in a time-division manner. As a comparison, in the prior art, after the epitaxial structure is fabricated as a single unit, an n-type doped GaN region is formed by etching the epitaxial structure to fabricate the source and drain electrodes above the n-type doped GaN region. However, the etching process can damage the epitaxial structure. However, in the embodiments of this application, the three epitaxial portions of the second epitaxial structure 30 are fabricated in a time-division manner. This eliminates the need for etching the epitaxial structure, allowing direct growth of n-type doped GaN in the first epitaxial portion, thus avoiding damage to the epitaxial structure and improving the performance of the semiconductor device.

[0121] The semiconductor device fabrication method provided in this application involves time-division multiplexing of the first epitaxial portion, the second epitaxial portion, and the third epitaxial portion. This ensures the independent growth of the second epitaxial structure, meaning the second epitaxial structure is not fabricated in a single process step but rather in three separate time-division epitaxial portions. This prevents damage or over-etching of the epitaxial structure during etching processes, thereby improving the performance of the semiconductor device. Furthermore, the independent arrangement of the three epitaxial portions facilitates differentiated configurations of the epitaxial structures corresponding to the ohmic contact region, Schottky contact region, and intermediate region within the semiconductor device, further enhancing its performance.

[0122] Optionally, Figure 5 is a schematic flowchart of a semiconductor device fabrication method provided in another exemplary embodiment of this application, and Figure 6 is a process flow diagram of the semiconductor device fabrication method corresponding to Figure 5. As shown in Figures 5 and 6, the semiconductor device fabrication method provided in this embodiment, based on the above embodiments, elaborates in detail the operations of fabricating the first epitaxial portion, fabricating the second epitaxial portion, and fabricating the third epitaxial portion. The semiconductor device fabrication method includes:

[0123] S201, Provide a substrate and prepare a first epitaxial structure on one side of the substrate.

[0124] Specifically, referring to step (a1) in Figure 6, a first epitaxial structure 20 is fabricated on one side of the substrate 10.

[0125] S202, A first mask layer is prepared on the side of the first epitaxial structure away from the substrate and in the Schottky contact region and the intermediate region, the first mask layer exposing the ohmic contact region.

[0126] Specifically, referring to step (b1) in Figure 6, a first mask layer 70 is prepared on the side of the first epitaxial structure 20 away from the substrate 10 and in the Schottky contact region 200 and the intermediate region 300. That is, the first mask layer 70 covers the upper surface of the first epitaxial structure 20 in the Schottky contact region 200 and the intermediate region 300, and the first mask layer 70 exposes the upper surface of the first epitaxial structure 20 in the ohmic contact region 100. This facilitates the continued preparation of the first epitaxial portion on the upper surface of the first epitaxial structure 20 in the ohmic contact region 100.

[0127] S203. A first channel portion and an ohmic contact reinforcement structure are sequentially fabricated on the side of the first epitaxial structure away from the substrate and in the ohmic contact region; the ohmic contact reinforcement structure is located on the side of the first channel portion away from the substrate.

[0128] In one example, both the first channel portion and the ohmic contact reinforcement structure are immiscible with the first mask layer.

[0129] Specifically, referring to step (c1) in Figure 6, the material of the first mask layer 70 includes at least one of silicon dioxide, silicon nitride, and amorphous silicon. For example, the thickness of the first mask layer 70 can be 10 nm to 200 nm. Since both the first channel portion 3012 and the ohmic contact reinforcement structure 3011 are immiscible with the first mask layer 70, meaning the first epitaxial portion 301 can selectively grow on the exposed upper surface of the first epitaxial structure 20 and will not grow on the upper surface covering the first mask layer 70, this facilitates the fabrication of the first epitaxial portion 301 in the ohmic contact region 100.

[0130] S204. Remove the first mask layer.

[0131] Specifically, referring to step (d1) in Figure 6, the first mask layer is removed.

[0132] S205. A second mask layer is prepared on the side of the first epitaxial structure away from the substrate and in the ohmic contact region and the intermediate region, the second mask layer exposing the Schottky contact region.

[0133] Specifically, referring to step (e1) in Figure 6, a second mask layer 80 is prepared on the side of the first epitaxial structure 20 away from the substrate 10, in the ohmic contact region 100 and the intermediate region 300. That is, the second mask layer 80 covers the upper surface of the first epitaxial portion 301 in the ohmic contact region 100, covers the upper surface of the first epitaxial structure 20 in the intermediate region 300, and exposes the upper surface of the first epitaxial structure 20 in the Schottky contact region 200. This facilitates the continued preparation of the second epitaxial portion on the upper surface of the first epitaxial structure 20 corresponding to the Schottky contact region 200.

[0134] S206. A second channel portion and a first barrier portion are sequentially prepared on the side of the first epitaxial structure away from the substrate and in the Schottky contact region; the first barrier portion is located on the side of the second channel portion away from the substrate.

[0135] In one example, both the second channel portion and the first barrier portion are immiscible with the second mask layer.

[0136] Specifically, referring to step (f1) in Figure 6, the material of the second mask layer 80 includes at least one of silicon dioxide, silicon nitride, and amorphous silicon. For example, the thickness of the second mask layer 80 can be 10 nm to 200 nm. Since both the first barrier portion 3021 and the second channel portion 3022 are immiscible with the second mask layer 80, meaning the second epitaxial portion 302 can grow on the exposed upper surface of the first epitaxial structure 20 and will not grow on the upper surface covering the second mask layer 80, this facilitates the fabrication of the second epitaxial portion 302 within the Schottky contact region 200.

[0137] S207. Remove the second mask layer.

[0138] Specifically, referring to step (g1) in Figure 6, the second mask layer is removed.

[0139] S208. A third mask layer is prepared on the side of the first epitaxial structure away from the substrate and in the ohmic contact region and the Schottky contact region, the third mask layer exposing the intermediate region.

[0140] Specifically, referring to step (h1) in Figure 6, a third mask layer 90 is prepared on the side of the first epitaxial structure 20 away from the substrate 10 and in the ohmic contact region 100 and the Schottky contact region 200. That is, the third mask layer 90 covers the upper surface of the first epitaxial portion 301 in the ohmic contact region 100 and covers the upper surface of the second epitaxial portion 302 in the Schottky contact region 200. The third mask layer 90 exposes the upper surface of the first epitaxial structure 20 in the middle region 300. This facilitates the continued preparation of the third epitaxial portion on the upper surface of the first epitaxial structure 20 corresponding to the middle region 300.

[0141] S209. A third channel portion and a second barrier portion are sequentially prepared on the side of the first epitaxial structure away from the substrate and in the middle region; the second barrier portion is located on the side of the third channel portion away from the substrate.

[0142] In one example, both the third channel portion and the second barrier portion are immiscible with the third mask layer.

[0143] Specifically, referring to step (j1) in Figure 6, the material of the third mask layer 90 includes at least one of silicon dioxide, silicon nitride, and amorphous silicon. For example, the thickness of the third mask layer 90 can be 10 nm to 200 nm. Since both the third channel portion 3032 and the second barrier portion 3031 are immiscible with the third mask layer 90, meaning the third epitaxial portion 303 can grow on the exposed upper surface of the first epitaxial structure 20 and will not grow on the upper surface covering the third mask layer 90, this facilitates the fabrication of the third epitaxial portion 303 in the intermediate region 300.

[0144] S210, Remove the third mask layer.

[0145] Specifically, refer to step (k1) in Figure 6 to remove the third mask layer.

[0146] The semiconductor device fabrication method provided in this application involves time-division multiplexing the fabrication of the first epitaxial segment, the second epitaxial segment, and the third epitaxial segment. A first mask layer, a second mask layer, and a third mask layer are used to cover a portion of the upper surface of the first epitaxial structure, respectively. The three epitaxial segments are then sequentially fabricated in the uncovered areas. This ensures the independent growth of the second epitaxial structure; that is, the second epitaxial structure is not fabricated in the same process step, but rather selected from three epitaxial segments. This prevents damage or over-etching of the epitaxial structure during etching, thereby improving the performance of the semiconductor device. Furthermore, the independent arrangement of the three epitaxial segments facilitates differentiated configurations of the epitaxial structures corresponding to the ohmic contact region, the Schottky contact region, and the intermediate region within the semiconductor device, further enhancing its performance.

[0147] For example, Figure 7 is a schematic flowchart of a semiconductor device fabrication method provided in another exemplary embodiment of this application, and Figure 8 is a process flow diagram of the semiconductor device fabrication corresponding to Figure 7. The fabrication sequence of the second epitaxial structure can be to first fabricate the third epitaxial portion, then fabricate the first epitaxial portion, and finally fabricate the second epitaxial portion. Specifically, as shown in Figures 7 and 8, the semiconductor device fabrication method includes:

[0148] S301, Provide a substrate and prepare a first epitaxial structure on one side of the substrate.

[0149] Specifically, as shown in step (a2) of Figure 8.

[0150] S302. A third mask layer is prepared on the side of the first epitaxial structure away from the substrate and in the ohmic contact region and the Schottky contact region, the third mask layer exposing the intermediate region.

[0151] Specifically, as shown in step (b2) of Figure 8.

[0152] S303. A third channel portion and a second barrier portion are sequentially prepared on the side of the first epitaxial structure away from the substrate and in the middle region; the second barrier portion is located on the side of the third channel portion away from the substrate; both the third channel portion and the second barrier portion are immiscible with the third mask layer.

[0153] Specifically, as shown in step (c2) of Figure 8.

[0154] S304, Remove the third mask layer.

[0155] Specifically, as shown in step (d2) of Figure 8.

[0156] S305. A first mask layer is prepared on the side of the first epitaxial structure away from the substrate and in the Schottky contact region and the intermediate region, wherein the first mask layer exposes the ohmic contact region.

[0157] Specifically, as shown in step (e2) of Figure 8.

[0158] S306. A first channel portion and an ohmic contact reinforcement structure are sequentially prepared on the side of the first epitaxial structure away from the substrate and in the ohmic contact region; the ohmic contact reinforcement structure is located on the side of the first channel portion away from the substrate; both the first channel portion and the ohmic contact reinforcement structure are immiscible with the first mask layer.

[0159] Specifically, as shown in step (f2) of Figure 8.

[0160] S307, Remove the first mask layer.

[0161] Specifically, as shown in step (g2) of Figure 8.

[0162] S308. A second mask layer is prepared on the side of the first epitaxial structure away from the substrate and in the ohmic contact region and the intermediate region, the second mask layer exposing the Schottky contact region.

[0163] Specifically, as shown in step (h2) of Figure 8.

[0164] S309. A second channel portion and a first barrier portion are sequentially prepared on the side of the first epitaxial structure away from the substrate and at the Schottky contact; the first barrier portion is located on the side of the second channel portion away from the substrate; both the second channel portion and the first barrier portion are immiscible with the second mask layer.

[0165] Specifically, as shown in step (j2) of Figure 8.

[0166] S310, Remove the second mask layer.

[0167] Specifically, as shown in step (k2) of Figure 8.

[0168] It should be noted that the embodiments of this application do not specifically limit the preparation of the first epitaxial portion, the second epitaxial portion, and the third epitaxial portion; they can be prepared separately.

[0169] Optionally, Figure 9 is a schematic flowchart of a semiconductor device fabrication method provided in another exemplary embodiment of this application, and Figure 10 is a process flow diagram of the semiconductor device fabrication method corresponding to Figure 9. As shown in Figures 9 and 10, the semiconductor device fabrication method provided in this embodiment, based on the above embodiments, elaborates in detail the operations of time-division multiplexing the fabrication of the first epitaxial portion, the fabrication of the second epitaxial portion, and the fabrication of the third epitaxial portion on the side of the first epitaxial structure away from the substrate. The semiconductor device fabrication method includes:

[0170] S401, Provide a substrate and prepare a first epitaxial structure on one side of the substrate.

[0171] Specifically, refer to step (a3) ​​in Figure 10.

[0172] S402, a fourth mask layer is prepared on the side of the first epitaxial structure away from the substrate and in the Schottky contact region and the intermediate region, the fourth mask layer exposing the ohmic contact region.

[0173] Specifically, referring to step (b3) in Figure 10, a fourth mask layer 400 is prepared on the side of the first epitaxial structure 20 away from the substrate 10 and in the Schottky contact region 200 and the intermediate region 300, the fourth mask layer 400 exposing the ohmic contact region 100.

[0174] S403. A first channel portion is prepared on the side of the first epitaxial structure away from the substrate and in the ohmic contact region.

[0175] Specifically, referring to step (c3) in Figure 10, the first channel portion 3012 is prepared.

[0176] S404. A fifth mask layer is prepared on the side of the first channel portion away from the substrate and on the side of the first epitaxial structure corresponding to the middle region away from the substrate. The fifth mask layer exposes the Schottky contact region.

[0177] Specifically, after removing the fourth mask layer, referring to step (d3) in Figure 10, a fifth mask layer 500 is prepared on the side of the first channel portion 3012 away from the substrate 10 and on the side of the first epitaxial structure 20 corresponding to the middle region 300 away from the substrate 10. The fifth mask layer 500 exposes the Schottky contact region 200.

[0178] S405. Prepare a second channel portion on the side of the first epitaxial structure away from the substrate and in the Schottky contact region.

[0179] Specifically, referring to step (e3) in Figure 10, the second channel portion 3022 is prepared.

[0180] S406. A sixth mask layer is prepared on the side of the first communication portion and the second channel portion away from the substrate, and the sixth mask layer exposes the middle region.

[0181] Specifically, after removing the fifth mask layer, referring to step (f3) in Figure 10, a sixth mask layer 600 is prepared on the side of the first communication portion 3012 and the second channel portion 3022 away from the substrate 10, and the sixth mask layer 600 exposes the middle region 300.

[0182] S407. A third channel portion is prepared on the side of the first epitaxial structure away from the substrate and in the middle region.

[0183] Specifically, referring to step (g3) in Figure 10, the third channel portion 3032 is prepared.

[0184] S408. A seventh mask layer is prepared on the side of the second and third channel portions away from the substrate, exposing the ohmic contact region.

[0185] Specifically, after removing the sixth mask layer, referring to step (k3) in Figure 10, a seventh mask layer 700 is prepared on the side of the second channel portion 3022 and the third channel portion 3032 away from the substrate 10, and the seventh mask layer 700 exposes the ohmic contact region 100.

[0186] S409. An ohmic contact reinforcement structure is prepared on the side of the first channel portion away from the substrate.

[0187] Specifically, referring to step (j3) in Figure 10, the ohmic contact reinforcement structure 3011 is prepared.

[0188] S410. An eighth mask layer is prepared on the side of the ohmic contact reinforcement structure and the third channel portion away from the substrate, exposing the Schottky contact region.

[0189] Specifically, after removing the seventh mask layer, referring to step (k3) in Figure 10, an eighth mask layer 800 is prepared on the side of the ohmic contact reinforcement structure 3011 and the third channel portion 3032 away from the substrate 10, and the eighth mask layer 800 exposes the Schottky contact region 200.

[0190] S411. A first barrier portion is prepared on the side of the second channel portion away from the substrate and in the Schottky contact region.

[0191] Specifically, referring to step (l 3) in Figure 10, the first barrier portion 3021 is prepared.

[0192] S412. A ninth mask layer is prepared on the side of the ohmic contact reinforcement structure and the first barrier portion away from the substrate, exposing the middle region.

[0193] Specifically, after removing the eighth mask layer, referring to step (m3) in Figure 10, a ninth mask layer 900 is prepared on the side of the ohmic contact reinforcement structure 3011 and the first barrier portion 3021 away from the substrate 10, and the ninth mask layer 900 exposes the middle region 300.

[0194] S413. A second barrier portion is prepared on the side of the third channel portion away from the substrate and in the middle region.

[0195] Specifically, referring to step (n3) in Figure 10, the second barrier portion 3031 is prepared.

[0196] It should be noted that after the second barrier portion 3031 is prepared, the ninth mask layer is removed.

[0197] It should be noted that the present application does not specify the preparation order of the first channel portion, the second channel portion, and the third channel portion.

[0198] The semiconductor device fabrication method provided in this application firstly fabricates the first channel portion, the second channel portion, and the third channel portion corresponding to the first epitaxial portion, the second epitaxial portion, and the third epitaxial portion in a time-division manner. Then, it fabricates the ohmic contact enhancement structure, the first barrier portion, and the second barrier portion corresponding to the first epitaxial portion, the second epitaxial portion, and the third epitaxial portion in a time-division manner. This enables the fabrication of the second epitaxial structure, ensuring the independent growth of the second epitaxial structure. This is beneficial for achieving differentiated settings of the epitaxial structures corresponding to the ohmic contact region, the Schottky contact region, and the intermediate region in the semiconductor device, thereby improving the performance of the semiconductor device.

[0199] Optionally, Figure 11 is a schematic flowchart of a method for fabricating a semiconductor device according to another exemplary embodiment of this application. As shown in Figure 11, the method for fabricating the semiconductor device includes:

[0200] S501, Provide a substrate and prepare a first epitaxial structure on one side of the substrate.

[0201] S502. The first epitaxial portion, the second epitaxial portion, and the third epitaxial portion are prepared in a time-division manner on the side of the first epitaxial structure away from the substrate to obtain a second epitaxial structure located on the side of the first epitaxial structure away from the substrate. The first epitaxial portion is located in the ohmic contact region of the semiconductor device, the second epitaxial portion is located in the Schottky contact region of the semiconductor device, and the third epitaxial portion is located in the middle region of the semiconductor device between the ohmic contact region and the Schottky contact region. The first epitaxial portion, the second epitaxial portion, and the third epitaxial portion are all independently set and prepared in different processes.

[0202] S503. A source and a drain are prepared on the side of the first epitaxial portion away from the substrate, and the source and drain form ohmic contacts with the first epitaxial portion, respectively.

[0203] Specifically, referring to Figure 1, after the second epitaxial structure 30 is fabricated, a source electrode 40 and a drain electrode 60 are fabricated on the upper surface of the first epitaxial portion 301, and the source electrode 40 and the drain electrode 60 form ohmic contacts with the first epitaxial portion 301, respectively.

[0204] S504. A gate is prepared on the side of the second epitaxial portion away from the substrate, and the gate forms a Schottky contact with the second epitaxial portion.

[0205] Specifically, referring to Figure 1, after the second epitaxial structure 30 is fabricated, a gate 50 is fabricated on the upper surface of the second epitaxial portion 302, and the gate 50 forms a Schottky contact with the second epitaxial portion 302.

[0206] The semiconductor device fabrication method provided in this application embodiment can fabricate the source and drain on the first epitaxial portion and the gate on the second epitaxial portion after the second epitaxial structure is fabricated, thereby completing the overall fabrication of the semiconductor device.

[0207] Note that the above description is merely a preferred embodiment and the technical principles employed in this application. Those skilled in the art will understand that this application is not limited to the specific embodiments described herein, and various obvious changes, readjustments, combinations, and substitutions can be made without departing from the scope of protection of this application. Therefore, although this application has been described in detail through the above embodiments, this application is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of this application, the scope of which is determined by the scope of the appended claims.

Claims

1. A semiconductor device, characterized in that, The semiconductor device has an ohmic contact region, a Schottky contact region, and an intermediate region between the ohmic contact region and the Schottky contact region; The semiconductor device includes: Substrate; A first epitaxial structure located on one side of the substrate; A second epitaxial structure is located on the side of the first epitaxial structure away from the substrate. The second epitaxial structure includes a first epitaxial portion, a second epitaxial portion, and a third epitaxial portion. The first epitaxial portion is located in the ohmic contact region, the second epitaxial portion is located in the Schottky contact region, and the third epitaxial portion is located in the intermediate region. The first epitaxial portion, the second epitaxial portion, and the third epitaxial portion are all independently configured.

2. The semiconductor device according to claim 1, characterized in that, The first epitaxial portion includes a first channel portion and an ohmic contact enhancement structure stacked together; the ohmic contact enhancement structure is located on the side of the first channel portion away from the substrate; The second epitaxial portion includes a second channel portion and a first barrier portion stacked together; the first barrier portion is located on the side of the second channel portion away from the substrate; The third epitaxial portion includes a third channel portion and a second barrier portion stacked together; the second barrier portion is located on the side of the third channel portion away from the substrate; The thickness of the first channel section is less than the thickness of the second channel section and less than the thickness of the third channel section.

3. The semiconductor device according to claim 2, characterized in that, A first carrier layer is formed between the first barrier portion and the second channel portion, and a second carrier layer is formed between the second barrier portion and the third channel portion; The distance between the surface of the ohmic contact enhancement structure closest to the substrate and the substrate is less than the distance between the first charge carrier layer and the second charge carrier layer and the substrate.

4. The semiconductor device according to claim 2 or 3, characterized in that, The ohmic contact enhancement structure, the first barrier portion, and the second barrier portion are all independently configured and prepared in different processes; The thickness of the first barrier portion is less than the thickness of the second barrier portion.

5. The semiconductor device according to any one of claims 2 to 4, characterized in that, The first channel segment, the second channel segment, and the third channel segment are all independently constructed and prepared in different processes.

6. The semiconductor device according to claim 4, characterized in that, The second channel section and the third channel section are integrally formed.

7. The semiconductor device according to any one of claims 2 to 6, characterized in that, The first epitaxial portion has a first side surface near the third epitaxial portion, the second epitaxial portion has a second side surface near the third epitaxial portion, and the third epitaxial portion has a third side surface near the first epitaxial portion and a fourth side surface near the second epitaxial portion. The first side and the third side abut against each other, and the second side and the fourth side abut against each other.

8. The semiconductor device according to claim 7, characterized in that, The first side surface includes a first sub-side surface and a second sub-side surface; the first sub-side surface is the surface of the first channel portion near the third channel portion; the second sub-side surface is the surface of the ohmic contact enhancement structure near the second barrier portion; the angle θ1 between the first sub-side surface and the plane where the substrate is located satisfies 85°≤θ1≤95°; the angle θ2 between the second sub-side surface and the plane where the substrate is located satisfies 85°≤θ2≤95°; The second side surface includes a third sub-side surface and a fourth sub-side surface; the third sub-side surface is the surface of the second channel portion near the third channel portion; the fourth sub-side surface is the surface of the first barrier portion near the second barrier portion; the angle θ3 between the third sub-side surface and the plane where the substrate is located satisfies 85°≤θ3≤95°; the angle θ4 between the fourth sub-side surface and the plane where the substrate is located satisfies 85°≤θ4≤95°; The third side surface includes a fifth sub-side surface and a sixth sub-side surface; the fifth sub-side surface is the surface of the third channel portion near the first channel portion; the sixth sub-side surface is the surface of the second barrier portion near the ohmic contact enhancement structure; the angle θ5 between the fifth sub-side surface and the plane where the substrate is located satisfies 85°≤θ5≤95°; the angle θ6 between the sixth sub-side surface and the plane where the substrate is located satisfies 85°≤θ6≤95°; The fourth side surface includes a seventh sub-side surface and an eighth sub-side surface; the seventh sub-side surface is the surface of the third channel portion near the second channel portion; the eighth sub-side surface is the surface of the second barrier portion near the first barrier portion; the angle θ7 between the seventh sub-side surface and the plane where the substrate is located satisfies 85°≤θ7≤95°; the angle θ8 between the eighth sub-side surface and the plane where the substrate is located satisfies 85°≤θ8≤95°.

9. The semiconductor device according to any one of claims 2 to 8, characterized in that, The ohmic contact enhancement structure comprises n-type doped GaN, wherein the doping concentration N of the n-type doped GaN satisfies 1*10^2. 18 / cm 3 ≤N≤1*10 21 / cm 3 .

10. A method for fabricating a semiconductor device, characterized in that, include: A substrate is provided, and a first epitaxial structure is fabricated on one side of the substrate; A first epitaxial portion, a second epitaxial portion, and a third epitaxial portion are prepared in a time-division manner on the side of the first epitaxial structure away from the substrate to obtain a second epitaxial structure located on the side of the first epitaxial structure away from the substrate. The first epitaxial portion is located in the ohmic contact region of the semiconductor device, the second epitaxial portion is located in the Schottky contact region of the semiconductor device, and the third epitaxial portion is located in the intermediate region of the semiconductor device between the ohmic contact region and the Schottky contact region. The first epitaxial portion, the second epitaxial portion, and the third epitaxial portion are all independently configured.

11. The preparation method according to claim 10, characterized in that, The first epitaxial portion, the second epitaxial portion, and the third epitaxial portion are prepared in different processes.

12. The preparation method according to claim 10 or 11, characterized in that, The preparation of the first epitaxial portion includes: A first mask layer is prepared on the side of the first epitaxial structure away from the substrate and in the Schottky contact region and the intermediate region, the first mask layer exposing the ohmic contact region; A first channel portion and an ohmic contact reinforcement structure are sequentially formed on the side of the first epitaxial structure away from the substrate and in the ohmic contact region; the ohmic contact reinforcement structure is located on the side of the first channel portion away from the substrate.

13. The preparation method according to any one of claims 10 to 12, characterized in that, The preparation of the second epitaxial portion includes: A second mask layer is prepared on the side of the first epitaxial structure away from the substrate and in the ohmic contact region and the intermediate region, the second mask layer exposing the Schottky contact region; A second channel portion and a first barrier portion are sequentially formed on the side of the first epitaxial structure away from the substrate and in the Schottky contact region; the first barrier portion is located on the side of the second channel portion away from the substrate.

14. The preparation method according to any one of claims 10 to 13, characterized in that, The preparation of the third epitaxial portion includes: A third mask layer is prepared on the side of the first epitaxial structure away from the substrate and in the ohmic contact region and the Schottky contact region, the third mask layer exposing the intermediate region; A third channel portion and a second barrier portion are sequentially formed on the side of the first epitaxial structure away from the substrate and in the middle region; the second barrier portion is located on the side of the third channel portion away from the substrate.

15. The preparation method according to claim 10 or 11, characterized in that, The first epitaxial portion, the second epitaxial portion, and the third epitaxial portion are fabricated in a time-division manner on the side of the first epitaxial structure away from the substrate, including: A fourth mask layer is prepared on the side of the first epitaxial structure away from the substrate and in the Schottky contact region and the intermediate region, the fourth mask layer exposing the ohmic contact region; A first channel portion is formed on the side of the first epitaxial structure away from the substrate and in the ohmic contact region; A fifth mask layer is prepared on the side of the first channel portion away from the substrate and on the side of the first epitaxial structure corresponding to the intermediate region away from the substrate, the fifth mask layer exposing the Schottky contact region; A second channel portion is formed on the side of the first epitaxial structure away from the substrate and in the Schottky contact region; A sixth mask layer is prepared on the side of the first communication portion and the second channel portion away from the substrate, the sixth mask layer exposing the intermediate region; A third channel portion is formed on the side of the first epitaxial structure away from the substrate and in the middle region; A seventh mask layer is prepared on the side of the second channel portion and the third channel portion away from the substrate, the seventh mask layer exposing the ohmic contact region; An ohmic contact enhancement structure is prepared on the side of the first channel portion away from the substrate; An eighth mask layer is prepared on the side of the ohmic contact enhancement structure and the third channel portion away from the substrate, the eighth mask layer exposing the Schottky contact region; A first barrier portion is formed on the side of the second channel portion away from the substrate and in the Schottky contact region; A ninth mask layer is prepared on the side of the ohmic contact enhancement structure and the first barrier portion away from the substrate, the ninth mask layer exposing the intermediate region; A second barrier portion is formed on the side of the third channel portion away from the substrate and in the middle region.

Images