Electrostatic discharge protection device with improved timing

Abstract

An electrostatic discharge, ESD, protection device coupled between a first node and a second node, said ESD protection device comprising: a first branch between the first node and the second node, said first branch comprising a switching device with an activation node; and a second branch between the first node and the second node, said second branch comprising a triggering device coupled to the activation node of the switching device and configured to switch on the switching device during an ESD event, wherein said triggering device comprises: a transient detector having an output node, and a buffering device having an input node coupled to the output node of the transient detector, and having an output node coupled to the activation node, wherein the buffering device further comprises a current limiting device configured to limit a discharge current from the activation node to the first node or the second node.

Description

[0001] ELECTROSTATIC DISCHARGE PROTECTION DEVICE WITH IMPROVED TIMING

[0002] FIELD OF THE INVENTION

[0003] The invention generally relates to electrostatic discharge (ESD) protection devices, and in particular to ESD protection devices with a switching device and a triggering device.

[0004] BACKGROUND

[0005] During ESD, large currents can flow through an integrated circuit (IC) which can potentially cause damage. Damage can occur within the devices that conduct the current, as well as in devices that are subjected to a significant voltage drop due to the large current flow. To avoid damage caused by an ESD event, an ESD protection device is added to the IC. These ESD protection devices are configured to shunt the large ESD currents without causing high voltage over sensitive nodes of the IC.

[0006] Figures la-lc depict conventional ESD protection devices. Each of these conventional ESD protection devices comprises a switching device 110, for example consisting of an NMOS transistor, and a transient triggering device 500 configured to switch on the switching device 110 during an ESD event. Herein, the switching device 110 and the transient triggering device 500 are connected in parallel between the node to be protected, here called the first node A, and a second node B. As such, these conventional ESD protection devices in fact comprise a first branch 100 and a second branch 200 coupled between the first node A and the second node B, wherein the first branch 100 consists of the switching device 110 and the second branch 200 consists of the transient triggering device 500.

[0007] This transient triggering device 500 comprises a transient detector 300, as well as an output node 430 coupled to an activation node 120 of the switching device 110. Said activation node is formed by the gate of the switching device in case the switching device consists of an NMOS transistor. The transient detector 300 typically consists of a series connection of a resistive element, for example a resistor 310, and a capacitive element, for example a capacitor 320.

[0008] In the device of Figure la, the output node 430 of the triggering device 500 is formed by an intermediate node between the resistor 310 and the capacitor 320. In the devices of Figures lb and 1c on the other hand, the transient triggering device 500 further comprises a buffering device 400 with an input node 420 which is connected to an intermediate node 330 between the resistor 310 and the capacitor 320, and with an output node which forms the output node 430 of the transienttriggering device 500. Said buffering device 400 comprises an inverting device consisting of a stack of a PMOS transistor 510 and an NMOS transistor 520, wherein the PMOS transistor 510 is coupled between the first node A and the output node 430, the NMOS transistor is coupled between the output node 430 and the second node B, and the input node 420 is coupled to the gate of the PMOS transistor 510 and to the gate of the NMOS transistor 520. In Figure lb, the buffering device 400 solely consists of the described inverting device, whereas in Figure 1c, the buffering device 400 comprises, apart from the described inverting device, a second inverting device 600 whose output node 431 is connected to the gates of the transistors 510 and 520.

[0009] The functionality of these conventional ESD protection devices can be summarized as follows. When an ESD event occurs, a transient signal is generated by the transient detector 300, which creates a transient current through capacitor 320. This in turn causes a voltage surge over resistor 310. In case said voltage surge exceeds the threshold voltage of the switching device 110, said switching device is consequently switched on, thereby allowing excessive charges to run from the first node A via the switching device 110 to the second node B, and as such shunting the large ESD currents. Consequently, in order for the ESD protection device to safely shunt said ESD currents without causing any damage on sensitive nodes in the IC, it is crucial for the triggering device 500 to deliver a sufficiently high voltage surge to the switching device 110 during a sufficiently long period of time.

[0010] In the simple RC-circuit formed by the device of Figure la, the time constant indicating the duration of time during which the transient detector 300 delivers a high voltage, is calculated as the product of the resistance R of the resistor 310 (in Ohm) and the capacitance C of the capacitor 320 (in Farad). The described requirements for the triggering device 500 translate into a high value for said time constant, and thus into high values for R and C, and disadvantageously large dimensions for both the resistor 310 and the capacitor 320.

[0011] Moreover, large dimensions are also required for the switching device 110, typically a MOS transistor, as it must be configured to shunt large currents. As a result, the switching device’s internal capacitances, such as the gate-to-drain capacitance and the gate-to-source capacitance in case the switching device 110 is a MOS transistor, are so high that in order for the switching device 110 to remain switched on during an ESD event, a considerable amount of current must be provided to said switching device. Simple transient triggering devices 500 like the one of Figure la, may not be capable of delivering such high currents during the full duration of the ESD event, thus resulting in the switching device 110 being repeatedly switched on and off during a transient. Consequently, the desired protection against ESD damage cannot be guaranteed.ESD protection devices comprising a buffering device 400 with a single or multiple inverting devices 600, like the ones of Figures lb and 1c respectively, have the benefit that the voltage level on the activation node 120 of the switching device 110 is not directly provided by the transient detector 300 as in Figure la, but is rather amplified by the inverting device(s). As a result, the dimensional requirements on the resistor 310 and the capacitor 320 are somewhat reduced. Nevertheless, the required amounts of current remain higher than the typical transient detectors 300 are able to deliver, thus still resulting in said detrimental effect of the switching device 110 being repeatedly switched on and off again. Indeed, not only do the required physical dimensions of the switching device 110, despite the addition of inverting device(s) 600, remain considerable, also the transistors 510 and 520 comprised in the buffering device 400 must be of significant dimensions in order for said transistors to withstand large charging and discharging currents. Indeed, the voltage amplification created by the inverting device(s) of the buffering device 400 of Figures lb and 1c, allows for the values R and C (associated with the resistor 310 and the capacitor 320) to be optimized for area reduction compared to Figure la, but such optimization comes with an increased risk of the switching device 110 switching off too early, i.e. before the end of the ESD event, so that the level of protection against ESD damage is undesirably reduced.

[0012] SUMMARY

[0013] The object of embodiments of the invention is to provide an electrostatic discharge (ESD) protection device which reduces the above-described disadvantages of existing technologies, without compromising protective functionality, while at the same time allowing to reduce the surface area required to implement the different components, notably the triggering device, of the ESD protection device, and / or allowing to implement more recent and more advanced transistor technologies in said ESD protection device and / or improve the triggering capabilities of said triggering device.

[0014] According to a first aspect, an electrostatic discharge (ESD) protection device is provided, which is coupled between a first node and a second node. Said ESD protection device comprises a first branch between the first node and the second node, said first branch comprising a switching device with an activation node, and comprises a second branch between the first node and the second node, said second branch comprising a triggering device coupled to the activation node of the switching device and configured to switch on the switching device during an ESD event. Said triggering device comprises a transient detector having an output node, and a buffering device having an input node coupled to the output node of the transient detector, and having an output node coupled to the activation node. The buffering device further comprises a current limiting device configured to limit a discharge current from the activation node to the first node or the second node.Compared to the above-described conventional ESD protection devices, the advantageous component of the claimed ESD protection device is the current limiting device. In principle, the functionality of this ESD protection device is to a large extent similar to that of the above-described conventional devices. When an ESD event occurs, said event is detected by the transient detector, causing the triggering device to switch on the switching device. As explained above, in order to guarantee protection of sensitive nodes against ESD damage, it is crucial for the triggering device to deliver a sufficiently strong signal to keep the switching device activated during a sufficiently long period of time, i.e. so that it is capable of shunting ESD currents until the ESD event has come to an end.

[0015] This is precisely the functionality that is offered by the current limiting device. Indeed, the current limiting device is configured to limit a discharge current from the activation node to the first node or the second node. As such, it has the effect of delaying the point in time when the switching device switches off. Indeed, once the switching device has switched on as a result of the signal received from the triggering device, its internal capacitance starts to be charged. Said internal capacitance may, for instance, be the gate-source capacitance if the switching device is a MOS transistor, and may be the junction capacitance if the switching device is a bipolar transistor. At some point in time, possibly prior to the end of the ESD event, the triggering device ceases to generate said signal, so that the internal capacitance of the switching device is no longer being charged, and starts to discharge by allowing a discharge current to run from the activation node to the first node or to the second node. The current limiting device actively delays this discharging process by limiting said discharge current, i.e. by limiting the amount of built up charge that is able to escape from the activation node of the switching device per unit of time. Thereby, the total duration of time during which the switching device remains switched on is prolonged beyond the point in time where the triggering device ceases to generate its signal.

[0016] Such an ESD protection device has the advantage that compared to conventional ESD protection devices, the switching device remains switched on during a longer period of time, in particular during the full duration of a typical ESD event, without the undesirable behavior of repeatedly switching off and back on again. In other words, the triggering capabilities of the corresponding triggering device are improved. As such, it is guaranteed that sensitive nodes in the considered IC remain protected during the full duration of such an ESD event, since during said entire duration large ESD currents are shunted, as excessive charges may pass through the device from the first node via the switching device to the second node.

[0017] Furthermore, the physical dimensions of the components of the transient detector, and thus also the dimensions of the entire resulting chip, may be reduced compared to conventional devices, without thereby adversely affecting the timing of the discharging process. Indeed, thanks to the above-described prolongation of the relevant time duration beyond the time constant of the transient detector, it suffices for the latter time constant to merely cover the beginning of the ESD event, rather than the entire ESD event as would be needed in conventional existing devices. Consequently, the ESD protection device may be implemented with a transient detector which is smaller in size, in particular in surface area, and thus has a smaller time constant, compared to prior art alternatives. In effect, an ESD protection device with the described properties has two different time constants, namely a first time constant for the charging process and a second time constant for the discharging process, where the former is mainly determined by the transient detector, whereas the latter is to a large extent determined by the current limiting device. The present invention allows the time constant for the charging process to be smaller than the time constant for the discharging process, and in particular smaller than that of conventional ESD protection devices. This has the advantage that the start-up phase of the power supply, during which the voltage over the chip builds up from 0 V to normal operation values, and during which typically large amounts of current are dissipated, is shortened in duration, without compromising the protection against ESD events.

[0018] In a preferred embodiment, the current limiting device comprises a resistive element, preferably a resistive element which is coupled between the activation node and the first node or the second node. Such an ESD protection device may then be obtained by altering any of the described conventional ESD protection devices by adding a resistive element along the path that is typically followed by the discharge current from the activation node to the first or second node, for example by coupling said resistive element between the respective nodes. This will have the effect of increasing the total resistance along said current path without significantly altering the voltage, so that the discharge current that passes along said path is effectively lowered.

[0019] The higher the resistance associated with said resistive element, the stronger will be the corresponding reduction in current value, and hence the longer it will take for the charge built up on the internal capacitance of the switching device to reach the first or second node. Consequently, in order to increase the time constant for the discharging process, it is beneficial to choose a resistive element with sufficiently high resistance as the current limiting device. On the other hand, a higher resistance typically gives rise to an increase in surface area needed to implement the current limiting device, which is to be avoided when aiming to make the ESD protection device as small as possible in size.

[0020] Said resistive element preferably comprises a resistor, or a MOS transistor configured to be low resistive during an ESD event, high resistive immediately after an ESD event, and low resistive during normal operation. Both of these options have the effect of limiting the discharge current that runs from the activation node to the first or second node after an ESD event. Indeed, when an ESDevent occurs, the internal capacitance of the switching device will first be charged as long as it receives a signal from the triggering device, and will only afterwards, when the triggering device ceases to generate a sufficiently strong signal, start to discharge. As such, in order for the resistive element to be capable of limiting the resulting discharge currents, it suffices for the resistive element to be high resistive only during said second phase immediately after the ESD event.

[0021] A resistor substantially maintains its resistance over time, so that the above requirement is certainly fulfilled for resistive elements comprising a resistor. For resistive elements comprising a MOS transistor, said requirement is fulfilled when said MOS transistor is configured to be high resistive immediately after an ESD event. In order to make sure that during normal operation, the ESD protection device is only turned on for a short period of time, it is beneficial for the MOS transistor to be configured to be low resistive during an ESD event and during normal operation.

[0022] This may be achieved by coupling said MOS transistor to an internal node which allows the MOS transistor to detect, on the basis of the enable / disable signals it receives from said node, whether the power supply of the IC is on or off, with the former corresponding to normal operation and the latter corresponding to the critical periods in time when discharge following an ESD event may occur. The MOS transistor is then configured to be either low or high resistive, depending on the outcome of said detection, namely low resistive when it detects that the power supply is on, and high resistive when it detects that the power supply is off.

[0023] According to a preferred embodiment, the switching device comprises, preferably consists of, a transistor, preferably a MOS transistor having a gate corresponding with the activation node. Indeed, transistors are highly effective switching devices configured to be switched on when a certain threshold voltage is surpassed. In the present device, said voltage is delivered by the triggering device when an ESD event occurs.

[0024] In case the switching device comprises a MOS transistor with a gate corresponding to the activation node, as preferred, the discussed charging / discharging process amounts to the charging / discharging of the internal capacitance of said gate, and the timing of said charging / discharging is reflected in the evolution over time of the gate voltage. More precisely, the slower the discharging process of the gate, the longer the voltage on the gate remains at a high value.

[0025] The buffering device preferably comprises a stack of a PMOS transistor and an NMOS transistor. Indeed, these transistors are then configured to act as switching devices, which, as part of the buffering device which is coupled to the transient detector, are configured to switch on and thus start conducting when a sufficiently strong signal is received from the transient detector. Once the transient detector ceases to generate a sufficiently strong signal, typically one of the two transistors will switch off, while the other will remain active during a longer period of time and as such becapable of conducting the discharge current. In particular, the path followed by said discharge current will lead from the activation node via said longest-conducting transistor to either the first node or the second node, depending on which of these two nodes said transistor is coupled to. Said transistor configured to remain in a conducting state during a longer time period may be either the PMOS transistor of the NMOS transistor of the stack, depending on the nature of the switching device. The conventional ESD protection devices discussed above also comprise at least one stack of a PMOS transistor and an NMOS transistor. The main characterizing feature of the considered preferred embodiments of the present invention is the fact that these comprise, apart from said stack, also a current limiting device as part of the buffering device. Compared to said conventional ESD protection devices, said current limiting device aids in increasing the extent of freedom one has in tuning the transistors of said stack, thereby rendering the resulting ESD protection devices more suitable for the implementation of the most recent and advanced transistor technologies. Indeed, said most recent and advanced transistor technologies, such as FinFET transistors and gate-all-around transistors, come with more severe restrictions in gate length and / or gate width, and thus less tunability, compared to older transistor technologies. The insertion of a current limiting device into the buffering device, coupled to or in between the stack of a PMOS transistor and an NMOS transistor, allows the transistors in the stack to be tuned when correspondingly tuning the current limiting device as well. Consequently, ESD protection devices equipped with such a current limiting device are configured to be more efficient than prior art alternatives when implemented with said most recent and most advanced types of transistors.

[0026] In a preferred embodiment, the transient detector comprises a resistive element and a capacitive element connected in series between the first node and the second node, and wherein the output node of the transient detector is an intermediate node between said resistive element and said capacitive element. Such a configuration of a resistive element and a capacitive element is configured to act as a transient detector, and thus a detector of ESD events, thanks to the following functionality. When an ESD event occurs, a high voltage is installed between the first node and the second node. The resistive element and capacitive element, which are connected in series between said nodes, sense this high voltage and react to it by creating a transient current through the capacitive element and a voltage surge over the resistive element. The signal corresponding with said transient current and voltage surge are amplified by the buffering device before they reach the switching device. The amplified signal then activates the switching device, thereby allowing it to shunt the large ESD currents from the first to the second node.

[0027] When such transient detectors are combined with the previously described feature that the buffering device comprises a stack of a PMOS and an NMOS transistor, typically one of both transistors will be coupled to the resistive device, whereas the other will be coupled to the capacitive device. Duringthe discharging of the switching device, the latter of the two transistors will remain in a conducting state during a longer period of time than the former transistor, since during discharge of the switching device, the capacitive element will discharge as well and meanwhile deliver to the transistor it is coupled to, a sufficiently high voltage for said transistor to remain activated and thus to conduct the activation node’s discharge current.

[0028] In what follows, we will first describe a first preferred embodiment wherein the current limiting device is configured to limit a discharge current from the activation node to the second node, and subsequently we will describe in parallel a second preferred embodiment wherein the current limiting device is configured to limit a discharge current from the activation node to the first node.

[0029] According to said first preferred embodiment, the switching device comprises an NMOS transistor, and the buffering device comprises a PMOS transistor which is coupled between the first node and the output node of the buffering device, as well as a stack of the current limiting device and an NMOS transistor, which stack is connected between the output node of the buffering device and the second node. The output node of the transient detector is coupled to the gate of the PMOS transistor and to the gate of the NMOS transistor, and the current limiting device is configured to limit a discharge current from the activation node to the second node.

[0030] When an ESD event occurs in an ESD protection device according to this first preferred embodiment, the transient detector generates a signal to the buffering device which cause the gate capacitances of the PMOS transistor and the NMOS transistor of the buffering device to start charging, and moreover said transistors transmit said signal in an amplified way to the NMOS transistor of the switching device. This causes said NMOS transistor to switch on in case the corresponding voltage surge over this transistor exceeds its threshold voltage, so that its internal gate capacitance starts to be charged. Subsequently, when the transient detector ceases to generate a sufficiently strong signal, the gate of the NMOS transistor of the switching device starts to discharge via the stack of the current limiting device and the NMOS transistor of the buffering device. Since said stack is coupled to the second node in these embodiments, the corresponding discharge current will run from the activation node, which consists of or is coupled to the gate of the NMOS transistor of the switching device, towards the second node. As a result, in these embodiments the discharge current which is being limited by the current limiting device is a discharge current from the activation node to the second node.

[0031] In a first preferred variant of said first preferred embodiment, the output node of the transient detector is directly connected to the gate of the PMOS transistor and to the gate of the NMOS transistor, and the transient detector comprises a resistive element which is coupled between the first node and theoutput node of the transient detector, as well as a capacitive element which is coupled between the output node of the transient detector and the second node.

[0032] This implies that the PMOS transistor of the buffering device is coupled to the resistive element, in such a way that said PMOS transistor and said resistive element are coupled in parallel between the first node and the output node of the transient detector, whereas the NMOS transistor of the buffering device is coupled to the capacitive element, in such a way that said NMOS transistor and said capacitive element are coupled in parallel between the output node of the transient detector and the second node. As such, once the NMOS transistor of the switching device starts to discharge, the PMOS transistor of the buffering device will switch off and cease to conduct any current, whereas the NMOS transistor of the buffering device will remain activated for a longer period of time, precisely because the latter transistor is coupled to the capacitive element of the transient detector, whereas the former transistor is not. Indeed, during charging of the switching device, a charge has also been building up on this capacitive element, so that once the discharging of the switching device has been initiated, said capacitive element continues to deliver a sufficient voltage to the NMOS transistor of the switching device during a short yet significant time.

[0033] In a second preferred variant of said first preferred embodiment, the buffering device further comprises an inverting device coupled between the first node and the second node, with an input node which coincides with the input node of the buffering device and with an output node connected to the gate of the PMOS transistor of the buffering device and to the gate of the NMOS transistor of the buffering device. The transient detector then comprises a resistive element which is coupled between the output node of the transient detector and the second node, as well as a capacitive element which is coupled between the first node and the output node of the transient detector.

[0034] The insertion of such an additional inverting device has the advantage that the signal generated by the transient detector, in particular the voltage surge said transient detector delivers to the switching device, is amplified even further before it reaches the switching device. Indeed, said signal is now subjected to two phases of amplification, namely a first such phase when the signal is passed from the transient detector onto the inverting device, and a second such phase when the signal is passed from the inverting device onto the branch that connects the PMOS transistor of the buffering device with the stack of the NMOS transistor and the current limiting device. This has the effect that the impedance at the switching device is further reduced, so that during the charging process a higher amount of charge is being built up on the gate capacitance of the NMOS transistor of the switching device, and that compared to embodiments without additional inverting devices, the stack comprising the current limiting device will receive a higher gate voltage value, close to the value of the voltage on the first or second node, and the on-resistance of the transistors in this stack will be reduced, resulting in a more complete on / off state.It should be noted that, contrary to the first preferred variant of the first preferred embodiment, the resistive element and capacitive element comprised in the transient detector, have in fact switched places. The capacitive element is now connected to the first node and the resistive element is now connected to the second node, instead of the other way around. This is required in order to make sure the NMOS transistor of the buffering device, which is coupled to the current limiting device, remains in a conducting state during a longer period of time than the PMOS transistor of the buffering device.

[0035] According to said second preferred variant of said first preferred embodiment, the inverting device preferably comprises a PMOS transistor coupled between the first node and the output node of the inverting device, as well as an NMOS transistor coupled between the output node of the inverting device and the second node. The input node of the buffering device is then connected to the gate of the PMOS transistor of the inverting device and to the gate of the NMOS transistor of the inverting device.

[0036] Such an inverting device is indeed configured to further amplify the signal generated by the transient detector, and in particular the voltage surge delivered to the switching device, since compared to the first preferred variant of this first preferred embodiment, the additional two transistors in the inverting device provide two additional internal capacitances configured to be charged as long as the transient detector generates a sufficient signal, and to be discharged subsequently.

[0037] Both within said first preferred variant of said first preferred embodiment as well as within said second preferred variant of said first preferred embodiment, two preferred alternatives can be distinguished.

[0038] In a first preferred alternative of said first preferred embodiment, the current limiting device is coupled to the output node of the buffering device and the NMOS transistor is coupled to the second node, preferably so that the source of the NMOS transistor is coupled to the second node and the drain of the NMOS transistor is coupled to the current limiting device.

[0039] In a second preferred alternative of said first preferred embodiment, the NMOS transistor is coupled to the output node of the buffering device and the current limiting device is coupled to the second node, preferably so that the source of the NMOS transistor is coupled to the current limiting device and the drain of the NMOS transistor is coupled to the output node of the buffering device.

[0040] This implies that in said first preferred alternative, the discharge current from the activation node passes first through the current limiting device and subsequently through the NMOS transistor of the buffering device, whereas in said second preferred alternative, said discharge current flows firstthrough said NMOS transistor and then through the current limiting device, before reaching the second node. Said second preferred alternative has an additional advantage in case the bulk terminal of the NMOS transistor of its buffering device is coupled to ground: the source bulk junction may then be reverse biased, i.e. have a bulk voltage lower than the source voltage, so that said NMOS transistor becomes less efficient and in particular higher resistive compared to the first preferred alternative. As such, the NMOS transistor aids in further limiting the discharge current from the activation node to the second node, and thus in slowing down said discharging process, since said current is to pass through both the resistance of the current limiting device and the resistance of the NMOS transistor, which is then elevated compared to the corresponding value for the NMOS transistor in the first preferred alternative.

[0041] In parallel to the description of the first preferred embodiment above, we will now describe a second preferred embodiment of an ESD protection device, wherein the current limiting device is configured to limit a discharge current from the activation node to the first node rather than to the second node as in the first preferred embodiment.

[0042] According to said second preferred embodiment, the switching device comprises a PMOS transistor, and the buffering device comprises an NMOS transistor which is coupled between the output node of the buffering device and the second node, as well as a stack of the current limiting device and a PMOS transistor, which stack is coupled between the first node and the output node of the buffering device. The output node of the transient detector is coupled to the gate of the PMOS transistor and to the gate of the NMOS transistor, and the current limiting device is configured to limit a discharge current from the activation node to the first node.

[0043] The technical effects and advantages associated with the different alternatives and variants of the first preferred embodiment apply mutatis mutandis to the second preferred embodiment, and will therefore not be explicitly repeated.

[0044] In a first preferred variant of said second preferred embodiment, the output node of the transient detector is directly connected to the gate of the PMOS transistor and to the gate of the NMOS transistor, and the transient detector comprises a resistive element which is coupled between the output node of the transient detector and the second node, as well as a capacitive element which is coupled between the first node and the output node of the transient detector.

[0045] In a second preferred variant of said second preferred embodiment, the buffering device further comprises an inverting device coupled between the first node and the second node, with an input node which coincides with the input node of the buffering device and with an output node connectedto the gate of the PMOS transistor and to the gate of the NMOS transistor. The transient detector then comprises a resistive element which is coupled between the first node and the output node of the transient detector, as well as a capacitive element which is coupled between the output node of the transient detector and the second node.

[0046] According to said second preferred variant of said first preferred embodiment, the inverting device comprises a PMOS transistor coupled between the first node and the output node of the inverting device, as well as an NMOS transistor coupled between the output node of the inverting device and the second node. The input node of the buffering device is then connected to the gate of the PMOS transistor of the inverting device and to the gate of the NMOS transistor of the inverting device.

[0047] Both within said first preferred variant of said second preferred embodiment as well as within said second preferred variant of said second preferred embodiment, two preferred alternatives can be distinguished.

[0048] In a first preferred alternative of said second preferred embodiment, the PMOS transistor is coupled to the first node and the current limiting device is coupled to the output node of the buffering device, preferably so that the source of the PMOS transistor is coupled to the first node and the drain of the PMOS transistor is coupled to the current limiting device.

[0049] In a second preferred alternative of said second preferred embodiment, the current limiting device is coupled to the first node and the PMOS transistor is coupled to the output node of the buffering device, preferably so that the source of the PMOS transistor is coupled to the current limiting device and the drain of the PMOS transistor is coupled to the output node of the buffering device.

[0050] The preferred embodiments described above may further possess any one of the following properties.

[0051] In an exemplary embodiment, the ESD protection device further comprises a capacitive element coupled between the activation node and the second node or the first node. More precisely, within the above-described first preferred embodiment, said capacitive element is coupled between the activation node and the second node, whereas within the above-described second preferred embodiment, said capacitive element is coupled between the activation node and the first node. This additional capacitive element has the advantage that, like the internal capacitance of the switching device, it is configured to charge as long as the transient detector generates a sufficiently strong signal, and to start discharging when the transient detector ceases to generate a sufficiently strong signal. As such, said additional capacitive element in fact serves to virtually increase theinternal capacitance of the switching device, without thereby altering the surface area corresponding to said switching device. This has the effect that the discharging process is further slowed down and thus that the switching device is kept in a conducting state during a longer period of time, simply since larger capacitances take longer to discharge. Consequently, compared to embodiments that lack such an additional capacitive element, one may even implement the current limiting device with a device with a smaller resistance value, or choose the switching device to be of smaller physical dimensions.

[0052] Indeed, referring to said latter option, choosing the switching device to be of smaller size will negatively impact the internal capacitance of the switching device, but since said additional capacitive element causes the overall discharging process to slow down, it is guaranteed that despite said reduction of internal capacitance of the switching device, said switching device does not risk to switch off before the ESD event has come to an end. Nevertheless, the dimensions of the switching device are bound by certain minimal values, since switching devices of too small sizes risk to be incapable of conducting the ESD currents.

[0053] On the other hand, the additional capacitive element also allows to implement the current limiting device with a smaller resistance value, without thereby impacting the time constant of the corresponding RC-circuit. Indeed, the lower value of the resistance component within said time constant is sufficiently compensated by the higher value of the capacitance component by virtue of the additional capacitive element, so that said time constant remains more or less unaltered.

[0054] According to an exemplary embodiment, the switching device may be a silicon controlled rectifier (SCR) ESD clamp, or a bipolar transistor.

[0055] Such a bipolar transistor may be triggered by the triggering device in a similar way as would be the case with a MOS transistor as the switching device, whereas in case the switching device comprises an ESD clamp, it comprises in particular an NMOS transistor configured to be directly triggered by the triggering device, so that the rest of the SCR ESD clamp is triggered by the activation of said NMOS transistor due to a feedback mechanism.

[0056] In an advantageous embodiment, the first branch further comprises a second switching device with an activation node, and the second branch further comprises a second triggering device coupled to the activation node of the second switching device and configured to switch on the second switching device during an ESD event. Said second triggering device comprises a second transient detector having an output node, and a second buffering device. Said second buffering device has an input node coupled to the output node of the second transient detector, an output node coupled to the activation node of the second switching device, and a second current limiting device configuredto limit a discharge current from the activation node of the second switching device to the first node or the second node.

[0057] Such embodiments have the advantage of offering protection against even higher voltage differences between the first node and the second node. Indeed, in case an ESD event occurs, both the transient detector and the second transient detector react to the sensed voltage by generating a signal, in the form of a voltage surge over respectively the switching device and the second switching device. Said signals are amplified by the respective buffering devices, so that the switching device is triggered by the triggering device and the second switching device is triggered by the second triggering device. As a result, both switching devices are activated, provided the delivered voltages exceed their respective threshold voltages. When both switching devices are in a conducting state, the first branch offers a path for the charge built up on the first node to escape to the second node, and as such, an ESD current is shunted by the two switching devices. As such, domains with a voltage rating that exceeds the maximum tolerated voltage of the individual constituent devices may be protected. Thereby, it becomes possible to allow a power domain of e.g. 3.3 V (as a voltage difference between the first and second node) in a circuit implemented with transistors with individual maximum tolerated voltages of e.g. only 1.8 V.

[0058] Once the transient detector ceases to generate a sufficient signal, the switching device will switch off and start to discharge. Similarly, the second switching device will switch off and start to discharge once the second transient detector ceases to generate a sufficient signal. In order to guarantee protection against ESD damage, it is crucial for both switching devices to continue conducting during a sufficiently long period of time, in particular beyond the duration of the ESD event. Therefore, it is advantageous for both the buffering device and the second buffering device to comprise a current limiting device, configured to limit a discharge current from the respective activation node to the first or second node, so that both of the considered discharging processes are sufficiently slowed down. The functionality of the second current limiting device is similar to that of the current limiting device described above.

[0059] The advantageous embodiment described above may further possess any one of the following properties.

[0060] The switching device is preferably connected in series to the second switching device, and the transient detector is preferably coupled to the second transient detector.

[0061] Indeed, as such the ESD currents to be shunted may pass from the first node A via the series connection of the switching device and the second switching device to the second node, and the voltage difference between the first node and the second node during an ESD event may be dividedover the transient detector and the second transient detector. As a result of said voltage division, the voltage on any of the different constituent devices does not exceed the maximum tolerated voltage value of said device, i.e. the maximal value the voltage on said device may attain without risking damage or degradation of these devices.

[0062] Preferably, the ESD protection device further comprises a voltage divider coupled to the transient detector and to the second transient detector, and configured for dividing a voltage between the first node and the second node.

[0063] As such, it is guaranteed that the voltage difference present between the first node and the second node during an ESD event is divided, preferably more or less equally divided, between on the one hand the triggering device and the switching device, and on the other hand the second triggering device and second switching device. Thereby, protection is offered against ESD voltages of about double the value of the maximum voltages withstood by the different components of the internal circuit, since said voltage divider guarantees that only a fraction, preferably at most only half, of the ESD voltage is delivered to any component at any point in time. Each of the components hence remains under safe operation conditions.

[0064] This ability to function under high total ESD voltages is particularly beneficial in circuits wherein recent and advanced transistor technologies, such as FinFETs, are implemented.

[0065] The output node of the second triggering device is preferably coupled to the buffering device. In principle, an ESD protection device according to the above-described advantageous embodiments, consists of a stack of two ESD protection devices which each have at least a single switching device and at least a single triggering device. Several options arise for mutually connecting said two ESD protection devices. Classically, one would consider a first ESD protection device and a second ESD protection device, which each have a separate first node and second node, and couple the first node of the first ESD protection device to the second node of the second ESD protection device, so that in the stacked device the first node of the second device may serve as the first node, and the second node of the first device may serve as the second node. An alternative for said classical coupling is to couple the output node of the second triggering device to the buffering device of the (first) triggering device. The advantages of such a coupling have been described in US8830641 in the name of the applicant, in reference to Figure 6a, with respect to a similar stacked circuit without current limiting devices. More precisely, said coupling has the effect of enabling said buffering device to discharge and of coupling the (first) switching device more directly to the first node compared to embodiments with classical coupling, as well as the effect that the second buffering device allows the gates or control ports of the constituent devices of the (first) buffering device to be pulled to a voltage that exceeds their respective drain voltages.BRIEF DESCRIPTION OF THE FIGURES

[0066] The accompanying drawings are used to illustrate presently preferred non-limiting exemplary embodiments of devices of the present invention. The above and other advantages of the features and objects of the invention will become more apparent, and the invention will be better understood from the following detailed description when read in conjunction with the accompanying drawings, in which:

[0067] Figures la-lc are circuit schematics of three conventional ESD protection devices;

[0068] Figure 2a-2b are circuit schematics of an ESD protection device according to respectively the first and second preferred alternative of the first preferred variant of the first preferred embodiment of an ESD protection device as described above;

[0069] Figures 3a and 3c are circuit schematics of the ESD protection device of Figure 2a, wherein the switching device is respectively an NMOS transistor and an SCR ESD clamp;

[0070] Figure 3b is a circuit schematic of the ESD protection device of Figure 2b, wherein the switching device is an NMOS transistor;

[0071] Figures 4a-4b are circuit schematics of the ESD protection device of Figures 3a and 3b respectively, wherein the current limiting device is a resistor;

[0072] Figure 4c is a circuit schematic of the ESD protection device of Figures 3a, wherein the current limiting device is a MOS transistor;

[0073] Figures 5a-5b are circuit schematics of an ESD protection device according to respectively the first preferred alternative of the second preferred variant of the first preferred embodiment, and the second preferred alternative of the second preferred variant of the first preferred embodiment;

[0074] Figures 6a-6b are circuit schematics of an ESD protection device according to respectively the first and second preferred alternative of the first preferred variant of the second preferred embodiment of an ESD protection device as described above;

[0075] Figure 7 is a circuit schematic of an embodiment of an ESD protection device with an additional capacitive element coupled between the activation node of the switching device and the second node; and

[0076] Figure 8 is a circuit schematic of an embodiment of an ESD protection device with two switching devices and two triggering devices.DETAILED DESCRIPTION OF EMBODIMENTS

[0077] In the following descriptions, common numerical designations may be used for similar, corresponding parts across multiple figures.

[0078] Figure 2a depicts a circuit schematic of an ESD protection device according to the first preferred alternative of the first preferred variant of the first preferred embodiment of an ESD protection device, in the terminology of the Summary section. This ESD protection device is coupled between a first node A, which is a power node or VDD node, and a second node B, which is a ground node or Vss node. The device comprises a first branch 100 between the first node A and the second node B, and a second branch 200 between the first node A and the second node B.

[0079] Herein, the first branch 100 comprises a switching device 110 with an activation node 120. The switching device 110 is depicted in the circuit schematic simply as a rectangular box, to emphasize that Figure 2a covers several different implementations of the switching device 110. The switching device 110 of Figure 2a has three different terminals, one of which is connected to the first node A, a second of which is connected to the second node B, and a third of which, depicted on the left side of the switching device 110, corresponds to the activation node 120.

[0080] The second branch 200 comprises, and in fact in Figure 2a consists of, a triggering device 500 which is coupled to the activation node 120 of the switching device 110 through an output node 430, and which is configured to switch on the switching device 110 during an ESD event. Said triggering device 500 comprises a transient detector 300 and a buffering device 400.

[0081] Herein, the transient detector 300 consists of a series connection of a resistive element 310, a capacitive element 320 and a node 330 which is an intermediate node between the resistive element 310 and the capacitive element 320 and which serves as an output node of the transient detector 300. More precisely, in Figure 2a the resistive element 310 is a resistor which is connected between the first node A and the output node 330, whereas the capacitive element 320 is a capacitor connected between the output node 330 and the second node B.

[0082] The buffering device 400 of Figure 2a consists of a stack of a PMOS transistor 510, a current limiting device 410, an NMOS transistor 520, an input node 420 and an output node 430. More precisely, the first node A is connected to the source of the PMOS transistor 510, the drain of the PMOS transistor 510 is coupled to the current limiting device 410, the current limiting device 410 is further connected to the drain of the NMOS transistor 520, and the source of the NMOS transistor 520 is connected to the second node B. Furthermore, the gate of the PMOS transistor 510 is connected to the gate of the NMOS transistor 520. Herein, the output node 430 is an intermediate node between the drain of the PMOS transistor 510 and the current limiting device 410, and the input node 420 is an intermediate node between the gate of the PMOS transistor 510 and the gate of the NMOS transistor 520. Theoutput node 430 of the buffering device 400 is further connected to the activation node 120, and the input node 420 of the buffering device 400 is further connected to the output node 330 of the transient detector 300.

[0083] In the embodiment of Figure 2a, the current limiting device 410 is configured to limit a discharge current from the activation node 120 to the second node B. Indeed, once the switching device 110 switches off, the PMOS transistor 510 switches off as well. However, the NMOS transistor 520 remains activated during a longer period, as it is connected with the capacitive element 320, which at the considered point in time, is charged and thus configured to deliver a sufficiently high voltage to the NMOS transistor 520. As such, the charge that has built up on the activation node 120 of the switching device 110 may be guided away through the current limiting device 410 and the NMOS transistor 520 to the second node B. The current limiting device 410 is depicted simply as a rectangular box with two terminals, to emphasize that Figure 2a covers several different implementations of the current limiting device 410.

[0084] Figure 2a describes a canonical embodiment of an ESD protection device according to the present invention, wherein only the essential components of the device have been described. However, it should be emphasized that additional components, such as resistive, capacitive or inductive elements, transistors, diodes, or power supplies, may be added to the described circuit without altering its essential functionality, and that such modified circuits are equally covered by the embodiment of Figure 2a. Similarly, the described components of the circuit of Figure 2a may be replaced by an alternative component configured to carry out substantially the same function. For example, the resistor 310 may be replaced by a different component configured to behave as a resistive element when confronted with the typical voltages surges of an ESD event. These remarks equally apply to the embodiments of the Figures 2b-8 that will be described in what follows.

[0085] Figure 2b depicts a circuit schematic of an ESD protection device according to the second preferred alternative of the first preferred variant of the first preferred embodiment of an ESD protection device, in the terminology of the Summary section. In fact, the ESD protection device of Figure 2b is obtained from the one of Figure 2a upon switching the order of the current limiting device 410 and the NMOS transistor 520. This implies that in the device of Figure 2b, each of the described electrical connections of Figure 2a is maintained, except that now the output node 430 of the buffering device is connected to the drain of the NMOS transistor 520 instead of to the current limiting device, the source of the NMOS transistor 520 is connected to the current limiting device 410 instead of to the second node B, and the current limiting device 410 is connected to the second node B instead of to the output node 430. Again, both the switching device 110 and the currentlimiting device 410 are depicted as boxes to emphasize that several different implementations are covered by Figure 2b.

[0086] According to a preferred embodiment, the switching device 110 may comprise a transistor, preferably a MOS transistor having a gate corresponding with the activation node 120. ESD protection devices with such a switching device 110 are shown in each of the Figures 3a-3c, 4a-4c, 5a-5b, 6a-6b, 7 and 8. More precisely, in Figures 3a-3b, 4a-4c, 5a-5b, 7 and 8, the switching device 110 consists of an NMOS transistor having a gate corresponding with the activation node 120. In Figures 6a-6b, the switching device 110 consists of a PMOS transistor having a gate corresponding with the activation node 120. Finally, in Figure 3c, the switching device 110 comprises, but does not consist of, a NMOS transistor 111 whose gate corresponds with the activation node 120. To be precise, the switching device 110 of Figure 3c consists of a silicon controlled rectifier (SCR) ESD clamp comprising, apart from the NMOS transistor 111, a first bipolar transistor 112, a second bipolar transistor 113 and a resistor 114. The aforementioned examples of switching devices 110 will be carefully described in what follows.

[0087] Figure 3a corresponds with Figure 2a, yet wherein the switching device 110 has been specified to be an NMOS transistor 110. The gate of said NMOS transistor 110 corresponds with the activation node 120 of the switching device 110. As such, the NMOS transistor 110 is connected with its gate to the output node 430 of the buffering device 400, with its drain to the first node A and with its source to the second node B. Similarly, Figure 3b corresponds with Figure 2b, yet wherein the switching device 110 has been specified to an NMOS transistor 110. In other words, the ESD protection device of Figure 3b corresponds to that of Figure 3a, yet wherein the order of the NMOS transistor 520 and the current limiting device 410 has been switched. In both Figures 3 a and 3b, the current limiting device 410 remains depicted by a rectangular box, to emphasize that several different implementations are covered.

[0088] The embodiments of Figures 3a-3b, like those of Figures 2a-2b, have a buffering device 400 comprising a stack of a PMOS transistor 510 and an NMOS transistor 520. Herein, said PMOS transistor 510 and NMOS transistor 520 may be of smaller physical dimensions than the NMOS transistor that serves as the switching device 110, as can be explained by comparing the functions of the different transistors. The NMOS transistor of the switching device 110 serves to shunt large currents during ESD events, and must thus have sufficient physical dimensions to be able to withstand high current values. The transistors of the buffering device 400 on the other hand, serve to amplify the signal generated by the transient detector 300. As explained above, compared to conventional ESD protection devices, it is less crucial for said signal amplification to cover the fullduration of the ESD event, since the current limiting device 410 actively aids in slowing down the discharging process, beyond the point in time where the ESD event has come to an end. Therefore, the PMOS transistor 510 and the NMOS transistor 520 of the buffering device 400 may have smaller physical dimensions than their counterparts in conventional ESD protection devices. In particular, the gate length of the PMOS transistor 510 and that of the NMOS transistor 520 may 20 to 100 times smaller than the gate length of the NMOS transistor that serves as the switching device 110.

[0089] Figure 3c corresponds with Figure 2a, yet wherein the switching device 110 has been specified to be an SCR ESD clamp 110. Said SCR ESD clamp comprises an NMOS transistor 111, a first bipolar (PNP) transistor 112, a second bipolar (NPN) transistor 113 and a resistor 114. The first bipolar transistor 112 is a PNP bipolar transistor, whereas the second bipolar transistor 113 is an NPN bipolar transistor. Herein, the gate of the NMOS transistor 111 corresponds to the activation node 120 and is hence connected to the output node 430 of the buffering device 400. The drain of the NMOS transistor 111 is connected to the base of the first bipolar transistor 112, and the source of the NMOS transistor 111 is coupled to the second node B. The first bipolar transistor 112 and the resistor 114 are connected in series between the first node A and the second node B. The emitter of the first bipolar transistor 112 is connected to the first node A, and the collector of the first bipolar transistor 112 is connected to the resistor 114. The resistor 114 is further coupled to the second node B. The second bipolar transistor 113 is connected with its base to an intermediate node 115 between the first bipolar transistor 112 and the resistor 114, with its collector to an intermediate node 116 between the drain of the NMOS transistor 111 and the base of the first bipolar transistor 112, and with its emitter to the second node B. In fact, the second node B is directly connected to a node 117 which is an intermediate node between the resistor 114, the second bipolar transistor 113 and the NMOS transistor 111, and both the source of the NMOS transistor 111, the emitter of the second bipolar transistor 113 and the resistor 114 are connected to the second node B via said intermediate node 117.

[0090] The ESD protection device of Figure 3c functions in a similar way as the device of Figures 3a-3b, in that the NMOS transistor 111 is configured to be directly triggered by the triggering device 500, whereas the ensemble of the bipolar transistors 112, 113 and the resistor 114 is configured to be triggered by the activation of the NMOS transistor 111. More precisely, when the NMOS transistor 111 is activated, it starts to draw current through the base-emitter of the first bipolar transistor 112. The resulting base current then gives rise to a growing collector current, which is injected into the base of the second bipolar transistor 113, thereby also giving rise to a growing collector current of the second bipolar transistor 113, which is equally drawn from the emitter of the first bipolar transistor 112. As such, a feedback mechanism is initiated, allowing the current within the SCR ESD clamp to grow rapidly. Apart from the NMOS transistor 111, the bipolar transistors 112, 113 and theresistor 114, the switching device 110 may further comprise one of several diodes, just like a conventional SCR ESD clamp, yet these are not essential to the behavior of the clamp. The switching device 110 is then configured to shunt ESD currents like a conventional SCR ESD clamp, yet the presence of the current limiting device 410 in the buffering device 400 creates the effect of a slowed down discharging of the activation node 120.

[0091] In a preferred embodiment, the current limiting device 410 comprises a resistive element, in particular an element configured to be high resistive immediately after an ESD event. Indeed, such an element will have the effect of increasing the electrical resistance along the path followed by the considered discharge current from the activation node 120, without significantly altering the voltage, so that said discharge current is effectively lowered. Typical values for the resistance of the current limiting device 410 immediately after an ESD event range from I kfl to 100 kfl.

[0092] Examples of such a resistive element include resistors, like in Figures 4a-4b, as well as MOS transistors configured to be low resistive during an ESD event, high resistive immediately after an ESD event, and low resistive during normal operation, like in Figure 4c.

[0093] More precisely, Figure 4a corresponds with Figure 3a, yet with the current limiting device 410 specified to be a resistor 410. Herein, the resistor 410 may for example be a poly resistor, a metal resistor or a junction resistor. Said resistor is thus connected between the output node 430 of the buffering device 400 and the drain of the NMOS transistor 520. Similarly, Figure 4b corresponds with Figure 3b, yet with the current limiting device 410 specified to be a resistor 410. Said resistor is thus connected between the source of the NMOS transistor 520 and the second node B. In other words, the ESD protection device of Figure 4b corresponds to that of Figure 4a, yet with the order of the NMOS transistor 520 and the current limiting device 410 switched.

[0094] Figure 4c corresponds with Figure 3a, yet with the current limiting device 410 specified to be a MOS transistor 411 whose gate is coupled to an internal node 412. One may choose said node 412 in such a way that the gate of the MOS transistor 411 is controlled by the node 412 to be low resistive during an ESD event, high resistive immediately after an ESD event, and low resistive during normal operation. This may be achieved by configuring the node 412 to deliver a high voltage to the MOS transistor 411 during normal operation and during an ESD event, and a low voltage immediately after an ESD event. Examples of such nodes are so-called enable / disable nodes, or power-up nodes, configured to indicate by means of a voltage signal whether the power supply is on (high voltage delivered) or off (low voltage delivered).Figure 5a depicts a circuit schematic of an ESD protection device according to the first preferred alternative of the second preferred variant of the first preferred embodiment, in the terminology of the Summary section. Said device is obtained from the ESD protection device of Figure 3a upon inserting an inverting device 600 between the first node A and the second node B, and switching the order of the resistive element 310 and the capacitive element 320 in the transient detector 300. More precisely, the inverting device 600 and the transient detector 300 are implemented as follows. The inverting device 600 consists of a stack of a PMOS transistor 610, an NMOS transistor 620, an input node 420 and an output node 431. More precisely, the first node A is connected to the source of the PMOS transistor 610, the drain of the PMOS transistor 610 is connected to the drain of the NMOS transistor 620, and the source of the NMOS transistor 620 is connected to the second node B. Furthermore, the gate of the PMOS transistor 610 is connected to the gate of the NMOS transistor 620. Herein, the output node 431 is an intermediate node between the drain of the PMOS transistor 610 and the drain of the NMOS transistor 620, and the input node 420 is an intermediate node between the gate of the PMOS transistor 610 and the gate of the NMOS transistor 620. The input node 420 of the inverting device 600 also forms the input node of the buffering device 400, and is hence connected to the output node 330 of the transient detector 300. The output node 431 of the inverting device 600 is connected to an intermediate node 421 between the gate of the PMOS transistor 510 and the gate of the NMOS transistor 520.

[0095] The transient detector 300 consists of a series connection of a capacitive element 320, a resistive element 310 and a node 330 which is an intermediate node between the capacitive element 320 and the resistive element 310 and which serves as an output node of the transient detector 300. More precisely, in Figure 5a the capacitive element 320 is connected between the first node A and the output node 330, whereas the resistive element 310 is connected between the output node 330 and the second node B.

[0096] As such, in the ESD protection device of Figure 5a, the triggering device 500 in fact consists of the transient detector 300 and the buffering device 400, and said buffering device 400 consists of two stages of inverting devices, namely a first stage consisting of the inverting device 600, and a second stage consisting of the stack of the PMOS transistor 510, the NMOS transistor 520 and the current limiting device 410. The composition of said stack is identical to that of the inverting device 600, yet with the current limiting device 410 inserted between the output node 430 and the NMOS transistor 520.

[0097] The ESD protection device of Figure 5b corresponds with the device of Figure 5a, yet with the order of the PMOS transistor 520 and the current limiting device 410 switched, so that the drain of the NMOS transistor 520 is connected to the output node 430 of the buffering device 400, and the current limiting device 410 is connected between the source of the NMOS transistor 520 and the secondnode B. In other words, the device of Figure 5b is the analog of the device of Figure 3b wherein an additional inverting device 600 was inserted between the first node A and the second node B.

[0098] As explained above, ESD protection devices according to the presented embodiments have the advantage, amongst other advantages, to be characterized, contrary to prior art alternatives, by two different time constants: a first time constant for the charging of the activation node 120 of the switching device, and a second time constant for the discharging of said activation node 120. Herein, the former may be much shorter than the latter, so that the start-up phase wherein large amounts of current are dissipated, is short compared to the discharging phase, which is required to encompass the entire duration of an ESD event. Indeed, thanks to the presence of the current limiting device 410, the resistive element 310 and the capacitive element 320 of the transient detector 300 may be reduced in both physical dimensions and respective electrical resistance and capacitance values R and C, and thus in the time constant for the charging process which is calculated as the product of R (in Ohm) and C (in Farad), without thereby adversely affecting the time constant for said discharging process.

[0099] Conventional ESD protection devices, as presented in Figures la-lc, typically have identical time constants for charging and discharging, ranging from 1 ps to 2ps. In the ESD protection devices according to Figures 2a-8, the time constant for discharging may remain in the range between 1 ps and 2 ps, but the time constant for charging may be reduced to between 10 and 20 ns. This holds for embodiments with an additional inverting device 600 (Figures 5a-5b) as well as for embodiments without such an additional inverting device. The advantage of the addition of such an inverting device 600 lies in that it gives rise to further amplification of the signal generated by the transient detector 300 and further reduction of the impedance at the switching device 110. Consequently, the physical dimensions of the resistive element 310 and the capacitive element 320, as well as the values R and C, may be further reduced, and a more complete on / off state of the inverting stages may be achieved, with the gate voltages closer to the voltage of the second node B (ground node) or to the voltage of the first node A (power node).

[0100] Along the same lines, the PMOS transistor 610 and NMOS transistor 620 of the inverting device 600 may be of even smaller physical dimensions than the transistors 510 and 520 of the second inverting stage. For example, in case the NMOS transistor of the switching device 110 has a gate width of 1000 pm, the gate widths of the transistors 510 and 520 may range from 10 to 50 pm, whereas the gate widths of the transistors 610 and 620 of the inverting device 600 may range from 1 to 5 pm.

[0101] In the embodiments of Figures 5a-5b, the current limiting device 410 has been placed in the second inverting stage, i.e. in the stage of the PMOS transistor 510 and the NMOS transistor 520, whose drains are coupled to the activation node 120. Alternatively, the current limiting device 410 may beplaced in the first inverting stage, i.e. in the stage of the inverting device 600, and may thus be coupled to the PMOS transistor 610 and the NMOS transistor 620 whose gates are connected to the output node 330 of the transient detector 300. Two options then arise: either the current limiting device 410 may be coupled between the drain of the PMOS transistor 610 and the intermediate node 431, or the current limiting device 410 may be coupled between the source of the PMOS transistor 610 and the first node A. As such, the current limiting device 410 actively limits the discharge current corresponding with the charge that has built up on the gate of the PMOS transistor 510 of the second inverting stage. Said discharge current then runs from the gate of the PMOS transistor 510, via the current limiting device 410 and the PMOS transistor 610 to the first node A. Indeed, while the NMOS transistor 620 switches off as soon as the switching device 110 switches off, the PMOS transistor 610 remains activated during a longer period of time as the latter is directly connected to the capacitive element 320. Thereby, the current limiting device 410 indirectly also limits the discharge current that runs from the activation node 120 via the NMOS transistor 520 to the second node B. However, compared to the embodiments of Figures 5a-5b, such embodiments with the current limiting device 410 in the first inverting stage have a disadvantageously smaller internal gate capacitance of the switching device 110, resulting in an undesirably faster discharging of the activation node 120.

[0102] The ESD protection devices of Figures 2a-2b, 3a-3c, 4a-4c, 6a-6b and 7 comprise a single inverting stage within the buffering device 400, whereas the devices of Figures 5a-5b comprise two inverting stages: a first inverting stage comprising of the inverting device 600, and a second inverting stage comprising the stack of the transistors 510 and 520, with at least one of the inverting stages comprising a current limiting device 410. However, the invention is not limited to devices with one or two inverting stages: additional inverting devices 600 may be added between the first node A and the second node B without essentially altering the device’s functionality. Such additional inverting devices 600 have the effect of further amplifying the signal generated by the transient detector 300 during an ESD event, and thus of speeding up the charging of the switching device 110. As explained above, the insertion of an additional inverting device 600 into the circuit requires the order of the resistive element 310 and the capacitive element 320 in the circuit to be switched. As a result, ESD protection devices with an odd number of inverting stages will have a transient detector 300 comprising a resistive element 310 coupled to the first node A and a capacitive element 320 coupled to the second node B, whereas devices with an even number of inverting stages will have a resistive element 310 coupled to the second node B and a capacitive element 320 coupled to the first node A.

[0103] Figure 6a depicts a circuit schematic of an ESD protection device according to the first preferred alternative of the first preferred variant of the second preferred embodiment of an ESD protectiondevice, in the terminology of the Summary section. This ESD protection device is coupled between a first node A and a second node B and comprises a first branch 100 between the first node A and the second node B, and a second branch 200 between the first node A and the second node B. Herein, the first branch 100 comprises a PMOS transistor which serves as the switching device 110, wherein the gate of said PMOS transistor forms the activation node 120. The source of the PMOS transistor 110 is connected to the first node A, whereas its drain is connected to the second node B. The second branch 200 comprises, and in fact in Figure 6a consists of, a triggering device 500 which is coupled to the activation node 120 of the switching device 110 through an output node 430, and which is configured to switch on the switching device 110 during an ESD event. Said triggering device 500 comprises a transient detector 300 and a buffering device 400.

[0104] The transient detector 300 is implemented in the same way as in the device of Figures 5a-5b: it consists of a series connection of a capacitive element 320, a resistive element 310 and a node 330 which is an intermediate node between the capacitive element 320 and the resistive element 310 and which serves as an output node of the transient detector 300. More precisely, in Figure 6a the capacitive element 320 is connected between the first node A and the output node 330, whereas the resistive element 310 is connected between the output node 330 and the second node B.

[0105] The buffering device 400 of Figure 6a consists of a stack of a PMOS transistor 510, a current limiting device 410, an NMOS transistor 520, an input node 420 and an output node 430. More precisely, the first node A is connected to the source of the PMOS transistor 510, the drain of the PMOS transistor 510 is coupled to the current limiting device 410, the current limiting device 410 is further connected to the drain of the NMOS transistor 520, and the source of the NMOS transistor 520 is connected to the second node B. Furthermore, the gate of the PMOS transistor 510 is connected to the gate of the NMOS transistor 520. Herein, the output node 430 is an intermediate node between the current limiting device 410 and the drain of the NMOS transistor 520, and the input node 420 is an intermediate node between the gate of the PMOS transistor 510 and the gate of the NMOS transistor 520. The output node 430 of the buffering device 400 is further connected to the activation node 120, and the input node 420 of the buffering device 400 is further connected to the output node 330 of the transient detector 300. The current limiting device 410 is depicted simply as a rectangular box with two terminals, to emphasize that Figure 6a covers several different implementations of the current limiting device 410. In particular, the current limiting device 410 may comprise a resistor as in Figures 4a-4b or a MOS transistor coupled to an internal node 412 as in Figure 4c.

[0106] The ESD protection device of Figure 6a differs from that of Figure 3a in that its switching device 110 is a PMOS transistor rather than an NMOS transistor, in that the output node 430 of the buffering device 400 is located between the current limiting device 410 and the drain of the NMOS transistor 520, rather than between the current limiting device 410 and the drain of the PMOS transistor 510, and in that the order of the resistive element 310 and the capacitive element 320 has been switched.Consequently, in the embodiment of Figure 6a, the current limiting device 410 will be configured to limit a discharge current from the activation node 120 to the first node A, rather than to the second node B. Indeed, once the switching device 110 switches off, the NMOS transistor 520 will also switch off, making it impossible for current to escape from the activation node 120 to the second node B via the NMOS transistor 520. However, the PMOS transistor 510 will remain activated during a longer period of time, as it is connected to the capacitive element 320 which, at the moment the switching device 110 switches off, is charged and thus configured to deliver to the PMOS transistor 510 a sufficient voltage to remain activated. Consequently, the charge built up on the gate of the switching device 110 may escape to the first node A via the current limiting device 410 and the PMOS transistor 510.

[0107] The ESD protection device of Figure 6b amounts to that of Figure 6a, yet with the order of the PMOS transistor 510 and the current limiting device 410 switched. As a result, the current limiting device is connected between the first node A and the source of the PMOS transistor 510, while the drain of the PMOS transistor 510 is connected to the output node 430 of the buffering device 400.

[0108] An important difference between the first preferred embodiment, embodiments of which are shown in Figures 2a-5b, and the second preferred embodiment, as shown in Figures 6a-6b, is that in the first preferred embodiment, with the switching device 110 consisting of an NMOS transistor, the buffering device 400 will deliver a low output voltage during normal operation and a high output voltage during ESD events, whereas in the second preferred embodiment, wherein the switching device 110 is a PMOS transistor, this will be the other way around: the buffering device 400 will deliver a high output voltage during normal operation and a low output voltage during ESD events. This can be understood as follows.

[0109] The output voltage delivered by the buffering device 400 must be such that during ESD events, a high voltage is maintained between the gate and the source of the switching device 110, whereas during normal operation the voltage between the gate and the source of the switching device 110 is low. Said voltages are considered relative to the second node B, which is preferably a ground node. In the first preferred embodiment, the switching device 110 is an NMOS transistor whose source is connected to the second node B. Therefore, and since the output node 430 of the buffering device 400 is connected to the gate of the switching device 110, the voltage between the gate and the source of said switching device, relative to the second node B, coincides with the output voltage of the buffering device 400. The latter voltage must therefore be high during ESD events and low during normal operation.

[0110] In the second preferred embodiment, the switching device 110 is a PMOS transistor whose source is connected to the first node A and whose drain is connected to the second node B. During ESD events,the voltage between the first node A and the second node B is high, so that relative to the second node B, the source of the NMOS transistor 110 is at a high voltage. Consequently, in order for the voltage between the gate and the source of the NMOS transistor 110 to be high, the gate voltage of the NMOS transistor 110, and thus the output voltage delivered by the buffering device 400, must be low. During normal operation, the source of the NMOS transistor 110, being connected to the first node A, is still at a high voltage while the gate-source voltage must be low, so that the gate voltage of the NMOS transistor 110, and thus the output voltage delivered by the buffering device 400, is also pulled high.

[0111] The reader understands that embodiments of the invention are not limited to the specific circuit schematics shown in the Figures 2a-8, but may also cover variants of these devices obtained by inserting additional components into the circuit. For example, Figure 7 depicts a circuit schematic of an ESD protection device according to the first preferred alternative of the first preferred variant of the first preferred embodiment, which is obtained from the circuit schematic of Figure 3a upon adding an additional capacitive element 700 coupled between the second node B and the activation node 120 of the switching device 110. Said capacitive element 700 has the effect of further slowing down the discharging of the activation node 120, so that the current limiting device 410 may be implemented with a device with a smaller resistance value, or so that the physical dimensions of the switching device 110 may be reduced without compromising protective functionality against ESD events. Indeed, said capacitive element 700 in fact adds additional capacitance to the switching device 110 and thus serves to keep the switching device 110 in a conducting state during a longer period of time. Choosing the switching device 110 to be of smaller size will negatively impact its internal capacitance, but since said additional capacitive element 700 causes the overall discharging process to slow down, a deactivation of the switching device 110 before the end of the ESD event is avoided. Similarly, choosing the resistance value of the current limiting device 410 to be smaller causes the time constant of the corresponding RC-circuit to decrease, but said decrease is compensated by the insertion of the additional capacitive element 700, so that eventually said time constant remains more or less unchanged.

[0112] This same effect could be achieved by the ESD protection devices of Figures 6a-6b, by coupling a capacitive element 700 between the activation node 120 and the first node A. Indeed, in the embodiments of Figures 6a-6b, the discharge of the activation node 120 takes place through the PMOS transistor 510, the current limiting device 410 and the first node A, and said capacitive element 700 is connected to said first node A, resulting in an improved discharge process.

[0113] Finally, an ESD protection device according to an advantageous embodiment comprising a switching device 110, a triggering device 500, a second switching device 110’ and a second triggering device500’ is depicted in Figure 8. Note that the device of Figure 8 is similar to that of Figure 6a in US8830641 in the name of the applicant, yet differs from it at least in that it further comprises a current limiting device 410, a second current limiting device 410’ and an inverting device 600’. More precisely, the device of Figure 8 is coupled between a first node A and a second node B, comprises a first branch 100 and a second branch 200 between said first node A and said second node B, and can be described as follows.

[0114] The first branch 100 comprises a series connection of a switching device 100 with an activation node 120 and a second switching device 100’ with an activation node 120’. In the embodiment of Figure 8, both switching devices are NMOS transistors, with their respective gates serving as the activation node, and coupled in such a way that the first node A is connected to the drain of the NMOS transistor 110’, the source of the NMOS transistor 110’ is connected to the drain of the NMOS transistor 110, and the source of the NMOS transistor 110 is connected to the second node B. However, in analogy to the embodiments of Figures 2a-7, other choices of switching devices are possible.

[0115] The second node B comprises a triggering device 500 coupled to the activation node 120 of the switching device 110 and configured to switch on the switching device 110 during an ESD event, as well as a second triggering device 500’ coupled to the activation node 120’ of the second switching device 110’ and configured to switching on the second switching device 110’ during an ESD event. Said triggering devices 500 and 500’ are highly similar to those of the embodiments of Figures 2a-7. More precisely, the triggering device 500 comprises a transient detector 300 having an output node 330, and a buffering device 400 having an input node 420 coupled to the output node 330 of the transient detector, and having an output node 430 coupled to the activation node 120 of the switching device 110. The buffering device 400 further comprises a current limiting device 410 configured to limit a discharge current from the activation node 120 of the switching device 110 to the first node A or the second node B. Similarly, the second triggering device 500’ comprises a second transient detector 300’ having an output node 330’, and a second buffering device 400’ having an input node 420’ coupled to the output node 330’ of the second transient detector 300’, an output node 430’ coupled to the activation node 120’ of the second switching device 110’, and a second current limiting device 410’ configured to limit a discharge current from the activation node 120’ of the second switching device 110’ to the first node A or the second node B.

[0116] We will now describe the specific components and electrical connections of the embodiment of Figure 8, yet the reader understands that the invention also covers several alternative configurations. The triggering device 500 is similar to that of Figure 4a, yet with the resistive element 310 and the source of the PMOS transistor 510 not directly connected to the first node A, but rather to respectively a node 360 and the output node 430’ of the second buffering device 400’. Similarly, the switching device 110 is similar to that of Figure 4a, yet with the drain of the NMOS transistor that serves as the switching device 110 not directly connected to the first node A, but rather to the sourceof the NMOS transistor that serves as the second switching device 110’. The second triggering device 500’ is similar to that of Figure 5a, yet with the second transient detector 300’ and the second buffering device 400’ not directly connected to the second node B, but rather to a node 360, and with the output node 430’ of the second buffering device 400’ additionally coupled to the source of the PMOS transistor 510 of the buffering device 400. The second buffering device 400’ thus comprises a first inverting stage consisting of an inverting device 600’, and a second inverting stage consisting of a stack of a PMOS transistor 510’, a resistor serving as the second current limiting device 410’, and an NMOS transistor 520’, of the same type as the corresponding stack in the buffering device 400. The inverting device 600’ is depicted as a triangle, which symbolically represents a device which is identical to the inverting device 600 of Figure 5a, and thus consist of a stack of a PMOS transistor and an NMOS transistor whose gates are connected to the output node 330’ of the second transient detector 300’. The source of the NMOS transistor 520’ of the first inverting stage of the second buffering device 400’, the source of the NMOS transistor 620’ of the inverting device 600’, the resistive element 310 of the transient detector 300 and the resistive element 310’ of the second transient detector 300’ are all mutually connected in a single intermediate node 360. In particular, the transient detector 300 is connected in series to the second transient detector 300’, wherein the node 360 is an intermediate node between both detectors.

[0117] Moreover, the output node 430’ of the second buffering device 400’ is not only connected to the second current limiting device 410’, the PMOS transistor 510’ and the activation node 120’ of the second switching device 110’, but also to the source of the PMOS transistor 510 of the buffering device 400. As such, the output node 430’ of the second buffering device 400’ is in particular coupled to the buffering device 400.

[0118] The ESD protection device of Figure 8 further comprises a voltage divider 800 coupled to the transient detector 300 and to the second transient detector 300’, and configured for dividing a voltage between the first node A and the second node B. Said voltage divider 800 consists of a series connection of a first resistor 340 and a second resistor 350. The first resistor 340 is connected between the second node B and an intermediate node 370, whereas the second resistor 350 is connected between the first node A and said intermediate node 370. The intermediate node 370 is moreover connected via the node 360 to the resistive element 310 of the transient detector 300, the resistive element 310’ of the second transient detector 300’ and the second buffering device 400’. The resistors 340 and 350 are preferably of identical resistance.

[0119] During an ESD event, a high voltage arises between the first node A and the second node B. Said voltage is divided over the two buffering devices 500 and 500’ by the voltage divider 800, so that preferably half of said voltage is sensed by the transient detector 300, and the remaining fraction,preferably the remaining half, of said voltage is sensed by the second transient detector 300’. In reaction, the transient detector 300 sends a signal to the switching device 110 in the form of a voltage surge, which is amplified by the buffering device 400, and the second transient detector 300’ sends a signal to the second switching device 110’ in the form a voltage surge, which is amplified by the second buffering device 400’. Provided the received voltage surges exceed the respective threshold voltages of the switching devices 110 and 110’, both switching devices are switched on and excessive charges on the first node A can escape to the second node B via the second switching device 110’ and the switching device 110. Thus, the ESD currents are shunted by the switching devices 110 and 110’.

[0120] Once the switching device 110 switches off due to insufficient received signal strength, its gate needs to discharge. The excessive charge on said gate may escape to the second node B via the current limiting device 410 and the NMOS transistor 520, which remains activated whilst the PMOS transistor 510 switches off, since the NMOS transistor 520 is connected to the charged capacitive element 320.

[0121] Similarly, once the second switching device 110’ switches off due to insufficient received signal strength, either simultaneously with the switching device 110 or not, its gate needs to discharge. This is achieved by means of a discharge current that runs from the activation node 120’ of the second switching device 110’, via the second current limiting device 410’, the NMOS transistor 520’ of the second buffering device 400’, the intermediate nodes 360 and 370, and the resistive element 340 of the voltage divider 800, to the second node B.

[0122] The current limiting device 410 thereby actively limits the discharge current from the activation node 120 of the switching device 110 to the second node B, whereas the second current limiting device 410’ actively limits the discharge current from the activation node 120’ of the second switching device 110’ to the second node B.

[0123] As mentioned before, the embodiment of Figure 8 is particularly advantageous for internal circuits implemented with FinFETs and similar recent and advanced transistor technologies, since such transistors require ESD protection devices configured to protect the circuit from damage under high ESD voltages. The embodiment of Figure 8 has this functionality, thanks to the presence of the two switching devices 110 and 110’, the two triggering devices 500 and 500’, and the voltage divider 800. The same holds for the numerous variants of the embodiment of Figure 8 that can be obtained upon replacing the triggering device 500 and / or the second triggering device 500’ by the triggering device of any of the Figures 2a-2b, 3a-3c, 4a-4c, 5a-5b and 7, and / or upon replacing both the triggering device 500 and the switching device 110, and / or both the second triggering device 500’ and the switching device 110’, by those of Figures 6a-6b, and / or upon modifying the internal circuit without altering the essential functionality. In particular, each of the preferable and optionalproperties of the triggering device 500 described above may also apply to the second triggering device 500’ .

[0124] Whilst the principles of the invention have been set out above in connection with specific embodiments, it is to be understood that this description is merely made by way of example and not as a limitation of the scope of protection which is determined by the appended claims.

Claims

CLAIMS1. An electrostatic discharge, ESD, protection device coupled between a first node (A) and a second node (B), said ESD protection device comprising:a first branch (100) between the first node and the second node, said first branch comprising a switching device (110) with an activation node (120); anda second branch (200) between the first node and the second node, said second branch comprising a triggering device (500) coupled to the activation node of the switching device and configured to switch on the switching device during an ESD event, wherein said triggering device comprises: a transient detector (300) having an output node (330), anda buffering device (400) having an input node (420) coupled to the output node of the transient detector, and having an output node (430) coupled to the activation node;characterized in thatthe buffering device (400) further comprises a current limiting device (410) configured to limit a discharge current from the activation node to the first node or the second node.

2. The ESD protection device according to claim 1, wherein the current limiting device (410) comprises a resistive element.

3. The ESD protection device according to the previous claim, wherein the resistive element comprises any one of the following:- a resistor, or- a MOS transistor configured to be low resistive during an ESD event, high resistive immediately after an ESD event, and low resistive during normal operation.

4. The ESD protection device according to any one of the previous claims, wherein the switching device (110) comprises, preferably consists of, a transistor, preferably a MOS transistor having a gate corresponding with the activation node (120).

5. The ESD protection device according to any one of the previous claims, wherein the buffering device (400) comprises a stack of a PMOS transistor (510) and an NMOS transistor (520).

6. The ESD protection device according to any one of the previous claims, wherein the transient detector (300) comprises a resistive element (310) and a capacitive element (320) connected in series between the first node and the second node, and wherein the output node (330) of the transient detector is an intermediate node between said resistive element and said capacitive element.

7. The ESD protection device according to any one of the previous claims, wherein the switching device (110) comprises an NMOS transistor; and whereinthe buffering device (400) comprises- a PMOS transistor (510) which is coupled between the first node (A) and the output node (430) of the buffering device,- a stack (440) of the current limiting device (410) and an NMOS transistor (520), which stack is connected between the output node (430) of the buffering device and the second node (B); wherein the output node (330) of the transient detector (300) is coupled to the gate of the PMOS transistor (510) and to the gate of the NMOS transistor (520);and wherein the current limiting device (410) is configured to limit a discharge current from the activation node (120) to the second node (B).

8. The ESD protection device according to claim 7, wherein the output node (330) of the transient detector (300) is directly connected to the gate of the PMOS transistor (510) and to the gate of the NMOS transistor (520); and wherein the transient detector comprises- a resistive element (310) which is coupled between the first node (A) and the output node (330) of the transient detector, and- a capacitive element (320) which is coupled between the output node (330) of the transient detector and the second node (B).

9. The ESD protection device according to claim 7, wherein the buffering device (400) further comprises an inverting device (600) coupled between the first node (A) and the second node (B), with an input node which coincides with the input node (420) of the buffering device (400) and with an output node (431) connected to the gate of the PMOS transistor (510) and to the gate of the NMOS transistor (520); and wherein the transient detector (300) comprises- a resistive element (310) which is coupled between the output node (330) of the transient detector and the second node (B), and- a capacitive element (320) which is coupled between the first node (A) and the output node (330) of the transient detector.

10. The ESD protection device according to the previous claim, wherein the inverting device (600) comprises- a PMOS transistor (610) coupled between the first node (A) and the output node (431) of the inverting device, and- an NMOS transistor (620) coupled between the output node (431) of the inverting device and the second node (B);wherein the input node (420) of the buffering device (400) is connected to the gate of the PMOS transistor (610) of the inverting device and to the gate of the NMOS transistor (620) of the inverting device.

11. The ESD protection device according to any one of claims 7-10, wherein the current limiting device (410) is coupled to the output node (430) of the buffering device (400) and the NMOS transistor (520) is coupled to the second node (B), preferably so that the source of the NMOS transistor (520) is coupled to the second node (B) and the drain of the NMOS transistor (520) is coupled to the current limiting device (410).

12. The ESD protection device according to any one of claims 7-10, wherein the NMOS transistor (520) is coupled to the output node (430) of the buffering device (400) and the current limiting device (410) is coupled to the second node (B), preferably so that the source of the NMOS transistor (520) is coupled to the current limiting device (410) and the drain of the NMOS transistor (520) is coupled to the output node (430) of the buffering device (400).

13. The ESD protection device according to any one of the previous claims 1-6, wherein the switching device (110) comprises a PMOS transistor; and whereinthe buffering device (400) comprises- an NMOS transistor (520) which is coupled between the output node (430) of the buffering device and the second node (B); and- a stack (450) of the current limiting device (410) and a PMOS transistor (510), which stack is coupled between the first node (A) and the output node (430) of the buffering device; wherein the output node (330) of the transient detector (300) is coupled to the gate of the PMOS transistor (510) and to the gate of the NMOS transistor (520);and wherein the current limiting device (410) is configured to limit a discharge current from the activation node (120) to the first node (A).

14. The ESD protection device according to claim 13, wherein the output node (330) of the transient detector (300) is directly connected to the gate of the PMOS transistor (510) and to the gate of the NMOS transistor (520), and wherein the transient detector comprises- a resistive element (310) which is coupled between the output node (330) of the transient detector and the second node (B), and- a capacitive element (320) which is coupled between the first node (A) and the output node (330) of the transient detector.

15. The ESD protection device according to claim 13, wherein the buffering device (400) further comprises an inverting device (600) coupled between the first node (A) and the second node (B), with an input node which coincides with the input node (420) of the buffering device (400) and with an output node (431) connected to the gate of the PMOS transistor (510) and to the gate of the NMOS transistor (520); and wherein the transient detector (300) comprises- a resistive element (310) which is coupled between the first node (A) and the output node (330) of the transient detector, and- a capacitive element (320) which is coupled between the output node (330) of the transient detector and the second node (B).

16. The ESD protection device according to the previous claim, wherein the inverting device (600) comprises- a PMOS transistor (610) coupled between the first node (A) and the output node (431) of the inverting device, and- an NMOS transistor (620) coupled between the output node (431) of the inverting device and the second node (B);wherein the input node (420) of the buffering device (400) is connected to the gate of the PMOS transistor (610) of the inverting device and to the gate of the NMOS transistor (620) of the inverting device.

17. The ESD protection device according to any one of claims 13-16, wherein the PMOS transistor (510) is coupled to the first node (A) and the current limiting device (410) is coupled to the output node (430) of the buffering device (400), preferably so that the source of the PMOS transistor (510) is coupled to the first node (A) and the drain of the PMOS transistor (510) is coupled to the current limiting device (410).

18. The ESD protection device according to any one of claims 13-16, wherein the current limiting device (410) is coupled to the first node (A) and the PMOS transistor (510) is coupled to the output node (430) of the buffering device (400), preferably so that the source of the PMOS transistor (510) is coupled to the current limiting device (410) and the drain of the PMOS transistor (510) is coupled to the output node (430) of the buffering device (400).

19. The ESD protection device according to any one of the previous claims, further comprising a capacitive element (700) coupled between the activation node (120) and the second node (B) or the first node (A).

20. The ESD protection device according to any one of the previous claims, wherein the switching device (110) is any one of the following:- a silicon controlled rectifier ESD clamp, or- a bipolar transistor.

21. The ESD protection device according to any one of the previous claims, wherein the first branch (100) further comprises a second switching device (110’) with an activation node (120’), and wherein the second branch (200) further comprises a second triggering device (500’) coupled to the activation node (120’) of the second switching device (110’) and configured to switch on the second switching device (110’) during an ESD event, wherein the second triggering device (500’) comprises:a second transient detector (300’) having an output node (330’), anda second buffering device (400’) havingan input node (420’) coupled to the output node (330’) of the second transient detector, an output node (430’) coupled to the activation node (120’) of the second switching device (110’), anda second current limiting device (410’) configured to limit a discharge current from the activation node (120’) of the second switching device (110’) to the first node (A) or the second node (B).

22. The ESD protection device according to the previous claim, wherein the switching device (110) is connected in series to the second switching device (110’), and wherein the transient detector (300) is coupled to the second transient detector (300’).

23. The ESD protection device according to any one of the previous claims 21-22, further comprising a voltage divider (800) coupled to the transient detector (300) and to the second transient detector (300’), and configured for dividing a voltage between the first node (A) and the second node (B).

24. The ESD protection device according to any one of the previous claims 21-23, wherein the output node (430’) of the second triggering device (500’) is coupled to the buffering device (400).

25. The ESD protection device according to any one of the previous claims, wherein the switching device (110) comprises an NMOS transistor, and wherein the buffering device (400) comprises a stack (440) of the current limiting device (410) and an NMOS transistor (520), which stack is connected between the output node (430) of the buffering device and the second node (B), wherein the current limiting device (410) is coupled to the drain of the NMOS transistor (520).

26. The ESD protection device according to any one of the previous claims and claim 7, wherein the current limiting device (410) is coupled to the drain of the NMOS transistor (520).

27. The ESD protection device according to any one of the previous claims, wherein the switching device (110) comprises a PMOS transistor, and wherein the buffering device (400) comprises a stack (450) of the current limiting device (410) and a PMOS transistor (510), which stack is coupled between the first node (A) and the output node (430) of the buffering device, wherein the current limiting device (410) is coupled to the drain of the PMOS transistor (510).

28. The ESD protection device according to any one of the previous claims and claim 13, wherein the current limiting device (410) is coupled to the drain of the PMOS transistor (510).

29. The ESD protection device according to any one of the previous claims, wherein the buffering device (400) comprises at least one FinFET transistor, preferably comprises a stack of FinFET transistors.

30. The ESD protection device according to any one of the claims 3-5 or 7-18, wherein each MOS transistor is a FinFET transistor.

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