Semiconductor device, power conversion device, and method for producing semiconductor device

Abstract

The purpose of the present invention is to provide a technique capable of increasing the possibility that a mesa part adjacent to a gate trench structure is exposed from an interlayer insulating film. This semiconductor device comprises a semiconductor substrate, a gate trench structure provided to the semiconductor substrate in an active region, a dummy trench structure provided to the semiconductor substrate in a dummy region, and a first interlayer insulating film covering a portion of the semiconductor substrate from a first mesa part adjacent to the gate trench structure and the dummy trench structure to a terminal region via the dummy trench structure.

Description

Semiconductor device, power conversion device, and method of manufacturing semiconductor device

[0001] The present disclosure relates to a semiconductor device, a power conversion device, and a method of manufacturing a semiconductor device.

[0002] In a semiconductor device, a gate trench structure in which a gate electrode of a semiconductor switching element is provided in a trench of a semiconductor substrate is known (for example, Patent Document 1). In such a semiconductor device, a mesa portion including an impurity layer for flowing a main current between a source and a drain, adjacent to the gate trench structure, is exposed from an interlayer insulating film and electrically connected to a source electrode.

[0003] Japanese Patent Application Laid-Open No. 2016-111287

[0004] In the semiconductor device as described above, although the cause is unknown, the interlayer insulating film tends to become thicker from the active region to the termination region of the semiconductor substrate, so that the mesa portion near the termination region may not be exposed from the interlayer insulating film. As a result, since the mesa portion is not electrically connected to the source electrode, there are problems such that the performance of the semiconductor device varies or a performance failure of the semiconductor device occurs.

[0005] Therefore, the present disclosure has been made in view of the above problems, and an object thereof is to provide a technique capable of increasing the possibility that a mesa portion adjacent to a gate trench structure is exposed from an interlayer insulating film.

[0006] The semiconductor device according to the present disclosure includes a semiconductor substrate in which an active region, a dummy region, and a termination region are defined in this order from the inside to the outside in a plan view, a gate trench structure having a gate electrode provided via a first insulating film in a first trench provided in the semiconductor substrate in the active region, a dummy trench structure having a dummy electrode provided via a second insulating film in a second trench provided in the semiconductor substrate in the dummy region, and a first interlayer insulating film covering from a first mesa portion adjacent to the gate trench structure and the dummy trench structure of the semiconductor substrate to the termination region through the dummy trench structure.

[0007] According to this disclosure, the first interlayer insulating film covers the semiconductor substrate from the first mesa portion adjacent to the gate trench structure and the dummy trench structure through the dummy trench structure to the terminal region. With this configuration, the possibility of the mesa portion adjacent to the gate trench structure being exposed from the interlayer insulating film can be increased. The objectives, features, aspects and advantages of this disclosure will become clearer from the following detailed description and accompanying drawings.

[0008] Figure 1 is a plan view showing the configuration of a semiconductor device according to Embodiment 1. Figure 2 is an enlarged plan view showing the configuration of a semiconductor device according to Embodiment 1. Figure 3 is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 1. Figure 4 is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 1. Figure 5 is a cross-sectional view showing the manufacturing method of a semiconductor device according to Embodiment 1. Figure 6 is a cross-sectional view showing the manufacturing method of a semiconductor device according to Embodiment 1. Figure 7 is a cross-sectional view showing the manufacturing method of a semiconductor device according to Embodiment 1. Figure 8 is a cross-sectional view showing the manufacturing method of a semiconductor device according to Embodiment 1. Figure 9 is a cross-sectional view showing the manufacturing method of a semiconductor device according to Embodiment 1. Figure 10 is a cross-sectional view showing the manufacturing method of a semiconductor device according to Embodiment 1. Figure 11 is a cross-sectional view showing the manufacturing method of a semiconductor device according to Embodiment 1. Figure 12 is a cross-sectional view showing the manufacturing method of a semiconductor device according to Embodiment 1. Figure 13 is a cross-sectional view showing the manufacturing method of a semiconductor device according to Embodiment 1. Figure 14 is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 2. Figure 15 is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 3. Figure 16 is a plan view showing the configuration of a semiconductor device according to Embodiment 4. Figure 17 is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 4. Figure 18 is a plan view showing the configuration of a semiconductor device according to Embodiment 5. Figure 19 is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 5. Figure 20 is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 6. Figure 21 is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 7. Figure 22 is a cross-sectional view showing the configuration of a semiconductor device according to Embodiment 8. Figure 23 is a plan view showing the configuration of a semiconductor device according to Embodiment 9. Figure 24 is a block diagram showing the configuration of a power conversion system according to Embodiment 10.

[0009] The embodiments will be described below with reference to the attached drawings. The features described in each of the embodiments below are illustrative, and not all features are necessarily required. In addition, in the following descriptions, the same or similar reference numerals are used for similar components in multiple embodiments, and the different components are mainly described. Also, in the following descriptions, specific positions and directions such as "top," "bottom," "left," "right," "front," or "back" do not necessarily coincide with the positions and directions in actual implementation. Furthermore, a higher concentration in one part than in another part may mean, for example, that the average or peak concentration of one part is higher than the average or peak concentration of the other part. Conversely, a lower concentration in one part than in another part may mean, for example, that the average or peak concentration of one part is lower than the average or peak concentration of the other part. Also, in the following descriptions, n-type and p-type may be replaced with p-type and n-type, respectively.

[0010] <Embodiment 1> Figure 1 is a plan view showing the configuration of a semiconductor device according to this embodiment 1, and Figure 2 is an enlarged plan view showing the configuration of the portion marked by line A-A' in Figure 1. Figure 3 is a cross-sectional view showing the configuration of the portion marked by line A-A' in Figure 1, and Figure 4 is a cross-sectional view showing the configuration of the portion marked by line B-B' in Figure 1.

[0011] In Figure 3, the semiconductor device according to this embodiment 1 comprises a semiconductor substrate 1, a gate trench structure 2, a dummy trench structure 3, a first interlayer insulating film 4, a second interlayer insulating film 5, and a source electrode 6. In Figure 4, the semiconductor device according to this embodiment 1 comprises a gate sidewall 7, a field insulating film 8, a gate electrode 9, and gate wiring 10. Although not shown, the semiconductor device according to this embodiment 1 also comprises a drain electrode.

[0012] The semiconductor substrate 1 may be made of ordinary silicon (Si), or silicon carbide (SiC), gallium nitride (GaN), gallium oxide (Ga ２ O ３), or it may be composed of a wide-bandgap semiconductor such as diamond. When the semiconductor substrate 1 is composed of a wide-bandgap semiconductor, stable operation of the semiconductor device at high temperatures and high voltages, and faster switching speeds become possible. The semiconductor substrate 1 may be composed of a normal semiconductor wafer or an epitaxial growth layer.

[0013] In a plan view, the semiconductor substrate 1 has an active region 51, a dummy region 52, and a termination region 53 defined in that order from the inside outwards, as shown in Figure 1. The active region 51, dummy region 52, and termination region 53 will be described below.

[0014] <Active Region 51> A trench-type semiconductor switching element is provided in the active region 51. Below, an example in which the semiconductor switching element is a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) will be described. However, the semiconductor switching element is not limited to this, and may also be an IGBT (Insulated Gate Bipolar Transistor) or an RC-IGBT (Reverse Conducting-IGBT). In addition to the semiconductor switching element, diodes such as an SBD (Schottky Barrier Diode) and a PND (PN junction diode) may also be provided in the active region.

[0015] As shown in Figures 3 and 4, the semiconductor substrate 1 of the active region 51 includes an n-type drift layer 1a, a p-type base layer 1b, an n-type source layer 1c, a p-type contact layer 1d, and a p-type well layer 1e.

[0016] The base layer 1b is selectively provided on the drift layer 1a. The source layer 1c is selectively provided on the base layer 1b. The contact layer 1d is provided between the two source layers 1c in a cross-sectional view, and the p-type impurity concentration of the contact layer 1d is greater than the p-type impurity concentration of the base layer 1b. In the example in Figure 2, the contact layer 1d is provided in an island-like manner on the source layer 1c, but this is not the only configuration.

[0017] As shown in Figures 1 to 4, the gate trench structure 2 is provided in the active region 51. In Figures 1 and 2, the gate trench structure 2 is shown in a simplified manner, but as shown in Figures 3 and 4, the gate trench structure 2 includes a first insulating film 2a, which is a gate insulating film, and a gate electrode 2b.

[0018] The semiconductor substrate 1 in the active region 51 is provided with a first trench 2c that penetrates the base layer 1b and the source layer 1c and reaches the drift layer 1a. The gate electrode 2b is provided in the first trench 2c via a first insulating film 2a. The well layer 1e is provided at the bottom of the first trench 2c, which suppresses electric field concentration at the bottom of the first trench 2c.

[0019] The mesa portion of the semiconductor substrate 1 in the active region 51 adjacent to the gate trench structure 2 includes a base layer 1b, a source layer 1c, and a contact layer 1d. The height of the upper surface of the mesa portion is higher than the height of the upper end of the gate electrode 2b.

[0020] The second interlayer insulating film 5 is embedded within the first trench 2c and on the gate electrode 2b. Therefore, the height of the upper surface of the mesa adjacent to the gate trench structure 2 is higher than the height of the upper end of the second interlayer insulating film 5.

[0021] The source electrode 6 is provided on the mesa portion and the second interlayer insulating film 5, and is electrically connected to the source layer 1c and contact layer 1d of the mesa portion. A drain electrode (not shown) is provided on the lower surface of the semiconductor substrate 1. In the semiconductor switching element configured as described above, when a voltage above the threshold voltage is applied to the gate electrode 2b, a channel for the main current between the source and drain is formed in the base layer 1b adjacent to the gate trench structure 2.

[0022] <Dummy Region 52> As shown in Figures 1 to 4, the dummy trench structure 3 is provided in the dummy region 52. In Figures 1 and 2, the dummy trench structure 3 is shown in a simplified manner, but as shown in Figures 3 and 4, the dummy trench structure 3 includes a second insulating film 3a and a dummy electrode 3b.

[0023] The dummy electrode 3b is provided in the second trench 3c provided in the semiconductor substrate 1 of the dummy region 52, via a second insulating film 3a. In the examples of Figures 3 and 4, the width and depth of the second trench 3c are the same as the width and depth of the first trench 2c, but they may be slightly different. The well layer 1e is provided at the bottom of the second trench 3c, which helps to suppress electric field concentration at the bottom of the second trench 3c.

[0024] In the semiconductor substrate 1 of the dummy region 52, the first mesa portion 1m adjacent to the gate trench structure 2 and the dummy trench structure 3 includes a base layer 1b, a source layer 1c, and a contact layer 1d. On the other hand, in the semiconductor substrate 1 of the dummy region 52, the second mesa portion 1n adjacent to the dummy trench structure 3 on the terminal region 53 side does not include a base layer 1b, a source layer 1c, and a contact layer 1d. The height of the upper surfaces of the first mesa portion 1m and the second mesa portion 1n is higher than the height of the upper end of the dummy electrode 3b.

[0025] The first interlayer insulating film 4 is configured to cover the semiconductor substrate 1 from the first mesa portion 1m adjacent to the gate trench structure 2 and the dummy trench structure 3, through the dummy trench structure 3, to the terminal region 53. The position of the end of the first interlayer insulating film 4 on the active region 51 side corresponds to the boundary between the active region 51 and the dummy region 52. The position of the second mesa portion 1n adjacent to the dummy trench structure 3 on the terminal region 53 side of the semiconductor substrate 1 corresponds to the boundary between the dummy region 52 and the terminal region 53.

[0026] As described above, in the mesa portion adjacent to the gate trench structure 2 of the active region 51, the main source-drain current flows. In contrast, in the mesa portion adjacent to the dummy trench structure 3 of the dummy region 52, one of the following conditions is met: (i) the dummy electrode 3b is a floating electrode, (ii) the mesa portion does not include the base layer 1b and the source layer 1c, or (iii) the source layer 1c of the mesa portion is not electrically connected to the source electrode 6. Thus, the main current is substantially prevented from flowing. If (ii) is met, then (iii) is also necessarily met. As the number of conditions (i) to (iii) that are met increases, the probability that the main current will not flow in the mesa portion increases.

[0027] In the first mesa portion 1m shown in Figures 3 and 4, (iii) is filled by the second insulating film 3a and the first interlayer insulating film 4. In this case, regardless of whether at least one of (i) and (ii) is filled, the main current does not substantially flow in the first mesa portion 1m. For this reason, in the example of Figures 3 and 4, the dummy electrode 3b may be a floating electrode or may be electrically connected to the gate electrode 2b. Also, in the example of Figures 3 and 4, the first mesa portion 1m may not include the base layer 1b and the source layer 1c.

[0028] In the second mesa section 1n of Figures 3 and 4, (ii) and (iii) are satisfied. In this case, regardless of whether (i) is satisfied or not, the main current does not substantially flow in the second mesa section 1n. For this reason, in the example of Figures 3 and 4, the dummy electrode 3b may be a floating electrode or it may be electrically connected to the gate electrode 2b.

[0029] In this embodiment 1, as shown in Figure 3, the thickness of the first interlayer insulating film 4 on the second mesa portion 1n is greater than the thickness of the first interlayer insulating film 4 on the first mesa portion 1m. As will be described in detail later, when the interlayer insulating film 13 shown in Figure 11, which is the basis for the first interlayer insulating film 4, is formed, the interlayer insulating film 13 becomes thicker as you move from the active region 51 to the terminal region 53. Traces of this are reflected in the first interlayer insulating film 4 in Figure 3.

[0030] <Terminal Region 53> In the terminal region 53, the semiconductor substrate 1 is excavated so that the height of the upper surface of the semiconductor substrate 1 is the same as the height of the bottom surfaces of the first trench 2c and the second trench 3c. The well layer 1e is provided on the upper part of the excavated semiconductor substrate 1.

[0031] The second insulating film 3a of the dummy region 52 extends onto the semiconductor substrate 1 in the termination region 53. The gate sidewall 7 is provided on the side of the second mesa portion 1n and on the semiconductor substrate 1 in the termination region 53 via the second insulating film 3a. The field insulating film 8 in Figure 4 is provided on the semiconductor substrate 1 via the second insulating film 3a in a region spaced further apart from the dummy region 52 than the gate sidewall 7. The gate electrode 9 is provided on the field insulating film 8. This gate electrode 9 is electrically connected to the gate electrode 2b of the active region 51, although this gate electrode 9 is not shown.

[0032] A dummy region 52 of the first interlayer insulating film 4 extends over the gate electrode 9. The gate wiring 10 is provided on the first interlayer insulating film 4 and is electrically connected to the gate electrode 9 via contact holes in the first interlayer insulating film 4. This allows the voltage applied to the gate wiring 10 to be applied to the gate electrode 2b of the active region 51 via the gate electrode 9.

[0033] With the above configuration, the distance between the gate wiring 10 and the first trench 2c is relatively large. Therefore, the voltage applied to the gate wiring 10 can be suppressed from being applied to the corners of the first trench 2c, thereby improving the reliability of the semiconductor device. In addition, the field insulating film 8 suppresses the rise in voltage of the semiconductor substrate 1 due to the application of voltage to the gate electrode 9, thereby reducing gate leakage and improving the reliability of the semiconductor device.

[0034] <Manufacturing Method> Figures 5 to 13 are cross-sectional views showing the manufacturing method of a semiconductor device according to this embodiment 1, and are cross-sectional views corresponding to Figure 4.

[0035] As shown in Figure 5, an n-type semiconductor substrate 1 is prepared. Then, a patterned resist (not shown) is formed on the semiconductor substrate 1 by photolithography. Subsequently, p-type and n-type impurities are ion-implanted into the semiconductor substrate 1 of the active region 51 using the resist as a mask.

[0036] Next, by heat treatment of the p-type and n-type impurities, a base layer 1b and a source layer 1c are selectively formed on the semiconductor substrate 1 of the active region 51, as shown in Figure 6. The portion of the semiconductor substrate 1 of the active region 51 below the source layer 1c becomes the drift layer 1a. After that, the resist is removed. In the following explanation, for the sake of simplicity, the explanation of resist formation and removal, as well as the heat treatment, may be omitted.

[0037] Next, as shown in Figure 7, an oxide film 11 patterned by photolithography is formed. Then, the semiconductor substrate 1 is selectively etched using the oxide film 11 as a mask. As a result, a first trench 2c is formed in the active region 51 that penetrates the base layer 1b and the source layer 1c and reaches the drift layer 1a, a second trench 3c is formed in the dummy region 52, and the semiconductor substrate 1 in the termination region 53 is excised.

[0038] Subsequently, as shown in Figure 8, the oxide film 11 is used as a mask to selectively form well layers 1e on the semiconductor substrate 1 in the active region 51, dummy region 52, and termination region 53. After that, the oxide film 11 is removed.

[0039] Next, as shown in Figure 9, a contact layer 1d is selectively formed on the base layer 1b. Then, an insulating film 12 is formed on the semiconductor substrate 1, for example, by thermal oxidation.

[0040] Next, as shown in Figure 10, a field insulating film 8 is formed on the insulating film 12 of the terminal region 53. The field insulating film 8 may or may not have a tapered shape. If the field insulating film 8 has a tapered shape, the electric field can be mitigated, which can improve the reliability of the semiconductor device.

[0041] Subsequently, although not shown in the diagram, a conductive film made of, for example, polysilicon is formed on the insulating film 12 and the field insulating film 8 by, for example, CVD (Chemical Vapor Deposition). Then, the gate electrode 2b, dummy electrode 3b, gate sidewall 7, and gate electrode 9 are formed by selectively etching the conductive film so that the mesa portion and other parts are exposed from the conductive film. In this case, the materials of the gate electrode 2b, dummy electrode 3b, gate sidewall 7, and gate electrode 9 are generally the same.

[0042] Next, as shown in Figure 11, an interlayer insulating film 13 is formed on the gate electrode 2b, dummy electrode 3b, gate sidewall 7, gate electrode 9, and mesa portion, for example, by CVD. Subsequently, heat treatment is performed, causing thermal sagging in the interlayer insulating film 13. As a result, the upper surface of the interlayer insulating film 13 changes from an uneven state reflecting the unevenness formed by the upper surface of the mesa and the upper surface of the gate electrode 2b to a flat state. Although the reason is unknown, it was observed in the sample that the interlayer insulating film 13 tends to become thicker from the active region 51 towards the terminal region 53 after heat treatment.

[0043] Thereafter, as shown in FIG. 12, the mesa portions of the active region 51 are selectively etched so as to be exposed from the insulating film 12 and the interlayer insulating film 13, thereby forming the first insulating film 2a, the second insulating film 3a, the first interlayer insulating film 4, and the second interlayer insulating film 5. In this case, the materials of the first insulating film 2a and the second insulating film 3a are substantially the same, and the materials of the first interlayer insulating film 4 and the second interlayer insulating film 5 are substantially the same. By the process of FIG. 12, a gate trench structure 2 is formed in the active region 51, and a dummy trench structure 3 is formed in the dummy region 52.

[0044] Here, when the etching amount of the interlayer insulating film 13 is large, the second interlayer insulating film 5 is removed, and the gate electrode 2b and the source electrode 6 are short-circuited. On the other hand, when the dummy region 52 is not provided and the etching amount of the interlayer insulating film 13 is small, due to the thickness tendency of the interlayer insulating film 13, the mesa portion close to the terminal region 53 may not be exposed from the insulating film 12 or the interlayer insulating film 13. As a result, since the source layer 1c of the mesa portion is not electrically connected to the source electrode 6, there are problems such that the performance of the semiconductor device varies or a performance defect of the semiconductor device occurs.

[0045] In contrast, in the first embodiment, in the dummy region 52 where the interlayer insulating film 13 is relatively thick, the first mesa portion 1m and the second mesa portion 1n remain covered by the first interlayer insulating film 4 made of the interlayer insulating film 13. According to such a configuration, etching is not performed in the dummy region 52 where the interlayer insulating film 13 is relatively thick, and the interlayer insulating film 13 is etched in the active region 51 where the interlayer insulating film 13 is relatively thin. Therefore, it is possible to increase the possibility that the mesa portion adjacent to the gate trench structure 2 is exposed from the first interlayer insulating film 4 of the interlayer insulating film 13. Thereby, it is possible to suppress the variation in the performance of the semiconductor device and the occurrence of a performance defect of the semiconductor device.

[0046] Also, in the first embodiment, a dummy trench structure 3 is provided in the dummy region 52. According to such a configuration, the interlayer insulating film 13 on the first mesa portion 1m adjacent to the gate trench structure 2 and the dummy trench structure 3 can be thinned by thermal sag, so that the possibility that the first mesa portion 1m is exposed from the first interlayer insulating film 4 can be increased.

[0047] Next, as shown in FIG. 13, a source electrode 6 electrically connected to the source layer 1c and the contact layer 1d of the active region 51 and a gate wiring 10 electrically connected to the gate electrode 9 are formed.

[0048] <Summary of the First Embodiment> According to the semiconductor device according to the first embodiment as described above, the first interlayer insulating film 4 covers from the first mesa portion 1m adjacent to the gate trench structure 2 of the active region 51 and the dummy trench structure 3 of the dummy region 52 to the termination region 53 through the dummy trench structure 3. According to such a configuration, the possibility that the mesa portion adjacent to the gate trench structure 2 is exposed from the first interlayer insulating film 4 can be increased. Thereby, it is possible to suppress variations in the performance of the semiconductor device and occurrence of performance defects in the semiconductor device.

[0049] Note that, due to the reflection of the trace of the thickness of the interlayer insulating film 13 that becomes the first interlayer insulating film 4, the thickness of the first interlayer insulating film 4 on the second mesa portion 1n may be larger than the thickness of the first interlayer insulating film 4 of the first mesa portion 1m.

[0050] Also, in the first embodiment, the second interlayer insulating film 5 is embedded in the first trench 2c and on the gate electrode 2b. In such a configuration, it is necessary to reduce the etching amount to some extent so that the second interlayer insulating film 5 is not removed. Therefore, as described above, it is effective to increase the possibility that the mesa portion adjacent to the gate trench structure 2 is exposed from the first interlayer insulating film 4. Further, since the second interlayer insulating film 5 is embedded in the first trench 2c and on the gate electrode 2b, the pitch of the trench structure can be reduced, and an effect of reducing the on-resistance can be expected.

[0051] <Embodiment 2> Figure 14 is a cross-sectional view showing the configuration of a semiconductor device according to this second embodiment, and is a cross-sectional view corresponding to Figure 3. In this second embodiment, the second interlayer insulating film 5 protrudes upward from the first trench 2c and has contact holes on the mesa portion adjacent to the gate trench structure 2 of the active region 51.

[0052] In the active region 51, the source electrode 6 is electrically connected to the source layer 1c and contact layer 1d of the mesa portion via the contact holes of the second interlayer insulating film 5. On the other hand, in the dummy region 52, the source electrode 6 is electrically connected to the contact layer 1d of the mesa portion, but not to the source layer 1c, so the main current does not flow substantially.

[0053] The other configurations of this second embodiment are the same as those of the first embodiment. Even with this configuration, the first interlayer insulating film 4 covers from the first mesa portion 1m through the dummy trench structure 3 to the terminal region 53, thereby increasing the possibility that the mesa portion adjacent to the gate trench structure 2 will be exposed from the first interlayer insulating film 4.

[0054] <Embodiment 3> Figure 15 is a cross-sectional view showing the configuration of a semiconductor device according to this embodiment 3, and is a cross-sectional view corresponding to Figure 3. The configuration of this embodiment 3 is the same as that of embodiment 1, except that the height of the upper surface of the semiconductor substrate 1 in the termination region 53 is lower than the height of the bottom surfaces of the first trench 2c and the second trench 3c.

[0055] Although the cause is unknown, it was confirmed in the sample that, in the configuration shown in Figure 15, the interlayer insulating film 13 after heat treatment tends to become thicker as it moves from the active region 51 to the terminal region 53. For this reason, similar to Embodiment 1, it is effective to increase the possibility that the mesa portion adjacent to the gate trench structure 2 will be exposed from the first interlayer insulating film 4 by having the first interlayer insulating film 4 cover from the first mesa portion 1m through the dummy trench structure 3 to the terminal region 53.

[0056] <Embodiment 4> Figure 16 is a plan view showing the configuration of the semiconductor device according to Embodiment 4, and Figure 17 is a cross-sectional view showing the configuration of the portion indicated by line A-A' in Figure 16. The configuration of Embodiment 4 is the same as that of Embodiment 1, except that the height of the upper surface of the semiconductor substrate 1 in the termination region 53 is greater than or equal to the height of the upper surface of the first mesa portion 1m.

[0057] In the configuration shown in Figure 17, thermal sagging of the interlayer insulating film 13 is less likely to occur in the terminal region 53, so the interlayer insulating film 13 after heat treatment tends to become thicker as it moves from the active region 51 towards the terminal region 53. For this reason, similar to Embodiment 1, it is effective to increase the possibility that the mesa portion adjacent to the gate trench structure 2 will be exposed from the first interlayer insulating film 4 by having the first interlayer insulating film 4 cover from the first mesa portion 1m through the dummy trench structure 3 to the terminal region 53.

[0058] <Embodiment 5> Figure 18 is a plan view showing the configuration of a semiconductor device according to this embodiment 5, and Figure 19 is a cross-sectional view showing the configuration of the portion indicated by line A-A' in Figure 18. In the configuration of this embodiment 5, a terminal trench structure 16 is added to the configuration of embodiment 4.

[0059] As shown in Figures 18 and 19, the terminal trench structure 16 is provided in the terminal region 53 so as to surround the active region 51 and the dummy region 52. In Figure 18, the terminal trench structure 16 is shown in a simplified manner, but as shown in Figure 19, the terminal trench structure 16 includes a third insulating film 16a and a terminal electrode 16b. In the example of Figure 18, the second insulating film 3a and the third insulating film 16a are connected to each other, but they do not necessarily have to be connected to each other.

[0060] The termination electrode 16b is provided in a third trench 16c provided in the semiconductor substrate 1 of the termination region 53, via a third insulating film 16a. In the example of Figure 19, the width and depth of the third trench 16c are the same as the width and depth of the first trench 2c, but they may be slightly different. The well layer 1e is provided at the bottom of the third trench 16c, which helps to suppress electric field concentration at the bottom of the third trench 16c.

[0061] Furthermore, the distance between the dummy trench structure 3 and the end trench structure 16 is greater than the distance between the gate trench structures 2. Also, the distance between the end trench structures 16 is greater than the distance between the gate trench structures 2.

[0062] In this configuration, thermal sagging of the interlayer insulating film 13 occurs in the terminal region 53 due to the terminal trench structure 16. However, because the distance between the dummy trench structure 3 and the terminal trench structure 16 is relatively large, the interlayer insulating film 13 after heat treatment may still tend to become thicker as it moves from the active region 51 towards the terminal region 53. For this reason, similar to Embodiment 1, it is effective to increase the possibility that the mesa portion adjacent to the gate trench structure 2 will be exposed from the first interlayer insulating film 4 by having the first interlayer insulating film 4 cover from the first mesa portion 1m through the dummy trench structure 3 to the terminal region 53.

[0063] Furthermore, according to this embodiment 5, the terminal trench structure 16 and the well layer 1e provide a function similar to that of an FLR (Field Limiting Ring), thereby improving pressure resistance. Note that a pressure-resistant holding structure separate from the terminal trench structure 16 may be provided in the terminal region 53.

[0064] <Embodiment 6> Figure 20 is a cross-sectional view showing the configuration of a semiconductor device according to this embodiment 6, and is a cross-sectional view corresponding to Figure 3. The configuration of this embodiment 6 is the same as the configuration of embodiment 5, except that the height of the upper ends of the dummy electrode 3b and the termination electrode 16b is higher than the height of the upper end of the gate electrode 2b.

[0065] In this configuration, thermal sagging of the interlayer insulating film 13 due to the dummy trench structure 3 and the terminal trench structure 16 is less likely to occur, so the interlayer insulating film 13 after heat treatment tends to become thicker as it moves from the active region 51 towards the terminal region 53. For this reason, similar to Embodiment 1, it is effective to increase the possibility that the mesa portion adjacent to the gate trench structure 2 will be exposed from the first interlayer insulating film 4 by having the first interlayer insulating film 4 cover from the first mesa portion 1m through the dummy trench structure 3 to the terminal region 53. In addition, the equipotential lines can be changed by making the height of the upper ends of the dummy electrode 3b and the terminal electrode 16b higher than the height of the upper end of the gate electrode 2b.

[0066] <Embodiment 7> Figure 21 is a cross-sectional view showing the configuration of a semiconductor device according to this embodiment 7, and is a cross-sectional view corresponding to Figure 3. In this embodiment 7, the configuration is the same as that of embodiment 1, but in cross-sectional view, a plurality of dummy trench structures 3 are arranged in a dummy region 52. The first interlayer insulating film 4 covers the plurality of dummy trench structures 3. With this configuration, even if a relatively thick portion of the interlayer insulating film 13 after heat treatment extends across a plurality of trench structures, the possibility of the mesa portion adjacent to the gate trench structure 2 being exposed from the first interlayer insulating film 4 can be increased.

[0067] <Embodiment 8> Figure 22 is a cross-sectional view showing the configuration of a semiconductor device according to this embodiment 8, and is a cross-sectional view corresponding to Figure 3. The configuration of this embodiment 8 is the same as the configuration of embodiment 1, except that the second mesa portion 1n adjacent to the dummy trench structure 3 on the terminal region 53 side of the semiconductor substrate 1 includes at least one of an n-type layer source layer 1c and a p-type layer base layer 1b.

[0068] With this configuration, in the process shown in Figure 6, the base layer 1b and source layer 1c can be formed over the entire upper surface of the semiconductor substrate 1. Therefore, the number of photomasks used in the process shown in Figure 6 can be reduced, thereby lowering manufacturing costs.

[0069] <Embodiment 9> Figure 23 is a plan view showing the configuration of a semiconductor device according to Embodiment 9. In plan view, the configuration of Embodiment 9 is the same as that of Embodiment 1, except that the dummy trench structure 3 is provided intermittently in the extending direction of the dummy trench structure 3. The number of dummy trench structures 3 provided in the extending direction may be multiple, and their pitch may be, for example, 20 μm.

[0070] With this configuration, it is possible to suppress the collapse of the resist patterned to form the first trench 2c and the second trench 3c, which would prevent the first trench 2c and the second trench 3c from being properly formed.

[0071] <Embodiment 10> The power conversion device according to Embodiment 10 has the semiconductor device according to Embodiments 1 to 9 described above. The power conversion device according to Embodiment 10 is not limited to a specific power conversion device, but the following will describe the case in which the power conversion device according to Embodiment 10 is applied to a three-phase inverter.

[0072] Figure 24 is a block diagram showing the configuration of a power conversion system to which the power conversion device 200 according to this embodiment 10 is applied. The power conversion system shown in Figure 24 consists of a power supply 100, a power conversion device 200, and a load 300. The power supply 100 is a DC power supply and supplies DC power to the power conversion device 200. The power supply 100 can be composed of various power sources, for example, a DC grid, a solar cell, or a storage battery, or a rectifier circuit or AC / DC converter connected to an AC grid. Alternatively, the power supply 100 may be composed of a DC / DC converter that converts DC power output from a DC grid into a predetermined power.

[0073] The power converter 200 is a three-phase inverter connected between the power supply 100 and the load 300. The power converter 200 converts the DC power supplied from the power supply 100 into AC power and supplies the AC power to the load 300. As shown in Figure 24, the power converter 200 includes a main conversion circuit 201, which is a conversion circuit that converts DC power into AC power and outputs it; a drive circuit 202, which outputs drive signals to drive each switching element of the main conversion circuit 201; and a control circuit 203, which outputs control signals to the drive circuit 202 to control the drive circuit 202.

[0074] Load 300 is a three-phase motor driven by AC power supplied from power converter 200. Note that load 300 is not limited to a specific application; it is a motor mounted in various electrical devices, such as hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioning equipment.

[0075] The details of the power converter 200 are described below. The main conversion circuit 201 includes switching elements and freewheeling diodes (not shown). For example, the freewheeling diodes may be built into the switching elements. By switching the switching elements, the main conversion circuit 201 converts the DC power supplied from the power supply 100 into AC power and supplies the AC power to the load 300. Various specific circuit configurations can be envisioned for the main conversion circuit 201, but the main conversion circuit 201 according to this embodiment 10 is a two-level three-phase full-bridge circuit and can be composed of six switching elements and six freewheeling diodes antiparallel to each switching element. As the switching elements of the main conversion circuit 201, semiconductor devices according to any of the embodiments 1 to 9 described above are used. The six switching elements are connected in series in pairs to form upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0076] The drive circuit 202 generates drive signals to drive the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, the drive circuit 202 outputs drive signals to turn on the switching elements and drive signals to turn off the switching elements to the control electrodes of each switching element, according to the control signals from the control circuit 203, which will be described later. When the switching element is kept in the ON state, the drive signal is a voltage signal (ON signal) that is greater than the threshold voltage of the switching element, and when the switching element is kept in the OFF state, the drive signal is a voltage signal (OFF signal) that is less than the threshold voltage of the switching element.

[0077] The control circuit 203 controls the switching elements of the main converter circuit 201 so that the desired power is supplied to the load 300. Specifically, the control circuit 203 calculates the time (on time) that each switching element of the main converter circuit 201 should be in the ON state, based on the power to be supplied to the load 300. For example, the control circuit 203 calculates the time so that the main converter circuit 201 can be controlled by pulse width modulation (PWM) control, which modulates the on time of the switching elements according to the voltage to be output. The control circuit 203 then outputs a control command (control signal) to the drive circuit 202 so that an ON signal is output to the switching elements that should be in the ON state at each point in time, and an OFF signal is output to the switching elements that should be in the OFF state. The drive circuit 202 outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element according to this control signal.

[0078] In the power conversion device according to this embodiment 10, the semiconductor devices according to embodiments 1 to 9 are used as semiconductor devices constituting the main conversion circuit 201, thereby suppressing variations in the performance of the semiconductor devices and performance defects of the semiconductor devices.

[0079] In this embodiment 10, an example of applying the semiconductor device according to embodiments 1 to 9 to a two-level three-phase inverter was described. However, this embodiment 10 is not limited to this and can be applied to various power conversion devices. Although the power conversion device according to this embodiment 10 is described as a two-level power conversion device, it may also be a three-level or multi-level power conversion device, and when supplying power to a single-phase load, the power conversion device may be applied to a single-phase inverter. Furthermore, when supplying power to a DC load, it is also possible to apply the power conversion device to a DC / DC converter or an AC / DC converter.

[0080] Furthermore, the power conversion device according to this embodiment 10 is not limited to cases where the load is an electric motor, but can also be used, for example, as a power supply device for an electrical discharge machine, a laser processing machine, an induction heating cooker, or a non-contact power supply system, and can even be used as a power conditioner for a solar power generation system or an energy storage system.

[0081] In this disclosure in English, 'a' and 'an' mean one or more. Therefore, 'a', 'an', 'one or more', and 'at least one' can be used interchangeably.

[0082] Furthermore, it is possible to freely combine each embodiment and each variation, and to modify or omit each embodiment and each variation as appropriate.

[0083] The above explanation is illustrative and not limiting in all respects. It should be understood that countless variations not illustrated are conceivable.

[0084] 1 Semiconductor substrate, 1b base layer, 1c source layer, 1m first mesa region, 1n second mesa region, 2 gate trench structure, 2a first insulating film, 2b gate electrode, 2c first trench, 3 dummy trench structure, 3a second insulating film, 3b dummy electrode, 3c second trench, 4 first interlayer insulating film, 5 second interlayer insulating film, 16 termination trench structure, 16a third insulating film, 16b termination electrode, 16c third trench, 51 active region, 52 dummy region, 53 termination region, 200 power converter, 201 main converter circuit, 202 drive circuit, 203 control circuit.

Claims

1. A semiconductor device comprising: a semiconductor substrate in which an active region, a dummy region, and a termination region are defined in this order from the inside out in a plan view; a gate trench structure having a gate electrode provided via a first insulating film in a first trench provided in the semiconductor substrate in the active region; a dummy trench structure having a dummy electrode provided via a second insulating film in a second trench provided in the semiconductor substrate in the dummy region; and a first interlayer insulating film covering the semiconductor substrate from a first mesa portion adjacent to the gate trench structure and the dummy trench structure through the dummy trench structure to the termination region.

2. A semiconductor device according to claim 1, wherein the thickness of the first interlayer insulating film on the second mesa portion adjacent to the dummy trench structure on the terminal region side of the semiconductor substrate is greater than the thickness of the first interlayer insulating film on the first mesa portion.

3. A semiconductor device according to claim 1 or claim 2, further comprising a second interlayer insulating film embedded in the first trench and on the gate electrode.

4. A semiconductor device according to claim 1 or claim 2, further comprising a second interlayer insulating film that protrudes from the first trench and has contact holes on the mesa portion of the active region.

5. A semiconductor device according to any one of claims 1 to 4, wherein the height of the upper surface of the semiconductor substrate in the termination region is lower than the height of the bottom surfaces of the first trench and the second trench.

6. A semiconductor device according to any one of claims 1 to 5, wherein the height of the upper surface of the semiconductor substrate in the termination region is equal to or greater than the height of the upper surface of the first mesa portion.

7. A semiconductor device according to claim 6, further comprising a termination trench structure having a termination electrode provided via a third insulating film in a third trench provided in the semiconductor substrate in the termination region, wherein the distance between the dummy trench structure and the termination trench structure is greater than the distance between the gate trench structures.

8. A semiconductor device according to any one of claims 1 to 7, wherein the height of the upper end of the dummy electrode is greater than the height of the upper end of the gate electrode.

9. A semiconductor device according to any one of claims 1 to 8, wherein, in a cross-sectional view, a plurality of the dummy trench structures are arranged in the dummy region, and the first interlayer insulating film covers the plurality of dummy trench structures.

10. A semiconductor device according to any one of claims 1 to 9, wherein the dummy electrode is a floating electrode.

11. A semiconductor device according to claim 1, wherein the second mesa portion of the semiconductor substrate adjacent to the dummy trench structure on the terminal region side includes at least one of an n-type layer and a p-type layer.

12. A semiconductor device according to any one of claims 1 to 11, wherein, in a plan view, the dummy trench structure is provided intermittently in the direction of extension of the dummy trench structure.

13. A power conversion device comprising a semiconductor device according to any one of claims 1 to 12, a conversion circuit that converts and outputs input power, a drive circuit that outputs a drive signal to the semiconductor device for driving the semiconductor device, and a control circuit that outputs a control signal to the drive circuit for controlling the drive circuit.

14. A semiconductor device manufacturing method comprising: preparing a semiconductor substrate in which an active region, a dummy region, and a termination region are defined in this order from the inside out in a plan view; forming a gate trench structure having a gate electrode provided via a first insulating film in a first trench provided in the semiconductor substrate in the active region; forming a dummy trench structure having a dummy electrode provided via a second insulating film in a second trench provided in the semiconductor substrate in the dummy region; and forming a first interlayer insulating film covering the semiconductor substrate from a first mesa portion adjacent to the gate trench structure and the dummy trench structure through the dummy trench structure to the termination region.

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