On-substrate inductor for integrated packages

Abstract

A packaging substrate includes a core. The packaging substrate further includes multiple layers on a first side of the core. The multiple layers include a first conductive layer, a second conductive layer, a magnetic layer, and at least one dielectric layer. The magnetic layer and the at least one dielectric layer separate the first conductive layer and the second conductive layer. The packaging substrate further includes multiple vias electrically coupling the first conductive layer with the second conductive layer. The first conductive layer, the second conductive layer, and the multiple vias form a coil of an inductor. The magnetic layer forms a core of the inductor.

Description

Attorney Docket No.: 39361.321 (L0191PCT)ON-SUBSTRATE INDUCTOR FOR INTEGRATED PACKAGESTECHNICAL FIELD

[0001] Embodiments of the present disclosure relate, in general, to integrated packages, and in particular to monolithic on-substrate inductors for heterogeneously integrated packages and methods of forming such monolithic on-substrate inductors for heterogeneously integrated packages.BACKGROUND

[0002] Demand for compact yet powerful electronic technology has catalyzed a shift in the design and fabrication of internal components. One such shift is the miniaturization of integrated circuits (ICs). Smaller ICs mean more components can fit into a given area, leading to enhanced functionality and efficiency within a given technology. Modem, high-density configurations are essential for achieving target levels of performance and efficiency.

[0003] Within semiconductor device fabrication, connecting such high-density ICs to further circuity can be helpful. For instance, connecting such an IC to a packaging substrate not only provides a physical base for the IC but also facilitates the electrical connections for the IC to communicate and operate within a larger electronic system. However, as the components and contacts within ICs shrink to microscopic scales, establishing reliable and effective connections to such a packaging substrate becomes increasingly challenging.SUMMARY

[0004] The following is a simplified summary of the disclosure in order to provide a basic understanding of some aspects of the disclosure. This summary is not an extensive overview of the disclosure. It is intended to neither identify key or critical elements of the disclosure, nor delineate any scope of the particular implementations of the disclosure or any scope of the claims. Its sole purpose is to present some concepts of the disclosure in a simplified form as a prelude to the more detailed description that is presented later.

[0005] In some aspects of the present disclosure, a packaging substrate is provided. The packaging substrate includes a core. The packaging substrate further includes multiple layers on a first side of the core. The multiple layers include a first conductive layer, a second conductive layer, a magnetic layer, and at least one dielectric layer. The magnetic layer and the at least one dielectric layer separate the first conductive layer and the second conductive layer. The packaging substrate further includes multiple vias electrically coupling the first conductive layer with the second conductive layer. The first conductive layer, the secondAttorney Docket No.: 39361.321 (L0191PCT)conductive layer, and the multiple vias form a coil of an inductor. The magnetic layer forms a core of the inductor.

[0006] In some aspects of the present disclosure, a method is provided. The method includes depositing multiple layers on a surface of a packaging substrate. The multiple layers include a first conductive layer, a second conductive layer, a magnetic layer, and at least one dielectric layer. The magnetic layer and the at least one dielectric layer separate the first conductive layer and the second conductive layer. The method further includes forming multiple vias to electrically couple the first conductive layer with the second conductive layer. The first conductive layer, the second conductive layer, and the multiple vias form a coil of an inductor. The magnetic layer forms a core of the inductor.

[0007] In some aspects of the present disclosure, a system is provided. The system includes a packaging substrate. The system further includes an integrated chip (IC) conductively connected to a first side of the packaging substrate. The system further includes a printed circuit board (PCB) conductively connected to a second side of the packaging substrate. The packaging substrate includes a core. The packaging substrate further includes multiple layers on a first side of the core. The multiple layers include a first conductive layer, a second conductive layer, a magnetic layer, and at least one dielectric layer. The magnetic layer and the at least one dielectric layer separate the first conductive layer and the second conductive layer. The packaging substrate further includes multiple vias electrically coupling the first conductive layer with the second conductive layer. The first conductive layer, the second conductive layer, and the multiple vias form a coil of an inductor. The magnetic layer forms a core of the inductor.BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Aspects and implementations of the present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings, which are intended to illustrate aspects and implementations by way of example and not limitation.

[0009] FIG. 1A illustrates a cross-sectional view of an example packaging substrate, according to some embodiments of the present disclosure.

[0010] FIG. IB illustrates a flow diagram of a method to fabricate an example redistribution layer (RDL) of the packaging substrate of FIG. 1A, in accordance with some embodiments of the present disclosure.

[0011] FIG. IC illustrates a flow diagram of a method to form an RDL having an integrated inductor, in accordance with some embodiments of the present disclosure.Attorney Docket No.: 39361.321 (L0191PCT)

[0012] FIGS. 2A-I.2 illustrate a sequence of operations that may be performed to form RDLs having an integrated an inductor, in accordance with embodiments of the present disclosure.DETAILED DESCRIPTION

[0013] Embodiments described herein are directed to a packaging substrate used to connect an integrated circuit (IC) to a printed circuit board (PCB) or other type of circuit, where the packaging substrate includes one or more integrated inductors.

[0014] A packaging substrate can include many vias, pads and electrical interconnects that route pins on an IC (which can be very small and closely spaced) to electrical connections on a PCB (which can be larger and spaced further apart). In some embodiments, the packaging substrate includes a redistribution layer (RDL) that has contact pads for connecting to the IC that are even more closely spaced and / or densely positioned than is typically possible for a remainder of the packaging substrate. In some embodiments, the packaging substrate includes one or more redistribution layers (also referred to as buildup layers) on a core (e.g., such as a silicon core), wherein the one or more redistribution layers include one or more integrated inductors that are monolithically deposited and structured as part of the redistribution layer(s).

[0015] Traditionally, if inductors are to be included on a packaging substrate, those inductors are surface-mount inductors that are separately manufactured and attached to the redistribution layer(s). Such surface-mount inductors have a large area and are powered by long power delivery networks that supply voltage to a power-system-on-chip package for voltage step-down. The long power delivery networks lead to a lossy, high-impedance interconnection and low datacenter operation efficiency. The large area occupied by surfacemount inductors is inefficient for space constraints, especially as electronic devices are manufactured with increasingly smaller sizes. Other traditional methods of including inductors on a packaging substrate include embedding the inductor within the packaging substrate after the packaging substrate has been manufactured. Inductors embedded in this manner may also be inefficient for space constraints and may suffer alignment issues.

[0016] In some embodiments, a package architecture is introduced, with power inductors monolithically deposited and structured as part of the redistribution layer as opposed to assembled inductors or embedded inductor chips. Embodiments are described herein with reference to packaging substrate fabrication methods with inductor formation incorporated into redistribution layer construction for heterogeneous integration. This allows miniaturized inductors with greatly shortened interconnect to a power-system-on-chip package, along withAttorney Docket No.: 39361.321 (L0191PCT)increased component density of a heterogeneously integrated package for reduced routing losses and power delivery network impedance. Such a heterogeneously integrated package may achieve energy -efficient on-demand power conversion for, for example, internet of things (loT) and datacenter applications. This approach brings on-board or in-core inductors in the redistribution layer(s), greatly shrinking inductor dimensions and increasing component density in a package. Additionally, in some embodiments monolithically grown inductors in the redistribution layer(s) closely integrate other functional components together, remarkably shortening interconnects to reduce routing loss and power delivery network impedance. Embodiments provide energy-efficient, low-latency on-demand power conversion to packages.

[0017] A redistribution layer (RDL) of a packaging substrate can act as the link between the IC and the packaging substrate in some embodiments. The densification and miniaturization of ICs means the electrical connection points on them are also smaller and more closely spaced. A modern RDL as discussed herein acts as an intermediary layer that provides an expansion of the connection points within an integrated circuit (IC) to a more manageable size for interfacing with the packaging substrate at large. Thus, the RDL addresses this challenge by 'redistributing' these tiny connection points across a larger area, effectively translating the micro-scale pattern of the IC to a macro-scale pattern compatible with the packaging substrate. The RDL effectively acts as a bridge, enlarging the tiny connection points of an IC to a scale suitable for interfacing with the substrate. By providing a transition zone, the RDL reduces the risk of physical damage during the manufacturing process and operation, ensuring the long-term reliability and functionality of the semiconductor device.

[0018] An RDL can be fabricated layer by layer in some embodiments. Each layer can be developed using processes that involve deposition, etching, and / or patterning techniques.

[0019] Deposition (e.g., such as chemical vapor deposition (CVD) or physical vapor deposition (PVD), etc.) can be used for laying down the conductive and / or dielectric layers of an RDL. CVD involves the creation of a solid material from a gaseous precursor, while PVD deposits thin films through physical means, such as sputtering or evaporation.

[0020] Etching processes, wet or dry, can further be used to remove unwanted material, creating the RDL structure. Wet etching can use chemical solutions to remove material. Dry etching typically involves reactive gases in a vacuum environment.

[0021] Photolithography can play a role in defining the intricate patterns of the layers of an RDL. This often involves coating the packaging substrate with a light-sensitive material, such as photoresist, then exposing it to ultraviolet light through a patterned mask, and developingAttomey Docket No.: 39361.321 (L0191PCT)the image to remove or add either the exposed or unexposed photoresist, depending on the type of resist used.

[0022] The fabrication process for an RDL can involve multiple operations, which means repeated rounds of deposition, etching, and patterning. These processes are employed in a cyclical manner to build up the RDL with multiple layers, each of which can include the same or different materials and / or patterns tailored for specific functions within the device. This iterative process allows for the construction of a complex RDL with precise control over its geometry and material composition.

[0023] One type of connection point between and RDL of a packaging substrate and an IC can be a solder bump, which is a small, spherical deposit of solder material on the exterior of the RDL that is used to create a physical and electrical connection between the integrated circuit (IC) and the packaging substrate or another component. These solder bumps can be useful for technologies such as flip-chip packaging, where the IC is mounted upside-down onto the packaging substrate and the connections are made via these bumps. Other types of contact pads can also be formed on or in the packaging substrate.

[0024] Aspects and embodiments of the present disclosure address the issues implicit in use of assembled and mounted inductors on packages. Systems and methods disclosed herein provide inductors having a decreased area, and that use a shorter power delivery network as compared to traditional mounted or embedded inductors. Systems and methods disclosed herein provide for reduced loss, reduced impedance interconnections, reduced size, and increased operational efficiency in some embodiments.

[0025] FIG. 1A illustrates a cross-sectional view of an example packaging substrate 100A, in accordance with some embodiments of the present disclosure. In some embodiments, the packaging substrate 100A can be used to electrically connect one or more ICs (e.g., ICs 110A-B) to a PCB 170, through one or more electrical interconnects 136 (e.g., conductive pathways) through the packaging substrate.

[0026] The packaging substrate 100 A can include a core 120 and top and bottom redistribution layers (RDLs) 130A-B. Core 120 may be a patterned core in some embodiments. In some embodiments, the core 120may include a substrate formed from a III-V compound semiconductor material, silicon, crystalline silicon (e.g., Si<100> or Si<l 11>), silicon oxide, silicon germanium, doped or undoped silicon, doped or undoped poly silicon, silicon nitride, quartz, glass (e.g., borosilicate glass), sapphire, alumina, and / or ceramic materials. In some embodiments, the core 120 includes a monocrystalline p-type or n-type silicon substrate. In some embodiments, the core 120 includes a poly crystalline p-type or n-Attorney Docket No.: 39361.321 (L0191PCT)type silicon substrate. In some embodiments, the core 120 includes a p-type or an n-type silicon solar substrate. The substrate utilized to form the core 120 may further have a polygonal or circular shape. For example, the core 120 may include a substantially square silicon substrate having lateral dimensions between about 120 mm and about 180 mm, with or without chamfered edges. In another example, the core 120 may include a circular silicon-containing wafer having a diameter between about 20 mm and about 700 mm, such as between about 100 mm and about 50 mm, for example about 300 mm.

[0027] In some embodiments, the core 120 has a thickness Ti between about 50 pm and about 1000 pm, such as a thickness T i between about 70 pm and about 800 pm. For example, the core 120 may have a thickness Ti between about 80 pm and about 400 pm, such as a thickness T i between about 100 pm and about 200 pm. In another example, the core 120 may have a thickness Ti between about 70 pm and about 150 pm, such as a thickness Ti between about 100 pm and about 130 pm. In another example, the core 120 nay have a thickness Ti between about 700 pm and about 800 pm, such as a thickness Ti between about 725 pm and about 775 pm.

[0028] The core 120 may include one or more holes or core vias 122 formed therein to enable conductive electrical interconnections to be routed through the core 120. Generally, the one or more core vias 122 are substantially cylindrical in shape. However, other suitable morphologies for the core vias 122 are also contemplated. The core vias 122 may be formed as singular and isolated core vias 122 through the core 120 or in one or more groupings or arrays. In some embodiments, a minimum pitch Pi between each core via 122 is less than about 1000 pm, such as between about 25 pm and about 200 pm. For example, the pitch Pi may be between about 40 pm and about 150 pm. In some embodiments, the one or more core vias 122 have a diameter Vi less than about 500 pm, such as a diameter Vi less than about 250 pm. For example, the core vias 122 may have a diameter Vi between about 25 pm and about 100 pm, such as a diameter Vi between about 30 pm and about 60 pm. In some embodiments, the core vias 103 have a diameter Vi of about 40 pm.

[0029] An optional passivating layer (not shown) may be formed on one or more surfaces of the core 120, including a first surface (e.g., top surface), a second surface (e.g., bottom surface), and / or one or more sidewalls of the core vias 122. In some embodiments, the passivating layer is formed on substantially all exterior surfaces of the core 120 such that the passivating layer substantially surrounds the core 120. Thus, the passivating layer may provide a protective outer barrier for the core 120 against corrosion and other forms of damage. In some embodiments, the passivating layer is formed of an oxide film or layer, suchAttorney Docket No.: 39361.321 (L0191PCT)as a thermal oxide layer. In some examples, the passivating layer has a thickness between about 100 nm and about 3 pm, such as a thickness between about 200 nm and about 2.5 pm. In one example, the passivating layer 104 has a thickness between about 300 nm and about 2 pm, such as a thickness of about 1.5 pm.

[0030] In some embodiments, top and / or bottom RDLs 130A-B can be deposited or placed onto the core 120 (e.g., over a passivating layer). RDLs 130A-B can include one or more organic build-up layers and / or one or more inorganic build-up layer(s).

[0031] In some embodiments, the RDLs 130A-B can include multiple electrical interconnects 136 (i.e., conductive pathways) passing through a dielectric material. In some embodiments, interconnects 136 can include one or more conductive lines, pads, vias, etc. In some embodiments, conductive lines can span in the X direction as seen in FIG. 1A, while vias can connect the conductive lines in the Y direction. In some embodiments, interconnects 136 can extend through RDLs 130A-B and core 120. In some embodiments, interconnects 136 can extend through the core 120 in what is referred to as a via, or through-core vias (e.g., vias 122).

[0032] In some embodiments, one or more RDLs 130-A-B may include one or more inductors 140 formed therein, as described in greater detail below with reference to the following figures. The inductor 140 may be monolithically included within the one or more RDLs 130-A-B. For example, an inductor 140 may be monolithically formed within the RDL 130A during formation of the RDL 130A, such as during the deposition of the one or more layers comprising the RDL 130A. In some embodiments, the inductor 140 includes a coil surrounding a core. The coil may be made of conductive traces coupled by vias. The traces may be formed from conductive layers deposited during formation of the RDL. The vias may electrically couple corresponding traces to form a continuous coil. A magnetic layer may be disposed between the conductive layers in the RDL. Further details are described herein below.

[0033] In some embodiments, the packaging substrate 100A and / or RDLs 130A-B can include one or more vias 122 that can include at least one plated through-hole (PTH). A PTH refers to a hole that extends between exterior layers of a packaging substrate (i.e., the top layer of the packaging substrate and the bottom layer of the packaging substrate). A packaging substrate 100 A can further include at least one via.

[0034] One example of a via structure is a blind via. A blind via refers to a via that connects an exterior layer of a packaging substrate (e.g., the top layer or the bottom layer) to one or more interior layers of the packaging substrate. Accordingly, blind vias are only visible fromAttorney Docket No.: 39361.321 (L0191PCT)one side of the packaging substrate. Another example of a via is a buried via. A buried via refers to a via formed between two interior layers of a packaging substrate. Accordingly, a buried via may not be visible from either side of the packaging substrate.

[0035] Another example of a via structure that may be used is a through-core via or through-assembly via. One or more through-assembly vias may be formed through one or more of the RDLs 130A-B. In an example, the through-assembly vias may be centrally formed within the core vias 122 having an insulating layer disposed therein. Accordingly, theinsulating layer may form one or more sidewalls of the through-assembly vias, wherein the through-assembly vias may have a diameter V2lesser than the diameter Vi of the core vias 122. In some embodiments, the through-assembly vias have a diameter V2less than about 100 pm, such as less than about 75 m. For example, the through-assembly vias may have a diameter V2less than about 50 pm, such as less than about 35 pm. In some embodiments, the through-assembly vias 113 have a diameter of between about 25 pm and about 50 pm, such as a diameter of between about 35 pm and about 40 pm.

[0036] The through-assembly vias may provide channels through which one ormore electrical interconnections are formed in the packaging substrate 100A. In some embodiments, the electrical interconnections are formed through the entire thickness of the packaging substrate 100A (i.e. from a first major surface to a second major surface of the packaging substrate 100A). For example, the electrical interconnections may have a longitudinal length corresponding to a total thickness of the packaging substrate between about 50 pm and about 1000 pm, such as a longitudinal length between about 200 pm and about 800 pm. In one example, the electrical interconnections have a longitudinal length of between about 400 pm and about 600 pm, such as longitudinal length of about 500 pm. In another embodiment, the electrical interconnections are formed through a portion of the thickness of the packaging substrate 100A (e.g., through the core and through a subset of the RDL layers, such as through the core and through the organic buildup layers). In such embodiment, vias that extend through a portion of the RDL(s) 130A-B and through the cores may be referred to as through-core vias. In further embodiments, the electrical interconnections may protrude from a major surface of the packaging substrate 100A, such as the major surfaces of the packaging substrate 100A. The electrical interconnections may be formed of any conductive materials used in the field of integrated circuits, circuit boards, chip carriers, and the like. For example, the electrical interconnections may be formed of a metallic material, such as copper, aluminum, gold, nickel, silver, palladium, tin, or the like.Attorney Docket No.: 39361.321 (L0191PCT)

[0037] The resulting structure after formation of the through-assembly vias may be described as a “via-in-via” (e.g., a via centrally formed in a dielectric material within a via of the core structure). The via-in-via structure may include a dielectric sidewall passivation including a ceramic-particle-filled epoxy material and disposed on a thin layer of thermal oxide formed on the sidewalls of the core vias 122 in some embodiments.

[0038] In some embodiments, the packaging substrate 100 A can be formed using high density interconnect (HD I) technology. HDI technology can enable a denser packaging substrate design in which more electronics components can be included in a particular area (i.e., reduce the size of a packaging substrate). HD I-based packaging substrates can include at least one plated through-hole (PTH) via or at least one baseband processor (BB) via. HDI-based packaging substratescan further include one or more vias. In some implementations, the one or more vias can include or be referred to as one or more microvias. A microvia can refer to a via hole that has a depth -to-diameter aspect ratio of less than or equal to about 1:1. Due to their size, microvias can be used for high-speed implementations due to a lower parasitic capacitance. Microvias can be formed using any suitable techniques. For example, microvias can be formed by laser drilling via holes, and plating the holes with conductive material (e.g., electroplating).

[0039] The packaging substrate can include a core (e.g., core 120) disposed between the pair of RDLs 130A-B. In some embodiments, the core 120 can be a monolithic piece. In some embodiments, the core 120 is a silicon core, with electrical interconnects formed therein.

[0040] In some embodiments, vias formed in the core can be of a diameter of about 40 micrometers (pm) (e.g., in the X direction as seen in FIG. 1 A).

[0041] In some embodiments, the packaging substrate 100A can be fabricated using a number of cycles (e.g., lamination cycles), where the number of cycles can depend at least in part on the stack design of the packaging substrate. In some embodiments, fabrication can employ cycles to form the RDL including one or more organic buildup layers and / or one or more inorganic buildup layers with a pre-constructed core.

[0042] In some embodiments, the packaging substrate can conductively connect to one or more ICs (e.g., ICs 110A-B) and / or PCBs (e.g., PCB 170) through connecting portions 180 and 160. In some embodiments, connection portions 160 and / or 180 can be distinct types. E.g., in some cases, portions 180 can be input and output (VO) bumps while portions 160 can be VO balls.

[0043] In some embodiments, such connection portions 160 and / or 180 can interact with contact pads 138 of the packaging substrate.Attorney Docket No.: 39361.321 (L0191PCT)

[0044] In some embodiments I / O bumps can be, or include, one or more solder points, or copper pillars capped with solder points protruding from an IC (or PCB). In some embodiments, such I / O bumps and solder points can be small elements located on the surface of the IC. The bumps can serve as the primary points of electrical contact between the IC and the packaging substrate. When an IC is positioned onto the substrate, the bumps can align with corresponding pads of the substrate.

[0045] In some embodiments, I / O balls can be, or include, spheres of solder material attached to an exterior of the packaging substrate. The spheres can serve as a contact point between the substrate 100 and the PCB 170 (or the IC). During assembly, the balls can align with corresponding pads on the PCB 170. In some embodiments, a reflow process can be employed to meltthe spheres. This melting can create a solid and conductive bond between the substrate and the PCB 170.

[0046] A variety of structures and processes can be repeatedly used for fabrication of packaging substrate 100A, as described with respect to the following figures of the disclosure. As such, a brief description of processes, such a deposition, etching, lithography, planarization, etc. will now be given, that can apply to any and all fabrication processes as described below.

[0047] In some embodiments, a deposition process (e.g., such as a plasma-enhanced or plasma-based deposition process) or method can be used to deposit material onto a surface of a substrate. In an example, dielectric materials (e.g., silicon dioxide or silicon nitride) can be deposited via plasma-enhanced chemical vapor deposition (PECVD). For instance, conductive materials (e.g., copper, aluminum, silver, gold, tungsten, molybdenum, etc.) can be deposited via physical vapor deposition (PVD). In some embodiments, additional types of deposition processes (e.g., plasma spraying, atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), electron beam physical vapor deposition (EBPVD), etc.) can be used. Other examples of deposition processes include electroplating, anodization, electroless plating, electroless nickel, electroless palladium, and immersion gold (ENEPIG), etc.

[0048] In some embodiments, a deposition process can deposit dielectric materials or a dielectric layer onto a surface of a substrate. In some embodiments, inorganic dielectric materials may be used to form inorganic buildup layers. In some embodiments, organic dielectric materials may be used to form organic buildup layers. In some embodiments, such dielectric materials can include ABF, silicon dioxide (SiCE), silicon nitride (SislSLi),Attorney Docket No.: 39361.321 (L0191PCT)polyamide, etc. For instance, the dielectric material of a dielectric layer can be a polymer, e.g., polyimide. Such a layer can be used as an electrical insulator.

[0049] In some embodiments, a deposition process can deposit conductive materials that form leads, lines, vias, pads, interconnects, and so on. Deposited conductive materials may be metals, including copper, aluminum, silver, gold, tungsten, molybdenum, etc.

[0050] In some embodiments, a barrier layer can be applied using a deposition process. Such a barrier layer can be deposited between dielectric layers, conductive layers, etc., for example, and can be used to prevent the diffusion of atoms between different layers. Materials used for a barrier layer can include tantalum, titanium, aluminum, silicon etc., or their nitrides e.g., silicon nitride (SisTs ). A barrier layer can be applied when a conductive material such as copper (Cu) or silicon (Si) are used. This can prevent diffusion of the conductive material into the silicon or other materials and layers.

[0051] In some embodiments, a seed layer can be applied using a deposition process. Such a seed layer can be a thin conductive film that serves as a foundation for subsequent conductive material deposition. Such a seed layer can include copper, nickel, or similar metals. In some embodiments, a barrier and seed layer can be deposited simultaneously, as a barrier seed layer.

[0052] In some embodiments, photoresist material can be applied using a deposition process. Photoresist is a light-sensitive material used in lithographic processes to create a patterned mask on the substrate.

[0053] In some embodiments, a lithographic process can be used to pattern a deposited photoresist. Such a process can include exposing the photoresist-coated substrate to an actinic light source through a pattern or mask. Such a process can induce a chemical change in the exposed areas of the photoresist. This can create a pattern in the photoresist that corresponds to a target layout. Afterwards, an etching process can be used to remove material or layers as patterned by the photoresist.

[0054] In some embodiments, an etching process can be performed to etch exposed portions of one or more layers underlying a patterned photoresist. The etching process can be either wet (using chemical solutions) or dry (e.g., using gases or plasmas). Patterned photoresist can serve as a mask for protecting areas of the substrate that should not be etched away.

[0055] After the etching process is complete, remaining photoresist can be removed from a substrate surface. Such a stripping process can involve application of a solvent or chemical solution that dissolves the photoresist without damaging the underlying layers or materials.Attorney Docket No.: 39361.321 (L0191PCT)

[0056] In such away, an etching process can be used to form the cavities to be filled with a conductive material for formation of structures such as leads, lines, vias, contact pads, and so on.

[0057] In some embodiments, a planarization process can be used to produce a flat and smooth surface on the substrate. In some embodiments, a chemical mechanical planarization (CMP) process can be used. In some embodiments, any form of chemical etching or polishing in can be used as is feasible and appropriate.

[0058] In some embodiments, to form a packaging substrate, one or more organic layers of RDLs are formed. Formation of organic buildup layers may include one or more steps of inorganic dielectric layer formation (e.g., via deposition), patterning, etching, conductive material deposition (e.g., to form leads, vias, contact pads, etc.), chemical mechanical planarization, and so on. In some embodiments, organic buildup layers are manufactured using conventional techniques. Atop organic buildup layer may include contact pads and / or other electrically conductive features that protrude from the organic buildup layer.Alternatively, the top organic buildup layer may include contact pads and / or other electrically conductive features that are flush (e.g., co-planar) with a surface of the top organic buildup layer.

[0059] In some embodiments, one or more organic buildup layers include one or more insulating layers (also referred to as dielectric layers) formed on one or more surfaces of the core 120 (or the passivating layer) and may substantially encase the passivating layer and / or the core 120. In some embodiments, the insulating layer may extend into the core vias 122 and coat the passivating layer formed on the sidewalls thereof or directly coat the core 120. In some embodiments, the insulating layer has a thickness T2from an outer surface of the core 120 or the passivating layer to an adjacent outer surface of the insulating layer that is less than about 50 m, such as a thickness T2less than about 20 pm. For example, the insulating layer 118 has thickness T2between about 5 pm and about 10 pm.

[0060] In some embodiments, the organic buildup layer(s) are formed of polymer-based dielectric materials. For example, the organic buildup layer(s) may be formed from a flowable build-up material. In a further embodiment, the organic buildup layer(s) may be formed of an epoxy resin material having a ceramic filler, such as silica (SiO2) particles. Other examples of ceramic fillers that may be utilized include aluminum nitride (AIN), aluminum oxide (A12O3), silicon carbide (SiC), silicon nitride (Si3N4, Sr2Ce2Ti50i6, zirconium silicate (ZrSiO4), wollastonite (CaSiO3), beryllium oxide (BeO), cerium dioxide (CeO2), boron nitride (BN), calcium copper titanium oxide (CaCu3Ti40i2), magnesium oxideAttorney Docket No.: 39361.321 (L0191PCT)(MgO), titanium dioxide (TiO2), zinc oxide (ZnO) and the like. In some examples, the ceramic fillers utilized to form the insulating material of the organic buildup layer(s) have particles ranging in size between about 40 nm and about 1.5 pm, such as between about 80 nm and about 1 pm. For example, the ceramic fillers may have particles ranging in size between about 200 nm and about 800 nm, such as between about 300 nm and about 600 nm. In some embodiments, the ceramic fillers include particles having a size less than about 10% of the width or diameter of adjacent core vias 122 in the core 120, such as a size less than about 5% of the width or diameter of the core vias 122.

[0061] In some embodiments, one or more inorganic buildup layers are formedin addition to, or instead of, the one or more organic buildup layers.

[0062] FIG. IB is a flow chart of a method 190 for forming a package having one or more RDLs with integrated inductors, in accordance with embodiments of the present disclosure. At block 192, a rigid core is formed. This may include inorganic rigid core / substrate structuring that includes laser ablation on a monocrystalline Silicon wafer to create through-vias and / or through-slits.

[0063] At block 193, one or more RDLs with integrated inductors are formed. This may include:I. Performing organic dielectric formation and structuring in some embodiments. In some embodiments, the organic dielectric formation and structuring includes growing a thermal oxide all over the structured monocrystalline Silicon wafer in a furnace, and then laminating the sandwich of dielectric film- structured core / substrate- dielectric film with all through-vias / slits filled by the dielectric material to create a planarized assembly.II. Performing one or more organic dielectric structuring operations, such as drilling smaller vias / slits in the dielectric material through the existing through-Si vias / slits by laser.III. Performing metallization may be by a Semi-Additive Process (SAP).IV. Repeating I. to form one or more organic dielectric layers.V. Depositing one or more magnetic metal layers, followed by a subtractive process for metal patterning.VI. Repeating II. to structure vias surrounding the magnetic metal layer.VII. Repeating III. To build up a side and top Cu shielding.

[0064] FIG. 1C is a flow chart of a method 195 for forming a package having one or more RDLs with integrated inductors, in accordance with embodiments of the present disclosure.

[0065] At block 196, multiple layers are deposited on a surface of a packaging substrate (e.g., core 120). The multiple layers include a first conductive layer, a second conductive layer, aAttorney Docket No.: 39361.321 (L0191PCT)magnetic layer, and at least one dielectric layer. The magnetic layer and the at least one dielectric layer separate the first conductive layer and the second conductive layer. In some embodiments, the first and second conductive layers are deposited using a process such as an electroless plating deposition process, an electrolytic plating deposition process, a conductive paste deposition process, or a screen printing deposition process, etc. In some embodiments, the conductive material for the first and second conductive layers are independently selected from a group of conductive materials including copper, aluminum, silver, gold, etc. For example, the first conductive layer may be a copper layer and the second conductive layer may be an aluminum layer. In another example, the first conductive layer may be a silver layer and the second conductive layer may be a copper layer. Other variations are possible.

[0066] In some embodiments, the first conductive layer is deposited on the packaging substrate. The first conductive layer may be deposited on a dielectric layer on the substrate core, such as a barrier layer. The first conductive layer may be patterned to form first conductive traces (e.g., with a gap between each trace). A dielectric layer may be deposited on the first conductive layer. The deposited dielectric layer may fill gaps between the first conductive traces and / or may cover the first conductive traces. The dielectric layer may be deposited by a lamination deposition process, a spin-on process, a spray-on process, or a slit coating process, etc. A magnetic layer may be deposited on the dielectric layer. The magnetic layer may be deposited using a process such as a sputtering process, a lamination process, or a paste deposition process, etc. The magnetic layer may be comprised of a magnetic compound, such as cobalt zirconium tantalum or another suitable magnetic compound (e.g., a magnetic compound including boron, cobalt, iron, nickel, tantalum, zirconium, etc.). The magnetic layer may be patterned to form a magnetic core. Another dielectric layer may be deposited on the magnetic layer and / or on the patterned magnetic layer. The second conductive layer may be deposited on the dielectric layer so that the dielectric layer(s) and / or the magnetic layer separate the first and second conductive layers. The second conductive layer may be patterned form second conductive traces.

[0067] At block 198, multiple vias are formed to electrically couple the first conductive layer with the second conductive layer. The first conductive layer, the second conductive layer, and the multiple vias form a coil of an inductor (e.g., formed monolithically within the RDLs). The magnetic layer forms a core of the inductor. In some embodiments, holes are formed through the dielectric layer(s) that separate the first and second conductive layers. The holes may be formed to expose the first conductive layer beneath the dielectric layer(s). The holes may be formed by a material removal technique, such as by an etching process (e.g., wetAttomey Docket No.: 39361.321 (L0191PCT)etch, dry etch), or by a laser ablation process. In some embodiments, conductive material (e.g., conductive metal, etc.) is deposited into the holes (e.g., to fill the holes). In some embodiments, the holes are filled during deposition of the second conductive layer. For example, metal may be deposited into the holes. Additional metal may be deposited on top of the filled holes to form the second conductive layer. In some embodiments, the second conductive layer is patterned to form the second conductive traces (e.g., with a gap between each trace). The filled holes (e.g., filled with conductive metal) form vias. In some embodiments, the vias electrically couple a second conductive trace (e.g., of the second conductive layer) with a corresponding first conductive trace (e.g., of the first conductive layer) and so on. The first conductive traces, the second conductive traces, and the vias may form a coil around the magnetic core (e.g., the patterned magnetic layer), together forming an inductor.

[0068] Additional details regarding the monolithic formation of an inductor within RDLs (e.g., of a packaging substrate) are described herein below with respect to FIGS. 2A-I.2.

[0069] FIGS. 2A-I.2 illustrate a sequence of operations that may be performed to form RDLs having an integrated an inductor, in accordance with embodiments of the present disclosure.

[0070] FIG. 2A illustrates an operation 200A. In some embodiments, a rigid core 202 of a package is provided. The core 202 may be a substrate formed from a III-V compound semiconductor material, silicon, crystalline silicon (e.g., Si<100> or Si<l 11>), silicon oxide, silicon germanium, doped or undoped silicon, doped or undoped poly silicon, silicon nitride, quartz, glass (e.g., borosilicate glass), sapphire, alumina, and / or ceramic materials. In some embodiments, core 202 has a thickness between approximately 50 pm and approximately 1 mm. In some embodiments, core 202 corresponds to core 120 of FIG. 1A.

[0071] FIG.2B illustrates an operation 200B. In some embodiments, a dielectric layer 204 is deposited on the surface of the core 202 (e.g., on the top surface of core 202 as illustrated). The dielectric layer 204 may include a dielectric material such as ABF, silicon dioxide (SiCL), silicon nitride (SislSL), polyamide, etc. The dielectric layer 204 may be deposited by a deposition process such as a lamination deposition process, a spin-on process, a spray-on process, or a slit coating process, etc. Other deposition process(es) are possible, such as those described elsewhere herein.

[0072] FIG.2C.1 illustrates an operation 200C.1. In some embodiments, a conductive layer 206 (e.g., a first conductive layer) is deposited on the dielectric layer 204. The conductive layer 206 may be deposited using a process such as an electroless plating deposition process, an electrolytic plating deposition process, a conductive past deposition process, or a screen-Attorney Docket No.: 39361.321 (L0191PCT)printing deposition process, etc. The conductive layer 206 may be a conductive metal layer. The conductive layer 206 may be made of a metal such as copper, aluminum, silver, or gold, etc. Other conductive metals are possible.

[0073] FIG.2C.2 illustrate an operation 200C.2. FIG. 2C.1 may show a cross-sectional side view and FIG. 2C.2 may show a simplified top-down view. In some embodiments, the conductive layer 206 is patterned to form conductive traces 207 (e.g., first conductive traces). The conductive layer 206 may be patterned using known process(es), such as depositing a mask layer, patterning the mask layer (e.g., by digital lithography), and etching the conductive layer 206 based on the patterned mask layer, etc. Other patterning processes are possible. Details for process(es) for patterning a layer may be outside the scope of the present disclosure. Gaps 208 may be formed between the conductive traces 207 by the patterning process(es).

[0074] FIG.2D illustrates an operation 200D. In some embodiments, a dielectric layer 210 is deposited on the conductive layer 206. The dielectric layer 210 may include a dielectric material such as those described herein above. The dielectric layer 210 may be deposited using a suitable deposition process as described herein above. In some embodiments, the dielectric layer 210 fills the gaps 208 between traces 207.

[0075] FIG.2E illustrates an operation 200E. In some embodiments, a magnetic layer 212 is deposited on the dielectric layer 210. The dielectric layer 210 may separate the magnetic layer 212 from the conductive layer206. The magnetic layer 212 may be made of a magnetic material, such as a magnetic metal. The magnetic layer 212 may be deposited using a deposition process such as a sputtered thin film deposition process, a lamination deposition process, or a magnetic paste deposition process, etc. Other deposition processes (such as those described elsewhere herein) are possible. In some embodiments, the magnetic layer 212 includes boron, cobalt, iron, nickel, tantalum, zirconium, or combinations thereof. In some embodiments, the magnetic layer 212 is made from cobalt zirconium tantalum (CZT).

[0076] FIGS. 2F.1 and 2F.2 illustrates an operation 200F. FIG. 2F.1 may show a schematic side view and FIG. 2F.2 may show a simplified top-down view. In some embodiments, the magnetic layer 212 is patterned. The magnetic layer 212 may be patterned using known process(es). The magnetic layer 212 may be patterned to reduce the size (e.g., footprint) of the magnetic layer 212. For example, the footprint of the magnetic layer 212 may be reduced so that the traces 207 extend beyond the edges of the patterned magnetic layer 212.

[0077] FIG.2G illustrates an operation 200G. In some embodiments, a dielectric layer 214 is deposited on the magnetic layer 212 and / or on the dielectric layer 210. The dielectric layerAttorney Docket No.: 39361.321 (L0191PCT)214 may include a dielectric material such as those described herein above. In some embodiments, the dielectric layer 214 is comprised of a dielectric material different from dielectric layer 210. The dielectric layer 214 may be deposited using a suitable deposition process as described herein above.

[0078] FIG.2H.1 and 2H.2 illustrate an operation 200H. FIG. 2H.1 may show a schematic side view and FIG. 2H.2 may show a simplified top-down view. In some embodiments, holes 216 are formed through the dielectric layer 214 and / or the dielectric layer 210. The holes 216 may be formed to expose the conductive layer 206. In some embodiments, the holes 216 are formed by a material removal process such as a dry etch process, a wet etch process, or a laser ablation process, etc. The holes 216 maybe formed over the ends of the traces 207. For example, a first set of holes 216 may be formed over the left ends of the traces 207 (as shown in FIG. 2H.2) and a second set of holes 216 may be formed over the right ends of the traces 207. The magnetic layer 212 may be disposed between the first set of holes 216 and the second set of holes 216.

[0079] FIG. 21.1 illustrates an operation 2001.1. In some embodiments, a conductive layer 218 (e.g., a second conductive layer) is deposited on the dielectric layer 214. The conductive layer 218 may be deposited using a suitable deposition process as described herein above. The conductive layer 218 may be comprised of a conductive metal such as copper, aluminum, silver, or gold, etc. Other conductive metals are possible. In some embodiments, the conductive layer 218 is comprised of a conductive material different from conductive layer 206. In some embodiments, during deposition of the conductive layer 218, vias 220 are formed. The vias 220 may include the same metal as the conductive layer 218. The vias 220 may be formed by depositing the conductive metal (e.g., of conductive layer 218) within the holes 216. Thus, the vias may electrically couple the conductive layer 218 with the conductive layer 206.

[0080] FIG. 21.2 illustrates an operation 2001.2. FIG. 21.1 may show a cross-sectional side view and FIG. 21.2 may show a simplified top-down view. In some embodiments, the conductive layer 218 is patterned to form conductive traces 219 (e.g., second conductive traces). The conductivelayer218 may be patterned using known process(es). Gaps may be formed between the conductive traces 219 by the patterning process(es). In some embodiments, the conductive traces 219 are formed at a diagonal with respect to the traces 207. For example, a left end of a trace 219 (as shown in FIG. 21.2) may be disposed above the left end of a first trace 207 and a right end of the trace 219 may be disposed above the right end of a second trace 207 adjacent to the first trace 207. In some embodiments, the multipleAttorney Docket No.: 39361.321 (L0191PCT)vias electrically couple the traces 219 with the traces 207 in a continuous manner. For example, a first via electrically couples left ends of a trace 219 and a first trace 207, and a second via electrically couples right ends of the trace 219 and a second trace 207 adjacent to the first trace 207. Thus, the conductive traces 219 and 207, and the vias 220 form a continuous path along which electricity can flow.

[0081] In some embodiments, the conductive traces 219 and 207, and the vias 220 form a coil structure of an inductor. The conductive traces219 and 207, and the vias 220 maybe coupled (e.g., electrically coupled) in a coil-like manner. The magnetic layer 212 may form a core structure of the inductor. Electricity may flow through a first conductive trace 219, a first via 220, a first conductive trace 207, a second via 220, a second conductive trace 219, and so on, in a semi-spiral fashion. A magnetic field caused by the magnetic layer 212 may influence the flow of electricity in the conductive traces and vias. Together, the conductive traces 219 and 207, the vias 220, and the magnetic layer form an inductor monolithically formed within an RDL of a packaging substrate in some embodiments.

[0082] Other variations are within spirit of present disclosure. Thus, while disclosed techniques are susceptible to various modifications and alternative constructions, certain illustrated embodiments thereof are shown in drawings and have been described above in detail. It should be understood, however, that there is no intention to limit the disclosure to a specific form or forms disclosed, but on the contrary, the intention is to cover all modifications, alternative constructions, and equivalents falling within the spirit and scope of the disclosure, as defined in appended claims.

[0083] Use of terms “a” and “an” and “the” and similar referents in the context of describing disclosed embodiments (especially in the context of following claims) are to be construed to cover both singular and plural, unless otherwise indicated herein or clearly contradicted by context, and not as a definition of a term. Terms “comprising,” “having,” “including,” and “containing” are to be construed as open-ended terms (meaning “including, but not limited to,”) unless otherwise noted. “Connected,” when unmodified and referring to physical connections, is to be construed as partly or wholly contained within, attached to, or joined together, even if there is something intervening. Recitations of ranges of values herein are merely intended to serve as a shorthand method of referring individually to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated into the specification as if it were individually recited herein. In at least one embodiment, the use of the term “set” (e.g., “a set of items”) or “subset” unless otherwise noted or contradicted by context, is to be construed as a nonempty collection comprising oneAttorney Docket No.: 39361.321 (L0191PCT)or more members. Further, unless otherwise noted or contradicted by context, the term “subset” of a corresponding set does not necessarily denote a proper subset of the corresponding set, but subset and corresponding set can be equal.

[0084] Conjunctive language, such as phrases of the form “at least one of A, B, and C,” or “at least one of A, B and C,” unless specifically stated otherwise or otherwise clearly contradicted by context, is otherwise understood with the context as used in general to present that an item, term, etc., can be either A or B or C, or any nonempty subset of the set of A and B and C. For instance, in an illustrative example of a set having three members, conjunctive phrases “at least one of A, B, and C” and “at least one of A, B and C” refer to any of the following sets: {A}, {B }, {C}, {A, B}, {A, C}, {B, C}, {A, B, C}. Thus, such conjunctive language is not generally intended to imply that certain some embodiments include at least one of A, at least one of B and at least one of C each to be present. In addition, unless otherwise noted or contradicted by context, the term “plurality” indicates a state of being plural (e.g., “a plurality of items” indicates multiple items). In at least one embodiment, the number of items in a plurality is at least two, but can be more when so indicated either explicitly or by context. Further, unless stated otherwise or otherwise clear from context, the phrase “based on” means “based at least in part on” and not “based solely on.”

[0085] Operations of processes described herein can be performed in any suitable order unless otherwise indicated herein or otherwise clearly contradicted by context. In at least one embodiment, a process such as those processes described herein (or variations and / or combinations thereof) is performed under control of one or more computer systems configured with executable instructions and is implemented as code (e.g., executable instructions, one or more computer programs or one or more applications) executing collectively on one or more processors, by hardware or combinations thereof. In at least one embodiment, code is stored on a computer-readable storage medium, for example, in the form of a computer program comprising a plurality of instructions executable by one or more processors. In at least one embodiment, a computer-readable storage medium is a non-transitory computer-readable storage medium that excludes transitory signals (e.g., a propagating transient electric or electromagnetic transmission) but includes non-transitory data storage circuitry (e.g., buffers, cache, and queues) within transceivers of transitory signals. In at least one embodiment, code (e.g., executable code or source code) is stored on a set of one or more non-transitory computer-readable storage media having stored thereon executable instructions (or other memory to store executable instructions) that, whenAttorney Docket No.: 39361.321 (L0191PCT)executed (i.e., as a result of being executed) by one or more processors of a computer system, cause a computer system to perform operations described herein. In at least one embodiment, a set of non-transitory computer-readable storage media comprises multiple non-transitory computer-readable storage media and one or more of individual non-transitory storage media of multiple non-transitory computer-readable storage media lack all of the code while multiple non-transitory computer-readable storage media collectively store all of the code. In at least one embodiment, executable instructions are executed such that different instructions are executed by different processors.

[0086] Accordingly, in at least one embodiment, computer systems are configured to implement one or more services that singly or collectively perform operations of processes described herein and such computer systems are configured with applicable hardware and / or software that enable the performance of operations. Further, a computer system that implements at least one embodiment of present disclosure is a single device and, in another embodiment, is a distributed computer system comprising multiple devices that operate differently such that distributed computer system performs operations described herein and such that a single device does not perform all operations.

[0087] Use of any and all examples, or exemplary language (e.g., “such as”) provided herein, is intended merely to better illuminate embodiments of the disclosure and does not pose a limitation on the scope of the disclosure unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosure.

[0088] In description and claims, terms “coupled” and “connected,” along with their derivatives, can be used. It should be understood that these terms may not be intended as synonyms for each other. Rather, in particular examples, “connected” or “coupled” can be used to indicate that two or more elements are in direct or indirect physical or electrical contact with each other. “Coupled” can also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.

[0089] Although descriptions herein set forth example embodiments of described techniques, other architectures can be used to implement described functionality, and are intended to be within the scope of this disclosure. Furthermore, although specific distributions of responsibilities can be defined above for purposes of description, various functions and responsibilities might be distributed and divided in different ways, depending on circumstances.

[0090] Furthermore, although the subject matter has been described in language specific toAttorney Docket No.: 39361.321 (L0191PCT)structural features and / or methodological acts, it is to be understood that subject matter claimed in appended claims is not necessarily limited to specific features or acts described. Rather, specific features and acts are disclosed as exemplary forms of implementing the claims.

Claims

Attorney Docket No.: 39361.321 (L0191PCT)CLAIMSWhat is claimed is:

1. A packaging substrate, comprising:a core;multiple layers on a first side of the core, the multiple layers comprising a first conductive layer, a second conductive layer, a magnetic layer, and at least one dielectric layer, wherein the magnetic layer and the at least one dielectric layer separate the first conductive layer and the second conductive layer; andmultiple vias electrically coupling the first conductive layer with the second conductive layer, wherein the first conductive layer, the second conductive layer, and the multiple vias form a coil of an inductor, and wherein the magnetic layer forms a core of the inductor.

2. The packaging substrate of claim 1, wherein the multiple vias electrically couple multiple first conductive traces of the first conductive layer with multiple second conductive traces of the second conductive layer, wherein the multiple first conductive traces, the multiple second conductive traces, and the multiple vias form the coil of the inductor.

3. The packaging substrate of claim 2, wherein a first via electrically couples one of the multiple first conductive traces with a corresponding one of the multiple second conductive traces, and wherein a second via electrically couples the corresponding one of the multiple second conductive traces with another one of the multiple first conductive traces.

4. The packaging substrate of claim 1 , wherein the first conductive layer and the second conductive layer are comprised of a metal independently selected from a group of metals comprising copper, aluminum, silver, and gold.

5. The packaging substrate of claim 4, wherein the multiple vias are comprised of a same metal as one of the first conductive layer or the second conductive layer.

6. The packaging substrate of claim 1, wherein the magnetic layer is comprised of a magnetic material comprising at least one of cobalt, boron, iron, nickel, tantalum, or zirconium.Attorney Docket No.: 39361.321 (L0191PCT)7. The packaging substrate of claim 1, wherein the packaging substrate monolithically comprises the inductor within one or more redistribution layers.

8. A method, comprising:depositing multiple layers on a surface of a packaging substrate, wherein the multiple layers comprises a first conductive layer, a second conductive layer, a magnetic layer, and at least one dielectric layer, wherein the magnetic layer and the at least one dielectric layer separate the first conductive layer and the second conductive layer; andforming multiple vias to electrically couple the first conductive layer with the second conductive layer, wherein the first conductive layer, the second conductive layer, and the multiple vias form a coil of an inductor, and wherein the magnetic layer forms a core of the inductor.

9. The method of claim 8, wherein the multiple vias electrically couple multiple first conductive traces ofthe first conductive layer with multiple second conductive traces of the second conductive layer, wherein the multiple first conductive traces, the multiple second conductive traces, and the multiple vias form the coil of the inductor.

10. The method of claim 9, wherein a first via electrically couples one of the multiple first conductive traces with a corresponding one of the multiple second conductive traces, and wherein a second via electrically couples the corresponding one of the multiple second conductive traces with another one of the multiple first conductive traces.

11. The method of claim 8, wherein the first conductive layer and the second conductive layer are deposited using a process independently selected from a group of processes comprising an electroless plating process, an electrolytic plating process, a conductive paste deposition process, or a screen printing deposition process.

12. The method of claim 8, wherein the magnetic layer is deposited using a process selected form a group comprising a sputtering process, a lamination process, or a magnetic paste deposition process, and wherein the magnetic layer is patterned to form the core of the inductor.Attorney Docket No.: 39361.321 (L0191PCT)13. The method of claim 8, wherein the at least one dielectric layer is deposited using a process selected from a group comprising a lamination process, a spin-on process, a spray-on process, or a slit coating process.

14. The method of claim 8, wherein the first conductive layer and the second conductive layer are comprised of a metal independently selected from a group of metals comprising copper, aluminum, silver, and gold.

15. The method of claim 14, wherein the multiple vias are comprised of a same metal as one of the first conductive layer or the second conductive layer.

16. The method of claim 8, wherein the magnetic layer is comprised of a magnetic material comprising at least one of cobalt, boron, iron, nickel, tantalum, or zirconium.

17. The method of claim 8, wherein the packaging substrate monolithically comprises the inductor within one or more redistribution layers.

18. A system, comprising:a packaging substrate;an integrated chip (IC) conductively connected to a first side of the packaging substrate; anda printed circuit board (PCB) conductively connected to a second side of the packaging substrate, wherein the packaging substrate comprises:a core;multiple layers on a first side of the core, the multiple layers comprising a first conductive layer, a second conductive layer, a magnetic layer, and at least one dielectric layer, wherein the magnetic layer and the at least one dielectric layer separate the first conductive layer and the second conductive layer; and multiple vias electrically coupling the first conductive layer with the second conductive layer, wherein the first conductive layer, the second conductive layer, and the multiple vias form a coil of an inductor, and wherein the magnetic layer forms a core of the inductor.Attorney Docket No.: 39361.321 (L0191PCT)19. The system of claim 18, wherein the multiple vias electrically couple multiple first conductive traces ofthe first conductive layer with multiple second conductive traces of the second conductive layer, wherein the multiple first conductive traces, the multiple second conductive traces, and the multiple vias form the coil of the inductor.

20. The system of claim 18, wherein the packaging substrate monolithically comprises the inductor within one or more redistribution layers.

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