Chip, electronic device, capacitor, and manufacturing method therefor

Abstract

The present application relates to the technical field of capacitors. Disclosed in the embodiments of the present application are a chip, an electronic device, a capacitor, and a manufacturing method therefor, which solve the problem that a capacitance density limit occurs when the aspect ratio of holes formed in a deep trench capacitor reaches a limit. The capacitor comprises a substrate, a plurality of conductive layers, a plurality of dielectric layers, and at least two contact holes arranged in a spaced manner on a first side. The plurality of conductive layers and the plurality of dielectric layers are sequentially alternately stacked on the first side of the substrate. At least one contact hole is provided to extend from the topmost conductive layer through an intermediate conductive layer or the bottommost conductive layer, while the remaining contact holes are provided on the side of the topmost conductive layer away from the substrate. The at least two contact holes are connected to the conductive layers amongst the plurality of conductive layers that the contact holes pass through or where the contact holes are provided. At least one contact hole is connected to the at least two conductive layers that the contact hole passes through. The topmost conductive layer is the conductive layer amongst the plurality of conductive layers that is farthest away from the substrate. The bottommost conductive layer is the conductive layer amongst the plurality of conductive layers that is closest to the substrate.

Description

Chips, electronic devices, capacitors and their manufacturing methods

[0001] This application claims priority to Chinese Patent Application No. 202510025079.1, filed on January 7, 2025, entitled “Chip, Electronic Device, Capacitor and Method of Manufacturing Thereof”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of capacitor technology, and in particular to a chip, electronic device, capacitor and method of manufacturing the same. Background Technology

[0003] In the chip manufacturing industry, capacitors are commonly used to regulate the chip power supply system in order to reduce the impedance and noise of the power supply system. Currently, capacitors on the market mainly include planar capacitors and deep trench capacitors (DTC).

[0004] Planar capacitors primarily increase capacitance by adding more layers to expand the electrode area, but this results in a larger capacitor size. Deep trench capacitors, on the other hand, increase capacitance by creating holes or trenches with high aspect ratios to increase the electrode area. However, when the aperture ratio of the holes in a deep trench capacitor reaches its limit, it leads to a capacitance density limit problem. Summary of the Invention

[0005] This application provides a chip, electronic device, capacitor, and a method for manufacturing the same, which solves the problem that the capacitance density limit will occur when the aperture ratio of the holes in existing deep trench capacitors reaches its limit.

[0006] To achieve the above objectives, this application adopts the following technical solution:

[0007] In a first aspect, this application provides a capacitor. The capacitor includes a substrate, multiple conductive layers, multiple dielectric layers, and two or more contact holes (hereinafter referred to as "multiple contact holes" for ease of explanation). The multiple conductive layers and multiple dielectric layers are sequentially and alternately stacked on a first side of the substrate. That is, a dielectric layer is disposed between any two adjacent conductive layers, thereby forming a multilayer capacitor structure. The multiple contact holes are spaced apart on the first side of the substrate. The conductive layer furthest from the substrate among the multiple conductive layers is referred to as the top conductive layer. The conductive layer closest to the substrate among the multiple conductive layers is referred to as the bottom conductive layer.

[0008] Furthermore, the contact holes are specifically blind holes. The shape of the contact holes can be cylindrical, rectangular, or elongated (which can also be called contact grooves); this application does not limit this. One or part of the multiple contact holes penetrates through the middle or bottom conductive layers from the top conductive layer, and the remaining contact holes are located on the side of the top conductive layer away from the substrate. Alternatively, all the multiple contact holes penetrate through the middle or bottom conductive layers from the top conductive layer. The multiple contact holes are respectively connected to the conductive layers that are penetrated or disposed in the multi-layer conductive layers. Thus, the multiple contact holes can connect the multi-layer conductive layers to an external circuit. Alternatively, some of the multiple contact holes are used to connect to a power source, and the remaining contact holes are used for grounding. Thus, the circuit connection of the capacitor is realized.

[0009] In both of the aforementioned distribution methods of multiple contact holes, at least one contact hole is connected to at least two conductive layers it penetrates. That is, among the contact holes that penetrate from the top conductive layer to the middle or bottom conductive layers, at least one contact hole can be simultaneously connected to both conductive layers it penetrates, or to multiple conductive layers it penetrates (here, multiple layers refer to three or more layers). In summary, compared to the prior art, the capacitor of this application, without reducing the number of connected conductive layers, allows one or more of the multiple contact holes to be simultaneously connected to two or more conductive layers it penetrates. Therefore, the number of contact holes required for this capacitor is reduced, significantly decreasing the area occupied by the contact holes in the capacitor structure, resulting in a larger electrode area in the capacitor structure. Consequently, the capacitor of this application can have higher capacitance and capacitance density.

[0010] Based on the above structure, the capacitor of this application can be a planar capacitor or a deep trench capacitor. If the capacitor of this application is a deep trench capacitor, the capacitor can adopt the following structure: the surface on the first side of the substrate is a first surface. A first trench is provided on the first surface. Multiple conductive layers and multiple dielectric layers are sequentially and alternately stacked on the first side of the first surface and in the first trench. Multiple contact holes are respectively located in a portion of the capacitor structure on the first surface. Furthermore, when the substrate material is a dielectric material, the capacitor is a dielectric capacitor.

[0011] Furthermore, in some embodiments of this application, the aforementioned multilayer conductive layers include multiple layers of first conductive layers and multiple layers of second conductive layers arranged in an alternating pattern. The aforementioned plurality of contact holes include first contact holes, which can be connected to the aforementioned multilayer first conductive layers. The first contact holes can be used for grounding or for connection to a power supply or external circuit. Therefore, since all the multiple layers of first conductive layers are connected to the same first contact hole, the area occupied by the contact holes in the aforementioned capacitor structure can be significantly reduced, resulting in a larger electrode area in the capacitor structure and enabling the capacitor to have a higher capacitance value and capacitance density.

[0012] Similarly, based on the above structure, in some other embodiments of this application, the plurality of contact holes further include second contact holes, which are all connected to the multiple layers of second conductive layers. If the first contact hole is used for grounding, the second contact hole is used for connection to a power source. If the first contact hole is used for connection to a power source, the second contact hole is used for grounding. Alternatively, the first and second contact holes are respectively connected to an external circuit. Therefore, since the multiple layers of second conductive layers are all connected to the same second contact hole, the area occupied by the contact holes in the capacitor structure can be significantly reduced, resulting in a larger electrode area in the capacitor structure and a higher capacitance value and capacitance density.

[0013] It should be noted that the first and second conductive layers are staggered. Therefore, when a contact hole penetrates and connects to multiple layers of the first (or second) conductive layer, it needs to be insulated from the penetrated second (or first) conductive layer. Thus, in some embodiments of this application, the contact hole connected to all penetrated layers (here referring to two or more layers) of conductive layer is a stepped contact hole. A stepped contact hole has two or more steps (hereinafter referred to as multiple steps for ease of explanation) and sidewalls. Multiple steps can be located in the two or more conductive layers connected. The contact hole can be electrically connected to the conductive layer at the step. The sidewall is located in the remaining penetrated conductive and dielectric layers. The remaining penetrated conductive and dielectric layers refer to other conductive and dielectric layers that are not connected to the stepped contact hole but are penetrated. Furthermore, the sidewall is located on the side of the step away from the substrate, or between two steps. The capacitor of this application also includes an insulating layer disposed on the sidewall of the stepped contact hole. Therefore, the insulating layer can insulate the stepped contact hole from the conductive layer it penetrates, and can also prevent the conductive layer and dielectric layer from interfering with each other. The thermal expansion of the conductive layer and dielectric layer is more uniform, which can reduce the problem of stress concentration.

[0014] Furthermore, to further improve the capacitance of the capacitor, in some embodiments of this application, for deep trench capacitors, the capacitor has multiple first trenches, which are spaced apart on the first surface of the substrate. Multiple conductive layers and multiple dielectric layers are sequentially and alternately stacked on the first side of the first surface and within the multiple first trenches. Therefore, by increasing the number of first trenches, the area of ​​the electrodes in the capacitor structure is increased, thereby improving the capacitance and capacitance density of the capacitor.

[0015] In addition to the structure described above, the capacitor of this application may also include a dielectric filling layer, which is stacked on the top conductive layer. Furthermore, the capacitor of this application may also include an etch stop layer, which may be stacked between the top conductive layer and the dielectric filling layer. When fabricating multiple contact holes, etching is first performed from the dielectric filling layer to the etch stop layer, and then selective etching is performed on the conductive layers at different depths according to the different contact hole connections. The etch stop layer facilitates the fabrication of multiple contact holes at different depths.

[0016] Secondly, embodiments of this application also include a method for manufacturing a capacitor. The method for manufacturing the capacitor includes the following steps:

[0017] Multiple conductive layers and multiple dielectric layers are sequentially and alternately stacked on the first side of the substrate.

[0018] The capacitor is obtained by forming at least two contact holes at intervals on a first side. One or part of the plurality of contact holes extends from the top conductive layer through the middle or bottom conductive layers, and the remaining contact holes are located on the side of the top conductive layer away from the substrate. Alternatively, all of the plurality of contact holes extend from the top conductive layer through the middle or bottom conductive layers. The plurality of contact holes are respectively connected to the conductive layers that are penetrated or disposed in the multiple conductive layers. Furthermore, at least one contact hole is connected to at least two conductive layers through which it penetrates.

[0019] The capacitor of the first aspect can be manufactured through the above steps. Therefore, the manufacturing method of this application can also solve the above-mentioned technical problems and achieve the same technical effects, which will not be elaborated here.

[0020] The surface on the substrate located on the first side is the first surface. Based on the above method, in some embodiments of this application, the sequential staggered stacking of multiple conductive layers and multiple dielectric layers on the first side of the substrate specifically includes:

[0021] A first groove is formed on the first surface.

[0022] Multiple conductive layers and multiple dielectric layers are sequentially and alternately stacked on the first side of the first surface and in the first trench to form a first layer.

[0023] Therefore, deep trench capacitors can be manufactured through the above steps.

[0024] Furthermore, in some embodiments of this application, the aforementioned forming at least two contact holes at a distance on the first side specifically includes:

[0025] At least two second trenches are formed at intervals on the first side. One or part of the plurality of second trenches extends from the top conductive layer through the middle or bottom conductive layer, and the remaining second trenches are located on the side of the top conductive layer away from the substrate. Furthermore, at least one second trench extending from the top conductive layer through the middle or bottom conductive layer has at least two steps and sidewalls. The at least two steps are located on the at least two conductive layers it penetrates. The sidewalls are located in the remaining penetrated conductive layers and dielectric layers.

[0026] An insulating layer is formed on the sidewall of at least one second trench that extends from the top conductive layer through the middle or bottom conductive layer.

[0027] Conductive material is filled into at least two second trenches to form contact holes. Among these, contact holes having at least two steps and sidewalls are stepped contact holes. An insulating layer separates the stepped contact holes from the conductive layer they penetrate.

[0028] Furthermore, in some embodiments of this application, the method for manufacturing the capacitor further includes: (1) forming multiple conductive layers and multiple dielectric layers sequentially and alternately stacked on the first side of the substrate, with at least two contact holes spaced apart on the first side.

[0029] An etch stop layer and a dielectric fill layer are formed sequentially on the top conductive layer.

[0030] Thirdly, embodiments of this application also include a chip comprising the capacitor described in the first aspect. Since the capacitor in the chip of this application embodiment has the same structure as the capacitor described in the above embodiments, and both can solve the same technical problem and achieve the same technical effect, further details are omitted here.

[0031] Fourthly, embodiments of this application also include an electronic device, comprising a circuit board and the chip described in the above embodiments, wherein the chip is connected to the circuit board. Since the chip in the electronic device of this application has the same structure as the chip described in the above embodiments, and both can solve the same technical problem and achieve the same technical effect, further details are omitted here. Attached Figure Description

[0032] To illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be described below.

[0033] Figure 1 is a schematic diagram of the structure of a first type of capacitor according to an embodiment of this application;

[0034] Figure 2 is a schematic diagram of the structure of a capacitor with an insulating layer according to an embodiment of this application;

[0035] Figure 3 is a schematic diagram of the structure of a capacitor having a cylindrical contact hole in the XY plane according to an embodiment of this application;

[0036] Figure 4 is a schematic diagram of the structure of a capacitor with a contact hole having an elongated groove according to an embodiment of this application;

[0037] Figure 5 is a second schematic diagram of the structure of the first type of capacitor in this application;

[0038] Figure 6 is a schematic diagram of the structure of a capacitor in related technologies;

[0039] Figure 7 is a schematic diagram of the structure of the second type of capacitor according to an embodiment of this application;

[0040] Figure 8 is a schematic diagram of the structure of the third type of capacitor in this application;

[0041] Figure 9 is a schematic diagram of the structure of the fourth type of capacitor in this application;

[0042] Figure 10 is a schematic diagram of the structure of the fifth type of capacitor according to an embodiment of this application;

[0043] Figure 11 is a schematic diagram of the structure of a capacitor with a first trench according to an embodiment of this application;

[0044] Figure 12 is a schematic diagram of the structure of a capacitor with multiple first trenches according to an embodiment of this application;

[0045] Figure 13 is a top view schematic diagram of a sixth type of capacitor having multiple capacitor units according to an embodiment of this application;

[0046] Figure 14 is a top view of a seventh type of capacitor with multiple capacitor units according to an embodiment of this application;

[0047] Figure 15 is a top view of an eighth type of capacitor with multiple capacitor units according to an embodiment of this application;

[0048] Figure 16 is a top view of a ninth type of capacitor with multiple capacitor units according to an embodiment of this application;

[0049] Figure 17 is a schematic diagram of the structure of the tenth type of capacitor with a dielectric filling layer according to an embodiment of this application;

[0050] Figure 18 is a schematic diagram of the structure of the eleventh type of capacitor with an etched stop layer according to an embodiment of this application;

[0051] Figure 19 shows (a), (b), (c), (d), and (e) schematic diagrams of the various steps in the method for manufacturing a capacitor according to an embodiment of this application.

[0052] Figure 20 shows (a), (b), (c), (d), and (e) schematic diagrams of each step S200 in the capacitor manufacturing method of the present application embodiment.

[0053] Reference numerals: 100-Capacitor; R-Capacitor unit; 1-Substrate; 1a-First side; 101-First surface; 1011-First trench; 2 / 2a / 2b / 2c / 2d-Conductive layer; 21-First conductive layer; 22-Second conductive layer; 3 / 3a / 3b / 3c-Dielectric layer; 4 / 4a / 4b / 4c-Contact hole; 40-Second trench; 40S-Conductive material; 41-First contact hole; 42-Second contact hole; 40T-Stepped contact hole; 401 / 401a / 401b / 401c / 401d / 401e / 401f-Step; 402 / 402a / 402b / 402c / 402d / 402e / 402f-Sidewall; 5-Insulating layer; 6-Insulating isolation layer; 7-Dielectric filling layer; 8-Etching stop layer. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of this application clearer, the application will now be described in further detail with reference to the accompanying drawings.

[0055] In the following description, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0056] Furthermore, in this application, directional terms such as "upper," "lower," "left," "right," "horizontal," and "vertical" are defined relative to the indicated placement of the components in the accompanying drawings. It should be understood that these directional terms are relative concepts, used for relative description and clarification, and can change accordingly depending on the placement of the components in the accompanying drawings.

[0057] In this application, unless otherwise expressly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can refer to a mechanical or physical connection. It can be a fixed connection, a detachable connection, or an integral part; it can be a direct connection or an indirect connection through an intermediate medium. It can also be understood as the physical contact and electrical conduction of components, or as the form of connection between different components in a circuit structure through physical lines capable of transmitting electrical signals, such as PCB copper foil or wires.

[0058] This application provides an electronic device that can be used in fields such as base stations, servers, and artificial intelligence (AI). Therefore, the electronic device in this application embodiment may include base station equipment, servers, terminal equipment, and AI devices. The base station equipment may include antennas, baseband units, radio frequency equipment, transmission equipment, and power supply equipment. The terminal equipment may include mobile phones, laptops, tablets, scanners, printers, etc. The AI ​​devices may include smart bracelets, smartwatches, smart glasses, smart speakers, smart robot vacuums, and smart in-vehicle devices. This application embodiment does not impose any special limitations on the specific form of the above-mentioned electronic device.

[0059] Typically, electronic devices can include circuit boards and chips mounted on those boards. The types of chips on the circuit board vary depending on the specific electronic device. For example, chips can include AI chips, memory chips (such as high-bandwidth memory chips), network chips, mobile phone chips, capacitors, and so on.

[0060] Capacitors can be used to regulate power supply systems, reducing impedance and noise. They can be standalone chips or integrated into a single chip. Currently, planar capacitors (such as ceramic capacitors) employ a planar structure, consisting of multiple layers of dielectric and metal materials stacked alternately using mechanical processes. Planar capacitors increase capacitance by increasing the number of layers to expand the electrode area, but this results in a larger size.

[0061] Deep trench capacitors are manufactured by drilling holes (or trenches) with high aspect ratios into a silicon (Si) substrate, forming multiple layers of conductive and dielectric layers stacked within the holes and on the substrate surface, with the dielectric and conductive layers interleaved. Deep trench capacitors increase the area of ​​the capacitor electrodes through the high aspect ratio of the hole walls, thereby increasing the capacitance. However, the aperture ratio of the holes used in current deep trench capacitor fabrication has reached a limit, making it difficult to further increase the capacitance; that is, it reaches the capacitance density limit.

[0062] Therefore, in order to solve the problems of large volume of high-capacity planar capacitors and capacitance density limit of deep trench capacitors, this application provides a capacitor with improved structure. Referring to FIG1, the capacitor 100 of this application embodiment may include a substrate 1, multiple conductive layers 2, multiple dielectric layers 3, and contact holes 4.

[0063] The substrate 1 can be a semiconductor layer made of silicon (Si) or other semiconductor materials (such as silicon carbide (SiC) or germanium (Ge), or a dielectric layer 3 made of oxide or nitride, or a stacked structure composed of a semiconductor material (such as silicon (Si)) and a dielectric layer 3. For ease of explanation, the upper side of the substrate 1 in Figure 1 is referred to as the first side 1a, and the upper surface of the substrate 1 is referred to as the first surface 101. It is understood that when the placement orientation of the capacitor 100 is changed, the positions of the first side 1a and the first surface 101 also change accordingly.

[0064] The conductive layer 2 can be made of titanium nitride (TiN). The dielectric layer 3 can be made of one or more of zirconium oxide (ZrO2), aluminum oxide (Al2O3), and hafnium oxide (HfO2), and this application does not limit this. Furthermore, the multilayer conductive layers 2 and multilayer dielectric layers 3 are sequentially and alternately stacked on the first side 1a of the substrate 1. A dielectric layer 3 is disposed between any two adjacent conductive layers 2 to form a multilayer capacitor structure. The conductive layers 2 serve as the electrode plates of the capacitor.

[0065] For example, the multilayer capacitor structure in the capacitor 100 of this application embodiment can specifically have 3, 4, 5 or more layers, and this application does not limit this. If the capacitor structure is an N-layer structure, the capacitor 100 may include N dielectric layers 3 and N+1 conductive layers 2.

[0066] Taking the three-layer capacitor structure shown in Figure 1 as an example, the capacitor 100 includes three dielectric layers 3 and four conductive layers 2, which can be stacked on the first side 1a of the substrate 1 in the following order: one conductive layer 2, one dielectric layer 3, one conductive layer 2, one dielectric layer 3, one conductive layer 2, one dielectric layer 3, and one conductive layer 2. For ease of explanation, the conductive layer 2 furthest from the substrate 1 among the multiple conductive layers 2 is called the top conductive layer 2. The conductive layer 2 closest to the substrate 1 among the multiple conductive layers 2 is called the bottom conductive layer 2.

[0067] It should be noted that in embodiments where the substrate 1 is made of a semiconductor material, or where one of the layers in the substrate 1 and the bottommost conductive layer 2 is made of a semiconductor material, an insulating layer 5 as shown in Figure 2 can also be provided between the substrate 1 and the multilayer capacitor structure (multilayer conductive layer 2 and multilayer dielectric layer 3). The insulating layer 5 insulates and isolates the substrate 1 from the bottommost conductive layer 2. Specifically, the insulating layer 5 can be made of an oxide, such as silicon dioxide (SiO2).

[0068] In this application embodiment, the contact hole 4 can have various shapes. For example, the cross-section of the contact hole 4 in the XY plane can be a circle as shown in Figure 3, or a rectangle or square, or a strip shape as shown in Figure 4, etc., and this application does not limit this. Depending on the shape, the contact hole 4 can also be a via shape (such as a rectangular, square, or cylindrical hole as shown in Figure 3), or a trench shape (as shown in Figure 4, a strip trench, which can also be called a contact trench). This application embodiment does not limit the size of the contact hole 4; the size can include length, width, depth, etc.

[0069] Furthermore, the capacitor 100 in this application embodiment may have two or more contact holes 4, and this application does not impose any limitation on this. For ease of explanation, the two or more contact holes 4 in the embodiments of this application will be referred to as "multiple contact holes 4".

[0070] In some embodiments, as shown in FIG2, one or more contact holes 4 are disposed from the topmost conductive layer 2 through the middle or bottommost conductive layers 2, and the remaining contact hole 4 is disposed on the side of the topmost conductive layer 2 away from the substrate 1. The multiple contact holes 4 are respectively connected to the conductive layers 2 that are penetrated or disposed in the multilayer conductive layers 2. Specifically, the material of the contact holes 4 can be tungsten (W), aluminum (Al), copper (Cu), or other conductive materials, which are not limited in this application.

[0071] Furthermore, referring back to Figure 1, the multiple contact holes 4 can connect the aforementioned multilayer conductive layer 2 to an external circuit. Alternatively, as shown in Figure 2, some of the multiple contact holes 4 are used to connect to a power source, while the remaining contact holes 4 are used for grounding. This achieves the circuit connection of the capacitor. For ease of explanation, the following description will use the example of multiple contact holes 4 being connected to a power source and a grounding terminal respectively.

[0072] Based on the above structure, as exemplified in Figures 1 and 5, capacitor 100 includes three dielectric layers 3 and four conductive layers 2, forming a three-layer capacitor structure. The three dielectric layers 3 are dielectric layer 3a, dielectric layer 3b, and dielectric layer 3c. The four conductive layers 2 are conductive layer 2a, conductive layer 2b, conductive layer 2c, and conductive layer 2d. Conductive layer 2d is the topmost conductive layer. Conductive layer 2a is the bottommost conductive layer. Dielectric layer 3a is located between conductive layer 2a and conductive layer 2b. Dielectric layer 3b is located between conductive layer 2b and conductive layer 2c. Dielectric layer 3c is located between conductive layer 2c and conductive layer 2d.

[0073] Referring again to Figures 1 and 5, the capacitor 100 includes three contact holes 4, namely contact hole 4a, contact hole 4b, and contact hole 4c. Contact hole 4a can sequentially penetrate through conductive layer 2d, dielectric layer 3c, conductive layer 2c, dielectric layer 3b, conductive layer 2b, and dielectric layer 3a to reach or within conductive layer 2a. Contact hole 4a can be electrically connected to conductive layers 2c and 2a, and is insulated from conductive layers 2d and 2b (e.g., separated by insulating material). Contact hole 4b sequentially penetrates through conductive layer 2d, dielectric layer 3c, and dielectric layer 3b to reach or within conductive layer 2b. Contact hole 4b can be electrically connected to conductive layer 2b, and is insulated from conductive layers 2d and 2c. Contact hole 4c is disposed on conductive layer 2d and is electrically connected to conductive layer 2d. Contact hole 4a can connect conductive layer 2c and conductive layer 2a to the power supply, contact hole 4b can ground conductive layer 2b, and contact hole 4c can ground conductive layer 2d. Alternatively, contact hole 4a can ground both conductive layer 2c and conductive layer 2a, contact hole 4b can connect conductive layer 2b to the power supply, and contact hole 4c can connect conductive layer 2d to the power supply.

[0074] Therefore, compared to the capacitor 100 in Figure 6, which requires four contact holes 4 to be connected to four conductive layers 2 respectively, the four contact holes 4 occupy a larger area of ​​conductive layer 2 in the capacitor 100. The two examples above reduce the area occupied by one contact hole 4 in the conductive layer 2 in the capacitor structure, making the area of ​​conductive layer 2 in the capacitor structure larger and improving the capacitance value and capacitance density of the capacitor 100.

[0075] It should be noted that the above is only an example. The three contact holes 4 and the four conductive layers 2 in the capacitor 100 of this application can also adopt other connection combinations. This application does not limit this.

[0076] In other embodiments, as shown in FIG7, multiple contact holes 4 are provided extending from the topmost conductive layer 2 through the middle or bottommost conductive layers 2. The multiple contact holes 4 are respectively connected to the conductive layers 2 that are penetrated in the multi-layer conductive layers 2. Similarly, the multiple contact holes 4 can be used to connect to external circuits, or to connect to a power supply or ground to achieve the circuit connection of the capacitor; further details are omitted here.

[0077] Based on the above structure, for example, the capacitor 100 shown in Figure 7 is similar in structure to the capacitor 100 shown in Figure 5, except that the capacitor 100 shown in Figure 7 includes only 2 contact holes 4, which are contact hole 4a and contact hole 4b respectively.

[0078] The contact hole 4a can sequentially penetrate the conductive layer 2d, the dielectric layer 3c, the conductive layer 2c, the dielectric layer 3b, the conductive layer 2b, the dielectric layer 3a, and back to the conductive layer 2a. The contact hole 4a can be electrically connected to the conductive layers 2c and 2a, and is insulated from the conductive layers 2d and 2b through which it penetrates.

[0079] Contact hole 4b can sequentially penetrate conductive layer 2d, dielectric layer 3c, conductive layer 2c, dielectric layer 3b, and finally conductive layer 2b. Contact hole 4b can be electrically connected to conductive layers 2d and 2b, and is insulated from the conductive layer 2c it penetrates. Contact hole a can connect conductive layers 2c and 2a to a power source, and contact hole 4b can ground both conductive layers 2d and 2b. Alternatively, contact hole 4a can ground conductive layers 2c and 2a, and contact hole 4b can connect conductive layers 2d and 2b to a power source.

[0080] Alternatively, in another example, as shown in Figure 8, similar to the example shown in Figure 7 above, the difference is that both contact holes 4a and 4b can sequentially penetrate the conductive layer 2d, dielectric layer 3c, conductive layer 2c, dielectric layer 3b, conductive layer 2b, dielectric layer 3a, and conductive layer 2a to the insulating layer 5 (or, for a substrate 1 using a dielectric material, to the substrate 1). Contact hole 4a is also electrically connected to conductive layers 2c and 2a, and is insulated from the conductive layers 2d and 2b through which it penetrates. Contact hole 4b is also electrically connected to conductive layers 2d and 2b, and is insulated from the conductive layer 2c through which it penetrates.

[0081] Therefore, compared to the capacitor 100 in Figure 6, the capacitors shown in Figure 7 and Figure 8 only require two contact holes 4 to connect the four conductive layers 2 to the external circuit. This further reduces the area occupied by the contact holes 4 in the conductive layer 2 of the capacitor structure, making the area of ​​the conductive layer 2 in the capacitor structure larger, which further improves the capacitance value and capacitance density of the capacitor 100, without increasing the volume of the capacitor.

[0082] In the above example, the capacitor 100 has fewer conductive layers 2. For a capacitor 100 with more conductive layers 2, reducing the number of contact holes 4 can more significantly improve the capacitance and capacitance density of the capacitor 100.

[0083] In some embodiments of this application, as shown in FIG9, the multilayer conductive layer 2 includes multiple first conductive layers 21 and multiple second conductive layers 22. The number of first conductive layers 21 may be equal to the number of second conductive layers 22. The multiple first conductive layers 21 and multiple second conductive layers 22 are alternately distributed.

[0084] On the first side 1a of the substrate 1, the multiple conductive layers 2 are distributed in the following order: a first conductive layer 21, a dielectric layer 3, a second conductive layer 22, a dielectric layer 3, a first conductive layer 21, a dielectric layer 3, a second conductive layer 22, ..., a first conductive layer 21, a dielectric layer 3, and a second conductive layer 22.

[0085] Alternatively, on the first side 1a of the substrate 1, the multiple conductive layers 2 are distributed in the following order: a second conductive layer 22, a dielectric layer 3, a first conductive layer 21, a dielectric layer 3, a second conductive layer 22, a dielectric layer 3, a first conductive layer 21, ..., a second conductive layer 22, a dielectric layer 3, and a first conductive layer 21. This application does not limit this.

[0086] Furthermore, referring to Figure 9, the plurality of contact holes 4 include a first contact hole 41, which can be connected to all of the aforementioned multilayer first conductive layers 21. The remaining contact holes 4, excluding the first contact hole 41, are respectively connected to the multilayer second conductive layers 22. The first contact hole 41 can be used for grounding, and the remaining contact holes 4, excluding the first contact hole 41, are connected to a power source. Alternatively, the first contact hole 41 can also be used for connection to a power source, and the remaining contact holes 4, excluding the first contact hole 41, are used for grounding.

[0087] Therefore, since all the multiple first conductive layers 21 are connected to the same first contact hole 41, the area occupied by the contact hole 4 in the above capacitor structure of the conductive layer 2 can be significantly reduced, so that the area of ​​the conductive layer 2 in the capacitor structure is larger and the capacitor 100 can have higher capacitance and capacitance density.

[0088] Based on the above embodiments, in other embodiments of this application, as shown in FIG10, the plurality of contact holes 4 in the capacitor 100 include a first contact hole 41 and a second contact hole 42. The first contact hole 41 can be connected to all of the above-mentioned multilayer first conductive layers 21. The second contact hole 42 can be connected to all of the above-mentioned multilayer second conductive layers 22. The first contact hole 41 can be used for grounding, and the second contact hole 42 can be used for connection to a power source. Alternatively, the first contact hole 41 can be used for connection to a power source, and the second contact hole 42 can be used for grounding.

[0089] Therefore, all the multiple first conductive layers 21 are connected to the same first contact hole 41, and all the multiple second conductive layers 22 are connected to the same second contact hole 42. The capacitor 100 of this embodiment only needs two contact holes 4 to connect the multiple first conductive layers 21 and the multiple second conductive layers 22 to the external circuit. This significantly reduces the area occupied by the contact holes 4 in the conductive layers 2 of the capacitor structure, resulting in a larger area of ​​the conductive layers 2 in the capacitor structure, and enabling the capacitor 100 to have higher capacitance and capacitance density.

[0090] The above mainly describes different combination connection schemes of multiple contact holes 4 and multiple conductive layers 2. It should be noted that in the above embodiments, the contact holes 4 electrically connected to all the penetrating multiple (here referring to two or more) conductive layers 2 can be stepped contact holes. As shown in Figure 10, the stepped contact hole 40T has multiple (here referring to two or more) steps 401 and sidewalls 402. The multiple steps 401 are respectively located in the connected multiple conductive layers 2. Alternatively, one of the multiple steps 401 is located on the substrate 1 (without the insulating layer 5) or the insulating layer 5, and the remaining steps 401 are located in the connected multiple conductive layers 2. The contact hole 4 can be electrically connected to the conductive layer 2 at the step 401. The sidewall 402 is located in the remaining penetrating conductive layers 2 and dielectric layers 3. The remaining penetrating conductive layers 2 and dielectric layers 3 refer to other conductive layers 2 and dielectric layers 3 that are not connected to the stepped contact hole 40T but penetrate it. Furthermore, the sidewall 402 is located on the side of the topmost step 401 (referring to the step 401 furthest from the base 1) away from the base 1, or between two steps 401. It should be noted that ideally, step 401 is a plane, and ideally, sidewall 402 is a plane perpendicular to step 401. However, it is understandable that in actual manufacturing, both step 401 and sidewall 402 will have uneven structures.

[0091] Based on this, in some embodiments of this application, the capacitor 100 further includes an insulating spacer 6 as shown in Figures 1 to 10, which is disposed on the sidewall 402 of the stepped contact hole 40T. Thus, the insulating spacer 6 can insulate the contact hole 4 from the penetrating conductive layer 2, and also prevent the penetrating conductive layer 2 from interfering with the dielectric layer 3. The thermal expansion of the penetrating conductive layer 1 and dielectric layer 3 is more uniform, reducing stress concentration problems.

[0092] For example, as shown in Figure 7, the capacitor 100 has two stepped contact holes 40T, each with two steps 401 and two sidewalls 402. The two steps 401 of contact hole 4a are steps 401a and 401b, and the two sidewalls 402 are sidewalls 402a and 402b. Step 401a is located on or within conductive layer 2a. Similar descriptions follow later; taking step 401a being located within conductive layer 2a as an example, this means that certain process errors are allowed when manufacturing step 401, such as over-etching, which will not be elaborated further. Step 401b is located on or within conductive layer 2c. Sidewall 402a is located between steps 401a and 401b, and sidewall 402b is located above step 401b. Both sidewalls 402a and 402b are covered with an insulating layer 6. The insulating layer 6 on sidewall 402a can insulate and isolate the contact hole 4a from the dielectric layer 3a, conductive layer 2b, dielectric layer 3c and conductive layer 2c between the steps 401a and 401b. The insulating layer 6 on sidewall 402b can insulate and isolate the contact hole 4a from the dielectric layer 3c and conductive layer 2d above the conductive layer 2c.

[0093] The contact hole 4b has two steps 401, namely steps 401c and 401d, and two sidewalls 402, namely sidewalls 402c and 402d. Step 401c is located on or within the conductive layer 2b. Step 401d is located on or within the conductive layer 2d. Sidewall 402c is located in the film layer above the conductive layer 2d (as is the case with capacitor 100, which typically has other film layers on the top conductive layer 2d, as described in detail below). Sidewall 402c is located between steps 401c and 401d. Both the sidewalls 402c and 402d of the contact hole 4b are covered with an insulating layer 6. The insulating layer 6 on the sidewall 402c insulates and isolates the contact hole 4b from the dielectric layer 3b, conductive layer 2c, dielectric layer 3c and conductive layer 2d located between the steps 401c and 401d. The insulating layer 6 on the sidewall 402d insulates and isolates the contact hole 4b from the film layer located above the conductive layer 2d.

[0094] For example, as shown in Figure 8, the contact holes 4a and 4b in the capacitor 100 are both stepped contact holes 40T with three steps 401 and two sidewalls 402. The connection relationship between the contact holes 4 and the conductive layer 2 in the capacitor 100 shown in Figure 8 is the same as that shown in Figure 7. The difference is that the contact hole 4a also has a step 401e and a sidewall 402e, and the contact hole 4b also has a step 401f and a sidewall 402f. Steps 401e and 401f are both located on the insulating layer 5. The sidewall 402e is located between step 401e and step 401a. Step 401f is located between step 401f and step 401c. The sidewalls 402e and 402f are also covered with an insulating layer 6. The insulating layer 6 on sidewall 402e can insulate and isolate the contact hole 4a from the conductive layer 2a located between step 401e and step 401a. The insulating layer 6 on sidewall 402f can insulate and isolate the contact hole 4b from the conductive layer 2a, dielectric layer 3a, and conductive layer 2b located between step 401f and step 401c. In this example, the insulating layer 6 has a larger coverage area, which can further avoid mutual interference between the multilayer conductive layer 2 and the multilayer dielectric layer 3, making the thermal expansion of the multilayer conductive layer 2 and the multilayer dielectric layer 3 more uniform, and further reducing the problem of stress concentration.

[0095] The above describes the film layer where the contact hole 4 is located and the related film layer structure. It should be noted that the capacitor 100 in this embodiment can be a planar capacitor or a deep trench capacitor; this application does not impose any limitations on this.

[0096] In an embodiment where capacitor 100 is a deep trench capacitor, as shown in FIG11, a first trench 1011 is provided on the first surface 101 of the substrate 1. The first trench 1011 has a high aspect ratio. Multiple conductive layers 2 and multiple dielectric layers 3 are sequentially and alternately stacked within the first side 1a of the first surface 101 and the first trench 1011. Furthermore, due to manufacturing limitations, the area where the top conductive layer 2 is located on the inner sidewall of the first trench 1011 may have gaps. Multiple contact holes 4 are located in portions of the areas where the multiple conductive layers 2 and multiple dielectric layers 3 are located on the first surface 101. It can be understood that when the substrate 1 is made of a dielectric material, the aforementioned deep trench capacitor is specifically a dielectric capacitor.

[0097] Furthermore, in order to increase the coverage area of ​​the capacitor structure, in some embodiments of this application, as shown in FIG12, there are multiple first trenches 1011 in the capacitor 100, and the multiple first trenches 1011 are spaced apart on the first surface 101 of the substrate 1. Correspondingly, the multilayer conductive layer 2 and the multilayer dielectric layer 3 are sequentially and alternately stacked in the first side 1a of the first surface 101 and in the multiple first trenches 1011. Therefore, the embodiments of this application increase the coverage area of ​​the capacitor structure by increasing the number of first trenches 1011, thereby improving the capacitance and capacitance density of the capacitor 100.

[0098] It should be noted that the extension direction, shape, and size of the plurality of first trenches 1011 in capacitor 100 can be different, and this application does not impose any restrictions on this. In some scenarios, several first trenches 1011 extending in the same direction and several adjacent contact holes 4 (these contact holes 4 are all used to connect the multilayer conductive layer 2 covering the first trenches 1011) can be regarded as a single capacitor unit. Based on this, in some embodiments, capacitor 100 may include multiple such capacitor units. For example, the capacitor 100 shown in FIG13 includes four capacitor units R, each capacitor unit R including four first trenches 1011 and two contact holes 4, the two contact holes 4 respectively connecting the conductive layer 2 in the first trench 1011 to an external circuit. The contact holes 4 of the four capacitor units R are independent of each other, which can meet different circuit requirements.

[0099] In other scenarios, several first trenches 1011 extending in the same direction can be considered as a single capacitor unit R. Based on this, in some embodiments, the capacitor 100 may include multiple such capacitor units R and several shared contact holes 4, each contact hole 4 being connected to a conductive layer 2 covering the first trench 1011 in an adjacent capacitor unit R. For example, the capacitor 100 shown in FIG. 14 includes four capacitor units and eight shared contact holes 4. Every two adjacent contact holes 4 are arranged in parallel and can be connected to the conductive layers 2 in two adjacent capacitor units R.

[0100] Alternatively, in some other embodiments of this application, as shown in Figures 15 and 16, the extension directions of the first trenches 1011 in the plurality of capacitor cells R in the capacitor 100 may also be the same. The plurality of contact holes 4 in the capacitor 100 are respectively disposed on the outer periphery of the plurality of first trenches 1011.

[0101] In addition to the structure described above, the capacitor 100 of this embodiment may also include a dielectric filling layer 7 as shown in FIG17. The dielectric filling layer 7 is stacked on the top conductive layer 2 and fills the gaps. Specifically, the dielectric filling layer 7 may be an oxide film, a nitride film, or a stacked structure composed of two or more other dielectric layers.

[0102] Considering manufacturing processes, the capacitor 100 of this application may further include an etch-stop layer 8 as shown in FIG. 18. The etch-stop layer 8 may be stacked between the top conductive layer 2 and the dielectric filling layer 7. When fabricating multiple contact holes 4, etching is first performed from the dielectric filling layer 7 to the etch-stop layer 8, and then conductive layers 2 at different depths are connected according to different contact holes 4, allowing for further selective etching control. The etch-stop layer 8 facilitates the fabrication of multiple contact holes 4 at different depths. Specifically, the material of the etch-stop layer 8 may also include one or more of zirconium oxide (ZrO2), aluminum oxide (Al2O3), and hafnium oxide (HfO2), and this application does not impose any limitations on this.

[0103] The above is an illustrative example of using a capacitor 100 as an example in this application. It should be noted that the capacitor 100 in the above embodiment can be used not only as a standalone chip, but also as a device within an integrated circuit. For the latter, the chip can be an AI chip, a memory chip (such as a high-bandwidth memory chip), a network chip, a mobile phone chip, etc., and this application does not impose any limitations on this.

[0104] Based on the structure of the chip described above, to further illustrate this point, this application also provides a method for manufacturing the chip. Referring to FIG19, the manufacturing method includes the following steps:

[0105] S100: Multiple conductive layers 2 and multiple dielectric layers 3 are sequentially stacked on the first side 1a of the substrate 1 in an alternating manner.

[0106] The specific steps of S100 vary depending on the material of the substrate 1. Taking a deep trench capacitor as an example, capacitor 100 is used.

[0107] In some embodiments, if the substrate 1 is a semiconductor material, or if the topmost film layer in the stacked substrate 1 is a semiconductor material layer, then S100 specifically includes:

[0108] S101: A first groove 1011 is formed on the first surface 101 of the substrate 1.

[0109] In some examples, as shown in FIG19(a), a first trench 1011 can be formed on a first surface 101 of substrate 1 by an etching process. In some embodiments, a plurality of spaced first trenches 1011 can be simultaneously etched on the first surface 101 of substrate 1.

[0110] S1021a: An insulating layer 5 is formed on the first surface 101 and in the first trench 1011.

[0111] In some examples, as shown in Figure 19(b), the insulating layer 5 can be formed on the first surface 101 and within the first trench 1011 by atomic layer deposition (ALD) or thermal oxidation. It should be noted that the first trench 1011 is not completely filled with the insulating layer 5; only a thin layer of the insulating layer 5 covers the inner wall of the first trench 1011.

[0112] S1022a: Multiple conductive layers 2 and multiple dielectric layers 3 are sequentially and alternately stacked on the surface of the insulating layer 5 away from the substrate 1. Partial areas of the multiple conductive layers 2 and partial areas of the multiple dielectric layers 3 fill the first trench 1011. Due to process filling issues, the area of ​​the topmost conductive layer 2 located on the sidewall of the first trench 1011 may have gaps.

[0113] In some examples, as shown in Figure 19(c), multiple conductive layers 2 and multiple dielectric layers 3 can be sequentially and alternately stacked on the surface of the insulating layer 5 away from the substrate 1 by the same deposition process.

[0114] S103: An etch stop layer 8 and a dielectric filling layer 7 are sequentially formed on the top conductive layer 2.

[0115] In some examples, as shown in Figure 19(d), an etch stop layer 8 and a dielectric fill layer 7 can be sequentially formed on the top conductive layer 2 using a deposition process. Furthermore, when forming the dielectric fill layer 7, the gaps formed by the top conductive layer 2 can be completely filled.

[0116] In other embodiments, if the substrate 1 is a dielectric material, or if the topmost film layer in the stacked substrate 1 is a dielectric material layer, then the specific steps of S100 described above are similar to those of S100 of the deep trench capacitor described above (i.e., also including S101 and S103), the difference being:

[0117] S102b: Multiple conductive layers 2 and multiple dielectric layers 3 are sequentially and alternately stacked on the first surface 101 and in the first trench 1011.

[0118] In some examples, multiple conductive layers 2 and multiple dielectric layers 3 can be sequentially and alternately stacked on one side of the first surface 101 and within the first trench 1011 using the same deposition process. Similarly, due to process filling issues, the area where the topmost conductive layer 2 is located on the sidewall of the first trench 1011 may have gaps.

[0119] The above is a detailed explanation of S100 in the manufacture of capacitors with different depths.

[0120] S200: Two or more contact holes 4 are formed at intervals on the first side 1a to obtain the capacitor 100 described above. One or part of the plurality of contact holes 4 are disposed through the middle or bottom conductive layers 2 from the topmost conductive layer 2, and the remaining contact holes 4 are disposed on the side of the topmost conductive layer 2 away from the substrate 1. Alternatively, all of the plurality of contact holes 4 are disposed through the middle or bottom conductive layers 2 from the topmost conductive layer 2. The plurality of contact holes 4 are respectively connected to the conductive layers 2 that are penetrated or disposed in the multiple conductive layers 2. Furthermore, at least one contact hole 4 is connected to at least two conductive layers 2 through which it is penetrated.

[0121] In some examples, as shown in FIG19(e), two or more contact holes 4 are formed at intervals on the multilayer conductive layer 2 and the multilayer dielectric layer 3. Furthermore, in some embodiments, referring to FIG20, the above-described S200 specifically includes:

[0122] S201: Two or more second trenches 40 are formed at intervals on the first side 1a. One or part of the plurality of second trenches 40 penetrates from the topmost conductive layer 2 through the middle or bottommost conductive layer 2, and the remaining second trenches 40 are located on the side of the topmost conductive layer 2 away from the substrate 1. Furthermore, at least one second trench 40 penetrating from the topmost conductive layer 2 through the middle or bottommost conductive layer 2 has at least two steps 401 and sidewalls 402. The at least two steps 401 are respectively located on the at least two conductive layers 2 penetrated. The sidewalls 402 are located in the remaining penetrated conductive layers 2 and dielectric layers 3.

[0123] In some embodiments, as shown in FIG20(a), photolithography and etching processes can be used to etch from the dielectric filling layer 7 to the etching stop layer 8 on the first side 1a. Then, as shown in FIG20(b), selective etching is performed according to the desired depth of different second trenches 40, such as controlling parameters like etching rate and etching time, to obtain multiple second trenches 40 of different depths. During the etching process of one or more second trenches 40, two or more steps 401 can be formed on the penetrated conductive layer 2. The step 401 can be the exposed surface of the penetrated conductive layer 2 or the surface of the conductive layer 2 away from the substrate 1, and allows for a certain amount of over-etching on the conductive layer 2. The sidewall 402 of the step 401 on the side away from the substrate 1 or between two adjacent steps 401 is the aforementioned sidewall 402. Alternatively, multiple photolithography and etching processes can be used to form multiple second trenches 40 of different depths. For ease of explanation, a second trench 40 having two or more steps 401 and sidewalls 402 is referred to as a "stepped trench".

[0124] S202: An insulating layer 6 is formed on the sidewall 402 of one or more stepped trenches.

[0125] In some embodiments, as shown in FIG20(c), an insulating isolation layer 6 can be formed within the dielectric filling layer 7 and two or more second trenches 40 by a deposition process. Then, as shown in FIG20(d), the insulating isolation layer 6 on the surface of the step 401 and the upper surface of the dielectric filling layer 7 can be selectively etched away, leaving only the insulating isolation layer 6 on the sidewalls 402 of one or more second trenches 40. Thus, an insulating isolation layer 6 covering the sidewalls 402 of one or more stepped trenches can be obtained.

[0126] S203: Conductive material 40S is filled into all the second trenches 40 to form two or more contact holes 4. Among them, the contact hole 4 having at least two steps 401 and sidewalls 402 is a stepped contact hole 40T. An insulating layer 6 separates the stepped contact hole 40T from the conductive layer 2 it penetrates.

[0127] In some embodiments, as shown in FIG20(e), conductive material 40S can be filled into all second trenches 40 by deposition, and unwanted conductive material 40S in other areas (including areas located on the insulating layer 5 and protruding outside the second trenches 40) can be removed by chemical mechanical polishing (CMP), photolithography, and etching processes to obtain two or more contact holes. Specifically, the conductive material 40S can be tungsten (W), aluminum (Al), copper (Cu), or other conductive materials. It should be noted that if the conductive material 40S is copper, copper can be filled into all second trenches 40 by electroplating.

[0128] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A capacitor, characterized in that, include: Base; A multilayer conductive layer and a multilayer dielectric layer are sequentially and alternately stacked on the first side of the substrate; At least two contact holes are spaced apart on the first side, at least one of the contact holes is disposed through the middle or bottom conductive layer from the top conductive layer, and the remaining contact holes are disposed on the side of the top conductive layer away from the substrate; the at least two contact holes are respectively connected to the conductive layers that are penetrated or disposed in the multilayer conductive layers; and at least one contact hole is connected to at least two conductive layers that are penetrated. The topmost conductive layer is the conductive layer furthest from the substrate among the multilayer conductive layers; the bottommost conductive layer is the conductive layer closest to the substrate among the multilayer conductive layers.

2. The capacitor according to claim 1, characterized in that, The surface on the substrate located on the first side is a first surface; a first groove is provided on the first surface; The multilayer conductive layer and the multilayer dielectric layer are sequentially and alternately stacked on the first side of the first surface and in the first trench.

3. The capacitor according to claim 1 or 2, characterized in that, The multilayer conductive layer includes multiple layers of first conductive layer and multiple layers of second conductive layer arranged in an alternating pattern; the at least two contact holes include: The first contact hole is connected to all the multiple first conductive layers.

4. The capacitor according to claim 3, characterized in that, The at least two contact holes also include: The second contact hole is connected to all the multilayer second conductive layers.

5. The capacitor according to any one of claims 1-4, characterized in that, The contact hole that is connected to at least two conductive layers is a stepped contact hole; the stepped contact hole has at least two steps and sidewalls, and the at least two steps are respectively located on the at least two conductive layers that are connected; The sidewall is located within the remaining penetrating conductive layer and dielectric layer; the capacitor further includes: An insulating isolation layer is disposed on the sidewall of the stepped contact hole to separate the stepped contact hole from the conductive layer that it penetrates.

6. The capacitor according to any one of claims 2-5, characterized in that, There are multiple first trenches, which are spaced apart on the first surface; the multilayer conductive layer and the multilayer dielectric layer are sequentially and alternately stacked on the first side of the first surface and in the multiple first trenches.

7. A method for manufacturing a capacitor, characterized in that, Includes the following steps: Multiple conductive layers and multiple dielectric layers are sequentially and alternately stacked on the first side of the substrate; The capacitor is obtained by forming at least two contact holes spaced apart on the first side. In this configuration, at least one of the contact holes extends from the topmost conductive layer through the middle or bottommost conductive layer, and the remaining contact holes are located on the side of the topmost conductive layer away from the substrate. The at least two contact holes are respectively connected to the conductive layers that are penetrated or disposed within the multilayer conductive layers. Furthermore, at least one contact hole is connected to at least two conductive layers through which it penetrates. The topmost conductive layer is the conductive layer furthest from the substrate among the multilayer conductive layers, and the bottommost conductive layer is the conductive layer closest to the substrate among the multilayer conductive layers.

8. The method for manufacturing a capacitor according to claim 7, characterized in that, The surface on the substrate located on the first side is the first surface; the step of sequentially and alternately stacking multiple conductive layers and multiple dielectric layers on the first side of the substrate specifically includes: A first groove is formed on the first surface; The multilayer conductive layer and the multilayer dielectric layer are sequentially and alternately stacked on the first side of the first surface and in the first trench.

9. The method for manufacturing a capacitor according to claim 8, characterized in that, The step of forming at least two contact holes at intervals on the first side specifically includes: At least two second trenches are formed at intervals on the first side; wherein at least one second trench extends from the topmost conductive layer through the middle or bottommost conductive layer, and the remaining second trenches are disposed on the side of the topmost conductive layer away from the substrate; and at least one second trench extending from the topmost conductive layer through the middle or bottommost conductive layer has at least two steps and sidewalls; the at least two steps are respectively located on the at least two conductive layers that are penetrated; the sidewalls are located in the remaining penetrated conductive layers and the dielectric layer; An insulating layer is formed on the sidewall of at least one of the second trenches that extends from the topmost conductive layer through the middle or bottommost conductive layer; Conductive material is filled into the at least two second trenches to form contact holes; wherein, the contact holes having at least two steps and sidewalls are stepped contact holes; the insulating layer separates the stepped contact holes from the conductive layer that it penetrates.

10. A chip, characterized in that, The capacitor includes any one of claims 1-6 above.

11. An electronic device, characterized in that, include: Circuit board; The chip according to claim 10 is connected to the circuit board.

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