Semiconductor device and manufacturing method therefor

Abstract

The present invention provides a semiconductor device and a manufacturing method therefor. The semiconductor device comprises: a substrate; two body regions formed in the substrate, a groove being formed in the substrate between the two body regions; second epitaxial layers formed on the substrate, each second epitaxial layer extending from part of the corresponding body region to a side wall of the groove; source regions formed in the body regions, each source region extending from the side of the corresponding second epitaxial layer away from the groove to below the second epitaxial layer, and the doping types of the substrate, the second epitaxial layers and the source regions being opposite to the doping type of the body regions; a gate oxide layer formed on the surfaces of the second epitaxial layers and a bottom wall of the groove; and gate layers formed on the gate oxide layer, each gate layer extending from the gate oxide layer above the corresponding second epitaxial layer to the gate oxide layer on the side wall of the groove. The technical solution of the present invention can improve device performance.

Description

Semiconductor devices and their manufacturing methods Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] Compared to silicon, silicon carbide has a wider bandgap, a higher critical breakdown electric field, a higher electron saturation drift velocity, and higher thermal conductivity.

[0003] However, silicon carbide devices have the following problems:

[0004] (1) Silicon carbide power devices have the problem of high turn-on loss in high-frequency applications;

[0005] (2) The on-resistance of planar silicon carbide MOS devices does not reach the ideal level to a certain extent, which restricts the current capability of the devices;

[0006] (3) In applications, planar silicon carbide MOS devices often require the use of PN junction body diodes for freewheeling. However, when the body diode is bipolar conducting, it will produce silicon carbide bipolar degradation effect, which reduces the reliability of the device.

[0007] (4) Due to the wide bandgap of silicon carbide, the turn-on voltage of the body diode is high, resulting in high freewheeling loss of the device.

[0008] Therefore, the above problems need to be solved to improve the performance of silicon carbide devices. Summary of the Invention

[0009] The purpose of this invention is to provide a semiconductor device and a method for manufacturing the same, which enables improved device performance.

[0010] To achieve the above objectives, the present invention provides a semiconductor device, comprising:

[0011] Base;

[0012] Two body regions are formed in the substrate, and a groove is formed in the substrate between the two body regions;

[0013] A second epitaxial layer is formed on the substrate, the second epitaxial layer extending from a portion of the body region to the sidewall of the groove;

[0014] A source region is formed in the body region, extending from the side of the second epitaxial layer away from the groove to below the second epitaxial layer, wherein the doping type of the substrate, the second epitaxial layer, and the source region is opposite to the doping type of the body region;

[0015] A gate oxide layer is formed on the surface of the second epitaxial layer and the bottom wall of the groove;

[0016] A gate layer is formed on the gate oxide layer, the gate layer extending from the gate oxide layer above the second epitaxial layer to the gate oxide layer on the sidewall of the recess.

[0017] Optionally, the substrate includes a bottom-up substrate and a first epitaxial layer, wherein the body region is formed in the first epitaxial layer.

[0018] Optionally, the substrate and the second epitaxial layer are made of silicon carbide.

[0019] Optionally, the bottom wall of the groove is higher than the bottom surface of the body region.

[0020] Optionally, the doping concentration of the second epitaxial layer is greater than the doping concentration of the substrate and less than the doping concentration of the source region.

[0021] Optionally, the semiconductor device further includes:

[0022] A doped region is formed in the substrate on the bottom wall of the groove, the gate oxide layer covers the doped region, the doping type of the doped region is the same as the doping type of the body region, and the doping concentration of the doped region is greater than or equal to the doping concentration of the body region.

[0023] Optionally, the semiconductor device further includes:

[0024] An insulating dielectric layer is formed on the substrate, the insulating dielectric layer fills the groove, and the insulating dielectric layer covers the gate oxide layer and the gate layer;

[0025] A conductive structure is formed on the source region and the body region of the second epitaxial layer on the side away from the groove.

[0026] The present invention also provides a method for manufacturing a semiconductor device, comprising:

[0027] Provide a base;

[0028] Two body regions are formed in the substrate, and a groove is formed in the substrate between the two body regions;

[0029] A second epitaxial layer is formed on the substrate, the second epitaxial layer extending from a portion of the body region to the sidewall of the groove;

[0030] A source region is formed in the body region, the source region extending from the side of the second epitaxial layer away from the groove to below the second epitaxial layer, and the doping types of the substrate, the second epitaxial layer, and the source region are opposite to the doping types of the body region;

[0031] A gate oxide layer is formed on the surface of the second epitaxial layer and the bottom wall of the groove;

[0032] A gate layer is formed on the gate oxide layer, the gate layer extending from the gate oxide layer above the second epitaxial layer to the gate oxide layer on the sidewall of the recess.

[0033] Optionally, the substrate includes a bottom-up substrate and a first epitaxial layer, wherein the body region is formed in the first epitaxial layer.

[0034] Optionally, the substrate and the second epitaxial layer are made of silicon carbide.

[0035] Optionally, the bottom wall of the groove is higher than the bottom surface of the body region.

[0036] Optionally, the doping concentration of the second epitaxial layer is greater than the doping concentration of the substrate and less than the doping concentration of the source region.

[0037] Optionally, after forming the second epitaxial layer on the substrate and before forming the gate oxide layer on the surface of the second epitaxial layer and the bottom wall of the trench, the method of manufacturing the semiconductor device further includes:

[0038] A doped region is formed in the substrate on the bottom wall of the groove. The doping type of the doped region is the same as that of the body region, and the doping concentration of the doped region is greater than or equal to that of the body region.

[0039] Optionally, the method for manufacturing the semiconductor device further includes:

[0040] An insulating dielectric layer is formed on the substrate, the insulating dielectric layer fills the groove, and the insulating dielectric layer covers the source region and the body region of the gate oxide layer, the gate layer, and the side of the second epitaxial layer away from the groove;

[0041] A contact hole is formed in the insulating dielectric layer, the contact hole exposing the source region and the body region of the second epitaxial layer on the side away from the groove;

[0042] A conductive structure is formed in the contact hole.

[0043] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0044] 1. A method for manufacturing a semiconductor device according to the present invention includes: a substrate; two body regions formed in the substrate, with a groove formed in the substrate between the two body regions; a second epitaxial layer formed on the substrate, the second epitaxial layer extending from a portion of the body regions to a sidewall of the groove; a source region formed in the body regions, the source region extending from a side of the second epitaxial layer away from the groove to below the second epitaxial layer, the doping type of the substrate, the second epitaxial layer, and the source region being opposite to the doping type of the body regions; a gate oxide layer formed on the surface of the second epitaxial layer and the bottom wall of the groove; and a gate layer formed on the gate oxide layer, the gate layer extending from the gate oxide layer above the second epitaxial layer to the gate oxide layer on the sidewall of the groove. This enables the reduction of turn-on losses, the reduction of on-resistance, and the improvement of bipolar degradation effects, thereby improving device performance.

[0045] 2. The semiconductor device of the present invention includes: providing a substrate; forming two body regions in the substrate and forming a trench in the substrate between the two body regions; forming a second epitaxial layer on the substrate, the second epitaxial layer extending from a portion of the body regions to a sidewall of the trench; forming a source region in the body regions, the source region extending from a side of the second epitaxial layer away from the trench to below the second epitaxial layer, the doping type of the substrate, the second epitaxial layer, and the source region being opposite to the doping type of the body regions; forming a gate oxide layer on the surface of the second epitaxial layer and the bottom wall of the trench; forming a gate layer on the gate oxide layer, the gate layer extending from the gate oxide layer above the second epitaxial layer to the gate oxide layer on the sidewall of the trench. This enables the reduction of turn-on losses, the reduction of on-resistance, and the improvement of bipolar degradation effects, thereby improving device performance. Attached Figure Description

[0046] Figure 1 is a schematic diagram of the structure of a semiconductor device according to an embodiment of the present invention;

[0047] Figure 2 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0048] Figures 3 to 13 are schematic diagrams of one embodiment of the semiconductor device manufacturing method shown in Figure 2.

[0049] The reference numerals in Figures 1 to 13 are explained as follows: 10-substrate; 101-substrate; 102-first epitaxial layer; 11-body region; 111-body contact region; 12-groove; 13-second epitaxial layer; 131-epitaxy material layer; 14-source region; 15-doped region; 16-gate oxide layer; 17-gate layer; 18-insulating dielectric layer; 181-contact hole; 19-conductive structure. Detailed Implementation

[0050] To make the objectives, advantages, and features of the present invention clearer, the semiconductor device and its manufacturing method proposed in this invention will be further described in detail below. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0051] An embodiment of the present invention provides a semiconductor device comprising: a substrate; two body regions formed in the substrate, wherein a groove is formed in the substrate between the two body regions; a second epitaxial layer formed on the substrate, the second epitaxial layer extending from a portion of the body regions to a sidewall of the groove; a source region formed in the body regions, the source region extending from a side of the second epitaxial layer away from the groove to below the second epitaxial layer, wherein the doping type of the substrate, the second epitaxial layer, and the source region is opposite to the doping type of the body regions; a gate oxide layer formed on the surface of the second epitaxial layer and the bottom wall of the groove; and a gate layer formed on the gate oxide layer, the gate layer extending from the gate oxide layer above the second epitaxial layer to the gate oxide layer on the sidewall of the groove.

[0052] The semiconductor device provided in this embodiment is described in detail below with reference to FIG1, which is a longitudinal cross-sectional schematic diagram of the device.

[0053] The substrate 10 includes a substrate 101 from bottom to top and a first epitaxial layer 102.

[0054] The first epitaxial layer 102 serves as the drift region.

[0055] In one embodiment, the substrate 10 is made of silicon carbide.

[0056] Two body regions 11 are formed in the substrate 10, and a groove 12 is formed in the substrate 10 between the two body regions 11.

[0057] The body region 11 extends from the side of the first epitaxial layer 102 away from the substrate 101 into the first epitaxial layer 102, and the groove 12 is formed in the first epitaxial layer 102 between the two body regions 11.

[0058] The region between the two body regions 11 can be a JFET (Junction Field Effect Transistor) region, and the depth of the JFET region is the same as the depth of the body region 11. The groove 12 is formed in the JFET region.

[0059] The groove 12 is spaced apart from the body region 11 by a certain distance, that is, the sidewall of the groove 12 does not contact the side of the body region 11.

[0060] Preferably, the bottom wall of the groove 12 is higher than the bottom surface of the body region 11, that is, the depth of the groove 12 is less than the depth of the body region 11.

[0061] The second epitaxial layer 13 is formed on the substrate 10 and extends from a portion of the body region 11 to the sidewall of the groove 12.

[0062] In one embodiment, the second epitaxial layer 13 is made of silicon carbide.

[0063] The source region 14 is formed in the body region 11. The source region 14 extends from the side of the second epitaxial layer 13 away from the groove 12 to below the second epitaxial layer 13. The doping type of the substrate 10, the second epitaxial layer 13, and the source region 14 is opposite to the doping type of the body region 11.

[0064] The second epitaxial layer 13 between the source region 14 and the bottom wall of the groove 12 on the side near the groove 12 is used to form a channel.

[0065] In one embodiment, the semiconductor device further includes a body contact region 111 formed in the body region 11 on the side of the source region 14 away from the recess 12. The doping type of the body contact region 111 is the same as that of the body region 11, and the doping concentration of the body contact region 111 is greater than that of the body region 11. The body contact region 111 is used to lead out the body region 11.

[0066] Preferably, the doping concentration of the second epitaxial layer 13 is greater than the doping concentration of the substrate 10 and less than the doping concentration of the source region 14.

[0067] The gate oxide layer 16 is formed on the surface of the second epitaxial layer 13 and the bottom wall of the groove 12.

[0068] If the depletion layer (i.e., the depletion layer in the PN junction formed by the body region 11 and the substrate 10) located below the gate oxide layer 16 on the bottom wall of the groove 12 cannot be completely depleted, the electric field will cause the gate oxide layer 16 on the bottom wall of the groove 12 to break down. Therefore, by forming a doped region 15 in the substrate 10 on the bottom wall of the groove 12 with the same doping type as the body region 11, the depletion layer below the gate oxide layer 16 on the bottom wall of the groove 12 can be completely depleted, thus preventing the electric field from breaking down the gate oxide layer 16 on the bottom wall of the groove 12.

[0069] The gate layer 17 is formed on the gate oxide layer 16, and the gate layer 17 extends from the gate oxide layer 16 above the second epitaxial layer 13 to the gate oxide layer 16 on the sidewall of the recess 12.

[0070] The portions of the two gate layers 17 located on the bottom wall of the groove 12 are not connected, that is, the two gate layers 17 are split gates.

[0071] In one embodiment, the semiconductor device further includes a doped region 15 formed in the substrate 10 on the bottom wall of the recess 12, the gate oxide layer 16 covering the doped region 15, and the doping type of the doped region 15 being the same as the doping type of the body region 11.

[0072] In one embodiment, the doping concentration of the doped region 15 is greater than or equal to the doping concentration of the body region 11, and the doping concentration of the doped region 15 is less than the doping concentration of the body contact region 111.

[0073] In one embodiment, the substrate 10, the second epitaxial layer 13 and the source region 14 are N-type doped, and the body region 11, the body contact region 111 and the doped region 15 are P-type doped.

[0074] The semiconductor device further includes:

[0075] An insulating dielectric layer 18 is formed on the substrate 10, the insulating dielectric layer 18 fills the groove 12, and the insulating dielectric layer 18 covers the gate oxide layer 16 and the gate layer 17;

[0076] A conductive structure 19 is formed on the source region 14 and the body region 11 on the side of the second epitaxial layer 13 away from the groove 12, and the conductive structure 19 is electrically connected to the source region 14 and the body region 11. The conductive structure 19 may also extend to the insulating dielectric layer 18.

[0077] The conductive structure 19 may include an adhesive layer (not shown) and a metal layer (not shown). The adhesive layer is formed on the inner wall of the contact hole where the conductive structure 19 is located, and the metal layer fills the contact hole. The adhesive layer and the metal layer also extend to the insulating dielectric layer 18 around the contact hole.

[0078] If the body contact region 111 is formed in the body region 11 on the side of the source region 14 away from the groove 12, then the contact hole exposes the source region 14 and the body contact region 111 on the side of the second epitaxial layer 13 away from the groove 12, and the conductive structure 19 is electrically connected to the source region 14 and the body contact region 111.

[0079] The semiconductor device further includes a drain (not shown) formed on the side of the substrate 10 away from the groove 12.

[0080] In existing planar silicon carbide MOS devices, after applying voltage to the gate layer and the source region, the current path flows from the source region through the body region and the drift region to the drain. In this invention, after applying voltage to the gate layer 17 and the source region 14, as shown by the arrow in FIG13, the current path flows from the source region 14 through the second epitaxial layer 13 and the drift region (i.e., the first epitaxial layer 102) to the drain.

[0081] In existing planar silicon carbide MOS devices, the body diode formed by the body region and the drift region requires a relatively high turn-on voltage Vsd (i.e., the voltage of the source region relative to the drain) to conduct. However, in this invention, since a second epitaxial layer 13 extending from a portion of the body region 11 to the sidewall of the recess 12 is formed as a channel, when Vgs (i.e., the voltage of the gate layer 17 relative to the source region 14) is 0, a very small turn-on voltage Vsd (i.e., the voltage of the source region 14 relative to the drain) can open the forward current path, thereby avoiding the conduction of the body diode formed by the body region 11 and the drift region due to high Vsd. This is equivalent to eliminating the body diode in the module packaging, thereby saving overall production costs and reducing the device's freewheeling loss.

[0082] Furthermore, if the body diode formed by the body region 11 and the drift region is turned on, holes in the body region 11 (taking P-type doping as an example) will be injected into the drift region. Due to limitations of the epitaxial process, plane dislocation defects (BPDs) will exist in the drift region. Holes will recombine with electrons in the plane dislocation defects, thereby releasing energy. The energy released by the recombination of charge carriers by the plane dislocation defects will form stacking fault defects (SFs). The continuous conduction of the device will cause the stacking fault defects to continuously expand in the drift region. The presence of stacking fault defects will increase the on-resistance and leakage current of the device, and the higher the density of stacking fault defects, the greater the impact, i.e., a bipolar degradation effect occurs. Therefore, by avoiding the conduction of the body diode in this invention, the bipolar degradation effect can be improved, thereby improving the reliability of the device.

[0083] If the groove 12 is not formed between the two body regions 11, that is, if a portion of the substrate 10 between the two body regions 11 is not etched away, a depletion layer (located in the PN junction formed by the body regions 11 and the substrate 10) will be formed between the two body regions 11. To reduce the width of the depletion layer, the gate current needs to continuously charge Cgd (i.e., gate-drain capacitance) at a certain Vgs voltage. Therefore, there will be a plateau period during the device's turn-on process. In this invention, by forming the groove 12 between the two body regions 11, that is, by etching away most of the substrate 10 between the two body regions 11, most of the depletion layer between the two body regions 11 is removed. This reduces the portion of the gate current used to charge the depletion layer in Cgd, so that the gate current is mainly used to charge Cgs (i.e., gate-source capacitance). In other words, the plateau period is shortened, the device turn-on process is accelerated, and the device turn-on loss is reduced.

[0084] Furthermore, if the portions of the two gate layers 17 located above the bottom wall of the recess 12 are connected, a capacitor structure will be formed between the gate layer 17 above the bottom wall of the recess 12 and the drain. This capacitor structure is part of a Miller capacitance (i.e., gate-drain capacitance). Therefore, by forming a split gate in this invention, i.e., the portions of the two gate layers 17 located above the bottom wall of the recess 12 are not connected, the capacitance value of the Miller capacitance can be reduced. Since the capacitance value of the Miller capacitance is positively correlated with the turn-on loss, the turn-on loss of the device is further reduced.

[0085] Furthermore, by forming the groove 12 between the two body regions 11, most of the depletion layer between the two body regions 11 (i.e., the depletion layer in the PN junction formed by the body region 11 and the substrate 10) is removed, thereby eliminating part of the on-resistance of the JFET region between the two body regions 11. That is, the on-resistance of the JFET region between the two body regions 11 is reduced, thereby reducing the overall on-resistance of the device and improving the current capability of the device.

[0086] If the doping concentration of the second epitaxial layer 13 is greater than that of the substrate 10, the carrier mobility of the channel can be increased, thereby reducing the channel resistance. Furthermore, the on-resistance of the accumulation layer in the substrate 10 located directly below the gate layer 17 on the sidewall of the recess 12 can be reduced. This allows the current to flow not only from the second epitaxial layer 13 on the sidewall of the recess 12 towards the drain, but also to diffuse from the region where the accumulation layer is located towards the drain. In other words, the current flow path is widened, allowing the current to flow to the drain more quickly and improving device performance.

[0087] In summary, the present invention provides a semiconductor device comprising: a substrate; two body regions formed in the substrate, wherein a groove is formed in the substrate between the two body regions; a second epitaxial layer formed on the substrate, the second epitaxial layer extending from a portion of the body regions to a sidewall of the groove; a source region formed in the body regions, the source region extending from a side of the second epitaxial layer away from the groove to below the second epitaxial layer, wherein the doping types of the substrate, the second epitaxial layer, and the source region are opposite to the doping type of the body regions; a gate oxide layer formed on the surface of the second epitaxial layer and the bottom wall of the groove; and a gate layer formed on the gate oxide layer, the gate layer extending from the gate oxide layer above the second epitaxial layer to the gate oxide layer on the sidewall of the groove. The semiconductor device provided by the present invention enables improved device performance.

[0088] An embodiment of the present invention provides a method for manufacturing a semiconductor device. Referring to FIG2, it can be seen from FIG2 that the method for manufacturing the semiconductor device includes:

[0089] Step S1, provide a substrate;

[0090] Step S2: Form two body regions in the substrate, and form a groove in the substrate between the two body regions;

[0091] Step S3: Form a second epitaxial layer on the substrate, the second epitaxial layer extending from a portion of the body region to the sidewall of the groove;

[0092] Step S4: A source region is formed in the body region. The source region extends from the side of the second epitaxial layer away from the groove to below the second epitaxial layer. The doping types of the substrate, the second epitaxial layer, and the source region are opposite to the doping types of the body region.

[0093] Step S5: Form a gate oxide layer on the surface of the second epitaxial layer and the bottom wall of the groove;

[0094] Step S6: A gate layer is formed on the gate oxide layer, the gate layer extending from the gate oxide layer above the second epitaxial layer to the gate oxide layer on the sidewall of the recess.

[0095] The manufacturing method of the semiconductor device provided in this embodiment will be described in detail below with reference to Figures 3 to 13. Figures 3 to 13 show schematic longitudinal cross-sectional views of the device.

[0096] Following step S1, referring to Figure 3, a substrate 10 is provided.

[0097] The substrate 10 includes a substrate 101 from bottom to top and a first epitaxial layer 102.

[0098] The first epitaxial layer 102 serves as the drift region.

[0099] In one embodiment, the substrate 10 is made of silicon carbide.

[0100] According to step S2, referring to Figures 4 and 5, two body regions 11 are formed in the substrate 10, and a groove 12 is formed in the substrate 10 between the two body regions 11.

[0101] The body region 11 extends from the side of the first epitaxial layer 102 away from the substrate 101 into the first epitaxial layer 102, and the groove 12 is formed in the first epitaxial layer 102 between the two body regions 11.

[0102] The region between the two body regions 11 can be a JFET (Junction Field Effect Transistor) region, and the depth of the JFET region is the same as the depth of the body region 11. The groove 12 is formed in the JFET region.

[0103] The groove 12 is spaced apart from the body region 11 by a certain distance, that is, the sidewall of the groove 12 does not contact the side of the body region 11.

[0104] The body region 11 is formed by photolithography and ion implantation processes, and the groove 12 is formed by photolithography and etching processes.

[0105] As shown in Figures 4 and 5, the body region 11 can be formed first, and then the groove 12 can be formed; or the groove 12 can be formed first, and then the body region 11 can be formed.

[0106] Preferably, the bottom wall of the groove 12 is higher than the bottom surface of the body region 11, that is, the depth of the groove 12 is less than the depth of the body region 11.

[0107] According to step S3, referring to Figures 6 and 7, a second epitaxial layer 13 is formed on the substrate 10, and the second epitaxial layer 13 extends from a portion of the body region 11 to the sidewall of the groove 12.

[0108] The step of forming the second epitaxial layer 13 on the substrate 10 may include: as shown in FIG6, forming an epitaxial material layer 131 on the substrate 10 using an epitaxial process, wherein the epitaxial material layer 131 covers the body region 11 and fills the groove 12; then, performing photolithography and etching processes to remove a portion of the epitaxial material layer 131 on the body region 11 away from the groove 12 and a portion of the epitaxial material layer 131 in the groove 12, leaving the epitaxial material layer 131 on the sidewall of the groove 12 and on the substrate 11 surrounding the groove 12 as the second epitaxial layer 13.

[0109] In one embodiment, the second epitaxial layer 13 is made of silicon carbide.

[0110] According to step S4, referring to FIG8, a source region 14 is formed in the body region 11. The source region 14 extends from the side of the second epitaxial layer 13 away from the groove 12 to below the second epitaxial layer 13. The doping type of the substrate 10, the second epitaxial layer 13, and the source region 14 is opposite to the doping type of the body region 11.

[0111] The second epitaxial layer 13 between the source region 14 and the bottom wall of the groove 12 on the side near the groove 12 is used to form a channel.

[0112] In one embodiment, after forming the second epitaxial layer 13 on the substrate 10 and before subsequently forming the gate oxide layer 16 on the surface of the second epitaxial layer 13 and the bottom wall of the recess 12, the method of manufacturing the semiconductor device further includes: forming a body contact region 111 in the body region 11 on the side of the source region 14 away from the recess 12. The doping type of the body contact region 111 is the same as that of the body region 11, the doping concentration of the body contact region 111 is greater than that of the body region 11, and the body contact region 111 is used to lead out the body region 11.

[0113] Preferably, the doping concentration of the second epitaxial layer 13 is greater than the doping concentration of the substrate 10 and less than the doping concentration of the source region 14.

[0114] Preferably, as shown in FIG9, after the second epitaxial layer 13 is formed on the substrate 10 and before the gate oxide layer 16 is subsequently formed on the surface of the second epitaxial layer 13 and the bottom wall of the groove 12, the method of manufacturing the semiconductor device further includes: forming a doped region 15 in the substrate 10 on the bottom wall of the groove 12, wherein the doping type of the doped region 15 is the same as the doping type of the body region 11.

[0115] In one embodiment, the doping concentration of the doped region 15 is greater than or equal to the doping concentration of the body region 11, and the doping concentration of the doped region 15 is less than the doping concentration of the body contact region 111.

[0116] In one embodiment, the substrate 10, the second epitaxial layer 13 and the source region 14 are N-type doped, and the body region 11, the body contact region 111 and the doped region 15 are P-type doped.

[0117] The order in which the source region 14, the bulk contact region 111, and the doped region 15 are formed is not limited. The source region 14, the bulk contact region 111, and the doped region 15 can be formed using photolithography and ion implantation processes.

[0118] Furthermore, after the ion implantation processes corresponding to the body region 11, the source region 14, the body contact region 111, and the doped region 15 are all completed, an annealing process is performed to activate the implanted region.

[0119] According to step S5, referring to FIG10, a gate oxide layer 16 is formed on the surface of the second epitaxial layer 13 and the bottom wall of the groove 12.

[0120] In one embodiment, the step of forming the gate oxide layer 16 may include: performing a thermal oxidation process to form an oxide layer (not shown) covering the surfaces of the body contact region 111, the source region 14, the second epitaxial layer 13, and the doped region 15 of the bottom wall of the trench 12; and then performing photolithography and etching processes to remove the oxide layer on the body contact region 111 and the source region 14, leaving the oxide layer as the gate oxide layer 16.

[0121] If the depletion layer (i.e., the depletion layer in the PN junction formed by the body region 11 and the substrate 10) located below the gate oxide layer 16 on the bottom wall of the groove 12 cannot be completely depleted, the electric field will cause the gate oxide layer 16 on the bottom wall of the groove 12 to break down. Therefore, by forming a doped region 15 in the substrate 10 on the bottom wall of the groove 12 with the same doping type as the body region 11, the depletion layer below the gate oxide layer 16 on the bottom wall of the groove 12 can be completely depleted, thus preventing the electric field from breaking down the gate oxide layer 16 on the bottom wall of the groove 12.

[0122] According to step S6, referring to FIG11, a gate layer 17 is formed on the gate oxide layer 16, the gate layer 17 extending from the gate oxide layer 16 above the second epitaxial layer 13 to the gate oxide layer 16 on the sidewall of the recess 12.

[0123] The gate layer 17 can be formed through deposition, photolithography and etching processes.

[0124] The portions of the two gate layers 17 located on the bottom wall of the groove 12 are not connected, that is, the two gate layers 17 are split gates.

[0125] After forming the gate layer 17 on the gate oxide layer 16, the method for manufacturing the semiconductor device further includes:

[0126] As shown in FIG12, an insulating dielectric layer 18 is formed on the substrate 10, the insulating dielectric layer 18 fills the groove 12, and the insulating dielectric layer 18 covers the source region 14 and the body region 11 of the gate oxide layer 16, the gate layer 17 and the second epitaxial layer 13 on the side away from the groove 12.

[0127] As shown in FIG12, a contact hole 181 is formed in the insulating dielectric layer 18, and the contact hole 181 exposes the source region 14 and the body region 11 of the second epitaxial layer 13 on the side away from the groove 12;

[0128] As shown in Figure 13, a conductive structure 19 is formed in the contact hole 181, and the conductive structure 19 is electrically connected to the source region 14 and the body region 11. The conductive structure 19 can also extend from the contact hole 181 to the insulating dielectric layer 18 surrounding the contact hole 181.

[0129] The conductive structure 19 may include an adhesive layer (not shown) formed on the inner wall of the contact hole 181 and a metal layer (not shown) filling the contact hole 181, the adhesive layer and the metal layer also extending to the insulating dielectric layer 18 on the periphery of the contact hole 181.

[0130] If the body contact region 111 is formed in the body region 11 on the side of the source region 14 away from the groove 12, then the contact hole 181 exposes the source region 14 and the body contact region 111 on the side of the second epitaxial layer 13 away from the groove 12, and the conductive structure 19 is electrically connected to the source region 14 and the body contact region 111.

[0131] The method of manufacturing the semiconductor device further includes forming a drain (not shown) on the side of the substrate 10 away from the groove 12.

[0132] In existing planar silicon carbide MOS devices, after applying voltage to the gate layer and the source region, the current path flows from the source region through the body region and the drift region to the drain. In this invention, after applying voltage to the gate layer 17 and the source region 14, as shown by the arrow in FIG13, the current path flows from the source region 14 through the second epitaxial layer 13 and the drift region (i.e., the first epitaxial layer 102) to the drain.

[0133] In existing planar silicon carbide MOS devices, the body diode formed by the body region and the drift region requires a relatively high turn-on voltage Vsd (i.e., the voltage of the source region relative to the drain) to conduct. However, in this invention, since a second epitaxial layer 13 extending from a portion of the body region 11 to the sidewall of the recess 12 is formed as a channel, when Vgs (i.e., the voltage of the gate layer 17 relative to the source region 14) is 0, a very small turn-on voltage Vsd (i.e., the voltage of the source region 14 relative to the drain) can open the forward current path, thereby avoiding the conduction of the body diode formed by the body region 11 and the drift region due to high Vsd. This is equivalent to eliminating the body diode in the module packaging, thereby saving overall production costs and reducing the device's freewheeling loss.

[0134] Furthermore, if the body diode formed by the body region 11 and the drift region is turned on, holes in the body region 11 (taking P-type doping as an example) will be injected into the drift region. Due to limitations of the epitaxial process, plane dislocation defects (BPDs) will exist in the drift region. Holes will recombine with electrons in the plane dislocation defects, thereby releasing energy. The energy released by the recombination of charge carriers by the plane dislocation defects will form stacking fault defects (SFs). The continuous conduction of the device will cause the stacking fault defects to continuously expand in the drift region. The presence of stacking fault defects will increase the on-resistance and leakage current of the device, and the higher the density of stacking fault defects, the greater the impact, i.e., a bipolar degradation effect occurs. Therefore, by avoiding the conduction of the body diode in this invention, the bipolar degradation effect can be improved, thereby improving the reliability of the device.

[0135] If the groove 12 is not formed between the two body regions 11, that is, if a portion of the substrate 10 between the two body regions 11 is not etched away, a depletion layer (located in the PN junction formed by the body regions 11 and the substrate 10) will be formed between the two body regions 11. To reduce the width of the depletion layer, the gate current needs to continuously charge Cgd (i.e., gate-drain capacitance) at a certain Vgs voltage. Therefore, there will be a plateau period during the device's turn-on process. In this invention, by forming the groove 12 between the two body regions 11, that is, by etching away most of the substrate 10 between the two body regions 11, most of the depletion layer between the two body regions 11 is removed. This reduces the portion of the gate current used to charge the depletion layer in Cgd, so that the gate current is mainly used to charge Cgs (i.e., gate-source capacitance). In other words, the plateau period is shortened, the device turn-on process is accelerated, and the device turn-on loss is reduced.

[0136] Furthermore, if the portions of the two gate layers 17 located above the bottom wall of the recess 12 are connected, a capacitor structure will be formed between the gate layer 17 above the bottom wall of the recess 12 and the drain. This capacitor structure is part of a Miller capacitance (i.e., gate-drain capacitance). Therefore, by forming a split gate in this invention, i.e., the portions of the two gate layers 17 located above the bottom wall of the recess 12 are not connected, the capacitance value of the Miller capacitance can be reduced. Since the capacitance value of the Miller capacitance is positively correlated with the turn-on loss, the turn-on loss of the device is further reduced.

[0137] Furthermore, by forming the groove 12 between the two body regions 11, most of the depletion layer between the two body regions 11 (i.e., the depletion layer in the PN junction formed by the body region 11 and the substrate 10) is removed, thereby eliminating part of the on-resistance of the JFET region between the two body regions 11. That is, the on-resistance of the JFET region between the two body regions 11 is reduced, thereby reducing the overall on-resistance of the device and improving the current capability of the device.

[0138] If the doping concentration of the second epitaxial layer 13 is greater than that of the substrate 10, the carrier mobility of the channel can be increased, thereby reducing the channel resistance. Furthermore, the on-resistance of the accumulation layer in the substrate 10 located directly below the gate layer 17 on the sidewall of the recess 12 can be reduced. This allows the current to flow not only from the second epitaxial layer 13 on the sidewall of the recess 12 towards the drain, but also to diffuse from the region where the accumulation layer is located towards the drain. In other words, the current flow path is widened, allowing the current to flow to the drain more quickly and improving device performance.

[0139] In summary, the present invention provides a method for manufacturing a semiconductor device, comprising: providing a substrate; forming two body regions in the substrate and forming a groove in the substrate between the two body regions; forming a second epitaxial layer on the substrate, the second epitaxial layer extending from a portion of the body regions to a sidewall of the groove; forming a source region in the body regions, the source region extending from a side of the second epitaxial layer away from the groove to below the second epitaxial layer, wherein the doping types of the substrate, the second epitaxial layer, and the source region are opposite to the doping types of the body regions; forming a gate oxide layer on the surface of the second epitaxial layer and the bottom wall of the groove; and forming a gate layer on the gate oxide layer, the gate layer extending from the gate oxide layer above the second epitaxial layer to the gate oxide layer on the sidewall of the groove. The semiconductor device manufacturing method provided by the present invention can improve device performance.

[0140] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: Base; Two body regions are formed in the substrate, and a groove is formed in the substrate between the two body regions; A second epitaxial layer is formed on the substrate, the second epitaxial layer extending from a portion of the body region to the sidewall of the groove; A source region is formed in the body region, extending from the side of the second epitaxial layer away from the groove to below the second epitaxial layer, wherein the doping type of the substrate, the second epitaxial layer, and the source region is opposite to the doping type of the body region; A gate oxide layer is formed on the surface of the second epitaxial layer and the bottom wall of the groove; A gate layer is formed on the gate oxide layer, the gate layer extending from the gate oxide layer above the second epitaxial layer to the gate oxide layer on the sidewall of the recess.

2. The semiconductor device as claimed in claim 1, characterized in that, The substrate includes a substrate from bottom to top and a first epitaxial layer, wherein the body region is formed in the first epitaxial layer.

3. The semiconductor device as described in claim 1, characterized in that, The substrate and the second epitaxial layer are made of silicon carbide.

4. The semiconductor device as claimed in claim 1, characterized in that, The bottom wall of the groove is higher than the bottom surface of the body region.

5. The semiconductor device as claimed in claim 1, characterized in that, The doping concentration of the second epitaxial layer is greater than the doping concentration of the substrate and less than the doping concentration of the source region.

6. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor device further includes: A doped region is formed in the substrate on the bottom wall of the groove, the gate oxide layer covers the doped region, the doping type of the doped region is the same as the doping type of the body region, and the doping concentration of the doped region is greater than or equal to the doping concentration of the body region.

7. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor device further includes: An insulating dielectric layer is formed on the substrate, the insulating dielectric layer fills the groove, and the insulating dielectric layer covers the gate oxide layer and the gate layer; A conductive structure is formed on the source region and the body region of the second epitaxial layer on the side away from the groove.

8. A method for manufacturing a semiconductor device, characterized in that, include: Provide a base; Two body regions are formed in the substrate, and a groove is formed in the substrate between the two body regions; A second epitaxial layer is formed on the substrate, the second epitaxial layer extending from a portion of the body region to the sidewall of the groove; A source region is formed in the body region, the source region extending from the side of the second epitaxial layer away from the groove to below the second epitaxial layer, and the doping types of the substrate, the second epitaxial layer, and the source region are opposite to the doping types of the body region; A gate oxide layer is formed on the surface of the second epitaxial layer and the bottom wall of the groove; A gate layer is formed on the gate oxide layer, the gate layer extending from the gate oxide layer above the second epitaxial layer to the gate oxide layer on the sidewall of the recess.

9. The method for manufacturing a semiconductor device as described in claim 8, characterized in that, The substrate includes a substrate from bottom to top and a first epitaxial layer, wherein the body region is formed in the first epitaxial layer.

10. The method for manufacturing a semiconductor device as described in claim 8, characterized in that, The substrate and the second epitaxial layer are made of silicon carbide.

11. The method for manufacturing a semiconductor device as described in claim 8, characterized in that, The bottom wall of the groove is higher than the bottom surface of the body region.

12. The method for manufacturing a semiconductor device as described in claim 8, characterized in that, The doping concentration of the second epitaxial layer is greater than the doping concentration of the substrate and less than the doping concentration of the source region.

13. The method for manufacturing a semiconductor device as described in claim 8, characterized in that, After forming the second epitaxial layer on the substrate and before forming the gate oxide layer on the surface of the second epitaxial layer and the bottom wall of the trench, the method of manufacturing the semiconductor device further includes: A doped region is formed in the substrate on the bottom wall of the groove. The doping type of the doped region is the same as that of the body region, and the doping concentration of the doped region is greater than or equal to that of the body region.

14. The method for manufacturing a semiconductor device as described in claim 8, characterized in that, The method for manufacturing the semiconductor device further includes: An insulating dielectric layer is formed on the substrate, the insulating dielectric layer fills the groove, and the insulating dielectric layer covers the source region and the body region of the second epitaxial layer on the side away from the groove; A contact hole is formed in the insulating dielectric layer, the contact hole exposing the source region and the body region of the second epitaxial layer on the side away from the groove; A conductive structure is formed in the contact hole.

Images