Semiconductor device and method for producing a semiconductor device

Abstract

A semiconductor device (1) is specified herein, comprising: - a light emitting semiconductor chip (2), and - a bond wire arrangement (3) comprising a plurality of bond wires (31,…,3n) for electrically contacting the light emitting semiconductor chip (2), wherein - a spatial electrical resistance distribution of the bond wire arrangement (3) is adjusted to tune an electric operating current density across the light emitting semiconductor chip (2) during operation. Further, a method for producing a semiconductor device is specified herein.

Description

[0001] 2024PF01016 January 2, 2026

[0002] P2024, 0963 WO N 1

[0003] Description

[0004] SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE

[0005] A semiconductor device and a method for producing a semiconductor device are disclosed herein.

[0006] At least one obj ect of certain embodiments is to provide a semiconductor device with a more uniform temperature distribution during operation. At least one further obj ect of certain embodiments is to provide a method for producing a semiconductor device with a more uniform temperature distribution during operation.

[0007] According to an aspect, the semiconductor device comprises a light emitting semiconductor chip . For example, the light emitting semiconductor chip is a laser diode chip or a light emitting diode chip . In particular, the light emitting semiconductor chip comprises or consists of a semiconductor layer stack with an active region for converting an electric operating current into electromagnetic radiation during operation. For example, the light emitting semiconductor chip is a high-power light emitting semiconductor chip with a maximum electric operating current density between 10 A / mm2and 50 A / mm2, inclusive, for laser diode chips, or a maximum electric operating current density of around 1 A / mm2for light emitting diode chips . Moreover, the light emitting semiconductor chip can further comprise metallic contacts and / or at least one metallic contact layer that is arranged on the semiconductor layer stack for electrically contacting the semiconductor layer stack.2024PF01016 January 2, 2026

[0008] P2024, 0963 WO N 2

[0009] Preferably, the semiconductor layer stack is epitaxially grown. For example, the semiconductor layer stack comprises an n-doped semiconductor region and a p-doped semiconductor region with the active region arranged in between. In particular, the active region comprises a single or multiple quantum well structure . For example, the active region comprises one or more quantum well layers that are separated by barrier layers . For example, a bandgap of each barrier layer is larger than a bandgap of each quantum well layer .

[0010] For example, the semiconductor layer stack comprises or consists of a III / V compound semiconductor material, such as an arsenide, a phosphide or a nitride compound semiconductor material . For example, the semiconductor layer stack comprises aluminum indium gallium arsenide, AlxInyGai-x-yAs with 0<x<l, 0<y<l and x+y<l . Further, the semiconductor material may include one or more dopants as well as additional components .

[0011] For example, the light emitting semiconductor chip emits electromagnetic radiation in a spectral range between infrared light and ultraviolet light during operation. In particular, the light emitting semiconductor chip emits electromagnetic laser radiation during operation.

[0012] Electromagnetic laser radiation is generated by stimulated emission. Compared to electromagnetic radiation that is generated by spontaneous emission, electromagnetic laser radiation has a longer coherence length, a smaller spectral linewidth and / or a higher degree of polarization, for example .

[0013] According to a further aspect, the semiconductor device comprises a bond wire arrangement comprising a plurality of2024PF01016 January 2, 2026

[0014] P2024, 0963 WO N 3

[0015] bond wires for electrically contacting the light emitting semiconductor chip . In particular, bond wires of the bond wire arrangement are directly bonded onto the light emitting semiconductor chip . For example, the bond wires of the bond wire arrangement are bonded onto a common contact layer of the light emitting semiconductor chip . For example, the light emitting semiconductor chip is a laser diode chip or a light emitting diode chip, and the bond wire arrangement is configured for electrically contacting an anode or a cathode of the light emitting semiconductor chip .

[0016] In particular, the bond wire arrangement is configured for providing the electric operating current to the light emitting semiconductor chip . For example, some or all of the plurality of bond wires of the bond wire arrangement are electrically connected in parallel . For example, the bond wire arrangement comprises at least 10, at least 20, or at least 50 bond wires . In particular, some or all of the bond wires comprise or consist of a metal, such as gold, silver, copper, or aluminum. The bond wires can also comprise or consist of a metallic alloy that can include one or more of the aforementioned metals .

[0017] According to a further aspect of the semiconductor device, a spatial electrical resistance distribution of the bond wire arrangement is adjusted to tune an electric operating current density across the light emitting semiconductor chip during operation. For example, the spatial electrical resistance distribution of the bond wire arrangement is adjusted such that an electric operating current density across the light emitting semiconductor chip is homogenized during operation and / or such that a temperature distribution across the light emitting semiconductor chip is homogenized during operation,2024PF01016 January 2, 2026

[0018] P2024, 0963 WO N 4

[0019] and / or such that a charge carrier density in the active layer of the light emitting semiconductor chip is tuned and / or optimized during operation.

[0020] For example, the spatial electrical resistance distribution of the bond wire arrangement is adjusted such the electric operating current density across the light emitting semiconductor chip is more homogeneous than in the case of a bond wire arrangement with a homogeneous electrical resistance distribution, i . e . a bond wire arrangement where all of the plurality of bond wires are identical and / or where the bond wires are uniformly distributed across the contact layer of the light emitting semiconductor chip .

[0021] For example, the spatial electrical resistance distribution of the bond wire arrangement is configured for at least partially compensating local variations in a series resistance of the light emitting semiconductor chip during operation. For example, a bond wire that is connected to a region of the light emitting semiconductor chip where its local series resistance is small during operation has a higher resistance than a bond wire that is connected to a region of the light emitting semiconductor chip where its local series resistance is high during operation. In particular, the series resistance refers to a resistance of the light emitting semiconductor chip for an electric current flowing in a direction perpendicular to a main extension plane of the semiconductor layers of the semiconductor layer stack. Further, local variations in the series resistance refer in particular to different series resistances in different regions of a cross-section of the light emitting semiconductor chip, wherein the cross-section is parallel to the main extension plane of the semiconductor layers . For2024PF01016 January 2, 2026

[0022] P2024, 0963 WO N 5

[0023] example, local variations in the series resistance of the light emitting semiconductor chip can arise due to a non-homogeneous temperature distribution across the light emitting semiconductor chip, in particular at or close to a maximum operating power of the light emitting semiconductor chip .

[0024] In particular, the spatial electrical resistance distribution of the bond wire arrangement is adjusted such that the electric operating current density across the main extension plane of semiconductor layers of the light emitting semiconductor chip is homogenized during operation. For example, the spatial arrangement of the plurality of bond wires, wherein at least some of the plurality of bond wires can have resistances that differ from each other, gives rise to the spatial electrical resistance distribution of the bond wire arrangement .

[0025] According to an embodiment, the semiconductor device comprises :

[0026] - the light emitting semiconductor chip, and

[0027] - the bond wire arrangement comprising the plurality of bond wires for electrically contacting the light emitting semiconductor chip, wherein

[0028] - the spatial electrical resistance distribution of the bond wire arrangement is adjusted to tune an electric operating current density across the light emitting semiconductor chip during operation.

[0029] The semiconductor device disclosed herein is based on the idea to reduce a non-uniform or non-homogeneous current inj ection into the light emitting semiconductor chip, in particular at or close to a maximum operating power of the2024PF01016 January 2, 2026

[0030] P2024, 0963 WO N 6

[0031] light emitting semiconductor chip . Such a non-uniform current inj ection can result from variations in the local series resistance of the light emitting semiconductor chip, for example due to a non-uniform heating of the light emitting semiconductor chip during operation, even though a series resistance of the light emitting semiconductor chip at ambient temperature and / or at low electric operating current may be uniform. Moreover, the semiconductor device disclosed herein is based on the further idea to reduce a non-uniform current inj ection into the light emitting semiconductor chip that can result from wire bonding the light emitting semiconductor chip using a plurality of bond wires with a wide range of different bond wire lengths .

[0032] For example, the contact layer of the light emitting semiconductor chip, onto which the bond wire arrangement is bonded, has a sheet resistivity that is too high for effectively spreading the electrical operating current and / or for effectively spreading heat that is generated during operation of the light emitting semiconductor chip . For example, a sufficiently large sheet resistivity of the contact layer is necessary such the spatial electrical resistance distribution of the bond wire arrangement can be used to tune the electric operating current density across the light emitting semiconductor chip . For example, the sheet resistivity of the contact layer is at least 30 mQ / D or at least 50 mQ / D. In particular, the sheet resistivity of the contact layer has to be sufficiently large in order not to counteract the tuning of the electric operating current density across the light emitting semiconductor chip by means of the bond wire arrangement . Alternatively or in addition, the contact layer comprises at least two segments that are physically separated from one another or that are connected2024PF01016 January 2, 2026

[0033] P2024, 0963 WO N - 7 -

[0034] by a part of the contact layer that has a higher sheet resistivity than the at least two segments .

[0035] Moreover, the resistance of the bond wires can be significant in relation to a total series resistance of the semiconductor device and thus can be used for adjusting the local electric operating current density flowing through the light emitting semiconductor chip . Advantageously, adding additional electrical resistance by means of the bond wire arrangement and thus outside of the light emitting semiconductor chip can to a large degree avoid generating more heat inside the light emitting semiconductor chip during operation and thus can prevent a thermal roll-over of the light emitting semiconductor chip at a lower maximum electrical operating current .

[0036] For example, long cavity and high-power semiconductor laser chips can suffer from current crowding and local over-heating during operation. This can have several reasons, such as non-uniform optical absorption losses due to an asymmetric laser cavity that can lead to a higher photon density at an outcoupling facet of the semiconductor laser chip . Moreover, the outcoupling facet can be located at a very edge of a submount that is used for dissipating heat generated during operation. This can lead to a non-uniform in-plane heat spreading via the submount and thus can cause a higher temperature of the light emitting semiconductor chip at the outcoupling facet . Lastly, a positive feedback in the form of a higher electrical operating current due to a lower quantum well bandgap in regions where the temperature is already higher can amplify a local heating effect .2024PF01016 January 2, 2026

[0037] P2024, 0963 WO N - 8 -

[0038] For example, the light emitting semiconductor chip is not capable of spreading the electric operating current across its own cross-section, as a sheet resistivity of the semiconductor layer stack and of metallic contact layers is too high. For example, the spreading of the electric operating current relies on a side of the light emitting semiconductor chip that can be soldered onto a thick metallic layer on the submount . On an opposite side of the light emitting semiconductor chip, onto which the bond wires are bonded, for example, a positioning of the bond wires can be important for effectively spreading the electrical operating current . Homogenizing the electrical operating current density through the light emitting semiconductor chip by means of adjusting the spatial electrical resistance distribution of the bond wire arrangement advantageously allows to reduce the effects of current crowding and local over-heating of the light emitting semiconductor chip during operation .

[0039] Further, large semiconductor laser chips with multiple laser cavities emitting in parallel can require a much larger number of bond wires for electrically contacting the different laser cavities . Due to the geometry of the semiconductor laser chip, these bond wires can also extend parallel rather than transverse to the laser cavity and thus can be significantly longer than bond wires that only extend transversally to the laser cavity. In particular, long bond wires can add large local resistances to regions of the light emitting semiconductor chip . For example, bond wires that are bonded in the vicinity of the outcoupling facet of the light emitting semiconductor chip can be much longer, for example at least two times longer or at least five times longer, than bond wires that are bonded onto an opposite side of the light2024PF01016 January 2, 2026

[0040] P2024, 0963 WO N - 9 -

[0041] emitting semiconductor chip, i . e . on a side in the vicinity of a high-reflectivity mirror of the laser cavity, where the temperature can be lower . This can lead to a non-uniform electrical operating current inj ection across a length of the laser waveguide, for example, as the sheet resistance of the light emitting semiconductor chip can be too high for substantially spreading the electric operating current that is inj ected via the bond wires . Homogenizing the electrical operating current density through the light emitting semiconductor chip by means of adjusting the spatial electrical resistance distribution of the bond wire arrangement advantageously allows to reduce the effects of current crowding and local over-heating of the light emitting semiconductor chip during operation.

[0042] For example, the bond wire arrangement disclosed herein is configured for at least partially compensating at least some of the local variations in the series resistance of the light emitting semiconductor chip that can appear during operation. Consequently, the electrical operating current density can be advantageously homogenized across the cross-section of the light emitting semiconductor chip .

[0043] For example, the electric operating current density is adjusted such that an electric carrier distribution in the light emitting semiconductor chip matches or approximately matches a photon distribution in the light emitting semiconductor chip during operation. Advantageously, this increases an efficiency of the semiconductor device, for example .

[0044] According to a further aspect of the semiconductor device, the light emitting semiconductor chip is an edge emitting2024PF01016 January 2, 2026

[0045] P2024, 0963 WO N - 10 -

[0046] laser diode chip . In particular, an emission direction of electromagnetic laser radiation generated during operation is parallel to the main extension plane of semiconductor layers of the edge emitting laser diode chip . For example, facets on opposite side faces of the edge emitting semiconductor chip form the laser cavity.

[0047] According to a further aspect of the semiconductor device, electrical resistances of the bond wire arrangement increase along a light emission direction of the light emitting semiconductor chip . For example, bond wires that are bonded to the light emitting semiconductor chip closer to a light outcoupling facet of the light emitting semiconductor chip have a larger resistance than bond wires that are bonded to the light emitting semiconductor chip farther away from the light outcoupling facet . For example, the electrical resistances of the bond wire arrangement gradually increase or increase stepwise along the emission direction. For example, two or more different types of bond wires are used in the bond wire arrangement, wherein each type of bond wire has a different electrical resistance . For example, the electrical resistances of the bond wire arrangement increase along the light emission direction by at least 5 % or by at least 10 % or by at least 20 % . For example, the electrical resistances of the bond wire arrangement increase along the light emission direction by at most 30 % or by at most 100 % or by at most 200 % .

[0048] According to a further aspect of the semiconductor device, the bond wire arrangement comprises at least ten bond wires, or at least 20 bond wires, or at least 50 bond wires, that are directly connected to a contact layer of the light emitting semiconductor chip . In particular, the plurality of2024PF01016 January 2, 2026

[0049] P2024, 0963 WO N - 11 -

[0050] bond wires of the bond wire arrangement are bonded onto the same contact layer or onto different segments of the same contact layer of the light emitting semiconductor chip . For example, the electrical sheet resistivity of the contact layer and / or of semiconductor layers of the light emitting semiconductor chip is too high to spread the electrical operating current across the main extension plane of the semiconductor layers, and / or the contact layer comprises two or more segments that are physically separated from one another .

[0051] According to a further aspect of the semiconductor device, the contact layer comprises at least two, at least three, or a plurality of segments that are physically separated from one another and / or that are arranged adj acent to one another . For example, the bond wire arrangement comprises at least two groups of bond wires, at least three groups of bond wires, or a plurality of groups of bond wires . Each group of bond wires can comprise one, two, or more bond wires . The number of bond wires per group can differ between groups . For example, each group of bond wires is bonded onto a corresponding segment of the contact layer . For example, the segments are arranged in a direction parallel and / or perpendicular to the light emission direction of the light emitting semiconductor chip, in a main extension plane of the contact layer .

[0052] For example, the contact layer comprising two or more segments can prevent or reduce a spreading of the electrical operating current across the light emitting semiconductor chip . Consequently, the contact layer comprising two or more segments allows to efficiently tune the electric operating current density across the light emitting semiconductor chip2024PF01016 January 2, 2026

[0053] P2024, 0963 WO N - 12 -

[0054] by means of the spatial electrical resistance distribution of the bond wire arrangement .

[0055] According to a further aspect of the semiconductor device, at least one bond wire extends longitudinally or transversally to a light emission direction of the light emitting semiconductor chip . For example, a main extension direction of at least one, a majority, or all of the plurality of bond wires is parallel or transverse to the light emission direction. It is also possible that at least some bond wires extend longitudinally and transversally to the light emission direction .

[0056] According to a further aspect of the semiconductor device, the spatial electrical resistance distribution of the bond wire arrangement is adjusted by using bond wires with different electrical resistances and / or by changing a local density of wire bonds across a contact layer of the light emitting semiconductor chip . For example, the electrical resistance of the bond wire arrangement is locally increased if fewer bond wires are bonded to the contact layer per unit area of the contact layer, or vice versa . For example, the electrical resistance of the bond wire arrangement is locally increased if bond wires with a higher electrical resistance are locally bonded to the contact layer, or vice versa .

[0057] According to a further aspect of the semiconductor device, the spatial electrical resistance distribution of the bond wire arrangement is adjusted by using bond wires with different lengths, different diameters, and / or different material compositions . For example, the diameter of the bond wires in the bond wire arrangement varies between 10 pm and 100 pm, inclusive . Here, the diameter refers in particular to2024PF01016 January 2, 2026

[0058] P2024, 0963 WO N - 13 -

[0059] a maximal linear extension of a cross-section of one bond wire, i . e . a maximal linear extension perpendicular to the length of the bond wire .

[0060] For example, the bond wire arrangement comprises at least two, three or more groups of bond wires . For example, bond wires in the same group have the same properties, e . g. the same length, the same diameter, and / or the same material composition. For example, the properties of the bond wires differ between different groups . In particular, bond wires in different groups can have different lengths, diameters, and / or material compositions .

[0061] For example, the groups of bond wires are connected to different segments of the contact layer . For example, a first group of bond wires is connected to a first segment of the contact layer, whereas a second group of bond wires is connected to a second segment of the contact layer . In particular, different segments of the contact layer are not in direct physical contact with each other . In particular, the bond wires in the first group have different properties than the bond wires in the second group, e . g. different lengths, diameters and / or material compositions .

[0062] According to a further aspect of the semiconductor device, the electrical resistance of a bond wire that is electrically connected to a region adj acent to a light outcoupling surface of the light emitting semiconductor chip is larger than the electrical resistance of a bond wire that is electrically connected to a region opposite to or farther away from the light outcoupling surface of the light emitting semiconductor chip .2024PF01016 January 2, 2026

[0063] P2024, 0963 WO N - 14 -

[0064] According to a further aspect of the semiconductor device, the electrical resistances of the bond wires of the bond wire arrangement are adjusted in a range between 25 % and 400 %, inclusive, or in a range between 50 % and 200 %, inclusive, or in a range between 70 % and 130 %, inclusive, of a mean electrical resistance of the plurality of bond wires .

[0065] According to a further aspect, the semiconductor device further comprises a submount . For example, the submount comprises or consists of a semiconductor material, such as AIN. For example, the submount is configured for electrically contacting the light emitting semiconductor chip and / or as a heat sink for the light emitting semiconductor chip . The submount can also comprise a metallic contact layer for electrically contacting the light emitting semiconductor chip . For example, the metallic contact layer comprises copper and / or has a thickness of at least 50 pm.

[0066] According to a further aspect of the semiconductor device, the light emitting semiconductor chip is arranged on and in electrical contact with an electric contact surface of the submount . In particular, the electric contact surface is provided by the metallic contact layer of the submount . For example, the light emitting semiconductor chip is soldered onto the metallic contact layer of the submount .

[0067] According to a further aspect of the semiconductor device, the bond wire arrangement is configured for electrically contacting a side of the light emitting semiconductor chip facing away from the submount . In particular, the plurality of bond wires of the bond wire arrangement are bonded onto the contact layer of the light emitting semiconductor chip that faces away from the submount .2024PF01016 January 2, 2026

[0068] P2024, 0963 WO N - 15 -

[0069] According to a further aspect of the semiconductor device, at least some of the plurality of bond wires are electrically connected in series to corresponding resistors . For example, a part of the bond wires or each bond wire of the bond wire arrangement has a corresponding resistor that is electrically connected to the respective bond wire in series . For example, some of the bond wires that are bonded onto one region of the light emitting semiconductor chip are electrically connected in series to corresponding resistors, while other bond wires that are bonded onto a different region of the light emitting semiconductor chip are not electrically connected to resistors . For example, the resistors are configured for adjusting the spatial electrical resistance distribution of the bond wire arrangement . For example, bond wires that are bonded to different regions of the light emitting semiconductor chip are electrically connected in series to resistors with different electrical resistances .

[0070] According to a further aspect of the semiconductor device, the resistors are micro-patterned on a submount of the semiconductor device . For example, the resistors are micropatterned on the same submount, onto which the light emitting semiconductor chip is mounted. For example, the micropatterned resistors comprise a metallic layer that is micropatterned into metallic strips, such that each resistor comprises or consists of one metallic strip . For example, the metallic layer is disposed on an insulating layer that is in turn disposed on the submount . For example, a resistance of the micro patterned resistor can be adjusted by adjusting a width and / or a length of the metallic strip .2024PF01016 January 2, 2026

[0071] P2024, 0963 WO N 16

[0072] According to a further aspect of the semiconductor device, the spatial electrical resistance distribution of the bond wire arrangement is adjusted by using resistors with different resistances for bond wires that are connected to different regions of the light emitting semiconductor chip .

[0073] According to a further aspect of the semiconductor device, the light emitting semiconductor chip comprises a plurality of spatially separated light emission regions . For example, the light emitting semiconductor chip is a micro-laser array chip or a laser bar chip . For example, the light emitting semiconductor chip comprises a plurality of ridge waveguides and / or a plurality of trenches that at least partially extend through the semiconductor layer stack, such that a plurality of parallel laser cavities are formed. For example, each light emission region is individually electrically addressable and / or individually controllable .

[0074] Further a method of producing a semiconductor device is specified herein. In particular, the method can be used for producing a semiconductor device as disclosed herein. All features of the semiconductor device are also disclosed for the method of producing a semiconductor device, and vice versa .

[0075] According to an embodiment, the method of producing a semiconductor device comprises the steps of :

[0076] - providing a light emitting semiconductor chip, and

[0077] - electrically contacting the light emitting semiconductor chip using a bond wire arrangement comprising a plurality of bond wires, wherein

[0078] - a spatial electrical resistance distribution of the bond wire arrangement is designed to tune an electric operating2024PF01016 January 2, 2026

[0079] P2024, 0963 WO N 17

[0080] current density across the light emitting semiconductor chip during operation. For example, the electric operating current density across the light emitting semiconductor chip is homogenized during operation at or near a maximum operating power of the light emitting semiconductor chip .

[0081] According to a further aspect of the method, the spatial electrical resistance distribution of the bond wire arrangement is designed such that a temperature distribution across the light emitting semiconductor chip is uniform during operation at a maximum operating power of the light emitting semiconductor chip .

[0082] Further advantageous embodiments and further developments of the semiconductor device and of the method for producing a semiconductor device will become apparent from the following exemplary embodiments described in connection with the Figures .

[0083] Figures 1A and IB show a schematic cross-section and a schematic plan view of a semiconductor device according to an example .

[0084] Figures 2A and 2B show a schematic cross-section and a schematic plan view of a semiconductor device according to a further example .

[0085] Figures 3, 4 and 5 show schematic plan views of semiconductor devices according to different exemplary embodiments .

[0086] Figure 6 shows a schematic cross-section of a semiconductor device according to an exemplary embodiment .2024PF01016 January 2, 2026

[0087] P2024, 0963 WO N 18

[0088] Figures 7A and 7B show a schematic plan view and a schematic cross-section of a part of a semiconductor device according to an exemplary embodiment .

[0089] Figures 8A and 8B show a schematic plan view and a schematic cross-section of a part of a semiconductor device according to a further exemplary embodiment .

[0090] Figures 9A and 9B show a schematic plan view and a schematic cross-section of a part of a semiconductor device according to a further exemplary embodiment .

[0091] Figure 10 shows a schematic cross-section of a semiconductor device according to a further exemplary embodiment .

[0092] Elements that are identical, similar, or have the same effect, are denoted by the same reference signs in the Figures . The Figures and the proportions of the elements shown in the Figures are not to be regarded as true to scale . Rather, individual elements, in particular layer thicknesses, may be shown exaggeratedly large for better representability and / or better understanding.

[0093] The semiconductor device 1 according to the example in Figures 1A and IB comprises a light emitting semiconductor chip 2 and a bond wire arrangement 3 comprising a plurality of bond wires 31, ..., 3n for electrically contacting the light emitting semiconductor chip 2 . Figure 1A shows a schematic cross-section perpendicular to a light emission direction E of the light emitting semiconductor chip, whereas Figure IB shows a plan view onto a main surface of the carrier 9 of the semiconductor device 1 .2024PF01016 January 2, 2026

[0094] P2024, 0963 WO N - 19 -

[0095] The light emitting semiconductor chip 2 is an edge emitting laser diode chip that emits laser light in a spectral range between infrared and ultraviolet light during operation. In particular, facets on opposite sides of the light emitting semiconductor chip 2 act as partially reflective mirrors for the laser light generated during operation and form a laser cavity of the edge emitting laser diode chip . The light emitting semiconductor chip 2 has a light emission direction E that is perpendicular to the drawing plane of the crosssection shown in Figure 1A. In particular, the light emitting semiconductor chip 2 is a high-power edge emitting laser diode chip . For example, a maximal electric operating current of the light emitting semiconductor chip is at least 50 Ampere and a length of the laser cavity is at least 4 mm, for example .

[0096] The light emitting semiconductor chip 2 is mounted on a submount 4 that is in turn arranged on a carrier 9. The submount 4 comprises a metallic contact layer 42 for electrically contacting the light emitting semiconductor chip 2. The metallic contact layer 42 comprises a copper layer with a thickness of at least 50 pm. For example, the metallic contact layer 42 further comprises one or more diffusion barrier layers comprising a diffusion barrier metal, such as Ni, Cr, Ti, and / or Pt . For example, the metallic contact layer 42 is further plated with Au to enhance a soldering ability of the metallic contact layer 42. The light emitting semiconductor chip 2 is soldered onto an electric contact surface 41 of the submount 4 that corresponds to a surface of the metallic contact layer 42 facing the light emitting semiconductor chip 2. The submount 4 comprises a semiconductor material, such as AIN, and is configured for dissipating heat H that is generated by the light emitting2024PF01016 January 2, 2026

[0097] P2024, 0963 WO N 20

[0098] semiconductor chip during operation. In particular, the generated heat H is mainly transported from the light emitting semiconductor chip 2 via the submount 4 to the carrier 9, as indicated by the arrow in Figure 1A. The carrier 9 is configured as a heat sink or as a heat spreader . For example, the carrier 9 comprises or consists of a metal, such as copper .

[0099] The bond wire arrangement 3 comprises at least 10 bond wires 31, ..., 3n, for example 50 bond wires, that are configured for electrically contacting a side of the light emitting semiconductor chip 2 facing away from the submount 4 . A main extension direction of the bond wires 31, ..., 3n is transverse or perpendicular to the light emission direction E, as shown in Figure IB . It is also possible that at least some of the bond wires 31, ..., 3n extend in different directions, such as parallel or at an angle to the light emission direction E, when viewed in plan view of the main surface of the carrier 9.

[0100] The bond wires 31, ..., 3n are directly bonded to a contact layer 21 of the light emitting semiconductor chip 2. For example, the contact layer 21 is a thin layer comprising or consisting of a metal, such as gold. In particular, a sheet resistivity of the contact layer 21 is too high for effectively spreading the electric operating current across the light emitting semiconductor chip 2 during operation. For example, the sheet resistivity of the contact layer 21 is low enough for spreading the electric operating current in the immediate vicinity of a wire bond, but high enough to avoid effectively spreading the electric operating current between adj acent wire bonds .2024PF01016 January 2, 2026

[0101] P2024, 0963 WO N - 21 -

[0102] In addition, the semiconductor device 1 comprises further submounts 8 that are electrically connected via further bond wires 7 to the metallic contact layer 42 of the submount 4, as well as to a further metallic contact layer 43 that is arranged on the submount 4 and electrically isolated from the metallic contact layer 42. The further metallic contact layer 43 is in electrical contact with the bond wire arrangement 3. The further submounts 8 are configured for routing the electric operating current from connection terminals (not shown) of the semiconductor device 1 to the metallic contact layer 42 and to the bond wire arrangement 3, respectively. Alternatively or in addition, the semiconductor device 1 can also comprise vias that extend through the submount 4 for electrically connecting the metallic contact layer 42 and / or the bond wire arrangement 3 to connection terminals of the semiconductor device 1, for example .

[0103] The light emitting semiconductor chip 2 of the semiconductor device 1 according to Figures 1A and IB can suffer from current crowding due to local temperature variations that in turn lead to local variations of a series resistance of the light emitting semiconductor chip 2, in particular when operated close to or at a maximum operating power .

[0104] Figures 2A and 2B show a further example of a semiconductor device 1. In contrast to Figures 1A and IB, the light emitting semiconductor chip 2 is an edge emitting laser bar or a laser array with a plurality of individually controllable light emission regions 61, ..., 6n, i . e . a plurality of laser cavities (not shown) that are arranged parallel to each other . The bond wire arrangement 3 comprises a plurality of bond wires 31, ..., 3n that have a main extension direction parallel to the light emission direction E and are configured2024PF01016 January 2, 2026

[0105] P2024, 0963 WO N 22

[0106] for electrically contacting the plurality of light emission regions 61, ..., 6n of the light emitting semiconductor chip 2. In particular, each of the light emission regions 61, ..., 6n is electrically contacted by a part of the plurality of bond wires 31 , ..., 3n .

[0107] The bond wires 31, ..., 3n have vastly different lengths for contacting different regions of the light emitting semiconductor chip 2 along the light emission direction E . For example, the longest bond wire 31 is at least 5 times longer or at least 10 times longer than the shortest bond wire 3n. Accordingly, if the bond wires 31, ..., 3n have the same cross-sectional area and a formed of the same material, the longest bond 31 wire has an electrical resistance that is at least 5 times larger or at least 10 times larger than the electrical resistance of the shortest bond wire 3n.

[0108] The light emitting semiconductor chip 2 is soldered onto a metallic contact layer 42 of a submount 4. The bond wires 31, ..., 3n of the bond wire arrangement 3 extend from a contact layer 21 (not shown) of the light emitting semiconductor chip 2 that faces away from the submount 4 to a further submount 8. Electrical connections between the metallic contact layers 42 and connection terminals of the semiconductor device 1 are not shown in Figures 2A and 2B .

[0109] The light emitting semiconductor chip 2 of the semiconductor device 1 according to Figures 2A and 2B can suffer from a non-uniform current inj ection and thus from a non-uniform heating during operation. In particular, longer bond wires 31 can contribute significantly more to a series resistance of the semiconductor device 1 than shorter bond wires 3n. In the example of Figure 2A, longer bond wires 31 add a large local2024PF01016 January 2, 2026

[0110] P2024, 0963 WO N - 23 -

[0111] resistance to a part of the light emitting semiconductor chip 2 in the vicinity of its light outcoupling surface 22. This can lead to a non-uniform current inj ection across the length L of the light emitting semiconductor chip 2, because the sheet resistance of the light emitting semiconductor chip 2 is too high to substantially spread the electric operating current from the bond wires 31, ..., 3n.

[0112] For example, a light emitting semiconductor chip 2 as shown in Figures 2A and 2B comprising a laser cavity with a length L of 4 mm might require bond wires 31, ..., 3n for electrically contacting the chip, where the longest bond wire 31 is around 8 mm long, while the shortest bond wire 3n is around 1 mm long. In the case of a wire diameter of 50 pm, the longest bond wire 31 may have a resistance that is around 77 m / 2 larger than that of the shortest bond wire 3n, for example . If the shortest bond wire 3n would account for 4 % of the total series resistance of the semiconductor device 1, the longest bond wire 31 would account for 30 % of the series resistance, for example, which can have a strong effect on the electrical operating current distribution and thus on the temperature distribution in the light emitting semiconductor chip 2 during operation.

[0113] Compared to the semiconductor device 1 described in connection with Figures 1A and IB, the exemplary embodiments of the semiconductor devices 1 shown in Figures 3, 4 and 5 comprise a bond wire arrangement 3 with a spatial electrical resistance distribution that is configured to homogenize an electric operating current density across the light emitting semiconductor chip 2 during operation. Specifically, the semiconductor devices 1 shown in Figures 3, 4 and 5 allow for a more homogeneous and / or a more uniform electrical current2024PF01016 January 2, 2026

[0114] P2024, 0963 WO N - 24 -

[0115] inj ection into the light emitting semiconductor chip 2 compared to the semiconductor device 1 described in connection with Figures 1A and IB, for example at or close to a maximum operating power of the light emitting semiconductor chip 2. In particular, the resistance of the bond wire arrangement 3 increases along the emission direction E of the light emitting semiconductor chip 2. This non-uniform spatial electrical resistance distribution of the bond wire arrangement 3 compensates for local variations of the series resistance of the light emitting semiconductor chip 2 during operation. Accordingly, the bond wire arrangement 3 according to Figures 3, 4 and 5 advantageously leads to a more uniform temperature distribution across the light emitting semiconductor chip 2 during operation compared to the bond wire arrangement 3 described in connection with Figures 1A and IB .

[0116] The bond wire arrangement 3 shown in the plan view of Figure 3 comprises two types of bond wires 31, ..., 3n with different lengths . The longer bond wires 31 are used for electrically connecting a part of the light emitting semiconductor chip 2 in the vicinity of the light outcoupling surface 22, while the shorter bond wires 3n are used for connecting a part of the light emitting semiconductor chip 2 farther away from the light outcoupling surface 22. For example, one half of the bond wires 31, ..., 3n is longer, while the other half of the bond wires 31, ..., 3n is shorter . The longer bond wires 31 and the shorter bond wires 3n comprise the same material and have the same cross-section and diameter, for example within a tolerance of less than 5 % . The longer bond wires 31 are between 5 % and 100 % longer than the shorter bond wires 3n, therefore the resistance of the longer bond wires 31 is also between 5 % and 100 % larger than the resistance of the2024PF01016 January 2, 2026

[0117] P2024, 0963 WO N 25

[0118] shorter bond wires 3n, for example . Accordingly, the spatial electrical resistance distribution of the bond wire arrangement 3 is adjusted such that a local resistance of the bond wire arrangement 3 increases along the light emission direction E .

[0119] In the semiconductor device 1 according to the exemplary embodiment shown in Figure 4 the bond wire arrangement 3 comprises two types of bond wires 31, ..., 3n with different diameters and / or different thicknesses . The thinner bond wires 31 are used for electrically connecting a part of the light emitting semiconductor chip 2 in the vicinity of the light outcoupling surface 22, while the thicker bond wires 3n are used for connecting a part of the light emitting semiconductor chip 2 farther away from the light outcoupling surface 22. For example, one half of the bond wires 31, ..., 3n is thinner, while the other half of the bond wires 31, ..., 3n is thicker . The thinner bond wires 31 and the thicker bond wires 3n comprise the same material and have the same length, within a tolerance of less than 5 %, for example . The thinner bond wires 31 have a cross-sectional area that is between 5 % and 200 % smaller than the cross-sectional area of the thicker bond wires 3n, therefore the resistance of the thinner bond wires 31 is also between 5 % and 200 % larger than the resistance of the thicker bond wires 3n, for example . Accordingly, the spatial electrical resistance distribution of the bond wire arrangement 3 is adjusted such that a local resistance of the bond wire 3 arrangement increases along the light emission direction E .

[0120] In the semiconductor device 1 according to the exemplary embodiment shown in Figure 5 the bond wire arrangement 3 comprises two types of bond wires 31, ..., 3n with different2024PF01016 January 2, 2026

[0121] P2024, 0963 WO N - 26 -

[0122] material compositions that have different electrical resistivities . The bond wires 31 with the higher resistivity (indicated by the hatched lines in Figure 5) are used for electrically connecting a part of the light emitting semiconductor chip 2 in the vicinity of the light outcoupling surface 22, while the bond wires 3n with the lower resistivity (indicated by the solid lines in Figure 5) are used for connecting a part of the light emitting semiconductor chip 2 farther away from the light outcoupling surface 22. For example, one half of the bond wires 31, ..., 3n has the higher resistivity, while the other half of the bond wires 31, ..., 3n has the lower resistivity. All bond wires 31, ..., 3n of the bond wire arrangement 3 have the same geometrical dimensions, within a tolerance of less than 5 %, for example . The resistances of the two different types of bond wires 31, ..., 3n differ in a range between 5 % and 400 %, for example . For example, the resistivities of the two different types of bond wires 31, ..., 3n differ in a range between 5 % and 400 % . Accordingly, the spatial electrical resistance distribution of the bond wire arrangement 3 is adjusted such that a local resistance of the bond wire arrangement 3 increases along the light emission direction E .

[0123] In the semiconductor devices 1 according to the exemplary embodiments of Figures 3, 4 and 5, the local resistance of the bond wire arrangement 3 increases stepwise along the light emission direction E with a single step in the spatial electrical resistance distribution. In the semiconductor device 1 according to Figure 3, the step occurs at the transition from the shorter bond wires 3n to the longer bond wires 31. In the semiconductor device 1 according to Figure 4, the step occurs at the transition from the thicker bond 3n wires to the thinner bond wires 31. In the semiconductor2024PF01016 January 2, 2026

[0124] P2024, 0963 WO N - 27 -

[0125] device according to Figure 5, the step occurs at the transition where the material composition of the bond wires 31, ..., 3n changes . It is also possible that the local resistance of the bond wire arrangement 3 increases in one, two, or more steps, or continuously along the light emission direction E, for example . In particular, the lengths, thicknesses and / or material compositions of the bond wires 31, ..., 3n can increase or decrease in one, two, or more steps, or continuously along the light emission direction E .

[0126] Figure 6 shows a schematic cross-section of the semiconductor device 1 according to the exemplary embodiments described in connection with Figures 3, 4 and 5. In particular, the additional heat generated by the Ohmic losses of the additional resistances of the longer bond wires 31, the thinner bond wires 31 and / or the bond wires 31 with higher resistivity that are connected closer to the light outcoupling surface 22 of the light emitting semiconductor chip 2 substantially flows via the bond wires 31 to the submount 4, as indicated by the small arrow in Figure 6. For example, more than half of the additional heat generated in the bond wires 31 flows to the submount 4. The additional heat H generated in the bond wire arrangement 3 flows substantially to the submount 4, because the submount 4 is usually colder than the light emitting semiconductor chip 2 during operation. Accordingly, the additional resistances of the bond wire arrangement 3 do not lead to a substantial increase of the temperature of the light emitting semiconductor chip 2 during operation.

[0127] Even though the additional resistances of the longer bond wires 31, the thinner bond wires 31 and / or the bond wires 31 with higher resistivity can reduce an efficiency of the2024PF01016 January 2, 2026

[0128] P2024, 0963 WO N - 28 -

[0129] semiconductor device 1 compared to a semiconductor device 1 without these additional resistances, the more uniform current inj ection caused by the spatial electrical resistance distribution of the bond wire arrangement 3 can advantageously increase a brightness of the light emitted by the light emitting semiconductor chip 2 during operation. For example, the brightness is increased due to a more uniform gain along the length of the laser cavity due to the more uniform current inj ection. Moreover, the more uniform current inj ection can advantageously reduce electrical leakage currents through the light emitting semiconductor chip 2 that do not contribute to generating electromagnetic radiation in the active region. Further, the more uniform current inj ection can thereby also avoid a thermal roll-over through local overheating of the light emitting semiconductor chip, as leakage currents can be highly temperature dependent .

[0130] The bond wire arrangements 3 of the semiconductor devices 1 according to the different exemplary embodiments shown in Figures 7A, 7B, 8A, 8B, 9A and 9B comprise a plurality of resistors 5. Figures 7A, 8A and 9A show plan views of an enlarged region of the submount 4 where the further metallic contact layer 43 is arranged, while Figures 7B, 8B and 9B show schematic cross-sections of said regions . At least some of the plurality of bond wires 31, ..., 3n of the bond wire arrangement 3 are electrically connected in series to one of these resistors 5, respectively. The resistors 5 are configured to adjust the spatial electrical resistance distribution of the bond wire arrangement 3. For example, all bond wires 31, ..., 3n of the bond wire arrangement 3 are identical or almost identical within tolerances of less than 5 %, for example . Instead of using longer bond wires 31, thinner bond wires 31, or bond wires with a higher2024PF01016 January 2, 2026

[0131] P2024, 0963 WO N 29

[0132] resistivity 31 in order to adjust the spatial electrical resistance distribution, as described in connection with Figures 3, 4 and 5, at least some of the bond wires 31, ..., 3n of the bond wire arrangements 3 shown in Figures 7A to 9B are electrically connected in series to a corresponding resistor 5. The resistors 5 are micro-patterned on the submount 4.

[0133] The resistors 5 shown in Figures 7A and 7B are formed as pad-to-pad resistors 5, where bond wires 31, ..., 3n are bonded to both respective ends of a metallic strip that forms the resistor 5. In particular, an insulating layer 44 and a conductive layer 45 are disposed in this order on top of the further metallic contact 43 layer of the submount 4. The conductive layer 45 comprises or consists of a metal, such as gold. The conductive layer 45 is micro-patterned into a plurality of strips that are electrically isolated from each other . For example, the conductive layer 45 is micropatterned using a lithographic process . Each metallic strip forms a resistor 5. Resistances of the micro-patterned resistors 5 can be individually adjusted by changing a length L and / or a width W of the respective metallic strip . The bond wires 31, ..., 3n are bonded onto contact locations at the two respective ends of the metallic strip, indicated by the open circles in Figure 7A.

[0134] In contrast to the resistors 5 described in connection with Figures 7A and 7B, the resistors 5 of the semiconductor device 1 according to the exemplary embodiment shown Figures 8A and 8B are bond-to-equipotential resistors 5. In this case, one end of the metallic strip is in direct contact with the further metallic contact layer 43 of the submount 4, while the other end of the metallic strip is connected to a bond wire 31 of the bond wire arrangement 3. Again, the2024PF01016 January 2, 2026

[0135] P2024, 0963 WO N 30

[0136] resistance of each resistor 5 can be adjusted by changing a length L and / or a width W of the respective metallic strip .

[0137] In contrast to the resistors 5 described in connection with Figures 7A and 7B, the resistors 5 of the semiconductor device according to the exemplary embodiment shown Figures 9A and 9B are formed by directly micro-patterning the further metallic contact layer 43 of the submount 4.

[0138] Compared to the semiconductor device 1 described in connection with Figures 2A and 2B, the exemplary embodiment of the semiconductor device 1 shown in Figure 10 comprises a bond wire arrangement 3 with a spatial electrical resistance distribution that is configured to homogenize an electric operating current density across the light emitting semiconductor chip 2 during operation. Specifically, the semiconductor device 1 shown in Figures 10 allows for a more homogeneous and / or a more uniform electrical current inj ection into the light emitting semiconductor chip 2 compared to the semiconductor device 1 described in connection with Figures 2A and 2B, for example at or close to a maximum operating power of the light emitting semiconductor chip 2 .

[0139] In particular, the geometric arrangement of the bond wires 31, ..., 3n in Figure 10 corresponds to the geometric arrangement described in connection with Figures 2A and 2B . However, in the exemplary embodiment of Figure 10 the longer bond wires 31 are thicker or have a larger diameter D, i . e . they have a larger cross-sectional area, than the shorter bond wires 3n. By increasing the thickness of the bond wires 31, ..., 3n, their resistance is decreased, and vice versa . Accordingly, the thicknesses of the bond wires 31, ..., 3n can be adjusted such2024PF01016 January 2, 2026

[0140] P2024, 0963 WO N 31

[0141] that all bond wires have the same or almost the same resistance, irrespective of their length. For example, the resistances of the bond wires 31, ..., 3n of the bond wire arrangement 3 vary in a range between 70 % and 130 %, inclusive, of a mean electrical resistance of all bond wires 31, ..., 3n. In addition, the bond wires 31, ..., 3n can be adjusted such that their resistances increase along the light emission direction E by at least 5 % and / or by at most 100 % or by at most 200 %, in order to compensate for local variations in the series resistance of the light emitting semiconductor chip 2 during operation, in particular close to or at a maximal operating power of the light emitting semiconductor chip 2 .

[0142] For example, the dimensions of Au bond wires 31, ..., 3n as given in the table below can be used for homogenizing the spatial electrical resistance distribution of the bond wire arrangement 3 described in connection with Figure 10.

[0143]

[0144] Here it is assumed that the bond wires 31, ..., 3n have a circular cross-section, although other cross-sections are possible as well . Moreover, it is further possible to2024PF01016 January 2, 2026

[0145] P2024, 0963 WO N 32

[0146] additionally vary the lengths of the bond wires by changing their loop height even if the bond length is fixed, for example, in order to further homogenize the spatial electrical resistance distribution.

[0147] This patent application claims the priority of German patent application 102025100271.1, the disclosure content of which is hereby incorporated by reference .

[0148] The invention is not restricted to the exemplary embodiments by the description on the basis of said exemplary embodiments . Rather, the invention encompasses any new feature and also any combination of features, which in particular comprises any combination of features in the patent claims and any combination of features in the exemplary embodiments, even if this feature or this combination itself is not explicitly specified in the patent claims or exemplary embodiments .2024PF01016 January 2, 2026

[0149] P2024, 0963 WO N

[0150] - 33 -

[0151] References

[0152] 1 semiconductor device

[0153] 2 light emitting semiconductor chip 21 contact layer

[0154] 22 light outcoupling surface

[0155] 3 bond wire arrangement

[0156] 31...3n bond wire

[0157] 4 submount

[0158] 41 electric contact surface

[0159] 42 metallic contact layer

[0160] 43 further metallic contact layer 44 insulating layer

[0161] 45 conductive layer

[0162] 5 resistor

[0163] 61...6n light emission region

[0164] 7 further bond wire

[0165] 8 further submount

[0166] 9 carrier

[0167] E light emission direction

[0168] L length

[0169] D diameter

[0170] W width

[0171] H heat

Claims

2024PF01016 January 2, 2026P2024, 0963 WO N - 34 -Claims1. A semiconductor device ( 1 ) , comprising:- a light emitting semiconductor chip (2 ) , and- a bond wire arrangement (3) comprising a plurality of bond wires (31, ..., 3n) for electrically contacting the light emitting semiconductor chip (2 ) , wherein- a spatial electrical resistance distribution of the bond wire arrangement (3) is adjusted to tune an electric operating current density across the light emitting semiconductor chip during operation.

2. The semiconductor device ( 1 ) according to the previous claim,wherein the light emitting semiconductor chip (2 ) is an edge emitting laser diode chip .

3. The semiconductor device ( 1 ) according to any of the previous claims,wherein the bond wire arrangement (3) comprises at least ten bond wires (31, ..., 3n) that are directly connected to a contact layer (21 ) of the light emitting semiconductor chip (2 ) .

4. The semiconductor device ( 1 ) according to claim 3, wherein the contact layer (21 ) comprises at least two segments that are physically separated from one another and / or that are arranged adj acent to one another .

5. The semiconductor device ( 1 ) according to any of the previous claims, whereinat least one bond wire (31, ..., 3n) extends longitudinally or transversally to a light emission direction (E) of the light emitting semiconductor chip (2 ) .2024PF01016 January 2, 2026P2024, 0963 WO N - 35 -6. The semiconductor device ( 1 ) according to any of the previous claims,wherein the spatial electrical resistance distribution of the bond wire arrangement (3) is adjusted by using bond wires (31, ..., 3n) with different electrical resistances and / or by changing a local density of wire bonds across a contact layer (21 ) of the light emitting semiconductor chip (2 ) .

7. The semiconductor device ( 1 ) according to any of the previous claims,wherein the spatial electrical resistance distribution of the bond wire arrangement (3) is adjusted by using bond wires (31, ..., 3n) with different lengths (L) , different diameters (D) , and / or different material compositions .

8. The semiconductor device ( 1 ) according to any of the previous claims,wherein the electrical resistance of a bond wire (31, ..., 3n) that is electrically connected to a region adj acent to a light outcoupling surface (22 ) of the light emitting semiconductor chip (2 ) is larger than the electrical resistance of a bond wire (31, ..., 3n) that is electrically connected to a region opposite to the light outcoupling surface (22 ) of the light emitting semiconductor chip (2 ) .

9. The semiconductor device ( 1 ) according to any of the previous claims,wherein the electrical resistances of the bond wires (31, ..., 3n) are adjusted in a range between 50 % and 200 % of a mean electrical resistance of the plurality of bond wires (31, ..., 3n) .2024PF01016 January 2, 2026P2024, 0963 WO N - 36 -10. The semiconductor device ( 1 ) according to any of the previous claims, wherein- the semiconductor device ( 1 ) further comprises a submount (4 ) ,- the light emitting semiconductor chip (2 ) is arranged on and in electrical contact with an electric contact surface (41 ) of the submount, and- the bond wire arrangement (3) is configured for electrically contacting a side of the light emitting semiconductor chip (2 ) facing away from the submount (4 ) .

11. The semiconductor device ( 1 ) according to any of the previous claims, whereinat least some of the plurality of bond wires (31, ..., 3n) are electrically connected in series to corresponding resistors (5) .

12. The semiconductor device ( 1 ) according to claim 11, whereinthe resistors (5) are micro-patterned on a submount (4 ) of the semiconductor device ( 1 ) .

13. The semiconductor device ( 1 ) according to claim 11 or 12, whereinthe spatial electrical resistance distribution of the bond wire arrangement (3) is adjusted by using resistors (5) with different resistances for bond wires (31, ..., 3n) that are connected to different regions of the light emitting semiconductor chip (2 ) .

14. The semiconductor device ( 1 ) according to any of the previous claims, wherein2024PF01016 January 2, 2026P2024, 0963 WO N 37the light emitting semiconductor chip (2 ) comprises a plurality of spatially separated light emission regions ( 61, ..., 6n) .

15. A method of producing a semiconductor device ( 1 ) , comprising the steps of :- providing a light emitting semiconductor chip (2 ) , and - electrically contacting the light emitting semiconductor chip (2 ) using a bond wire arrangement (3) comprising a plurality of bond wires (31, ..., 3n) , wherein- a spatial electrical resistance distribution of the bond wire arrangement (3) is designed to tune an electric operating current density across the light emitting semiconductor chip (2 ) during operation.

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