Display substrate and display device

Abstract

A display substrate and a display device. The display substrate comprises a plurality of pixel driving circuits; each pixel driving circuit at least comprises a first capacitor (10) and a second capacitor (20); the first capacitor (10) comprises a first electrode sheet (11) and a second electrode sheet (12), and the second capacitor (20) comprises a third electrode sheet (13) and a fourth electrode sheet (14); the first electrode sheet (11) is connected to a gate electrode of a third transistor, the second electrode sheet (12) and the third electrode sheet (13) are connected to a second electrode of the third transistor, and the fourth electrode sheet is connected to a second electrode of a fourth transistor; in the direction perpendicular to the display substrate, the display substrate at least comprises a first conductive layer and a second conductive layer, the first electrode sheet (11) and the third electrode sheet (13) are arranged in the first conductive layer, and the second electrode sheet (12) and the fourth electrode sheet (14) are arranged in the second conductive layer.

Description

Display substrate and display device Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, specifically to a display substrate and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) and quantum dot light-emitting diodes (QLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely fast response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and controlled by thin-film transistors (TFTs) have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] On one hand, this disclosure provides a display substrate including a plurality of circuit units, at least one circuit unit including a pixel driving circuit, the pixel driving circuit including at least a first capacitor, a second capacitor, a third transistor as a driving transistor, and a fourth transistor as a data writing transistor, the first capacitor including at least a first electrode plate and a second electrode plate, the second capacitor including at least a third electrode plate and a fourth electrode plate, the orthographic projection of the second electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the first electrode plate on the display substrate plane, the orthographic projection of the fourth electrode plate on the display substrate plane at least partially overlaps with the orthographic projection of the third electrode plate on the display substrate plane; the first electrode plate is connected to the gate electrode of the third transistor, the second electrode plate and the third electrode plate are connected to the second electrode of the third transistor, and the fourth electrode plate is connected to the second electrode of the fourth transistor; in a direction perpendicular to the display substrate, the display substrate includes at least a first conductive layer disposed on a substrate and a second conductive layer disposed on a side of the first conductive layer away from the substrate, the first electrode plate and the third electrode plate are disposed in the first conductive layer, and the second electrode plate and the fourth electrode plate are disposed in the second conductive layer.

[0005] In an exemplary embodiment, the pixel driving circuit further includes a first transistor as a first reset transistor and a second transistor as a second reset transistor. The second terminal of the first transistor is connected to the gate electrode of the first plate and the third transistor, respectively. The second terminal of the second transistor is connected to the second terminal of the fourth plate and the fourth transistor, respectively. At least one of the first terminal of the first transistor and the first terminal of the second transistor is connected to the first initial signal line.

[0006] In an exemplary embodiment, the pixel driving circuit further includes a fifth transistor as a first light-emitting control transistor and a sixth transistor as a third reset transistor. The first terminal of the fifth transistor is connected to the second terminal of the third transistor, the second terminal of the fifth transistor is connected to the second terminal of the sixth transistor and the light-emitting device, and the first terminal of the sixth transistor is connected to the second initial signal line.

[0007] In an exemplary embodiment, the pixel driving circuit further includes a fifth transistor as a first light-emitting control transistor and a sixth transistor as a third reset transistor. The first terminal of the fifth transistor is connected to the second terminal of the third transistor and the second terminal of the sixth transistor, respectively. The second terminal of the fifth transistor is connected to the light-emitting device, and the first terminal of the sixth transistor is connected to the second initial signal line.

[0008] In an exemplary embodiment, at least one circuit unit further includes a second power line extending along a second direction and a second power connection line extending along a first direction, the first direction intersecting the second direction, the second power line being configured to provide a second power signal to the light-emitting device, the second power line being connected to the second power connection line, and a mesh-like interconnection structure for transmitting the second power signal being formed on the display substrate.

[0009] In an exemplary embodiment, the first transistor includes at least a first active layer, the second transistor includes at least a second active layer, and the fourth transistor includes at least a fourth active layer. In at least one circuit unit, the orthographic projection of the second power line on the display substrate plane at least partially overlaps with the orthographic projection of the first active layer, the second active layer, or the fourth active layer on the display substrate plane.

[0010] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the second power line on the display substrate plane at least partially overlaps with the orthographic projections of the first electrode plate and the second electrode plate on the display substrate plane; in a direction perpendicular to the display substrate, the second electrode plate is disposed between the first electrode plate and the second power line.

[0011] In an exemplary embodiment, at least one circuit unit further includes a second initial connection line extending along a second direction. The shape of the second initial signal line is a straight line or a broken line extending along a first direction. The first direction intersects with the second direction. The second initial signal line is connected to the second initial connection line, forming a mesh-like interconnected structure for transmitting the second initial signal on the display substrate.

[0012] In an exemplary embodiment, the first transistor includes at least a first active layer, the second transistor includes at least a second active layer, and the fourth transistor includes at least a fourth active layer. In at least one circuit unit, the orthographic projection of the second initial connection line on the display substrate plane at least partially overlaps with the orthographic projection of the first active layer, the second active layer, or the fourth active layer on the display substrate plane.

[0013] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the second initial connection line on the display substrate plane at least partially overlaps with the orthographic projections of the first electrode plate and the second electrode plate on the display substrate plane; in a direction perpendicular to the display substrate, the second electrode plate is disposed between the first electrode plate and the second initial connection line.

[0014] In an exemplary embodiment, the first terminal of the third transistor is connected to a first power line, which is configured to provide a first power signal to the pixel driving circuit.

[0015] In an exemplary embodiment, the pixel driving circuit further includes a seventh transistor as a second light-emitting control transistor, the first terminal of the seventh transistor being connected to a first power line, the second terminal of the seventh transistor being connected to the first terminal of the third transistor, and the first power line being configured to provide a first power signal to the pixel driving circuit.

[0016] In an exemplary embodiment, at least one circuit unit further includes a first power connection line extending along a first direction. The first power line is in the shape of a straight line or a broken line extending along a second direction. The first direction intersects the second direction. The first power line is connected to the first power connection line, forming a mesh-like interconnected structure on the display substrate for transmitting the first power signal.

[0017] In an exemplary embodiment, the third transistor includes at least a third active layer, the fifth transistor includes at least a fifth active layer, and in at least one circuit unit, the orthographic projection of the first power line on the display substrate plane at least partially overlaps with the orthographic projection of the third active layer or the fifth active layer on the display substrate plane.

[0018] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first power line on the display substrate plane at least partially overlaps with the orthographic projections of the first electrode plate and the second electrode plate on the display substrate plane; in a direction perpendicular to the display substrate, the second electrode plate is disposed between the first electrode plate and the first power line.

[0019] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first power line on the display substrate plane at least partially overlaps with the orthographic projection of the gate electrode of the third transistor on the display substrate plane.

[0020] In an exemplary embodiment, in at least one circuit unit, the first power line includes at least a first region that overlaps with the gate electrode of the third transistor and a second region that does not overlap with the gate electrode of the third transistor, wherein the width of the first region is greater than the width of the second region, and the width is the dimension in the first direction.

[0021] In an exemplary embodiment, the display substrate further includes a first initial connection line extending along a second direction. The shape of the first initial signal line is a straight line or a broken line extending along a first direction. The first direction intersects with the second direction. The first initial signal line is connected to the first initial connection line to form a mesh-like interconnected structure for transmitting the first initial signal on the display substrate.

[0022] In an exemplary embodiment, in the first direction, the first initial connection line is disposed between the first power lines of adjacent circuit units.

[0023] In an exemplary embodiment, the first electrode plate is connected to the second electrode of the first transistor and the gate electrode of the third transistor via a first connection electrode, the second electrode plate is connected to the second electrode of the third transistor via a fourth connection electrode, the third electrode plate is connected to the second electrode of the third transistor via a second connection electrode, and the fourth electrode plate is connected to the second electrode of the second transistor and the second electrode of the fourth transistor via a third connection electrode.

[0024] On the other hand, this disclosure also provides a display device including the aforementioned display substrate.

[0025] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0026] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0027] Figure 1 is a schematic diagram of the structure of a display device;

[0028] Figure 2 is a schematic diagram of a planar structure of a display substrate;

[0029] Figure 3 is a schematic cross-sectional view of a display substrate;

[0030] Figure 4A is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0031] Figure 4B shows an extension of the pixel driving circuit shown in Figure 4A;

[0032] Figure 5 is a driving timing diagram of the pixel driving circuit shown in Figure 4B;

[0033] Figure 6 is another driving timing diagram of the pixel driving circuit shown in Figure 4B;

[0034] Figure 7 is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0035] Figure 8 is a schematic diagram of a mesh connectivity structure according to an exemplary embodiment of the present disclosure;

[0036] Figure 9 is a schematic diagram of a display substrate after the formation of the first conductive layer pattern according to the present disclosure;

[0037] Figures 10A and 10B are schematic diagrams of a display substrate after the formation of a second conductive layer pattern according to the present disclosure;

[0038] Figures 11A and 11B are schematic diagrams of a display substrate after a semiconductor layer pattern has been formed in this disclosure;

[0039] Figures 12A and 12B are schematic diagrams of a display substrate after the formation of a third conductive layer pattern according to the present disclosure;

[0040] Figure 13 is a schematic diagram of a display substrate after the formation of a fourth insulating layer pattern according to the present disclosure;

[0041] Figures 14A and 14B are schematic diagrams of a display substrate after the formation of a fourth conductive layer pattern according to the present disclosure.

[0042] Figure 15 is a schematic diagram of a display substrate after the formation of a first planarization layer pattern according to the present disclosure;

[0043] Figures 16A and 16B are schematic diagrams of a display substrate after the formation of the fifth conductive layer pattern according to the present disclosure.

[0044] Figure 17A is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0045] Figure 17B shows an extension of the pixel driving circuit shown in Figure 17A;

[0046] Figure 18 is a driving timing diagram of the pixel driving circuit shown in Figure 17B;

[0047] Figure 19A is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure;

[0048] Figure 19B shows an extension of the pixel driving circuit shown in Figure 19A;

[0049] Figure 20 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0050] Figure 21 is a schematic diagram of another display substrate of the present disclosure after the formation of the first conductive layer pattern;

[0051] Figure 22 is a schematic diagram of another display substrate after the formation of the second conductive layer pattern according to the present disclosure;

[0052] Figure 23 is a schematic diagram of another display substrate after a semiconductor layer pattern has been formed in this disclosure;

[0053] Figure 24 is a schematic diagram of another display substrate of the present disclosure after the formation of the third conductive layer pattern;

[0054] Figure 25 is a schematic diagram of another display substrate after the formation of the fourth insulating layer pattern according to the present disclosure;

[0055] Figure 26 is a schematic diagram of another display substrate of the present disclosure after the formation of the fourth conductive layer pattern;

[0056] Figure 27 is a schematic diagram of another display substrate of the present disclosure after the formation of the first planarization layer pattern;

[0057] Figure 28 is a schematic diagram of another display substrate of this disclosure after the formation of the fifth conductive layer pattern. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in many ways without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0059] The scale of the figures in this disclosure can be used as a reference in actual manufacturing processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The figures described in this disclosure are only schematic diagrams of the structure, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0060] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0061] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0062] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0063] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the area through which current primarily flows.

[0064] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged, and the "source terminal" and "drain terminal" can be interchanged.

[0065] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0066] In this specification, "parallel" refers to two straight lines forming an angle of -10° or more and less than 10°, and therefore also includes angles of -5° or more and less than 5°. Similarly, "perpendicular" refers to two straight lines forming an angle of 80° or more and less than 100°, and therefore also includes angles of 85° or more and less than 95°.

[0067] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0068] In this specification, triangles, rectangles, trapezoids, pentagons, or hexagons are not strictly defined; they can be approximate triangles, rectangles, trapezoids, pentagons, or hexagons, and may have minor deformations due to tolerances, and may include chamfers, curved edges, and other variations. The term "approximately" in this disclosure means that the limits are not strictly defined, and the values ​​are within the allowable range of process and measurement errors.

[0069] Figure 1 is a schematic diagram of a display device. As shown in Figure 1, the display device may include a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver. The data driver is connected to multiple data signal lines (D1 to Dn), the scan driver is connected to multiple scan signal lines (S1 to Sm), and the light-emitting driver is connected to multiple first light-emitting signal lines (E1 to Eo). n, m, and o can be natural numbers. The pixel array may include multiple sub-pixels Pxij, where i and j can be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to the scan signal lines, the first light-emitting signal lines, and the data signal lines. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller can provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, clock signals, scan start signals, etc. suitable for the specifications of the scan driver to the scan driver, and clock signals, transmit stop signals, etc. suitable for the specifications of the light-emitting driver to the light-emitting driver. The data driver can use the grayscale values ​​and control signals received from the timing controller to generate data voltages to be provided to data signal lines D1, D2, D3, ..., Dn. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to grayscale values ​​to data signal lines D1 to Dn on a pixel-by-pixel basis. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals with on-level pulses to scan signal lines S1 to Sm. For example, a scan driver can be configured as a shift register and can generate scan signals by sequentially transmitting scan start signals, provided in the form of on-level pulses, to the next stage circuit under the control of a clock signal. A light-emitting driver can generate transmit signals to be provided to the first light-emitting signal lines E1, E2, E3, ..., Eo by receiving clock signals, transmit stop signals, etc., from a timing controller. For example, the light-emitting driver can sequentially provide transmit signals with cutoff level pulses to the first light-emitting signal lines E1 to Eo. For example, the light-emitting driver can be configured as a shift register and can generate transmit signals by sequentially transmitting transmit stop signals, provided in the form of cutoff level pulses, to the next stage circuit under the control of a clock signal. In an exemplary embodiment, a pixel array can be disposed on a display substrate.

[0070] Figure 2 is a schematic diagram of a planar structure of a display substrate. As shown in Figure 2, the display substrate may include multiple pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1, a second sub-pixel P2, and a third sub-pixel P3. Each sub-pixel may include a circuit unit and a light-emitting unit. The circuit unit may include at least a pixel driving circuit, which is connected to a scan signal line, a light-emitting signal line, and a data signal line, respectively. The pixel driving circuit is configured to receive the data voltage transmitted by the data signal line and output a corresponding current to the light-emitting unit under the control of the scan signal line and the light-emitting signal line. The light-emitting unit may include a light-emitting device, which is connected to the pixel driving circuit of the sub-pixel. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0071] In an exemplary embodiment, the first sub-pixel P1 can be a red sub-pixel (R) that emits red light, the second sub-pixel P2 can be a green sub-pixel (G) that emits green light, and the third sub-pixel P3 can be a blue sub-pixel (B) that emits blue light. In an exemplary embodiment, the shape of the sub-pixels can be rectangular, rhomboid, pentagonal, or hexagonal, and the three sub-pixels can be arranged in a horizontal, vertical, or triangular manner.

[0072] In other exemplary embodiments, a pixel unit may include four sub-pixels, which may be arranged in a horizontal, vertical, or square manner, etc., and this disclosure does not limit the arrangement.

[0073] Figure 3 is a cross-sectional schematic diagram of a display substrate, illustrating the structure of three sub-pixels in the display substrate. As shown in Figure 3, on a plane perpendicular to the display substrate, the display area may include a driving structure layer 102 disposed on the substrate 101, a light-emitting structure layer 103 disposed on the side of the driving structure layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on the side of the light-emitting structure layer 103 away from the substrate 101. In some possible implementations, the display area may include other film layers, such as a touch structure layer, etc., which are not limited herein.

[0074] In an exemplary embodiment, the substrate 101 can be a flexible substrate or a rigid substrate. The driving structure layer 102 can include multiple circuit units, each of which can include at least a pixel driving circuit composed of multiple transistors and storage capacitors. The light-emitting structure layer 103 can include multiple light-emitting units, each of which can include a light-emitting device. The light-emitting device can include at least an anode, an organic light-emitting layer, and a cathode. The anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, and the cathode is connected to the organic light-emitting layer. The organic light-emitting layer emits light of a corresponding color under the driving of the anode and cathode. The encapsulation structure layer 104 can include a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer stacked together. The first and third encapsulation layers can be made of inorganic materials, and the second encapsulation layer can be made of organic materials. The second encapsulation layer is disposed between the first and third encapsulation layers, forming an inorganic / organic / inorganic material stacked structure, which can ensure that external moisture cannot enter the light-emitting structure layer 103.

[0075] An exemplary embodiment of this disclosure provides a display substrate. In an exemplary embodiment, the display substrate may include a plurality of circuit units, at least one of which includes a pixel driving circuit. The pixel driving circuit includes at least a first capacitor, a second capacitor, a third transistor as a driving transistor, and a fourth transistor as a data writing transistor. The first capacitor includes at least a first electrode and a second electrode, and the second capacitor includes at least a third electrode and a fourth electrode. The orthographic projection of the second electrode on the plane of the display substrate at least partially overlaps with the orthographic projection of the first electrode on the plane of the display substrate, and the orthographic projection of the fourth electrode on the plane of the display substrate at least partially overlaps with the orthographic projection of the third electrode on the plane of the display substrate. The first electrode is connected to the gate electrode of the third transistor, the second electrode and the third electrode are connected to the second electrode of the third transistor, and the fourth electrode is connected to the second electrode of the fourth transistor. In a direction perpendicular to the display substrate, the display substrate includes at least a first conductive layer disposed on a substrate and a second conductive layer disposed on a side of the first conductive layer away from the substrate. The first electrode and the third electrode are disposed in the first conductive layer, and the second electrode and the fourth electrode are disposed in the second conductive layer.

[0076] In an exemplary embodiment, the pixel driving circuit further includes a first transistor as a first reset transistor and a second transistor as a second reset transistor. The second terminal of the first transistor is connected to the gate electrode of the first plate and the third transistor, respectively. The second terminal of the second transistor is connected to the second terminal of the fourth plate and the fourth transistor, respectively. At least one of the first terminal of the first transistor and the first terminal of the second transistor is connected to the first initial signal line.

[0077] In an exemplary embodiment, the pixel driving circuit further includes a fifth transistor as a first light-emitting control transistor and a sixth transistor as a third reset transistor. The first terminal of the fifth transistor is connected to the second terminal of the third transistor, the second terminal of the fifth transistor is connected to the second terminal of the sixth transistor and the light-emitting device, and the first terminal of the sixth transistor is connected to the second initial signal line.

[0078] In an exemplary embodiment, the pixel driving circuit further includes a fifth transistor as a first light-emitting control transistor and a sixth transistor as a third reset transistor. The first terminal of the fifth transistor is connected to the second terminal of the third transistor and the second terminal of the sixth transistor, respectively. The second terminal of the fifth transistor is connected to the light-emitting device, and the first terminal of the sixth transistor is connected to the second initial signal line.

[0079] In an exemplary embodiment, the first terminal of the third transistor is connected to a first power line, which is configured to provide a first power signal to the pixel driving circuit.

[0080] In an exemplary embodiment, the pixel driving circuit further includes a seventh transistor as a second light-emitting control transistor, the first terminal of the seventh transistor being connected to a first power line, the second terminal of the seventh transistor being connected to the first terminal of the third transistor, and the first power line being configured to provide a first power signal to the pixel driving circuit.

[0081] The following examples illustrate the display substrate of this embodiment.

[0082] An exemplary embodiment of this disclosure provides a display substrate. In a direction perpendicular to the display substrate, the display substrate may include at least a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate. In a plane parallel to the display substrate, the driving structure layer may include multiple circuit units forming multiple cell rows and multiple cell columns. Each circuit unit may include at least a pixel driving circuit. The light-emitting structure layer may include multiple light-emitting units, each light-emitting unit may include at least a light-emitting device. At least one pixel driving circuit is connected to at least one light-emitting unit, and the pixel driving circuit is configured to provide a driving signal to the connected light-emitting device to drive the corresponding light-emitting device to emit light.

[0083] In exemplary embodiments, the circuit unit referred to in this disclosure refers to a region divided according to the pixel driving circuit, and the light-emitting unit referred to in this disclosure refers to a region divided according to the light-emitting device. In exemplary embodiments, the position of the orthographic projection of the light-emitting unit on the substrate may correspond to the position of the orthographic projection of the circuit unit on the substrate, or the position of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position of the orthographic projection of the circuit unit on the substrate.

[0084] Figure 4A is an equivalent circuit diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure. As shown in Figure 4A, the pixel driving circuit of the exemplary embodiment of the present disclosure adopts a 6T2C structure. Each pixel driving circuit may include 6 transistors (first transistor T1 to sixth transistor T6) and 2 capacitors (first capacitor C1 and second capacitor C2). The pixel driving circuit is connected to 10 signal lines (first scan signal line S1, second scan signal line S2, third scan signal line S3, fourth scan signal line S4, first light emission signal line EM1, first initial signal line INIT1, second initial signal line INIT2, third initial signal line INIT3, data signal line DATA and first power supply line VDD).

[0085] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to the second electrode of the first transistor T1, the gate electrode of the third transistor T3, and the first terminal of the first capacitor C1. The second node N2 is connected to the second electrode of the third transistor T3, the first electrode of the fifth transistor T5, the second terminal of the first capacitor C1, and the second terminal of the second capacitor C2. The third node N3 is connected to the second electrode of the second transistor T2, the second electrode of the fourth transistor T4, and the first terminal of the second capacitor C2. The fourth node N4 is connected to the second electrode of the fifth transistor T5 and the second electrode of the sixth transistor T6.

[0086] In an exemplary embodiment, the first terminal of the first capacitor C1 is connected to the first node N1, and the second terminal of the first capacitor C1 is connected to the second node N2. The first terminal of the second capacitor C2 is connected to the third node N3, and the second terminal of the second capacitor C2 is connected to the second node N2.

[0087] In an exemplary embodiment, the first transistor T1 may be referred to as the first reset transistor. The gate electrode of the first transistor T1 is connected to the first scan signal line S1, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is connected to the first node N1.

[0088] In an exemplary embodiment, the second transistor T2 can be referred to as the second reset transistor. The gate electrode of the second transistor T2 is connected to the third scan signal line S3, the first electrode of the second transistor T2 is connected to the third initial signal line INIT3, and the second electrode of the second transistor T2 is connected to the third node N3.

[0089] In an exemplary embodiment, the third transistor T3 can be referred to as a driving transistor. The gate electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the first power line VDD, and the second electrode of the third transistor T3 is connected to the second node N2.

[0090] In an exemplary embodiment, the fourth transistor T4 can be referred to as a data write transistor. The gate electrode of the fourth transistor T4 is connected to the fourth scan signal line S4, the first electrode of the fourth transistor T4 is connected to the data signal line DATA, and the second electrode of the fourth transistor T4 is connected to the third node N3.

[0091] In an exemplary embodiment, the fifth transistor T5 can be referred to as the first light-emitting control transistor. The gate electrode of the fifth transistor T5 is connected to the first light-emitting signal line EM1, the first electrode of the fifth transistor T5 is connected to the second node N2, and the second electrode of the fifth transistor T5 is connected to the fourth node N4.

[0092] In an exemplary embodiment, the sixth transistor T6 can be referred to as the third reset transistor. The gate electrode of the sixth transistor T6 is connected to the second scan signal line S2, the first electrode of the sixth transistor T6 is connected to the second initial signal line INIT2, and the second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0093] In an exemplary embodiment, the first electrode of the light-emitting device EL is connected to the fourth node N4, and the second electrode of the light-emitting device EL is connected to the second power line VSS. The light-emitting device EL can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or it can be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode).

[0094] In an exemplary embodiment, the six transistors in the pixel driving circuit can be N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the processing difficulty of the display substrate, and improve the product yield.

[0095] In an exemplary embodiment, all six transistors in the pixel driving circuit can be oxide transistors, and the active layer of the oxide transistors can be oxide semiconductor. Oxide transistors have advantages such as high electron mobility, low operating voltage, and low leakage current. By using a display substrate with oxide transistors, low-frequency driving can be achieved, power consumption can be reduced, and display quality can be improved.

[0096] In an exemplary embodiment, the first power line VDD can be configured to provide a constant first voltage signal to the pixel driving circuit, and the second power line VSS can be configured to provide a constant second voltage signal to the light-emitting device. The voltage of the first voltage signal is greater than the voltage of the second voltage signal, i.e., the first voltage signal is a high-level signal and the second voltage signal is a low-level signal. The first initial signal line INIT1 and the second initial signal line INIT2 can be configured to provide constant voltage signals to the pixel driving circuit; this disclosure does not limit the scope of the application.

[0097] Figure 4B shows an extension of the pixel driving circuit shown in Figure 4A. As shown in Figure 4B, the structure of the pixel driving circuit in this embodiment is basically the same as that shown in Figure 4A. The difference is that the first initial signal line INIT1 and the third initial signal line INIT3 are the same initial signal line, that is, the first terminal of the first transistor T1 and the first terminal of the second transistor T2 are both connected to the first initial signal line INIT1.

[0098] Figure 5 is a timing diagram of one possible pixel driving circuit shown in Figure 4B. As shown in Figure 5, in an exemplary embodiment, the operation of the pixel driving circuit may include:

[0099] The first stage, A1, can be called the reset stage. The signals of the first scan signal line S1, the second scan signal line S2, the third scan signal line S3, and the first light-emitting signal line EM1 are high-level signals, and the signal of the fourth scan signal line S4 is low-level signal, which turns on the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6, and turns off the fourth transistor T4.

[0100] The first transistor T1 and the second transistor T2 are turned on, allowing the first initial signal provided by the first initial signal line INIT1 to be supplied to the first node N1 and the third node N3 respectively, initializing the first node N1 and the third node N3. The potentials of the first node N1 and the third node N3 are Vinit1. The sixth transistor T6 is turned on, allowing the second initial signal provided by the second initial signal line INIT2 to be supplied to the fourth node N4, initializing the fourth node N4. The fifth transistor T5 is turned on, connecting the second node N2 and the fourth node N4, with the potentials of the second node N2 and the fourth node N4 being Vinit2. During this stage, the voltage difference (Vinit1-Vinit2) between the first node N1 and the second node N2 can turn on the third transistor T3.

[0101] The second stage, A2, can be called the compensation stage. The signals of the first scan signal line S1, the second scan signal line S2, and the third scan signal line S3 are high-level signals, while the signals of the fourth scan signal line S4 and the first light-emitting signal line EM1 are low-level signals, causing the first transistor T1, the second transistor T2, and the sixth transistor T6 to be turned on, and the fourth transistor T4 and the fifth transistor T5 to be turned off.

[0102] The first transistor T1 and the second transistor T2 are turned on, causing the potentials of the first node N1 and the third node N3 to remain at Vinit1. The sixth transistor T6 is turned on, causing the potential of the fourth node N4 to remain at Vinit2. Since the third transistor T3 is turned on, the potential of the second node N2 at the end of the compensation phase is Vinit1-Vth. The current of the third transistor T3 is very small, and it is basically in the off state. Vth is the threshold voltage of the third transistor T3.

[0103] The third stage, A3, can be called the data writing stage. The signals of the first scan signal line S1 and the second scan signal line S2 are continuously high-level signals, the signal of the fourth scan signal line S4 is a short-term high-level signal, and the signals of the third scan signal line S3 and the first light-emitting signal line EM1 are continuously low-level signals, causing the first transistor T1 and the sixth transistor T6 to be continuously turned on, the fourth transistor T4 to be turned on for a short time, and the second transistor T2 and the fifth transistor T5 to be turned off.

[0104] The first transistor T1 is turned on, causing the potential of the first node N1 to remain at Vinit1. The sixth transistor T6 is turned on, causing the potential of the fourth node N4 to remain at Vinit2. The fourth transistor T4 is turned on, causing the data signal output from the data signal line DATA to be written into the third node N3, and the potential of the third node N3 is Vdata. Due to the voltage division of the second capacitor C2, the potential of the second node N2 is Vinit1 - Vth + [C2 / (C1+C2)]*(Vdata - Vinit1). At this time, the potential difference between the first node N1 and the second node N2 (i.e., the gate-source voltage Vgs of the third transistor T3) is Vth - [C2 / (C1+C2)]*(Vdata - Vinit1).

[0105] The fourth stage, A4, can be called the noise elimination stage. The signal of the second scan signal line S2 is a high-level signal, while the signals of the first scan signal line S1, the third scan signal line S3, the fourth scan signal line S4, and the first light-emitting signal line EM1 are low-level signals, turning on the sixth transistor T6 and turning off the first transistor T1, the second transistor T2, the fourth transistor T4, and the fifth transistor T5.

[0106] The sixth transistor T6 is turned on, keeping the potential of the fourth node N4 at Vinit2. The third transistor T3 is turned on, and the first power signal output from the first power line VDD can be quickly written into the second node N2. Due to the presence of the first capacitor C1, the potential difference between the first node N1 and the second node N2 is basically the same as in the previous stage.

[0107] The fifth stage, A5, can be called the light-emitting stage. The first light-emitting signal line EM1 is a high-level signal, while the signals of the first scan signal line S1, the second scan signal line S2, the third scan signal line S3, and the fourth scan signal line S4 are low-level signals. The fifth transistor T5 is turned on, while the first transistor T1, the second transistor T2, the fourth transistor T4, and the sixth transistor T6 are turned off.

[0108] In this stage, the first light-emitting signal line EM1 changes from a low-level signal to a high-level signal, the fifth transistor T5 is turned on, and the first power signal output by the first power line VDD provides a driving voltage to the first electrode of the light-emitting element EL through the turned-on third transistor T3 and fifth transistor T5, driving the light-emitting element EL to emit light.

[0109] The output current I of the third transistor T3 OLED Satisfy the following formula:

[0110] I OLED =1 / 2*k*{[C2 / (C1+C2)]*(Vdata-Vinit1)} 2

[0111] Where K is a constant related to the process and design.

[0112] As can be seen from the formula for the output current of the third transistor T3, the output current of the pixel driving circuit is independent of the threshold voltage Vth of the third transistor T3, thus eliminating the influence of the threshold voltage of the third transistor T3 on the output current. The output current can be controlled by controlling the voltage of the data signal, thereby controlling the brightness of the light-emitting device EL. This ensures uniform display brightness of the display product and improves the overall display effect.

[0113] The pixel driving circuit provided in this exemplary embodiment performs threshold voltage compensation in the second stage A2 and data writing in the third stage A3. The threshold voltage compensation and data writing are separated, and the threshold voltage compensation is no longer limited by the line cycle time, enabling high-frequency driving display and enhancing the threshold voltage compensation effect. Since the first transistor T1 is disconnected before the light-emitting stage, the first power signal output from the first power line VDD can be quickly written to the second node N2, avoiding brightness differences caused by charging the first capacitor C1 and the second capacitor C2 for different low-grayscale pixels. Because the signal of the second scan signal line S2 is a continuous high-level signal during the non-light-emitting stage, the sixth transistor T6 remains continuously conducting, thus the potential of the fourth node N4 is essentially unaffected. This effectively eliminates differences in transistors at different positions due to process variations, effectively eliminates the coupling of the fourth node N4 to different potentials, and effectively eliminates the problem of inconsistent potentials of the fourth node N4 when it is lit.

[0114] Figure 6 shows another driving timing diagram of the pixel driving circuit shown in Figure 4B. As shown in Figure 6, the operation process of the pixel driving circuit is basically the same as that shown in Figure 5. The difference is that in the first stage A1 and the fourth stage A4, the signal of the second scan signal line S2 is a high-level signal, the sixth transistor T6 is turned on, and the fourth node N4 is initialized. In the second stage A2 and the third stage A3, the signal of the second scan signal line S2 is a low-level signal, and the sixth transistor T6 is turned off.

[0115] Figure 7 is a schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of six circuit units. On a plane parallel to the display substrate, the display substrate may include multiple circuit units forming multiple unit rows and multiple unit columns. At least one circuit unit may include a pixel driving circuit, and a first light-emitting signal line 41, a first scan signal line 61, a second scan signal line 62, a third scan signal line 63, a fourth scan signal line 64, a first initial signal line 71, a second initial signal line 72, a first power supply line 81, and a data signal line 83 connected to the pixel driving circuit. At least one pixel driving circuit may include at least a first capacitor 10, a second capacitor 20, a first transistor T1 as a first reset transistor, a second transistor T2 as a second reset transistor, a third transistor T3 as a driving transistor, a fourth transistor T4 as a data writing transistor, a fifth transistor T5 as a first light-emitting control transistor, and a sixth transistor T6 as a third reset transistor. In an exemplary embodiment, the first transistor T1 to the sixth transistor T6 may be oxide transistors.

[0116] In an exemplary embodiment, the first capacitor 10 may include at least a first electrode 11 and a second electrode 12 stacked together, wherein the orthographic projection of the second electrode 12 onto the display substrate plane at least partially overlaps with the orthographic projection of the first electrode 11 onto the display substrate plane. The second capacitor 20 may include at least a third electrode 13 and a fourth electrode 14 stacked together, wherein the orthographic projection of the fourth electrode 14 onto the display substrate plane at least partially overlaps with the orthographic projection of the third electrode 13 onto the display substrate plane.

[0117] In an exemplary embodiment, the first light-emitting signal line 41 is configured to provide a first light-emitting control signal to the pixel driving circuit, the first scan signal line 61 to the fourth scan signal line 64 are configured to provide the first scan signal to the fourth scan signal to the pixel driving circuit respectively, the first initial signal line 71 and the second initial signal line 72 are configured to provide the first initial signal and the second initial signal to the pixel driving circuit respectively, the first power line 81 is configured to provide the first power signal to the pixel driving circuit, and the data signal line 83 is configured to provide the data signal to the pixel driving circuit.

[0118] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the first scan signal line 61, the first terminal of the first transistor T1 is connected to the first initial signal line 71, and the second terminal of the first transistor T1 is connected to the gate electrode 33 of the third transistor T3 and the first plate 11 of the first capacitor 10, respectively. The gate electrode of the second transistor T2 is connected to the third scan signal line 63, the first terminal of the second transistor T2 is connected to the first initial signal line 71, and the second terminal of the second transistor T2 is connected to the second terminal of the fourth transistor T4 and the fourth plate 14 of the second capacitor 20, respectively. The first terminal of the third transistor T3 is connected to the first power supply line 81, and the second terminal of the third transistor T3 is connected to the first terminal of the fifth transistor T5, the second plate 12 of the first capacitor 10, and the third plate 13 of the second capacitor 20, respectively. The gate electrode of the fourth transistor T4 is connected to the fourth scan signal line 64, and the first terminal of the fourth transistor T4 is connected to the data signal line 83. The gate electrode of the fifth transistor T5 is connected to the first light emission signal line 41, and the second terminal of the fifth transistor T5 is connected to the second terminal of the sixth transistor T6. The gate electrode of the sixth transistor T6 is connected to the second scan signal line 62, and the first electrode of the sixth transistor T6 is connected to the second initial signal line 72. Furthermore, the second electrodes of the fifth transistor T5 and the sixth transistor T6 are configured to be connected to a light-emitting device.

[0119] In an exemplary embodiment, the shapes of the first scan signal line 61, the second scan signal line 62, the third scan signal line 63, the fourth scan signal line 64, the first light emission signal line 41, the first initial signal line 71, and the second initial signal line 72 can be straight lines or broken lines extending along the first direction X of the main body, and the shapes of the first power line 81 and the data signal line 83 can be straight lines or broken lines extending along the second direction Y of the main body.

[0120] In this disclosure, "A extends along direction B" means that A may include a main part and a secondary part connected to the main part. The main part is a line, line segment, or strip-shaped body. The main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In the following description, "A extends along direction B" refers to "the main body of A extends along direction B".

[0121] In an exemplary embodiment, the first scan signal line 61 may be located on the side of the gate electrode 33 (i.e., the third gate electrode) of the third transistor T3 in the second direction Y; the first initial signal line 71 may be located on the side of the first scan signal line 61 away from the gate electrode 33 of the third transistor T3; the third scan signal line 63 may be located on the side of the first initial signal line 71 away from the gate electrode 33 of the third transistor T3; the fourth scan signal line 64 may be located on the side of the third scan signal line 63 away from the gate electrode 33 of the third transistor T3; the first light emission signal line 41 may be located on the side of the fourth scan signal line 64 away from the gate electrode 33 of the third transistor T3; the second scan signal line 62 may be located on the side of the first light emission signal line 41 away from the gate electrode 33 of the third transistor T3; and the second initial signal line 72 may be located on the side of the second scan signal line 62 away from the gate electrode 33 of the third transistor T3.

[0122] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include at least a first conductive layer (first gate metal layer) disposed on a substrate, a first insulating layer disposed on the side of the first conductive layer away from the substrate, a second conductive layer (second gate metal layer) disposed on the side of the first insulating layer away from the substrate, a second insulating layer disposed on the side of the second conductive layer away from the substrate, a semiconductor layer disposed on the side of the second insulating layer away from the substrate, a third insulating layer disposed on the side of the semiconductor layer away from the substrate, a third conductive layer (third gate metal layer) disposed on the side of the third insulating layer away from the substrate, a fourth insulating layer disposed on the side of the third conductive layer away from the substrate, and a fourth conductive layer (first source / drain metal layer) disposed on the side of the fourth insulating layer away from the substrate.

[0123] In an exemplary embodiment, the first electrode plate 11 and the third electrode plate 13 may be disposed in the first conductive layer, and the second electrode plate 12 and the fourth electrode plate 14 may be disposed in the second conductive layer. That is, the first electrode plate 11 and the third electrode plate 13 may be disposed in the same layer, and the second electrode plate 12 and the fourth electrode plate 14 may be disposed in the same layer.

[0124] In an exemplary embodiment, the first electrode 11 can serve as the first terminal of the first capacitor 10, having the potential of the first node N1 in the pixel driving circuit. The first electrode 11 can be connected to the second terminal of the first transistor T1 and the gate electrode 33 of the third transistor T3 via the first connecting electrode 51. The second electrode 12 can serve as the second terminal of the first capacitor 10, having the potential of the second node N2 in the pixel driving circuit. The second electrode 12 can be connected to the second terminal of the third transistor T3 via the fourth connecting electrode 54. The first electrode 11 having the potential of the first node and the second electrode 12 having the potential of the second node form the first capacitor C1 of the pixel driving circuit.

[0125] In an exemplary embodiment, the third electrode 13 can serve as the second terminal of the second capacitor 10, having the potential of the second node N2 in the pixel driving circuit. The third electrode 13 can be connected to the second terminal of the third transistor T3 and the first terminal of the fifth transistor T5 via the second connection electrode 52. The fourth electrode 14 can serve as the first terminal of the second capacitor 10, having the potential of the third node N3 in the pixel driving circuit. The fourth electrode 14 can be connected to the second terminal of the second transistor T2 and the second terminal of the fourth transistor T4 via the third connection electrode 53. The third electrode 13 having the potential of the second node and the fourth electrode 14 having the potential of the third node form the second capacitor C2 of the pixel driving circuit.

[0126] In an exemplary embodiment, the pixel driving circuits in some adjacent cell columns may be substantially identical. For example, the pixel driving circuits in the Nth cell column and the (N+3)th cell column may be substantially identical. Similarly, the pixel driving circuits in the (N+1)th cell column and the (N+4)th cell column may be substantially identical. And again, the pixel driving circuits in the (N+2)th cell column and the (N+5)th cell column may be substantially identical.

[0127] In an exemplary embodiment, the pixel driving circuits in some adjacent cell columns can be mirror-symmetrical with respect to the column center line, which can be a broken line located between adjacent cell columns and extending along the second direction Y. For example, the pixel driving circuits in the (N+1)th and (N+2)th cell columns can be mirror-symmetrical with respect to the column center line. Similarly, the pixel driving circuits in the (N+4)th and (N+5)th cell columns can be mirror-symmetrical with respect to the column center line.

[0128] In an exemplary embodiment, the third transistor T3 may include at least a third active layer, and the fifth transistor T5 may include at least a fifth active layer. In at least one circuit unit, the orthographic projection of the first power line 81 onto the display substrate plane at least partially overlaps with the orthographic projection of the third or fifth active layer onto the display substrate plane.

[0129] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first power line 81 on the display substrate plane at least partially overlaps with the orthographic projection of the gate electrode 33 of the third transistor T3 on the display substrate plane.

[0130] In an exemplary embodiment, in at least one circuit unit, the first power line 81 may include at least a first region that overlaps with the gate electrode 33 of the third transistor T3 and a second region that does not overlap with the gate electrode 33 of the third transistor T3. The width of the first region is greater than the width of the second region, and the width is the dimension of the first direction X.

[0131] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first power line 81 onto the display substrate plane at least partially overlaps with the orthographic projections of the first electrode plate 11 and the second electrode plate 12 onto the display substrate plane. In a direction perpendicular to the display substrate, the second electrode plate 12 is disposed between the first electrode plate 11 and the first power line 81.

[0132] Figure 8 is a schematic diagram of a mesh-like interconnected structure according to an exemplary embodiment of the present disclosure. As shown in Figure 8, the display substrate may further include a first power connection line 65, a second power connection line 66, a second power line 82, a first initial connection line 91, and a second initial connection line 92. The second power line 82 is configured to provide a second power signal to the light-emitting device. The shapes of the first power connection line 65 and the second power connection line 66 may be straight lines or broken lines extending along the first direction X, and the shapes of the second power line 82, the first initial connection line 91, and the second initial connection line 92 may be straight lines or broken lines extending along the second direction Y.

[0133] In an exemplary embodiment, the second power connection line 66 may be located on the side opposite to the second direction Y of the gate electrode 33 (i.e., the third gate electrode) of the third transistor T3, and the first power connection line 65 may be located on the side of the second power connection line 66 away from the gate electrode 33 of the third transistor T3.

[0134] In an exemplary embodiment, a first power connection line 65 extending along a first direction X is connected to a first power line 81 extending along a second direction Y, and the first power connection line 65 and the first power line 81 form a mesh-like interconnected structure on the display substrate for transmitting a first power signal.

[0135] In an exemplary embodiment, a first power connection line 65 may be provided in each cell row, and a first power line 81 may be provided in each cell column. The first power line 81 may be connected to the first power connection line 65 through a via.

[0136] In an exemplary embodiment, a second power connection line 66 extending along a first direction X is connected to a second power line 82 extending along a second direction Y. The second power connection line 66 and the second power line 82 form a mesh-like interconnected structure on the display substrate for transmitting a second power signal.

[0137] In an exemplary embodiment, the second power connection line 66 may be provided in each cell row, and the second power line 82 may be provided in some cell columns (such as the N+1 cell column, the N+2 cell column, the N+4 cell column and the N+5 cell column). The second power line 82 may be connected to the second power connection line 66 through a via.

[0138] In an exemplary embodiment, the first transistor T1 may include at least a first active layer, the second transistor T2 may include at least a second active layer, and the fourth transistor T4 may include at least a fourth active layer. In at least one circuit unit, the orthographic projection of the second power line 82 on the display substrate plane at least partially overlaps with the orthographic projection of the first active layer, the second active layer, or the fourth active layer on the display substrate plane.

[0139] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the second power line 82 onto the display substrate plane at least partially overlaps with the orthographic projections of the first electrode plate 11 and the second electrode plate 12 onto the display substrate plane. In a direction perpendicular to the display substrate, the second electrode plate 12 is disposed between the first electrode plate 11 and the second power line 82.

[0140] In an exemplary embodiment, a first initial signal line 71 extending along a first direction X is connected to a first initial connection line 91 extending along a second direction Y, and the first initial signal line 71 and the first initial connection line 91 form a mesh-like interconnected structure on the display substrate for transmitting the first initial signal.

[0141] In an exemplary embodiment, the first initial signal line 71 may be disposed in each cell row, and the first initial connection line 91 may be disposed between some cell columns (such as between the N+1th cell column and the N+2th cell column, and between the N+4th cell column and the N+5th cell column). The first initial connection line 91 may be connected to the first initial signal line 71 through a via.

[0142] In an exemplary embodiment, the first initial connection line 91 may be disposed between two first power lines 81 of adjacent cell columns.

[0143] In an exemplary embodiment, a second initial signal line 72 extending along a first direction X is connected to a second initial connection line 92 extending along a second direction Y, and the second initial signal line 72 and the second initial connection line 92 form a mesh-like interconnected structure on the display substrate for transmitting the second initial signal.

[0144] In an exemplary embodiment, the second initial signal line 72 may be disposed in each cell row, and the second initial connection line 92 may be disposed in some cell columns (such as the Nth cell column and the N+3th cell column). The second initial connection line 92 may be connected to the second initial signal line 72 through a via.

[0145] In an exemplary embodiment, the first transistor T1 may include at least a first active layer, the second transistor T2 may include at least a second active layer, and the fourth transistor T4 may include at least a fourth active layer. In at least one circuit unit, the orthographic projection of the second initial signal line 72 onto the display substrate plane at least partially overlaps with the orthographic projection of the first active layer, the second active layer, or the fourth active layer onto the display substrate plane.

[0146] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the second initial signal line 72 onto the display substrate plane at least partially overlaps with the orthographic projections of the first electrode plate 11 and the second electrode plate 12 onto the display substrate plane. The second electrode plate 12 is disposed between the first electrode plate 11 and the second initial signal line 72 in a direction perpendicular to the display substrate.

[0147] The following exemplary description illustrates the fabrication process of the display substrate using this exemplary embodiment. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as depositing a film layer, coating the film layer with photoresist, mask exposure, development, etching, and photoresist stripping; for organic materials, processes include coating the organic material, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching, and this disclosure does not limit the methods. A "thin film" refers to a thin film made by depositing, coating, or other processes onto a substrate using a certain material. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0148] In an exemplary embodiment, taking six circuit units with one cell row and six cell columns (cell N to cell N+5) as an example, the fabrication process of the display substrate in this embodiment may include the following operations.

[0149] (11) Forming a first conductive layer pattern. In an exemplary embodiment, forming a first conductive layer pattern may include: depositing a first conductive thin film on a substrate, patterning the first conductive thin film using a patterning process, and forming a first conductive layer pattern on the substrate, as shown in FIG9. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0150] In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the display substrate may include at least the first electrode 11 of the first capacitor and the third electrode 13 of the second capacitor.

[0151] In an exemplary embodiment, the shape of the first plate 11 of the first capacitor can be block-shaped (such as rectangular), the corners of the block shape can be rounded, and the edge of the block shape can be a straight line or a broken line. The first plate 11 is configured as a capacitor plate of the first capacitor (the first end of the first capacitor C1).

[0152] In an exemplary embodiment, a first electrode plate connecting block 11-1 may be provided on the first electrode plate 11. The shape of the first electrode plate connecting block 11-1 may be block-shaped (such as rectangular) and connected to the first electrode plate 11. The first electrode plate connecting block 11-1 is configured to be connected to the first connecting electrode subsequently formed.

[0153] In an exemplary embodiment, in at least one circuit unit, the first electrode plate 11 and the first electrode plate connecting block 11-1 can be an integral structure that is interconnected.

[0154] In an exemplary embodiment, the third plate 13 of the second capacitor can be block-shaped (such as rectangular), the corners of the block shape can be rounded, the edges of the block shape can be straight lines or broken lines, and it can be located on one side of the first plate 11 in the second direction Y. The third plate 13 is configured as a capacitor plate of the second capacitor (the second end of the second capacitor C2).

[0155] In an exemplary embodiment, a second electrode plate connecting block 13-1 may be provided on the third electrode plate 13. The shape of the second electrode plate connecting block 13-1 may be block-shaped (such as rectangular) and connected to the third electrode plate 13. The second electrode plate connecting block 13-1 is configured to be connected to the second connecting electrode subsequently formed.

[0156] In an exemplary embodiment, in at least one circuit unit, the third electrode plate 13 and the second electrode plate connecting block 13-1 can be an integral structure that is interconnected.

[0157] In an exemplary embodiment, the area of ​​the first electrode plate 11 projected onto the substrate can be larger than the area of ​​the third electrode plate 13 projected onto the substrate.

[0158] In an exemplary embodiment, the ratio of the area of ​​the first electrode plate 11 projected onto the substrate to the area of ​​the third electrode plate 13 projected onto the substrate can be greater than or equal to 2.

[0159] In an exemplary embodiment, the first conductive layers in some adjacent cell columns may be substantially identical. For example, the shapes and positions of the first electrode 11 and the third electrode 13 in the Nth, N+1th, N+3th, and N+4th cell columns may be substantially identical. Similarly, the shapes and positions of the first electrode 11 and the third electrode 13 in the N+2th and N+5th cell columns may be substantially identical.

[0160] In an exemplary embodiment, the first conductive layer in some adjacent cell columns may be mirror-symmetrical with respect to the column center line. For example, the first electrode 11 and the third electrode 13 in the (N+1)th and (N+2)th cell columns may be mirror-symmetrical with respect to the column center line. Similarly, the first electrode 11 and the third electrode 13 in the (N+2)th and (N+3)th cell columns may be mirror-symmetrical with respect to the column center line. Furthermore, the first conductive layer in the (N+4)th and (N+5)th cell columns may be mirror-symmetrical with respect to the column center line.

[0161] (12) Forming a second conductive layer pattern. In an exemplary embodiment, forming a second conductive layer pattern may include: sequentially depositing a first insulating film and a second conductive film on a substrate on which the aforementioned pattern is formed; patterning the second conductive film using a patterning process to form a first insulating layer covering the first conductive layer pattern; and a second conductive layer pattern disposed on the first insulating layer, as shown in Figures 10A and 10B, where Figure 10B is a planar schematic diagram of the second conductive layer in Figure 10A. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0162] In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display substrate includes at least: the second electrode 12 of the first capacitor and the fourth electrode 14 of the second capacitor.

[0163] In an exemplary embodiment, the shape of the second electrode plate 12 of the first capacitor can be block-shaped (such as rectangular), the corners of the block shape can be rounded, and the edge of the block shape can be a straight line or a broken line. The orthographic projection of the second electrode plate 12 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 11 on the substrate. The second electrode plate 12 is configured as another capacitor electrode plate of the first capacitor (the second end of the first capacitor C1). The stacked first electrode plate 11 and the second electrode plate 12 constitute the first capacitor C1 of the pixel driving circuit.

[0164] In an exemplary embodiment, the fourth electrode plate 14 of the second capacitor can be block-shaped (such as rectangular), with rounded corners at the corners and straight or broken edges. It can be located on one side of the second electrode plate 12 in the second direction Y. The orthographic projection of the fourth electrode plate 14 on the substrate at least partially overlaps with the orthographic projection of the third electrode plate 13 on the substrate. The fourth electrode plate 14 is configured as another capacitor electrode of the second capacitor (the first end of the second capacitor C2). The stacked third electrode plate 13 and the fourth electrode plate 14 constitute the second capacitor C2 of the pixel driving circuit.

[0165] In an exemplary embodiment, a first groove 12-1 may be provided on the second electrode plate 12, and the first groove 12-1 is configured to expose the first electrode plate connecting block 11-1 of the first electrode plate 11.

[0166] In an exemplary embodiment, a second groove 14-1 may be provided on the fourth electrode plate 14, the second groove 14-1 being configured to expose the second electrode plate connecting block 13-1 of the third electrode plate 13.

[0167] In an exemplary embodiment, the area of ​​the second electrode plate 12 projected onto the substrate can be larger than the area of ​​the fourth electrode plate 14 projected onto the substrate.

[0168] In an exemplary embodiment, the ratio of the area of ​​the second electrode plate 12 projected onto the substrate to the area of ​​the fourth electrode plate 14 projected onto the substrate can be greater than or equal to 2.

[0169] In an exemplary embodiment, the orthographic projection of the second electrode plate 12 on the substrate and the orthographic projection of the first electrode plate 11 on the substrate have a first overlapping area, and the orthographic projection of the fourth electrode plate 14 on the substrate and the orthographic projection of the third electrode plate 13 on the substrate have a second overlapping area. The ratio of the first overlapping area to the second overlapping area can be greater than or equal to 2, that is, the ratio of the capacitance value of the first capacitor to the capacitance value of the second capacitor can be greater than or equal to 2.

[0170] In an exemplary embodiment, the second conductive layers in some adjacent cell columns may be substantially identical. For example, the shapes and positions of the second electrode 12 and the fourth electrode 14 in the Nth, N+1th, N+3th, and N+4th cell columns may be substantially identical. Similarly, the shapes and positions of the second electrode 12 and the fourth electrode 14 in the N+2th and N+5th cell columns may be substantially identical.

[0171] In an exemplary embodiment, the second conductive layer in some adjacent cell columns may be mirror-symmetrical with respect to the column center line. For example, the second electrode 12 and the fourth electrode 14 in the N+1 and N+2 cell columns may be mirror-symmetrical with respect to the column center line. Similarly, the second conductive layer in the N+4 and N+5 cell columns may be mirror-symmetrical with respect to the column center line.

[0172] (13) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: depositing a second insulating film and a semiconductor film sequentially on a substrate on which the aforementioned pattern is formed, patterning the semiconductor film by a patterning process to form a second insulating layer covering the second conductive layer, and a semiconductor layer pattern disposed on the second insulating layer, as shown in FIG11A and FIG11B, FIG11B being a planar schematic diagram of the semiconductor layer in FIG11A.

[0173] In an exemplary embodiment, the semiconductor layer pattern of each circuit unit in the display substrate may include the first active layer 21 of the first transistor T1 to the sixth active layer 26 of the sixth transistor T6, and the first active layer 21, the second active layer 22 and the fourth active layer 24 may be an integral structure interconnected with each other, and the third active layer 23, the fifth active layer 25 and the sixth active layer 26 may be an integral structure interconnected with each other.

[0174] In an exemplary embodiment, the first active layer 21, the second active layer 22, and the fourth active layer 24 may be located on one side of the third active layer 23 in the first direction X or on the opposite side of the first direction X. The second active layer 22 may be located on one side of the first active layer 21 in the second direction Y, and the fourth active layer 24 may be located on one side of the second active layer 22 in the second direction Y, that is, the first active layer 21 and the fourth active layer 24 may be located on opposite sides of the second active layer 22 in the second direction Y.

[0175] In an exemplary embodiment, the fifth active layer 25 may be located on one side of the third active layer 23 in the second direction Y, and the sixth active layer 26 may be located on one side of the fifth active layer 25 in the second direction Y.

[0176] In an exemplary embodiment, the first active layer 21 to the fifth active layer 25 can be a strip shape extending along the second direction Y, and the sixth active layer 26 can be an "L" shape.

[0177] In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first and second regions. In an exemplary embodiment, the first region 21-1 of the first active layer and the first region 22-1 of the second active layer may be interconnected, and the first region 21-1 of the first active layer may serve as the first region 22-1 of the second active layer. The second region 22-2 of the second active layer and the second region 24-2 of the fourth active layer may be interconnected, and the second region 22-2 of the second active layer may serve as the second region 24-2 of the fourth active layer. The second region 23-2 of the third active layer and the first region 25-1 of the fifth active layer may be interconnected, and the second region 23-2 of the third active layer may serve as the first region 25-1 of the fifth active layer. The second region 25-2 of the fifth active layer and the second region 26-2 of the sixth active layer may be interconnected, and the second region 25-2 of the fifth active layer may serve as the second region 26-2 of the sixth active layer. The second zone 21-2 of the first active layer, the first zone 23-1 of the third active layer, the first zone 24-1 of the fourth active layer, and the first zone 26-1 of the sixth active layer can be set individually.

[0178] In some possible embodiments, the first region of the first active layer and the first region of the second active layer can be set separately, that is, the first region of the first active layer and the first region of the second active layer are not connected, so as to realize that the first region of the first active layer and the first region of the second active layer are connected to different initial signal lines. This disclosure does not limit this.

[0179] In an exemplary embodiment, in at least one cell row, the first region 23-1 of the third active layer in some adjacent circuit cells can be interconnected, and the third active layers 23 of two adjacent circuit cells can be an integral structure interconnected. For example, the third active layers 23 in the N+1 cell column and the third active layers 23 in the N+2 cell column can be an integral structure interconnected, and the two adjacent circuit cells share the same first region 23-1 of the third active layer. Similarly, the third active layers 23 in the N+4 cell column and the third active layers 23 in the N+5 cell column can be an integral structure interconnected, and the two adjacent circuit cells share the same first region 23-1 of the third active layer. By setting some adjacent circuit cells to share the first region of the third active layer (i.e., the first electrode of the third transistor T3), this disclosure can effectively reduce the lateral wiring space, reduce the number of vias, and reduce the area occupied by the pixel driving circuit, which is beneficial for achieving high resolution.

[0180] In an exemplary embodiment, in at least one cell row, the first region 26-1 of the sixth active layer in some adjacent circuit cells can be interconnected, and the sixth active layers 26 of two adjacent circuit cells can be an integral structure interconnected. For example, the sixth active layers 26 in the (N-1)th cell column and the sixth active layers 26 in the Nth cell column can be an integral structure interconnected, and the two adjacent circuit cells share the same first region 26-1 of the sixth active layer. The sixth active layers 26 in the N+2th cell column and the sixth active layers 26 in the N+3th cell column can be an integral structure interconnected, and the two adjacent circuit cells share the same first region 26-1 of the sixth active layer. As another example, the sixth active layers 26 in the N+5th cell column and the sixth active layers 26 in the N+6th cell column can be an integral structure interconnected, and the two adjacent circuit cells share the same first region 26-1 of the sixth active layer. This disclosure effectively reduces the lateral wiring space, the number of vias, and the area occupied by the pixel driving circuit by setting some adjacent circuit units to share the first region of the sixth active layer (i.e., the first pole of the sixth transistor T6), which is beneficial to achieving high resolution.

[0181] In an exemplary embodiment, the first region 21-1 of the first active layer can serve as the first electrode of the first transistor T1, the second region 21-2 of the first active layer can serve as the second electrode of the first transistor T1, the first region 22-1 of the second active layer can serve as the first electrode of the second transistor T2, the second region 22-2 of the second active layer can serve as the second electrode of the second transistor T2, the first region 23-1 of the third active layer can serve as the first electrode of the third transistor T3, the second region 23-2 of the third active layer can serve as the second electrode of the third transistor T3, the first region 24-1 of the fourth active layer can serve as the first electrode of the fourth transistor T4, the second region 24-2 of the fourth active layer can serve as the second electrode of the fourth transistor T4, the first region 25-1 of the fifth active layer can serve as the first electrode of the fifth transistor T5, the second region 25-2 of the fifth active layer can serve as the second electrode of the fifth transistor T5, the first region 26-1 of the sixth active layer can serve as the first electrode of the sixth transistor T6, and the second region 26-2 of the sixth active layer can serve as the second electrode of the sixth transistor T6.

[0182] In an exemplary embodiment, the orthographic projection of the third active layer 23 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate 12 on the substrate, and the second electrode plate 12 can also serve as the bottom gate electrode of the third transistor T3.

[0183] In exemplary embodiments, the semiconductor layers in some adjacent cell columns may be substantially identical. For example, the shapes and positions of the first active layers 21 to the sixth active layers 26 in the Nth and N+3th cell columns may be substantially identical. Similarly, the shapes and positions of the first active layers 21 to the sixth active layers 26 in the N+1th and N+4th cell columns may be substantially identical. Furthermore, the shapes and positions of the first active layers 21 to the sixth active layers 26 in the N+2th and N+5th cell columns may be substantially identical.

[0184] In an exemplary embodiment, the semiconductor layers in some adjacent cell columns may be mirror-symmetric with respect to the column center line. For example, the first active layer 21 to the sixth active layer 26 in the N+1 and N+2 cell columns may be mirror-symmetric with respect to the column center line. Similarly, the semiconductor layers in the N+4 and N+5 cell columns may be mirror-symmetric with respect to the column center line.

[0185] In an exemplary embodiment, the semiconductor layer can be an oxide layer, i.e., the first transistor T1 to the sixth transistor T6 are oxide transistors. Oxide transistors have advantages such as high electron mobility, low operating voltage, and low leakage current. In an exemplary embodiment, the semiconductor layer can be indium gallium zinc oxide (IGZO).

[0186] (14) Forming a third conductive layer pattern. In an exemplary embodiment, forming a third conductive layer pattern may include: sequentially depositing a third insulating film and a third conductive film on a substrate on which the aforementioned pattern is formed; patterning the third conductive film using a patterning process to form a third insulating layer covering the semiconductor layer pattern; and a third conductive layer pattern disposed on the third insulating layer, as shown in Figures 12A and 12B, where Figure 12B is a schematic diagram of the third conductive layer in Figure 12A. In an exemplary embodiment, the third conductive layer may be referred to as a third gate metal (GATE3) layer.

[0187] In an exemplary embodiment, the third conductive layer pattern of each circuit unit in the display substrate includes at least: a first gate electrode 31, a second gate electrode 32, a third gate electrode 33, a fourth gate electrode 34, a sixth gate electrode 36, and a first light-emitting signal line 41.

[0188] In an exemplary embodiment, the first gate electrode 31 may be block-shaped (such as rectangular), and the orthographic projection of the first gate electrode 31 on the substrate at least partially overlaps with the orthographic projection of the first active layer on the substrate. The first gate electrode 31 may serve as the gate electrode of the first transistor T1.

[0189] In an exemplary embodiment, in at least one cell row, the first gate electrodes 31 in some adjacent circuit cells can be interconnected, and the first gate electrodes 31 of two circuit cells can be an integrally connected structure. For example, the first gate electrodes 31 in the (N-1)th cell column and the first gate electrodes 31 in the Nth cell column can be an integrally connected structure. Similarly, the first gate electrodes 31 in the N+2th cell column and the first gate electrodes 31 in the N+3th cell column can be an integrally connected structure. Furthermore, the first gate electrodes 31 in the N+5th cell column and the first gate electrodes 31 in the N+6th cell column can be an integrally connected structure. By setting the first gate electrodes 31 in some adjacent circuit cells to an integrally connected structure, this disclosure can effectively reduce wiring space, reduce the number of vias, and reduce the area occupied by the pixel driving circuit, which is beneficial for achieving high resolution.

[0190] In an exemplary embodiment, the second gate electrode 32 may be block-shaped (such as rectangular) and may be disposed on one side of the first gate electrode 31 in the second direction Y. The orthographic projection of the second gate electrode 32 on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate. The second gate electrode 32 may serve as the gate electrode of the second transistor T2.

[0191] In an exemplary embodiment, in at least one cell row, the second gate electrodes 32 in some adjacent circuit cells can be interconnected, and the second gate electrodes 32 of two circuit cells can be an integrally connected structure. For example, the second gate electrodes 32 in the (N-1)th cell column and the second gate electrodes 32 in the Nth cell column can be an integrally connected structure. Similarly, the second gate electrodes 32 in the N+2th cell column and the second gate electrodes 32 in the N+3th cell column can be an integrally connected structure. Furthermore, the second gate electrodes 32 in the N+5th cell column and the second gate electrodes 32 in the N+6th cell column can be an integrally connected structure. By setting the second gate electrodes 32 in some adjacent circuit cells to an integrally connected structure, this disclosure can effectively reduce wiring space, reduce the number of vias, and reduce the area occupied by the pixel driving circuit, which is beneficial for achieving high resolution.

[0192] In an exemplary embodiment, the third gate electrode 33 may be block-shaped (such as rectangular) and may be disposed on one side of the first gate electrode 31 in the first direction X. The orthographic projection of the third gate electrode 33 on the substrate at least partially overlaps with the orthographic projection of the third active layer on the substrate. The third gate electrode 33 may serve as the top gate electrode of the third transistor T3.

[0193] In an exemplary embodiment, the fourth gate electrode 34 may be block-shaped (e.g., rectangular) and may be disposed on one side of the second gate electrode 32 in the second direction Y. The orthographic projection of the fourth gate electrode 34 on the substrate at least partially overlaps with the orthographic projection of the fourth active layer on the substrate. The fourth gate electrode 34 may serve as the gate electrode of the fourth transistor T4.

[0194] In an exemplary embodiment, the sixth gate electrode 36 may be block-shaped (e.g., rectangular) and may be disposed on one side of the fourth gate electrode 34 in the second direction Y. The orthographic projection of the sixth gate electrode 36 on the substrate at least partially overlaps with the orthographic projection of the sixth active layer on the substrate. The sixth gate electrode 36 may serve as the gate electrode of the sixth transistor T6.

[0195] In an exemplary embodiment, in at least one cell row, the sixth gate electrodes 36 in some adjacent circuit cells can be interconnected via gate connecting strips 36-1, and the two fourth gate electrodes 34 of two circuit cells and the gate connecting strips 36-1 can be an integrally connected structure. For example, the sixth gate electrodes 36 in the (N-1)th cell column and the sixth gate electrodes 36 in the Nth cell column can form an integrally connected structure via gate connecting strips 36-1. Similarly, the sixth gate electrodes 36 in the N+2th cell column and the sixth gate electrodes 36 in the N+3th cell column can form an integrally connected structure via gate connecting strips 36-1. Furthermore, the sixth gate electrodes 36 in the N+5th cell column and the sixth gate electrodes 36 in the N+6th cell column can form an integrally connected structure via gate connecting strips 36-1. By setting the sixth gate electrodes 36 in some adjacent circuit cells to be interconnected via gate connecting strips 36-1, this disclosure can effectively reduce wiring space, reduce the number of vias, and reduce the area occupied by the pixel driving circuit, which is beneficial for achieving high resolution.

[0196] In an exemplary embodiment, the shape of the first light-emitting signal line 41 can be a straight line or a broken line extending along the first direction X, and it can be disposed between the fourth gate electrode 34 and the sixth gate electrode 36. The orthographic projection of the first light-emitting signal line 41 on the substrate and the orthographic projection of the fifth active layer 25 on the substrate at least partially overlap. The overlapping area can serve as the gate electrode of the fifth transistor T5, thus realizing that the first light-emitting signal line 41 can control the conduction or disconnection of the fifth transistor T5.

[0197] In an exemplary embodiment, the first light-emitting signal line 41 can be a variable-width polygonal line structure, and the width of the first light-emitting signal line is the dimension of the second direction Y. The first light-emitting signal line 41 may include a first region that overlaps with the fifth active layer 25 and a second region that does not overlap with the fifth active layer 25, and the width of the first region may be greater than the width of the second region.

[0198] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first light-emitting signal line 41 on the substrate does not overlap with the orthographic projections of the first electrode plate 11, the second electrode plate 12, the third electrode plate 13, and the fourth electrode plate 14 on the substrate.

[0199] In exemplary embodiments, the third conductive layer in some adjacent cell columns may be substantially identical. For example, the shape and position of the first gate electrode 31 to the fourth gate electrode 34, the sixth gate electrode 36, and the first light-emitting signal line 41 in the Nth and N+3rd cell columns may be substantially identical. Similarly, the shape and position of the first gate electrode 31 to the fourth gate electrode 34, the sixth gate electrode 36, and the first light-emitting signal line 41 in the N+1th and N+4th cell columns may be substantially identical. Furthermore, the shape and position of the first gate electrode 31 to the fourth gate electrode 34, the sixth gate electrode 36, and the first light-emitting signal line 41 in the N+2th and N+5th cell columns may be substantially identical.

[0200] In an exemplary embodiment, the third conductive layer in some adjacent cell columns may be mirror-symmetrical with respect to the column center line. For example, the first gate electrode 31 to the fourth gate electrode 34, the sixth gate electrode 36, and the first light-emitting signal line 41 in the (N-1)th and N+1th cell columns may be mirror-symmetrical with respect to the column center line. Similarly, the first gate electrode 31 to the fourth gate electrode 34, the sixth gate electrode 36, and the first light-emitting signal line 41 in the N+2th and N+3th cell columns may be mirror-symmetrical with respect to the column center line. Furthermore, the first gate electrode 31 to the fourth gate electrode 34, the sixth gate electrode 36, and the first light-emitting signal line 41 in the N+5th and N+6th cell columns may be mirror-symmetrical with respect to the column center line.

[0201] (15) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming a fourth insulating layer pattern may include: depositing a fourth insulating film on a substrate on which the aforementioned pattern is formed, and patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the third conductive layer, wherein a plurality of vias are provided on the fourth insulating layer, as shown in FIG13.

[0202] In an exemplary embodiment, the plurality of vias in each circuit unit of the display substrate include at least: a first via V1 to an eighteenth via V18.

[0203] In an exemplary embodiment, the orthographic projection of the first via V1 onto the substrate is within the range of the orthographic projection of the first region of the first active layer (which is also the first region of the second active layer) onto the substrate. The third and fourth insulating layers within the first via V1 are etched away, exposing the surface of the first region of the first active layer (which is also the first region of the second active layer). The first via V1 is configured to allow a subsequently formed first initial signal line to be connected to the first region of the first active layer (which is also the first region of the second active layer) through the via.

[0204] In an exemplary embodiment, the orthographic projection of the second via V2 onto the substrate is within the range of the orthographic projection of the second region of the first active layer onto the substrate. The third and fourth insulating layers within the second via V2 are etched away, exposing the surface of the second region of the first active layer. The second via V2 is configured to allow a subsequently formed first connection electrode to be connected to the second region of the first active layer through the via.

[0205] In an exemplary embodiment, the orthographic projection of the third via V3 onto the substrate is within the range of the orthographic projection of the second region of the second active layer (which is also the second region of the fourth active layer) onto the substrate. The third and fourth insulating layers within the third via V3 are etched away, exposing the surface of the second region of the second active layer (which is also the second region of the fourth active layer). The third via V3 is configured to allow a subsequently formed third connection electrode to be connected to the second region of the second active layer (which is also the second region of the fourth active layer) through the via.

[0206] In an exemplary embodiment, the orthographic projection of the fourth via V4 onto the substrate lies within the orthographic projection of the first region of the third active layer onto the substrate. The third and fourth insulating layers within the fourth via V4 are etched away, exposing the surface of the first region of the third active layer. The fourth via V4 is configured to allow subsequently formed power connection lines to connect to the first region of the third active layer through this via. Since two partially adjacent circuit units share the same first region of the third active layer, they can share the same fourth via V4, effectively reducing the number of vias and decreasing the footprint of the pixel driving circuit, which is beneficial for achieving high resolution.

[0207] In an exemplary embodiment, the orthographic projection of the fifth via V5 onto the substrate is located within the range of the orthographic projection of the second region of the third active layer (which is also the first region of the fifth active layer) onto the substrate. The third and fourth insulating layers within the fifth via V5 are etched away, exposing the surface of the second region of the third active layer (which is also the first region of the fifth active layer). The fifth via V5 is configured to allow a subsequently formed second connection electrode to be connected to the second region of the third active layer (which is also the first region of the fifth active layer) through the via.

[0208] In an exemplary embodiment, the orthographic projection of the sixth via V6 onto the substrate is within the range of the orthographic projection of the first region of the fourth active layer onto the substrate. The third and fourth insulating layers within the sixth via V6 are etched away, exposing the surface of the first region of the fourth active layer. The sixth via V6 is configured to allow a subsequently formed fifth connection electrode to be connected to the first region of the fourth active layer through the via.

[0209] In an exemplary embodiment, the orthographic projection of the seventh via V7 onto the substrate is within the range of the orthographic projection of the second region of the fifth active layer (which is also the second region of the sixth active layer) onto the substrate. The third and fourth insulating layers within the seventh via V7 are etched away, exposing the surface of the second region of the fifth active layer (which is also the second region of the sixth active layer). The seventh via V7 is configured to allow the subsequently formed sixth connection electrode to be connected to the second region of the fifth active layer (which is also the second region of the sixth active layer) through the via.

[0210] In an exemplary embodiment, the orthographic projection of the eighth via V8 onto the substrate lies within the orthographic projection of the first region of the sixth active layer onto the substrate. The third and fourth insulating layers within the eighth via V8 are etched away, exposing the surface of the first region of the sixth active layer. The eighth via V8 is configured to allow a subsequently formed second initial signal line to connect to the first region of the sixth active layer through this via. Since two partially adjacent circuit units share the same first region of the sixth active layer, they can share the same eighth via V8, effectively reducing the number of vias and decreasing the footprint of the pixel driving circuit, which is beneficial for achieving high resolution.

[0211] In an exemplary embodiment, the orthographic projection of the ninth via V9 onto the substrate is within the range of the orthographic projection of the second region of the third active layer onto the substrate. The third and fourth insulating layers within the ninth via V9 are etched away, exposing the surface of the second region of the third active layer. The ninth via V9 is configured to allow a subsequently formed fourth connection electrode to be connected to the second region of the third active layer through the via.

[0212] In an exemplary embodiment, the orthographic projection of the tenth via V10 onto the substrate lies within the range of the orthographic projection of the first gate electrode 31 onto the substrate. The fourth insulating layer within the tenth via V10 is etched away, exposing the surface of the first gate electrode 31. The tenth via V10 is configured to allow the subsequently formed first scan signal line to connect to the first gate electrode 31 through this via. Since the first gate electrodes 31 in two partially adjacent circuit units are interconnected as a single structure, the two partially adjacent circuit units can share the tenth via V10, effectively reducing the number of vias and decreasing the area occupied by the pixel driving circuit, which is beneficial for achieving high resolution.

[0213] In an exemplary embodiment, the orthogonal projection of the eleventh via V11 onto the substrate lies within the range of the orthogonal projection of the second gate electrode 32 onto the substrate. The fourth insulating layer within the eleventh via V11 is etched away, exposing the surface of the second gate electrode 32. The eleventh via V11 is configured to allow the subsequently formed third scan signal line to connect to the second gate electrode 32 through this via. Due to the integrated structure where the second gate electrodes 32 in two partially adjacent circuit units are interconnected, two partially adjacent circuit units can share the eleventh via V11, effectively reducing the number of vias and decreasing the area occupied by the pixel driving circuit, which is beneficial for achieving high resolution.

[0214] In an exemplary embodiment, the orthogonal projection of the twelfth via V12 onto the substrate is within the range of the orthogonal projection of the third gate electrode 33 onto the substrate. The fourth insulating layer within the twelfth via V12 is etched away, exposing the surface of the third gate electrode 33. The twelfth via V12 is configured to allow the subsequently formed first connection electrode to be connected to the third gate electrode 33 through the via.

[0215] In an exemplary embodiment, the orthogonal projection of the thirteenth via V13 onto the substrate is within the range of the orthogonal projection of the fourth gate electrode 34 onto the substrate. The fourth insulating layer within the thirteenth via V13 is etched away, exposing the surface of the fourth gate electrode 34. The thirteenth via V13 is configured to allow the subsequently formed fourth scan signal line to be connected to the fourth gate electrode 34 through the via.

[0216] In an exemplary embodiment, the orthogonal projection of the fourteenth via V14 onto the substrate lies within the range of the orthogonal projection of the sixth gate electrode 36 onto the substrate. The fourth insulating layer within the fourteenth via V14 is etched away, exposing the surface of the sixth gate electrode 36. The fourteenth via V14 is configured to allow the subsequently formed second scan signal line to connect to the sixth gate electrode 36 through this via. Since the sixth gate electrodes 36 of two partially adjacent circuit units can be interconnected through the gate connection strip 36-1, only one fourteenth via V14 needs to be provided for two partially adjacent circuit units, effectively reducing the number of vias and reducing the area occupied by the pixel driving circuit, which is beneficial for achieving high resolution.

[0217] In an exemplary embodiment, the orthographic projection of the fifteenth via V15 on the substrate is located within the range of the orthographic projection of the first electrode plate connecting block 11-1 of the first electrode plate 11 on the substrate. The fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer in the fifteenth via V15 are etched away, exposing the surface of the first electrode plate connecting block 11-1. The fifteenth via V15 is configured to allow the subsequently formed first connection electrode to be connected to the first electrode plate connecting block 11-1 through the via.

[0218] In an exemplary embodiment, the orthographic projection of the sixteenth via V16 on the substrate is within the range of the orthographic projection of the second electrode connecting block 13-1 of the third electrode plate 13 on the substrate. The fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer in the sixteenth via V16 are etched away, exposing the surface of the second electrode connecting block 13-1. The sixteenth via V16 is configured to allow the subsequently formed second connection electrode to be connected to the second electrode connecting block 13-1 through the via.

[0219] In an exemplary embodiment, the orthographic projection of the seventeenth via V17 on the substrate is within the range of the orthographic projection of the second electrode plate 12 on the substrate. The fourth insulating layer, the third insulating layer and the second insulating layer in the seventeenth via V17 are etched away to expose the surface of the second electrode plate 12. The seventeenth via V17 is configured to allow the subsequently formed fourth connection electrode to be connected to the second electrode plate 12 through the via.

[0220] In an exemplary embodiment, the orthographic projection of the eighteenth via V18 on the substrate is within the range of the orthographic projection of the fourth electrode plate 14 on the substrate. The fourth insulating layer, the third insulating layer and the second insulating layer in the eighteenth via V18 are etched away to expose the surface of the fourth electrode plate 14. The eighteenth via V18 is configured to allow the subsequently formed third connection electrode to be connected to the fourth electrode plate 14 through the via.

[0221] (16) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on a substrate on which the aforementioned pattern is formed, and patterning the fourth conductive film using a patterning process to form a fourth conductive layer disposed on a fourth insulating layer, as shown in Figures 14A and 14B, where Figure 14B is a planar schematic diagram of the fourth conductive layer in Figure 14A. In an exemplary embodiment, the fourth conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0222] In an exemplary embodiment, the fourth conductive layer of each circuit unit in the display substrate includes at least: a first connection electrode 51 to a sixth connection electrode 56, a first scan signal line 61 to a fourth scan signal line 64, a first power connection line 65, a second power connection line 66, a first initial signal line 71, and a second initial signal line 72.

[0223] In an exemplary embodiment, the first connecting electrode 51 can be L-shaped. The first end of the first connecting electrode 51 is connected to the third gate electrode 33 through the twelfth via V12, and the second end is connected to the first electrode plate connecting block 11-1 through the fifteenth via V15. The portion between the first end and the second end is connected to the second region of the first active layer through the second via V2. Since the first electrode plate connecting block 11-1 is connected to the first electrode plate 11, the first connecting electrode 51 realizes the connection between the second electrode of the first transistor T1, the gate electrode of the third transistor T3, and the first end (first electrode plate 11) of the first capacitor C1, forming the first node N1 of the pixel driving circuit, that is, the first electrode plate 11, the gate electrode of the third transistor T3, and the first connecting electrode 51 have the potential of the first node.

[0224] In an exemplary embodiment, the second connecting electrode 52 can be a strip extending along the first direction X. The first end of the second connecting electrode 52 is connected to the second region of the third active layer (which is also the first region of the fifth active layer) through the fifth via V5, and the second end of the second connecting electrode 52 is connected to the second electrode plate connecting block 13-1 through the sixteenth via V16. Since the second electrode plate connecting block 13-1 is connected to the third electrode plate 13, the second connecting electrode 52 realizes the connection between the second electrode of the third transistor T3, the first electrode of the fifth transistor T5, and the second end of the second capacitor C2 (the third electrode plate 13), forming a partial second node N2 of the pixel driving circuit, that is, the second connecting electrode 52 and the third electrode plate 13 have the potential of the second node.

[0225] In an exemplary embodiment, the third connecting electrode 53 can be a strip extending along the first direction X. The first end of the third connecting electrode 53 is connected to the second region of the second active layer (which is also the second region of the fourth active layer) through the third via V3, and the second end of the third connecting electrode 53 is connected to the fourth electrode plate 14 through the eighteenth via V18. The third connecting electrode 53 realizes the interconnection between the second electrode of the second transistor T2, the second electrode of the fourth transistor T4, and the first end of the second capacitor C2 (the fourth electrode plate 14), forming the third node N3 of the pixel driving circuit, that is, the third connecting electrode 53 and the fourth electrode plate 14 have the potential of the third node.

[0226] In an exemplary embodiment, the fourth connecting electrode 54 can be a strip extending along the first direction X. The first end of the fourth connecting electrode 54 is connected to the second region of the third active layer through the ninth via V9, and the second end of the fourth connecting electrode 54 is connected to the second electrode plate 12 through the seventeenth via V17. The fourth connecting electrode 54 realizes the connection between the second electrode of the third transistor T3 and the second end (second electrode plate 12) of the first capacitor C1, forming a partial second node N2 of the pixel driving circuit, that is, the fourth connecting electrode 54 and the second electrode plate 12 have the potential of the second node.

[0227] In an exemplary embodiment, the second connecting electrode 52 and the fourth connecting electrode 54 together form the second node N2 of the pixel driving circuit, and the second electrode plate 12, the third electrode plate 13, the second connecting electrode 52 and the fourth connecting electrode 54 have the potential of the second node.

[0228] In an exemplary embodiment, since the first electrode plate 11 has a potential of a first node and the second electrode plate 12 has a potential of a second node, the first electrode plate 11 having a potential of a first node and the second electrode plate 12 having a potential of a second node form the first capacitor C1 of the pixel driving circuit.

[0229] In an exemplary embodiment, since the third electrode plate 13 has the potential of the second node and the fourth electrode plate 14 has the potential of the third node, the third electrode plate 13 having the potential of the second node and the fourth electrode plate 14 having the potential of the third node form the second capacitor C2 of the pixel driving circuit.

[0230] In an exemplary embodiment, since the second electrode 12 also serves as the bottom gate electrode of the third transistor T3, the bottom gate electrode of the third transistor T3 has the potential of the second node of the pixel driving circuit.

[0231] In an exemplary embodiment, the fifth connection electrode 55 may be block-shaped (e.g., rectangular), and the fifth connection electrode 55 is connected to the first region of the fourth active layer through the sixth via V6. The fifth connection electrode 55 is configured to be connected to a subsequently formed data signal line.

[0232] In an exemplary embodiment, the sixth connection electrode 56 may be block-shaped (e.g., rectangular), and the sixth connection electrode 56 is connected to the second region of the fifth active layer (which is also the second region of the sixth active layer) through the seventh via V7. The sixth connection electrode 56 is configured to be connected to the subsequently formed anode connection electrode.

[0233] In an exemplary embodiment, the shape of the first scan signal line 61 can be a straight line or a broken line extending along the first direction X, and it can be continuously arranged in a unit row. The orthographic projection of the first scan signal line 61 on the substrate at least partially overlaps with the orthographic projection of the first gate electrode 31 on the substrate. The first scan signal line 61 is connected to the first gate electrode 31 in each circuit unit through the tenth via V10, thereby realizing the connection between the first scan signal line 61 and the gate electrode of the first transistor T1 in each circuit unit. The first scan signal line 61 can control the conduction or disconnection of the first transistor T1.

[0234] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first scan signal line 61 onto the substrate at least partially overlaps with the orthographic projections of the first electrode plate 11 and the second electrode plate 12 onto the substrate. In the direction perpendicular to the display substrate, since the second electrode plate 12 is disposed between the first electrode plate 11 and the first scan signal line 61, the second electrode plate 12 can effectively shield the overlapping capacitance between the first electrode plate 11 (first node N1) and the first scan signal line 61, thereby effectively reducing the parasitic capacitance of the first node N1.

[0235] In an exemplary embodiment, the shape of the second scan signal line 62 can be a straight line or a broken line extending along the first direction X, and it can be continuously arranged in a unit row. The orthographic projection of the second scan signal line 62 on the substrate at least partially overlaps with the orthographic projection of the sixth gate electrode 36 on the substrate. The second scan signal line 62 is connected to the sixth gate electrode 36 in each circuit unit through the fourteenth via V14, thus realizing the connection between the second scan signal line 62 and the gate electrode of the sixth transistor T6 in each circuit unit. The second scan signal line 62 can control the conduction or disconnection of the sixth transistor T6.

[0236] In an exemplary embodiment, the shape of the third scan signal line 63 can be a straight line or a broken line extending along the first direction X, and it can be continuously arranged in a unit row. The orthographic projection of the third scan signal line 63 on the substrate at least partially overlaps with the orthographic projection of the second gate electrode 32 on the substrate. The third scan signal line 63 is connected to the second gate electrode 32 in each circuit unit through the eleventh via V11, thus realizing the connection between the third scan signal line 63 and the gate electrode of the second transistor T2. The third scan signal line 63 can control the conduction or disconnection of the second transistor T2.

[0237] In an exemplary embodiment, the shape of the fourth scan signal line 64 can be a straight line or a broken line extending along the first direction X, and it can be continuously arranged in a unit row. The orthographic projection of the fourth scan signal line 64 on the substrate at least partially overlaps with the orthographic projection of the fourth gate electrode 34 on the substrate. The fourth scan signal line 64 is connected to the fourth gate electrode 34 in each circuit unit through the thirteenth via V13, thereby realizing the connection between the fourth scan signal line 64 and the gate electrode of the fourth transistor T4 in each circuit unit. The fourth scan signal line 64 can control the conduction or disconnection of the fourth transistor T4.

[0238] This embodiment of the present disclosure, by placing the first scan signal line 61 to the fourth scan signal line 64 in the fourth conductive layer, can effectively reduce the resistance of the scan signal line, reduce the voltage drop of the scan signal, and improve the driving quality, display quality, and display quality.

[0239] In an exemplary embodiment, the shape of the first power connection line 65 can be a straight line or a broken line extending along the first direction X, and can be continuously arranged in a cell row. The first power connection line 65 is connected to the first region of the third active layer in each circuit cell through the fourth via V4. The first power connection line 65 is configured to connect to the subsequently formed first power line, thereby enabling the first power line to write the first power signal into the first terminal of the third transistor T3 in each circuit cell.

[0240] In an exemplary embodiment, a first power connection block 65-1 may be provided on the first power connection line 65. The first power connection block 65-1 may be block-shaped (e.g., rectangular) and connected to the first power connection line 65. The first power connection block 65-1 is configured to connect to a subsequently formed first power line. In an exemplary embodiment, the first power connection block 65-1 may be provided in the circuit unit of each unit column.

[0241] In an exemplary embodiment, the second power connection line 66 can be a straight line or a broken line extending along the first direction X, and can be continuously arranged in a unit row. A second power connection block 66-1 can be provided on the second power connection line 66. The second power connection block 66-1 can be block-shaped (e.g., rectangular) and connected to the second power connection line 66. The second power connection block 66-1 is configured to connect to a subsequently formed second power line. In an exemplary embodiment, the second power connection block 66-1 can be disposed in the circuit units of the N+1, N+2, N+4, and N+5 unit columns.

[0242] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the second power connection line 66 on the substrate at least partially overlaps with the orthographic projections of the first electrode plate 11 and the second electrode plate 12 on the substrate. In the direction perpendicular to the display substrate, since the second electrode plate 12 is disposed between the first electrode plate 11 and the second power connection line 66, the second electrode plate 12 can effectively shield the overlapping capacitance between the first electrode plate 11 (first node N1) and the second power connection line 66, thereby effectively reducing the parasitic capacitance of the first node N1.

[0243] In an exemplary embodiment, the shape of the first initial signal line 71 can be a straight line or a broken line extending along the first direction X, and it can be continuously arranged in a cell row. The first initial signal line 71 is connected to the first region of the first active layer (which is also the first region of the second active layer) in each circuit cell through the first via V1. The first initial signal line 71 enables the simultaneous writing of the first initial signal to the first terminal of the first transistor T1 and the first terminal of the second transistor T2 in each circuit cell.

[0244] In some possible embodiments, the first region of the first active layer and the first region of the second active layer can be set separately, and the fourth conductive layer may also include a third initial signal line. The first initial signal line is connected to the first region of the first active layer through a via, and the third initial signal line is connected to the first region of the second active layer through a via. This disclosure does not limit the scope of the invention.

[0245] In an exemplary embodiment, a first initial connection block 71-1 may be provided on the first initial signal line 71. The first initial connection block 71-1 may be block-shaped (such as rectangular), and may be provided on the side of the first initial signal line 71 close to the first scan signal line 61 and connected to the first initial signal line 71. The first initial connection block 71-1 is configured to connect to the subsequently formed first initial connection line.

[0246] In an exemplary embodiment, the first initial connection block 71-1 may be disposed between the N+1th and N+2th unit columns, and between the N+4th and N+5th unit columns. In at least one unit row, the first initial signal line 71 and the plurality of first initial connection blocks 71-1 may be an integral structure interconnected with each other.

[0247] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first initial signal line 71 onto the substrate at least partially overlaps with the orthographic projections of the first electrode 11 and the second electrode 12 onto the substrate. In the direction perpendicular to the display substrate, since the second electrode 12 is disposed between the first electrode 11 and the first initial signal line 71, the second electrode 12 can effectively shield the overlapping capacitance between the first electrode 11 (first node N1) and the first initial signal line 71, thereby effectively reducing the parasitic capacitance of the first node N1.

[0248] In an exemplary embodiment, the shape of the second initial signal line 72 can be a straight line or a broken line extending along the first direction X, and can be continuously arranged in a cell row. The second initial signal line 72 is connected to the first region of the sixth active layer in each circuit cell through the eighth via V8, thereby enabling the second initial signal line 72 to write the second initial signal into the first terminal of the sixth transistor T6 in each circuit cell.

[0249] In an exemplary embodiment, a second initial connection block 72-1 may be provided on the second initial signal line 72. The second initial connection block 72-1 may be block-shaped (such as rectangular) and connected to the second initial signal line 72. The second initial connection block 72-1 is configured to connect to the second initial connection line formed subsequently.

[0250] In an exemplary embodiment, the second initial connection block 72-1 may be disposed in the Nth and N+3th cell columns. In at least one cell row, the second initial signal line 72 and the plurality of second initial connection blocks 72-1 may be an integral structure interconnected with each other.

[0251] In an exemplary embodiment, in at least one circuit unit, the first power connection line 65 and the second power connection line 66 may be located on the side opposite to the second direction Y of the third gate electrode 33, and the first scan signal line 61, the second scan signal line 62, the third scan signal line 63, the fourth scan signal line 64, the first initial signal line 71 and the second initial signal line 72 may be located on the side of the second direction Y of the third gate electrode 33.

[0252] In an exemplary embodiment, in at least one circuit unit, the first power connection line 65 may be located on the side of the second power connection line 66 away from the third gate electrode 33. The first scan signal line 61 may be located on the side of the third gate electrode 33 in the second direction Y, the first initial signal line 71 may be located on the side of the first scan signal line 61 away from the third gate electrode 33, the third scan signal line 63 may be located on the side of the first initial signal line 71 away from the third gate electrode 33, the fourth scan signal line 64 may be located on the side of the third scan signal line 63 away from the third gate electrode 33, the second scan signal line 62 may be located on the side of the fourth scan signal line 64 away from the third gate electrode 33, and the second initial signal line 72 may be located on the side of the second scan signal line 62 away from the third gate electrode 33.

[0253] In an exemplary embodiment, in at least one circuit unit, the first light-emitting signal line 41 may be located between the second scan signal line 62 and the fourth scan signal line 64.

[0254] In an exemplary embodiment, the fourth conductive layer in some adjacent cell columns may be substantially identical. For example, the shape and position of the fourth conductive layer in the Nth cell column and the (N+3)th cell column may be substantially identical. Similarly, the shape and position of the fourth conductive layer in the (N+1)th cell column and the (N+4)th cell column may be substantially identical. Furthermore, the shape and position of the fourth conductive layer in the (N+2)th cell column and the (N+5)th cell column may be substantially identical.

[0255] In an exemplary embodiment, the fourth conductive layer in some adjacent cell columns may be mirror-symmetrical with respect to the column center line. For example, the fourth conductive layers in the (N+1)th and (N+2)th cell columns may be mirror-symmetrical with respect to the column center line. Similarly, the fourth conductive layers in the (N+2)th and (N+3)th cell columns may be mirror-symmetrical with respect to the column center line. Furthermore, the fourth conductive layers in the (N+4)th and (N+5)th cell columns may be mirror-symmetrical with respect to the column center line.

[0256] (17) Forming a first planarization layer pattern. In an exemplary embodiment, forming a first planarization layer pattern may include: coating a first planarization film on a substrate on which the aforementioned pattern is formed, and patterning the first planarization film using a patterning process to form a first planarization layer covering the pattern of the fourth conductive layer, wherein a plurality of vias are provided on the first planarization layer, as shown in FIG15.

[0257] In an exemplary embodiment, the plurality of vias in each circuit unit of the display substrate include at least: a twenty-first via V21, a twenty-second via V22, and a twenty-third via V23.

[0258] In an exemplary embodiment, the orthographic projection of the 21st via V21 onto the substrate is within the range of the orthographic projection of the fifth connecting electrode 55 onto the substrate. The first planarization layer within the 21st via V21 is removed, exposing the surface of the fifth connecting electrode 55. The 21st via V21 is configured to allow subsequently formed data signal lines to be connected to the fifth connecting electrode 55 through the via.

[0259] In an exemplary embodiment, the orthographic projection of the 22nd via V22 onto the substrate is within the range of the orthographic projection of the 6th connecting electrode 56 onto the substrate. The first planarization layer within the 22nd via V22 is removed, exposing the surface of the 6th connecting electrode 56. The 22nd via V22 is configured to allow a subsequently formed anode connecting electrode to be connected to the 6th connecting electrode 56 through the via.

[0260] In an exemplary embodiment, the orthographic projection of the 23rd via V23 on the substrate is within the range of the orthographic projection of the first power connection block 65-1 on the substrate on the first power connection line 65. The first planarization layer within the 23rd via V23 is removed, exposing the surface of the first power connection block 65-1. The 23rd via V23 is configured to allow the subsequently formed first power line to be connected to the first power connection block 65-1 through the via.

[0261] In an exemplary embodiment, at least one circuit unit may further include a twenty-fourth via V24. The orthographic projection of the twenty-fourth via V24 onto the substrate lies within the orthographic projection of the second power connection block 66-1 onto the substrate. A first planarization layer within the twenty-fourth via V24 is removed, exposing the surface of the second power connection block 66-1. The twenty-fourth via V24 is configured to allow a subsequently formed second power line to connect to the second power connection block 66-1 through this via. In an exemplary embodiment, the twenty-fourth via V24 may be disposed in circuit units in the N+1, N+2, N+4, and N+5 unit columns.

[0262] In an exemplary embodiment, at least one circuit unit may further include a twenty-fifth via V25. The orthographic projection of the twenty-fifth via V25 onto the substrate lies within the range of the orthographic projection of the first initial connection block 71-1 onto the substrate. A first planarization layer within the twenty-fifth via V25 is removed, exposing the surface of the first initial connection block 71-1. The twenty-fifth via V25 is configured to allow subsequently formed first initial connection lines to connect to the first initial connection block 71-1 through this via. In an exemplary embodiment, the twenty-fifth via V25 may be disposed between the N+1th and N+2th unit columns, and between the N+4th and N+5th unit columns.

[0263] In an exemplary embodiment, at least one circuit unit may further include a second sixteenth via V26. The orthographic projection of the second sixteenth via V26 onto the substrate lies within the orthographic projection of the second initial connection block 72-1 onto the substrate. A first planarization layer within the second sixteenth via V26 is removed, exposing the surface of the second initial connection block 72-1. The second sixteenth via V26 is configured to allow subsequently formed second initial connection lines to connect to the second initial connection block 72-1 through this via. In an exemplary embodiment, the second sixteenth via V26 may be located in the Nth unit column and the N+3th unit column.

[0264] (18) Forming a fifth conductive layer pattern. In an exemplary embodiment, forming the fifth conductive layer may include: depositing a fifth conductive thin film on the substrate on which the aforementioned pattern is formed, and patterning the fifth conductive thin film using a patterning process to form a fifth conductive layer disposed on the first planarization layer, as shown in Figures 16A and 16B, where Figure 16B is a planar schematic diagram of the fifth conductive layer in Figure 16A. In an exemplary embodiment, the fifth conductive layer may be referred to as the second source / drain metal (SD2) layer.

[0265] In an exemplary embodiment, the fifth conductive layer of each circuit unit includes at least: a first power line 81, a data signal line 83, and an anode connection electrode 84.

[0266] In an exemplary embodiment, the shape of the first power line 81 can be a straight line or a broken line extending along the second direction Y of the main body. The first power line 81 is connected to the first power connection block 65-1 through the twenty-third via V23. Since the first power connection block 65-1 is connected to the first power connection line 65, the interconnection between the first power connection line 65 extending along the first direction X of the main body and the first power line 81 extending along the second direction Y of the main body is realized. The first power connection line 65 and the first power line 81 form a mesh-like interconnected structure on the display substrate for transmitting the first power signal. This not only effectively reduces the resistance of the first power line and reduces the voltage drop of the first power signal, but also effectively improves the uniformity of the first power signal in the display substrate, effectively improving display uniformity, and enhancing display quality.

[0267] In an exemplary embodiment, a first power connection line 65 may be provided in each cell row, and a first power line 81 may be provided in each cell column.

[0268] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first power line 81 on the substrate at least partially overlaps with the orthographic projection of the third gate electrode 33 on the substrate, and the first power line 81 with a constant potential can effectively shield the potential of the first node N1.

[0269] In an exemplary embodiment, the first power line 81 can be a variable width structure, and the width of the first power line is the dimension in the first direction X. The first power line 81 may include a first region that overlaps with the gate electrode of the third transistor T3 and a second region that does not overlap with the gate electrode of the third transistor T3, and the width of the first region may be greater than the width of the second region.

[0270] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first power line 81 on the substrate at least partially overlaps with the orthographic projections of the third active layer and the fifth active layer on the substrate. Thus, the first power line 81 can block the third transistor T3 and the fifth transistor T5, preventing the light emitted by the light-emitting device and the reflected light from the film layer from illuminating the oxide third transistor T3 and the fifth transistor T5. This can prevent the oxide transistor from experiencing characteristic drift due to light exposure and improve the electrical characteristics of the oxide transistor.

[0271] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first power line 81 on the substrate at least partially overlaps with the orthographic projections of the first electrode plate 11 and the second electrode plate 12 on the substrate. In the direction perpendicular to the display substrate, since the second electrode plate 12 is disposed between the first electrode plate 11 and the first power line 81, the second electrode plate 12 can effectively shield the overlapping capacitance between the first electrode plate 11 (first node N1) and the first power line 81, thereby effectively reducing the parasitic capacitance of the first node N1.

[0272] In an exemplary embodiment, the data signal line 83 can be a straight line or a broken line extending along the second direction Y in its main body. The data signal line 83 is connected to the fifth connection electrode 55 through the twenty-first via V21. Since the fifth connection electrode 55 is connected to the first region of the fourth active layer through the via, the data signal line 83 can write data signals to the first electrode of the fourth transistor T4.

[0273] In an exemplary embodiment, the orthographic projection of the data signal line 83 on the substrate does not overlap with the orthographic projections of the first electrode plate 11 to the fourth electrode plate 14 and the first connecting electrode 51 to the sixth connecting electrode 56 on the substrate. This can avoid signal crosstalk caused by data voltage jumps in the data signal line, avoid the impact of data voltage jumps on transistors, improve the working stability of the pixel driving circuit, and improve the display effect.

[0274] In an exemplary embodiment, the anode connection electrode 84 can be block-shaped. The anode connection electrode 84 is connected to the sixth connection electrode 56 through the twenty-second via V22, and the anode connection electrode 84 is configured to be connected to the subsequently formed anode. Since the sixth connection electrode 56 is connected to the second region of the fifth active layer (which is also the second region of the sixth active layer) through the via, the pixel driving circuit can output driving current to the light-emitting device.

[0275] In an exemplary embodiment, the fifth conductive layer of at least one circuit unit may further include a second power line 82. The shape of the second power line 82 may be a straight line or a broken line extending along the second direction Y of the main body. The second power line 82 is connected to the second power connection block 66-1 through the twenty-fourth via V24. Since the second power connection block 66-1 is connected to the second power connection line 66, the interconnection between the second power connection line 66 extending along the first direction X of the main body and the second power line 82 extending along the second direction Y of the main body is realized. The second power connection line 66 and the second power line 82 form a mesh-like interconnected structure on the display substrate for transmitting the second power signal. This not only effectively reduces the resistance of the second power line and the voltage drop of the second power signal, but also effectively improves the uniformity of the second power signal in the display substrate, effectively improving display uniformity, display quality, and display performance. In addition, by setting the second power line in the display area, the second power line is located in the panel (VSS in Panel, or SIP) structure, which can significantly reduce the width of the bezel power leads, greatly reduce the width of the left and right bezels, increase the screen ratio, and facilitate the realization of full-screen display.

[0276] In an exemplary embodiment, the second power line 82 may be disposed in the circuit cells of the N+1th, N+2th, N+4th and N+5th cell columns, respectively.

[0277] In an exemplary embodiment, the orthographic projection of the second power line 82 on the substrate at least partially overlaps with the orthographic projection of the first active layer, the second active layer, or the fourth active layer on the substrate. Therefore, the second power line 82 can block the first transistor T1, the second transistor T2, and the fourth transistor T4, preventing the light emitted by the light-emitting device and the reflected light from the film layer from illuminating the first transistor T1, the second transistor T2, and the fourth transistor T4 of the oxide transistor. This can prevent the oxide transistor from experiencing characteristic drift due to light exposure and improve the electrical characteristics of the oxide transistor.

[0278] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the second power line 82 on the substrate at least partially overlaps with the orthographic projections of the first electrode plate 11 and the second electrode plate 12 on the substrate. In the direction perpendicular to the display substrate, since the second electrode plate 12 is disposed between the first electrode plate 11 and the second power line 82, the second electrode plate 12 can effectively shield the overlapping capacitance between the first electrode plate 11 (first node N1) and the second power line 82, thereby effectively reducing the parasitic capacitance of the first node N1.

[0279] In an exemplary embodiment, the fifth conductive layer of at least one circuit unit may further include a first initial connection line 91. The shape of the first initial connection line 91 may be a straight line or a broken line extending along the second direction Y of the main body portion. The first initial connection line 91 is connected to the first initial connection block 71-1 through the twenty-fifth via V25. Since the first initial connection block 71-1 is connected to the first initial signal line 71, the interconnection between the first initial signal line 71 extending along the first direction X of the main body portion and the first initial connection line 91 extending along the second direction Y of the main body portion is realized. The first initial signal line 71 and the first initial connection line 91 form a mesh-like interconnected structure on the display substrate for transmitting the first initial signal. This not only effectively reduces the resistance of the first initial connection line and reduces the voltage drop of the first initial signal, but also effectively improves the uniformity of the first initial signal in the display substrate, effectively improving display uniformity, display quality, and display performance.

[0280] In an exemplary embodiment, the first initial connection line 91 may be disposed between the N+1th and N+2th unit columns, and between the N+4th and N+5th unit columns.

[0281] In an exemplary embodiment, the first initial connection line 91 can be disposed between two first power lines 81 in adjacent unit columns. This not only keeps the first initial connection line 91 away from the data signal line 83, reducing the parasitic capacitance between the data signal line 83 and the first initial connection line 91, but also allows the first power line 81 with a constant potential to effectively shield the influence of the jumping voltage of the data signal line 83 on the first initial signal in the first initial connection line 91, improving the stability of the first initial signal. This effectively ensures the accuracy of the threshold voltage Vth compensation and the stability of the gate-source voltage Vgs of the third transistor during the light-emitting stage, effectively reduces the change in the output current of the pixel driving circuit, effectively reduces the change in the light-emitting brightness, and effectively improves the display quality and display effect.

[0282] In an exemplary embodiment, the fifth conductive layer of at least one circuit unit may further include a second initial connection line 92. The shape of the second initial connection line 92 may be a straight line or a broken line extending along the second direction Y of the main body portion. The second initial connection line 92 is connected to the second initial connection block 72-1 through the second sixteenth via V26. Since the second initial connection block 72-1 is connected to the second initial signal line 72, the interconnection between the second initial signal line 72 extending along the first direction X of the main body portion and the second initial connection line 92 extending along the second direction Y of the main body portion is realized. The second initial signal line 72 and the second initial connection line 92 form a mesh-like interconnected structure on the display substrate for transmitting the second initial signal. This not only effectively reduces the resistance of the second initial connection line and reduces the voltage drop of the second initial signal, but also effectively improves the uniformity of the second initial signal in the display substrate, effectively improving display uniformity, display quality, and display performance.

[0283] In an exemplary embodiment, the second initial connection line 92 may be provided in the Nth cell column and the N+3th cell column.

[0284] In an exemplary embodiment, the orthographic projection of the second initial connection line 92 on the substrate at least partially overlaps with the orthographic projection of the first active layer, the second active layer, or the fourth active layer on the substrate. Therefore, the second initial connection line 92 can block the first transistor T1, the second transistor T2, and the fourth transistor T4, preventing the light emitted by the light-emitting device and the reflected light from the film layer from illuminating the first transistor T1, the second transistor T2, and the fourth transistor T4 of the oxide transistor. This can prevent the oxide transistor from experiencing characteristic drift due to light exposure and improve the electrical characteristics of the oxide transistor.

[0285] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the second initial connection line 92 on the substrate at least partially overlaps with the orthographic projections of the first electrode plate 11 and the second electrode plate 12 on the substrate. In the direction perpendicular to the display substrate, since the second electrode plate 12 is disposed between the first electrode plate 11 and the second initial connection line 92, the second electrode plate 12 can effectively shield the overlapping capacitance between the first electrode plate 11 (first node N1) and the second initial connection line 92, thereby effectively reducing the parasitic capacitance of the first node N1.

[0286] Subsequent fabrication processes may include forming a second planarization layer having an anode via exposed on the surface of the anode connection electrode 84, the anode via being configured to allow the subsequent formation of an anode to be connected to the anode connection electrode through the via.

[0287] Thus, the driving structure layer of this embodiment is fabricated on the substrate. In a plane parallel to the display substrate, the driving structure layer may include multiple circuit units. Each circuit unit may include a pixel driving circuit, and a first scan signal line, a second scan signal line, a third scan signal line, a fourth scan signal line, a first light emission signal line, a first initial signal line, a second initial signal line, a first power supply line, and a data signal line connected to the pixel driving circuit.

[0288] In a plane perpendicular to the display substrate, the driving structure layer may include a first conductive layer, a first insulating layer, a second conductive layer, a second insulating layer, a semiconductor layer, a third insulating layer, a third conductive layer, a fourth insulating layer, a fourth conductive layer, a first planarization layer, a fifth conductive layer, and a second planarization layer, sequentially disposed on the substrate. The first conductive layer may include at least the first electrode of a first capacitor and the third electrode of a second capacitor; the second conductive layer may include at least the second electrode of a first capacitor and the fourth electrode of a second capacitor; the semiconductor layer may include at least the active layers of the first transistor T1 to the sixth transistor T6; the third conductive layer may include at least a first light-emitting signal line and the gate electrodes of multiple transistors; the fourth conductive layer may include at least a first scan signal line, a second scan signal line, a third scan signal line, a fourth scan signal line, a first power connection line, a second power connection line, a first initial signal line, and a second initial signal line; and the fifth conductive layer may include at least a first power line, a second power line, a data signal line, a first initial connection line, and a second initial connection line.

[0289] In an exemplary embodiment, the substrate can be a flexible substrate or a rigid substrate. The rigid substrate can be, but is not limited to, one or more of glass and quartz. The flexible substrate can be, but is not limited to, polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate can include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on a glass substrate. The materials of the first and second flexible material layers can be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer films, etc. The materials of the first and second inorganic material layers can be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also called barrier layers. The material of the semiconductor layer can be amorphous silicon (a-Si).

[0290] In an exemplary embodiment, the first, second, third, and fourth insulating layers can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The first, second, third, fourth, and fifth conductive layers can be made of metallic materials, such as silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), or molybdenum (Mo), or can be made of alloy materials composed of metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Ti / Al / Ti. The first and second planarization layers can be made of organic materials, such as resin or polyimide.

[0291] In an exemplary embodiment, after the driving structure layer is fabricated, a light-emitting structure layer can be fabricated on the driving structure layer, and an encapsulation structure layer can be fabricated on the light-emitting structure layer, which will not be described in detail here.

[0292] This exemplary embodiment provides a display substrate in which the pixel driving circuit only requires six transistors to meet the driving requirements. This not only simplifies the structure of the pixel driving circuit and reduces its footprint, thus facilitating high-resolution (PPI) displays, but also reduces the number of gate drive circuits (GOAs) in the scan driver, further reducing their footprint and enabling narrow bezels. Furthermore, this improves the yield rate of the display substrate and reduces production costs.

[0293] This disclosed display substrate, by employing a pixel driving circuit with a smaller number of transistors, can increase the area of ​​the capacitor plates of the first capacitor C1 and / or the second capacitor C2 while maintaining the same circuit unit size. This increases the capacitance values ​​of the first capacitor C1 and / or the second capacitor C2, effectively reducing the variation in the gate-source voltage Vgs of the third transistor T3, effectively reducing the variation in the output current of the pixel driving circuit, effectively reducing the variation in luminous brightness, and effectively improving display quality and effect. Simulation experiments show that the capacitance of the first capacitor C1 in this disclosed display substrate is approximately 350.56f, and the capacitance of the second capacitor C2 is approximately 137.01f; therefore, C2 / (C1+C2) is approximately 0.281.

[0294] This disclosed display substrate effectively avoids the formation of parasitic capacitance between multiple signal lines and the first electrode by placing a first electrode plate with a potential at a first node in a first conductive layer and a second electrode plate with a potential at a second node in a second conductive layer. This further reduces the proportion of parasitic capacitance at the first node, thereby improving display quality and effect. Simulation experiments show that the total capacitance of the first node in this disclosed display substrate is approximately 358.39 F, the parasitic capacitance of the first node is approximately 7.83 F, and the proportion of parasitic capacitance at the first node is approximately 2.19%.

[0295] This disclosure provides a more compact arrangement of the pixel driving circuit while meeting design requirements. This effectively improves the utilization of layout space, results in a more reasonable structural arrangement, and simplifies the signal line connection structure without complex overlap. This can effectively improve product yield and reduce production costs.

[0296] This disclosure improves the uniformity and symmetry of the pixel driving circuit by setting a mirrored arrangement of the pixel driving circuits in some adjacent unit columns. This not only enables the design of uniform process and coupling capacitors, but also enables the design of uniform current distribution, effectively improving display stability and uniformity, and effectively enhancing display effect and display quality.

[0297] This disclosure establishes a third and sixth active layer in some adjacent cell columns as an interconnected integrated structure, and the first, second, and sixth gate electrodes in some adjacent cell columns as an interconnected integrated structure. On the one hand, this can effectively reduce the lateral wiring space, reduce the number of vias, and reduce the area occupied by the pixel driving circuit, which is beneficial for achieving high resolution. On the other hand, it can effectively increase the size of the capacitor plate and effectively increase the capacitance value, thereby maximizing the stability of the pixel driving circuit.

[0298] This embodiment of the present disclosure provides a first power connection line and a first power line, which form a mesh-like interconnected structure on the display substrate to transmit the first power signal. This not only effectively reduces the resistance of the first power line and the voltage drop of the first power signal, but also effectively improves the uniformity of the first power signal in the display substrate, thereby improving display uniformity and display quality.

[0299] This embodiment of the disclosure, by setting a second power connection line and a second power line, and forming a mesh-like interconnected structure on the display substrate to transmit the second power signal, can not only effectively reduce the resistance of the second power line and the voltage drop of the second power signal, but also effectively improve the uniformity of the second power signal in the display substrate, thereby improving display uniformity, display quality, and display performance. By setting the second power line in the display area, the second power line is located in the panel (VSS in Panel, or SIP) structure, which can significantly reduce the width of the bezel power leads, greatly reduce the width of the left and right bezels, increase the screen-to-body ratio, and facilitate the realization of full-screen display.

[0300] This embodiment of the present disclosure, by setting a first initial connection line and a second initial connection line, forms a mesh-like interconnected structure on the display substrate to transmit a first initial signal, and the second initial signal line and the second initial connection line form a mesh-like interconnected structure on the display substrate to transmit a second initial signal. This not only effectively reduces the resistance of the initial signal line and the voltage drop of the initial signal, but also effectively improves the uniformity of the initial signal in the display substrate, thereby improving display uniformity, display quality, and display performance.

[0301] This embodiment of the present disclosure, by placing the first initial connection line between two first power lines of adjacent circuit units, not only allows the first initial connection line to be kept away from the data signal line, effectively reducing the parasitic capacitance between the data signal line and the first initial connection line, but also allows the first power line with a constant potential to effectively shield the impact of the data signal line's voltage jump on the first initial connection line, improving the stability of the first initial signal, effectively ensuring the accuracy of threshold voltage Vth compensation and the stability of the gate-source voltage Vgs of the third transistor during the light-emitting stage, effectively reducing the change in the output current of the pixel driving circuit, effectively reducing the change in light emission brightness, and effectively improving display quality and display effect.

[0302] This embodiment of the disclosure avoids signal crosstalk caused by data voltage jumps in the data signal lines by setting the data signal lines to not overlap with multiple connection electrodes, thus avoiding the impact of data voltage jumps on transistors, improving the working stability of the pixel driving circuit, and enhancing the display effect.

[0303] This embodiment of the invention effectively reduces the resistance of the scan signal lines and lowers the voltage drop of the scan signal by setting multiple scan signal lines in the first source-drain metal layer, thereby improving the compensation speed and display quality.

[0304] The preparation process of this disclosure is well compatible with existing preparation processes. The process is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0305] Figure 17A is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure. As shown in Figure 17A, the structure of the pixel driving circuit in this embodiment is substantially the same as that shown in Figure 4A, except that the second terminal of the sixth transistor T6 is connected to the second node N2.

[0306] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The structures of the first node N1 and the third node N3 may be substantially the same as those shown in FIG. 4A. The second node N2 is connected to the second terminal of the third transistor T3, the first terminal of the fifth transistor T5, the second terminal of the sixth transistor T6, the second terminal of the first capacitor C1, and the second terminal of the second capacitor C2, respectively.

[0307] Figure 17B shows an extension of the pixel driving circuit shown in Figure 17A. As shown in Figure 17B, the structure of the pixel driving circuit in this embodiment is basically the same as that shown in Figure 17A. The difference is that the first initial signal line INIT1 and the third initial signal line INIT3 are the same initial signal line, that is, the first terminal of the first transistor T1 and the first terminal of the second transistor T2 are both connected to the first initial signal line INIT1.

[0308] Figure 18 is a timing diagram of a pixel driving circuit shown in Figure 17B. As shown in Figure 18, in an exemplary embodiment, the operation of the pixel driving circuit in this embodiment is basically the same as that shown in Figure 5. The difference is that in the embodiment shown in Figure 5, the second scan signal line S2 is a continuous high-level signal from the first stage A1 to the fourth stage A4, while in this embodiment, the second scan signal line S2 is a high-level signal only in the first stage A1 (the sixth transistor T6 is turned on). The second initial signal line INIT2 provides the second initial signal to the second node N2 to initialize the second node N2.

[0309] Figure 19A is an equivalent circuit diagram of another pixel driving circuit according to an exemplary embodiment of the present disclosure. As shown in Figure 19A, the structure of the pixel driving circuit in this embodiment is substantially the same as that shown in Figure 4A, except that the pixel driving circuit in this embodiment may further include a seventh transistor T7.

[0310] In an exemplary embodiment, the first node N1 to the fourth node N4 in the pixel driving circuit of this embodiment can be substantially the same as those shown in FIG4A, and the structures of the first transistor T1, the second transistor T2, the fourth transistor T4 to the sixth transistor T6 can be substantially the same as those shown in FIG4A, which will not be described again here.

[0311] In an exemplary embodiment, the gate electrode of the third transistor T3 is connected to the first node N1, the first electrode of the third transistor T3 is connected to the second electrode of the seventh transistor T7, and the second electrode of the third transistor T3 is connected to the second node N2.

[0312] In an exemplary embodiment, the seventh transistor T7 can be referred to as the second light-emitting control transistor. The gate electrode of the seventh transistor T7 is connected to the second light-emitting signal line EM2, the first electrode of the seventh transistor T7 is connected to the first power supply line VDD, and the second electrode of the seventh transistor T7 is connected to the first electrode of the third transistor T3.

[0313] Figure 19B shows an extension of the pixel driving circuit shown in Figure 19A. As shown in Figure 19B, the structure of the pixel driving circuit in this embodiment is basically the same as that shown in Figure 19A. The difference is that the first initial signal line INIT1 and the third initial signal line INIT3 are the same initial signal line, that is, the first terminal of the first transistor T1 and the first terminal of the second transistor T2 are both connected to the first initial signal line INIT1.

[0314] Figure 20 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure. As shown in Figure 20, the main structure of the display substrate in this embodiment is basically the same as that in the embodiment shown in Figure 7, except that the pixel driving circuit in this embodiment further includes a seventh transistor T7.

[0315] In an exemplary embodiment, the gate electrode of the seventh transistor T7 is connected to the second light-emitting signal line 42, the first electrode of the seventh transistor T7 is connected to the first power supply line 81 via the first power supply connection line 65, and the second electrode of the seventh transistor T7 is directly connected to the first electrode of the third transistor T3.

[0316] In an exemplary embodiment, the fabrication process of the display substrate may include the following operations.

[0317] (21) Forming a first conductive layer pattern. In an exemplary embodiment, the process of forming the first conductive layer pattern and the formed first conductive layer pattern can be substantially the same as the embodiment shown in FIG7. The first conductive layer pattern of each circuit unit in the display substrate can include at least the first electrode plate 11 of the first capacitor and the third electrode plate 13 of the second capacitor, as shown in FIG21.

[0318] In an exemplary embodiment, since the pixel driving circuit includes a seventh transistor T7, a third groove 11-2 may be provided on the first electrode plate 11 of this embodiment. The area where the third groove 11-2 is located avoids the seventh transistor T7. Therefore, the area of ​​the first electrode plate 11 in this embodiment is smaller than the area of ​​the first electrode plate 11 in the embodiment shown in FIG7.

[0319] In an exemplary embodiment, the position, shape, and area of ​​the third electrode plate 13 in this embodiment can be substantially the same as those in the embodiment shown in FIG7.

[0320] (22) Forming a second conductive layer pattern. In an exemplary embodiment, the process of forming the second conductive layer pattern and the formed second conductive layer pattern can be substantially the same as the embodiment shown in FIG7. The second conductive layer pattern of each circuit unit in the display substrate includes at least the second electrode plate 12 of the first capacitor and the fourth electrode plate 14 of the second capacitor, as shown in FIG22.

[0321] In an exemplary embodiment, since the pixel driving circuit includes a seventh transistor T7, the area of ​​the second electrode plate 12 in this embodiment is smaller than the area of ​​the second electrode plate 12 in the embodiment shown in FIG7.

[0322] In an exemplary embodiment, the position, shape, and area of ​​the fourth electrode plate 14 in this embodiment can be substantially the same as those in the embodiment shown in FIG7.

[0323] (23) Forming a semiconductor layer pattern. In an exemplary embodiment, the process of forming a semiconductor layer pattern and the semiconductor layer pattern formed are substantially the same as those shown in FIG7 of this embodiment, except that the semiconductor layer pattern also includes the seventh active layer 27 of the seventh transistor T7, as shown in FIG23.

[0324] In an exemplary embodiment, the semiconductor layer pattern of each circuit unit in the display substrate may include the first active layer 21 of the first transistor T1 to the seventh active layer 27 of the seventh transistor T7, and the first active layer 21, the second active layer 22 and the fourth active layer 24 may be an integral structure interconnected with each other, and the third active layer 23, the fifth active layer 25, the sixth active layer 26 and the seventh active layer 27 may be an integral structure interconnected with each other.

[0325] In an exemplary embodiment, the structures of the first active layer 21, the second active layer 22, the fourth active layer 24 to the sixth active layer 26 are substantially the same as those shown in FIG7 in this embodiment.

[0326] In an exemplary embodiment, the third active layer 23 and the seventh active layer 27 can be strip-shaped extending along the second direction Y. The seventh active layer 27 can be located on the side of the third active layer 23 away from the fifth active layer 25. The first region 27-1 of the seventh active layer can be set separately. The first region 23-1 of the third active layer and the second region 27-2 of the seventh active layer can be connected to each other. The first region 23-1 of the third active layer can serve as the second region 27-2 of the seventh active layer.

[0327] In an exemplary embodiment, in at least one cell row, the first region 27-1 of the seventh active layer in some adjacent circuit cells can be interconnected, and the seventh active layer 27 of two adjacent circuit cells can be an integral structure interconnected. For example, the seventh active layer 27 in the N+1 cell column and the N+2 cell column can be an integral structure interconnected, and the two adjacent circuit cells share the same first region 27-1 of the seventh active layer. Similarly, the seventh active layer 27 in the N+4 cell column and the N+5 cell column can be an integral structure interconnected, and the two adjacent circuit cells share the same first region 27-1 of the seventh active layer. By setting some adjacent circuit cells to share the first region of the seventh active layer (i.e., the first electrode of the seventh transistor T7), this disclosure can effectively reduce the lateral wiring space, reduce the number of vias, and reduce the area occupied by the pixel driving circuit, which is beneficial for achieving high resolution.

[0328] (24) Forming a third conductive layer pattern. In an exemplary embodiment, the process of forming the third conductive layer pattern and the formed third conductive layer pattern are substantially the same as those shown in FIG7 of this embodiment, except that the third conductive layer pattern further includes a second light-emitting signal line 42, as shown in FIG24.

[0329] In an exemplary embodiment, the third conductive layer pattern of each circuit unit in the display substrate includes at least: a first gate electrode 31 to a fourth gate electrode 34, a sixth gate electrode 36, a first light-emitting signal line 41, and a second light-emitting signal line 42. The structure of the first gate electrode 31 to the fourth gate electrode 34, the sixth gate electrode 36, and the first light-emitting signal line 41 can be substantially the same as that shown in FIG7 in this embodiment.

[0330] In an exemplary embodiment, the shape of the second light-emitting signal line 42 can be a straight line or a broken line extending along the first direction X. It can be disposed on the side of the third gate electrode 33 away from the first gate electrode 31. The orthographic projection of the second light-emitting signal line 42 on the substrate and the orthographic projection of the seventh active layer 27 on the substrate at least partially overlap. The overlapping area can serve as the gate electrode of the seventh transistor T7, thus enabling the second light-emitting signal line 42 to control the conduction or disconnection of the seventh transistor T7.

[0331] In an exemplary embodiment, the second light-emitting signal line 42 can be a variable-width polygonal line structure, and the width of the second light-emitting signal line is the dimension of the second direction Y. The second light-emitting signal line 42 may include a first region that overlaps with the seventh active layer 27 and a second region that does not overlap with the seventh active layer 27, and the width of the first region may be greater than the width of the second region.

[0332] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the second light-emitting signal line 42 on the substrate does not overlap with the orthographic projections of the first electrode plate 11, the second electrode plate 12, the third electrode plate 13, and the fourth electrode plate 14 on the substrate.

[0333] (25) Forming a fourth insulating layer pattern. In an exemplary embodiment, the process of forming the fourth insulating layer pattern and the formed fourth insulating layer pattern can be substantially the same as those shown in FIG7, as shown in FIG25.

[0334] In an exemplary embodiment, each circuit unit in the display substrate includes at least a first via V1 to an eighteenth via V18. The orthographic projection of the fourth via V4 onto the substrate lies within the orthographic projection of the first region of the seventh active layer onto the substrate. The third and fourth insulating layers within the fourth via V4 are etched away, exposing the surface of the first region of the seventh active layer. The fourth via V4 is configured to allow subsequently formed power connection lines to connect to the first region of the seventh active layer through this via. Since two partially adjacent circuit units share the same first region of the seventh active layer, they can share the same fourth via V4, effectively reducing the number of vias and decreasing the area occupied by the pixel driving circuit, which is beneficial for achieving high resolution.

[0335] (26) Forming a fourth conductive layer pattern. In an exemplary embodiment, the process of forming the fourth conductive layer and the resulting fourth conductive layer pattern are substantially the same as those shown in FIG7, as shown in FIG26.

[0336] In an exemplary embodiment, the fourth conductive layer of each circuit unit in the display substrate includes at least: a first connection electrode 51 to a sixth connection electrode 56, a first scan signal line 61 to a fourth scan signal line 64, a first power connection line 65, a second power connection line 66, a first initial signal line 71, and a second initial signal line 72. The above structure can be substantially the same as that shown in FIG7 in this embodiment, except that the first power connection line 65 is connected to the first region of the seventh active layer through a fourth via V4.

[0337] (27) Forming a first planarization layer pattern. In an exemplary embodiment, the process of forming the first planarization layer pattern and the formed first planarization layer pattern can be substantially the same as those shown in FIG7, as shown in FIG27.

[0338] (28) Forming a fifth conductive layer pattern. In an exemplary embodiment, the process of forming the fifth conductive layer and the resulting fifth conductive layer pattern are substantially the same as those shown in FIG7, as shown in FIG28.

[0339] This embodiment of the display substrate, by optimizing the structure of the pixel driving circuit, can effectively increase the area of ​​the capacitor plates of the first capacitor C1 and / or the second capacitor C2, thereby increasing the capacitance values ​​of the first capacitor C1 and / or the second capacitor C2. This can effectively reduce the variation in the gate-source voltage Vgs of the third transistor T3, effectively reduce the variation in the output current of the pixel driving circuit, effectively reduce the variation in luminous brightness, and effectively improve the display quality and display effect. Simulation experiments show that the capacitance of the first capacitor C1 in this embodiment of the display substrate is approximately 287.14f, and the capacitance of the second capacitor C2 is approximately 137.01f. Therefore, C2 / (C1+C2) is approximately 0.323.

[0340] In this embodiment, the display substrate effectively avoids the formation of parasitic capacitance between multiple signal lines and the first electrode by placing a first electrode plate with a potential at a first node in a first conductive layer and a second electrode plate with a potential at a second node in a second conductive layer. This effectively reduces the total capacitance of the first node, the parasitic capacitance of the first node, and the proportion of the parasitic capacitance of the first node, thereby improving display quality and display effect. Simulation experiments show that the total capacitance of the first node in the display substrate of this embodiment is approximately 294.75 F, the parasitic capacitance of the first node is approximately 7.61 F, and the proportion of the parasitic capacitance of the first node is approximately 2.58%.

[0341] The structure and its preparation process described above in this disclosure are merely illustrative examples. In the exemplary embodiments, the corresponding structure and the patterning process can be changed or added or reduced according to actual needs, and this disclosure does not limit them.

[0342] In exemplary embodiments, the display substrate of this disclosure can be applied to display devices with pixel driving circuits, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., and this disclosure does not limit it.

[0343] This disclosure also provides a display device, which includes the aforementioned display substrate. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator, and the embodiments of the present invention are not limited thereto.

[0344] While the embodiments disclosed herein are as described above, it should be noted that these embodiments are merely exemplary and not restrictive. Therefore, this disclosure is not limited to the specific content shown and described herein. Various modifications, substitutions, or omissions can be made to the form and details of the embodiments without departing from the scope of this disclosure.

Claims

1. A display substrate comprising a plurality of circuit units, at least one circuit unit comprising a pixel driving circuit, the pixel driving circuit comprising at least a first capacitor, a second capacitor, a third transistor as a driving transistor, and a fourth transistor as a data writing transistor, the first capacitor comprising at least a first electrode and a second electrode, the second capacitor comprising at least a third electrode and a fourth electrode, the orthographic projection of the second electrode on a plane of the display substrate at least partially overlapping the orthographic projection of the first electrode on a plane of the display substrate, the orthographic projection of the fourth electrode on a plane of the display substrate at least partially overlapping the orthographic projection of the third electrode on a plane of the display substrate; the first electrode is connected to the gate electrode of the third transistor, the second electrode and the third electrode are connected to the second electrode of the third transistor, and the fourth electrode is connected to the second electrode of the fourth transistor; in a direction perpendicular to the display substrate, the display substrate comprises at least a first conductive layer disposed on a substrate and a second conductive layer disposed on a side of the first conductive layer away from the substrate, the first electrode and the third electrode being disposed in the first conductive layer, and the second electrode and the fourth electrode being disposed in the second conductive layer.

2. The display substrate according to claim 1, wherein, The pixel driving circuit further includes a first transistor as a first reset transistor and a second transistor as a second reset transistor. The second terminal of the first transistor is connected to the gate electrode of the first plate and the third transistor, respectively. The second terminal of the second transistor is connected to the second terminal of the fourth plate and the fourth transistor, respectively. At least one of the first terminal of the first transistor and the first terminal of the second transistor is connected to the first initial signal line.

3. The display substrate according to claim 2, wherein, The pixel driving circuit further includes a fifth transistor as a first light-emitting control transistor and a sixth transistor as a third reset transistor. The first terminal of the fifth transistor is connected to the second terminal of the third transistor, the second terminal of the fifth transistor is connected to the second terminal of the sixth transistor and the light-emitting device, and the first terminal of the sixth transistor is connected to the second initial signal line.

4. The display substrate according to claim 2, wherein, The pixel driving circuit further includes a fifth transistor as a first light-emitting control transistor and a sixth transistor as a third reset transistor. The first terminal of the fifth transistor is connected to the second terminal of the third transistor and the second terminal of the sixth transistor, respectively. The second terminal of the fifth transistor is connected to the light-emitting device, and the first terminal of the sixth transistor is connected to the second initial signal line.

5. The display substrate according to claim 3 or 4, wherein, At least one circuit unit further includes a second power line extending along a second direction and a second power connection line extending along a first direction, the first direction intersecting the second direction, the second power line being configured to provide a second power signal to the light-emitting device, the second power line being connected to the second power connection line, and forming a mesh-like interconnection structure on the display substrate for transmitting the second power signal.

6. The display substrate according to claim 5, wherein, The first transistor includes at least a first active layer, the second transistor includes at least a second active layer, and the fourth transistor includes at least a fourth active layer. In at least one circuit unit, the orthographic projection of the second power line on the display substrate plane at least partially overlaps with the orthographic projection of the first active layer, the second active layer, or the fourth active layer on the display substrate plane.

7. The display substrate according to claim 5, wherein, In at least one circuit unit, the orthographic projection of the second power line on the display substrate plane at least partially overlaps with the orthographic projections of the first electrode plate and the second electrode plate on the display substrate plane; In a direction perpendicular to the display substrate, the second electrode plate is disposed between the first electrode plate and the second power line.

8. The display substrate according to claim 3 or 4, wherein, At least one circuit unit further includes a second initial connection line extending along a second direction. The shape of the second initial signal line is a straight line or a broken line extending along a first direction. The first direction intersects the second direction. The second initial signal line is connected to the second initial connection line, forming a mesh-like interconnected structure for transmitting the second initial signal on the display substrate.

9. The display substrate according to claim 8, wherein, The first transistor includes at least a first active layer, the second transistor includes at least a second active layer, and the fourth transistor includes at least a fourth active layer. In at least one circuit unit, the orthographic projection of the second initial connection line on the display substrate plane at least partially overlaps with the orthographic projection of the first active layer, the second active layer, or the fourth active layer on the display substrate plane.

10. The display substrate according to claim 8, wherein, In at least one circuit unit, the orthographic projection of the second initial connection line on the display substrate plane at least partially overlaps with the orthographic projections of the first electrode plate and the second electrode plate on the display substrate plane; In a direction perpendicular to the display substrate, the second electrode plate is disposed between the first electrode plate and the second initial connection line.

11. The display substrate according to claim 2, wherein, The first terminal of the third transistor is connected to a first power line, which is configured to provide a first power signal to the pixel driving circuit.

12. The display substrate according to claim 2, wherein, The pixel driving circuit further includes a seventh transistor as a second light-emitting control transistor, the first terminal of the seventh transistor being connected to a first power line, the second terminal of the seventh transistor being connected to the first terminal of the third transistor, and the first power line being configured to provide a first power signal to the pixel driving circuit.

13. The display substrate according to claim 11 or 12, wherein, At least one circuit unit further includes a first power connection line extending along a first direction. The first power line is in the shape of a straight line or a broken line extending along a second direction. The first direction intersects the second direction. The first power line is connected to the first power connection line, forming a mesh-like interconnected structure on the display substrate for transmitting the first power signal.

14. The display substrate according to claim 13, wherein, The third transistor includes at least a third active layer, the fifth transistor includes at least a fifth active layer, and in at least one circuit unit, the orthographic projection of the first power line on the display substrate plane at least partially overlaps with the orthographic projection of the third active layer or the fifth active layer on the display substrate plane.

15. The display substrate according to claim 13, wherein, In at least one circuit unit, the orthographic projection of the first power line on the display substrate plane at least partially overlaps with the orthographic projections of the first electrode plate and the second electrode plate on the display substrate plane. In a direction perpendicular to the display substrate, the second electrode plate is disposed between the first electrode plate and the first power line.

16. The display substrate according to claim 13, wherein, In at least one circuit unit, the orthographic projection of the first power line on the display substrate plane at least partially overlaps with the orthographic projection of the gate electrode of the third transistor on the display substrate plane.

17. The display substrate according to claim 16, wherein, In at least one circuit unit, the first power line includes at least a first region that overlaps with the gate electrode of the third transistor and a second region that does not overlap with the gate electrode of the third transistor, wherein the width of the first region is greater than the width of the second region, and the width is the dimension in the first direction.

18. The display substrate according to claim 13, wherein, The display substrate further includes a first initial connection line extending along a second direction. The shape of the first initial signal line is a straight line or a broken line extending along a first direction. The first direction intersects with the second direction. The first initial signal line is connected to the first initial connection line to form a mesh-like interconnected structure for transmitting the first initial signal on the display substrate.

19. The display substrate according to claim 18, wherein, In the first direction, the first initial connection line is disposed between the first power lines of adjacent circuit units.

20. The display substrate according to claim 1, wherein, The first electrode plate is connected to the second electrode of the first transistor and the gate electrode of the third transistor via a first connecting electrode. The second electrode plate is connected to the second electrode of the third transistor via a fourth connecting electrode. The third electrode plate is connected to the second electrode of the third transistor via a second connecting electrode. The fourth electrode plate is connected to the second electrode of the second transistor and the second electrode of the fourth transistor via a third connecting electrode.

21. A display device comprising a display substrate as described in any one of claims 1 to 20.

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