Display module, display apparatus, and display driving method

Abstract

Disclosed are a display module, a display apparatus, and a display driving method, relating to the technical field of display. The display module comprises: a display panel, a backlight source, and a driving circuit. The display panel comprises a plurality of display partitions arranged in a scanning direction, and the plurality of display partitions include a first display partition and a second display partition; the backlight source is located on a backlight side of the display panel, and comprises a light-emitting element, the light-emitting element comprises an LED chip and a color conversion portion at least located on a light-exit side of the LED chip, and the LED chip emits blue light or mixed light of blue light and green light or mixed light of blue light and red light; and the driving circuit is configured to provide a pulse signal to the backlight source in a first display mode, and perform overshoot driving on the plurality of display partitions, the overshoot rate of the first display partition is different from the overshoot rate of the second display partition, and an overshoot rate is a proportion of an actual driving value of a display partition deviating from a target driving value, wherein the response time of the color conversion portion is less than 1 ms.

Description

Display module, display device, and display driving method

[0001] This application claims priority to PCT International Application No. PCT / CN2025 / 078641, filed on February 21, 2025, entitled “Display Module, Display Device and Display Driving Method”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of display technology, and in particular to a display module, display device, and display driving method. Background Technology

[0003] Thin-film transistor liquid crystal displays (TFT-LCDs) are characterized by their light weight, thinness, and low power consumption, and are widely used in devices such as mobile phones, monitors, and televisions. After TFT-LCDs entered the display market dominated by cathode ray tubes (CRTs), the requirements for the dynamic image display quality and response speed of liquid crystal displays became even more stringent. Summary of the Invention

[0004] This disclosure provides a display module, a display device, and a display driving method. The technical solution is as follows:

[0005] In a first aspect, a display module is provided, the display module comprising:

[0006] The display panel includes multiple display zones arranged along the scanning direction, wherein the multiple display zones include a first display zone and a second display zone;

[0007] A backlight source, located on the backlight side of the display panel, is configured to provide backlight to the display panel. The backlight source includes a light-emitting element, which includes a light-emitting diode (LED) chip and a color conversion section located at least on the light-emitting side of the LED chip. The LED chip emits blue light, a mixture of blue and green light, or a mixture of blue and red light.

[0008] A driving circuit, connected to the plurality of display zones and the backlight respectively, is configured to provide a pulse signal to the backlight in a first display mode and to perform overshoot driving on the plurality of display zones, wherein the overshoot rate of the first display zone is different from the overshoot rate of the second display zone, and the overshoot rate is the proportion by which the actual driving value of the display zone deviates from the target driving value. The response time of the color conversion unit is less than 1 ms.

[0009] In some embodiments, the first display partition and the second display partition are arranged sequentially along the scanning direction, and the overshoot rate of the second display partition is greater than the overshoot rate of the first display partition.

[0010] In some embodiments, the overshoot rate of multiple display zones in the display panel increases sequentially along the scanning direction.

[0011] In some embodiments, the plurality of display partitions further includes: a third display partition located on the side of the second display partition away from the first display partition, wherein the overshoot rate of the third display partition is less than the overshoot rate of the second display partition; or

[0012] The fourth display partition is located on the side of the first display partition that is far from the second display partition, and the overshoot rate of the fourth display partition is greater than that of the first display partition.

[0013] In some embodiments, a display cycle of the display panel includes a refresh phase and a hold phase, and the effective pulse of the pulse signal is located within the time range of the hold phase; and

[0014] Along the scanning direction, the overshoot rate of multiple display zones in the display panel increases sequentially.

[0015] In some embodiments, the plurality of display zones further includes a fifth display zone and a sixth display zone arranged sequentially along the scanning direction, wherein the effective pulse of the pulse signal overlaps with the refresh of the fifth display zone but does not overlap with the refresh of the sixth display zone; and

[0016] The overshoot rate of the fifth display partition is greater than that of the sixth display partition, and along the scanning direction, the overshoot rate of the sixth display partition and at least one display partition located on the side of the sixth display partition away from the fifth display partition increases sequentially.

[0017] In some embodiments, the display panel includes multiple display units, each display unit including the same number of display partitions, and the multiple display partitions in each display unit are sorted along the scanning direction, with the overshoot rate of the display partitions with the same sequence number in different display units being approximately the same.

[0018] In some embodiments, a display cycle of the display panel includes a refresh phase and a hold phase. When the refresh frequency of the display panel is a first refresh frequency, a display cycle of the display panel includes a first refresh phase and a first hold phase. The pulse signal includes a first pulse signal, and the duty cycle of the first pulse signal is less than or equal to the duration of the first hold phase in a display cycle.

[0019] In some embodiments, when the refresh rate of the display panel is a second refresh rate and the second refresh rate is less than the first refresh rate, the pulse signal further includes:

[0020] The second pulse signal includes a second effective pulse, the first pulse signal includes a first effective pulse, the duty cycle of the second effective pulse is the same as the duty cycle of the first effective pulse, and the duration of one second effective pulse is the same as the duration of one first effective pulse.

[0021] In some embodiments, the second pulse signal further includes a third effective pulse, the duty cycle of which is the same as that of the first effective pulse, and the duration of one third effective pulse is less than the duration of one first effective pulse.

[0022] In some implementations, the first effective pulse overlaps with the first display cycle, and the start time of the first effective pulse is delayed by a first preset duration relative to the start time of the first display cycle.

[0023] The second valid pulse overlaps with the second display cycle, and the start time of the second valid pulse is delayed by the first preset duration relative to the start time of the second display cycle;

[0024] The start time of the third effective pulse adjacent to the second effective pulse is delayed by a second preset duration relative to the start time of the second effective pulse, and the second preset duration is equal to the duration of the first display cycle.

[0025] In some implementations, the first valid pulse overlaps with the first refresh phase;

[0026] The second display cycle includes a second refresh phase and a second hold phase, the second valid pulse overlaps with the second refresh phase, and the third valid pulse overlaps with the second hold phase.

[0027] In some implementations, the first effective pulse overlaps with the first hold phase;

[0028] The second display cycle includes a second refresh phase and a second hold phase, and the second effective pulse and the third effective pulse overlap with the second hold phase.

[0029] In some implementations, the first valid pulse is located within the time range of the first hold phase, and the second valid pulse and the third valid pulse are both located within the time range of the second hold phase.

[0030] In some implementations, the duty cycle of the first pulse signal is equal to the proportion of the duration of the first hold phase in a display cycle;

[0031] When the refresh rate of the display panel is a third refresh rate, one display cycle of the display panel includes a third refresh phase and a third hold phase. The pulse signal also includes a third pulse signal, the duty cycle of which is equal to the proportion of the duration of the third hold phase in one display cycle.

[0032] The third refresh frequency is different from the first refresh frequency, the third refresh phase has the same duration as the first refresh phase, and the third hold phase has a different duration than the first hold phase.

[0033] In some implementations, the duty cycle of the first pulse signal is less than the duration of the first hold phase in a display cycle.

[0034] The first pulse signal includes a first valid pulse, which is located within the time range of the first hold phase. The duration of the first valid pulse is less than the duration of the first hold phase, and the end time of the first valid pulse is the same as the end time of the first hold phase.

[0035] In some implementations, when the first refresh frequency is greater than or equal to the first threshold, the frequency of the first pulse signal is equal to the first refresh frequency; when the first refresh frequency is less than the first threshold, the frequency of the first pulse signal is greater than the first refresh frequency and less than or equal to ten times the first refresh frequency.

[0036] In some embodiments, the frequency of the pulse signal is greater than or equal to 200 Hz and less than or equal to 25 kHz.

[0037] In some embodiments, the backlight is a side-lit backlight, which includes a lamp bar and a light guide plate. The light-emitting elements are arranged on the lamp bar, and the light-emitting surfaces of the light-emitting elements are opposite to the side of the light guide plate. Alternatively, the backlight is a direct-lit backlight, which includes an optical film layer and a plurality of light-emitting elements arranged in an array. The light-emitting surfaces of the light-emitting elements are opposite to the display panel, and the optical film layer is located between the light-emitting elements and the display panel.

[0038] In some embodiments, the color conversion unit includes color conversion particles; the material of the color conversion particles includes one or more of nitride phosphors, silicate phosphors, and yttrium aluminum garnet phosphors, or the color conversion particles include quantum dots.

[0039] Optionally, the light-emitting diode chip emits blue light, and the color conversion unit includes phosphors for emitting red light and phosphors for emitting green light; or, the light-emitting diode chip emits a mixture of blue and green light, and the color conversion particles include phosphors for emitting red light; or, the light-emitting diode chip emits a mixture of blue and red light, and the color conversion particles include phosphors for emitting green light; wherein the phosphors for emitting red light include one or more of nitride phosphors and silicate phosphors, and the phosphors for emitting green light include one or more of nitride phosphors and silicate phosphors.

[0040] Optionally, the nitride phosphor for emitting red light includes one or more of the following: CaAlSiN3, (Sr,Ca)AlSiN3, CaAlSi(ON)3, Sr2SiN8; the silicate phosphor for emitting red light includes: Y2SiO5; and the nitride phosphor for emitting green light includes one or more of the following: La3Si6N 11 (La,Y)3Si6N 11 The silicate phosphors used to emit green light include one or more of the following: BaSi2O2N2, (Si,Al)6(ON)8, β-SiAlON;

[0041] Optionally, the color conversion unit includes a phosphor for emitting yellow light, wherein the phosphor for emitting yellow light includes one or more of nitride phosphor, silicate phosphor, and yttrium aluminum garnet.

[0042] In some embodiments, the color conversion section does not contain fluoride phosphors.

[0043] In some embodiments, the color conversion section further includes a matrix in which the color conversion particles are distributed, and the matrix material includes at least one of silicone resin, epoxy resin, and polyurethane.

[0044] In some embodiments, the light-emitting diode chip includes: an electroluminescent layer for emitting blue light when an electric current is applied; a first photoluminescent layer for emitting green light when excited by a portion of the blue light; and a color conversion unit that is a second photoluminescent layer for emitting red light when excited by another portion of the blue light; wherein the electroluminescent layer and the first photoluminescent layer are stacked together, and the second photoluminescent layer covers the first photoluminescent layer and the electroluminescent layer.

[0045] In some embodiments, the light-emitting diode chip further includes a first semiconductor layer, a second semiconductor layer, a first electrode, and a second electrode. The first semiconductor layer, the first photoluminescent layer, the electroluminescent layer, and the second semiconductor layer are stacked sequentially. The second photoluminescent layer is at least partially located on the side of the second semiconductor layer away from the electroluminescent layer. The electroluminescent layer includes a first multiple quantum well layer, and the first photoluminescent layer includes a second multiple quantum well layer. The first electrode is electrically connected to the second semiconductor layer, and the second electrode is electrically connected to the first semiconductor layer.

[0046] In some embodiments, the light-emitting diode chip further includes an isolation layer located between the first photoluminescent layer and the electroluminescent layer.

[0047] In some embodiments, the material of the first semiconductor layer includes one of N-GaN and P-GaN, and the material of the second semiconductor layer includes the other of N-GaN and P-GaN; the light-emitting diode chip further includes a first reflective layer located on the side of the first semiconductor layer away from the second semiconductor layer.

[0048] In some embodiments, the light-emitting element further includes a support, the support including a receiving groove, wherein the first semiconductor layer, the first photoluminescent layer, the electroluminescent layer, the second semiconductor layer and the second photoluminescent layer are located in the receiving groove; the second photoluminescent layer is also located on the periphery of the stacked structure formed by the first semiconductor layer, the second semiconductor layer, the first photoluminescent layer, the electroluminescent layer and the second semiconductor layer.

[0049] In some embodiments, the driving circuit includes a timing controller configured to receive a display command, and if the command indicates entry into the first display mode, to provide a pulse signal to the backlight and perform overshoot driving on a plurality of display zones, wherein the overshoot rate of the first display zone is different from that of the second display zone; if the display command indicates entry into the second display mode, to provide a DC signal to the backlight and perform overshoot driving on a plurality of display zones, wherein the overshoot rate of different display zones is the same.

[0050] Secondly, this disclosure provides a display device including any of the aforementioned display modules.

[0051] Optionally, the display device is a laptop computer, a game console, or a monitor.

[0052] Thirdly, this disclosure provides a display driving method applied to a display module, the display module including a display panel and a backlight, the display panel including a plurality of display zones arranged along a scanning direction, the plurality of display zones including a first display zone and a second display zone, the backlight including a light-emitting element, the light-emitting element including a light-emitting diode chip and a color conversion section at least located on the light-emitting side of the light-emitting diode chip, the light-emitting diode chip emitting blue light or a mixture of blue and green light; wherein, the response time of the color conversion section is less than 1ms; the display driving method includes:

[0053] Get the display command;

[0054] If the display command indicates entry into the first display mode, a pulse signal is provided to the backlight and overshoot driving is performed on the multiple display zones. The overshoot rate of the first display zone is different from the overshoot rate of the second display zone. The overshoot rate is the proportion of the actual driving value of the display zone deviating from the target driving value.

[0055] In some embodiments, after the step of obtaining the display instruction, the display driving method further includes:

[0056] If the display command indicates entry into the second display mode, a DC signal is provided to the backlight and overshoot drive is performed on multiple display zones, with the overshoot rate being the same for different display zones. Attached Figure Description

[0057] To more clearly illustrate the technical solutions in the embodiments or related technologies of this disclosure, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. It should be noted that the scale in the drawings is for illustration only and does not represent the actual scale.

[0058] Figure 1 illustrates a schematic diagram of a display partition structure in a display panel;

[0059] Figure 2 illustrates an exemplary schematic diagram of a display partition structure in another display panel;

[0060] Figure 3 illustrates, for example, a curve showing the change in the driving value of a display partition;

[0061] Figure 4 illustrates, for example, the actual drive value lookup table and the target drive value lookup table;

[0062] Figure 5 illustrates an exemplary timing diagram of the first pulse signal and the second pulse signal;

[0063] Figure 6 illustrates another timing diagram of the first pulse signal and the second pulse signal;

[0064] Figure 7 illustrates the timing diagrams of the first and third pulse signals;

[0065] Figure 8 illustrates an exemplary timing diagram of the first pulse signal;

[0066] Figure 9 illustrates, by way of example, a schematic diagram of the structure of a display unit in a display panel;

[0067] Figure 10 illustrates a schematic diagram of the connection structure of two display modules;

[0068] Figure 11 shows an exemplary schematic diagram of a light-emitting element;

[0069] Figure 12 shows an exemplary structural schematic diagram of an LED chip;

[0070] Figure 13 shows, exemplarily, the emission spectrum of the LED chip in Figure 12;

[0071] Figure 14 illustrates a schematic diagram of a direct-lit backlight structure;

[0072] Figure 15 illustrates a schematic diagram of a side-lit backlight;

[0073] Figure 16 illustrates, for example, the timing diagram of the display mode command and pulse signal. Detailed Implementation

[0074] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0075] As refresh rates continue to increase, users' demands for display quality are becoming increasingly stringent. Game consoles generally require overdrive (OD) technology to reduce the response time of the display panel. OD technology works by changing the driving voltage during grayscale changes in the display panel, increasing the torque on the liquid crystal molecules, accelerating their rotation, and forcing them to change their alignment to a predetermined transmittance within a short time. This improves response speed, reduces response time, and minimizes motion blur.

[0076] This disclosure provides a display module, as shown in FIG10. The display module includes: a display panel PNL, as shown in FIG1 or FIG2, the display panel PNL including a plurality of display partitions A0 arranged along the scanning direction fs, the plurality of display partitions A0 including a first display partition A01 and a second display partition A02; a backlight BL, located on the backlight side of the display panel PNL (i.e. the side away from the light-emitting surface), configured to provide backlight to the display panel PNL; and a driving circuit DR, connected to the plurality of display partitions A0 and the backlight BL of the display panel PNL respectively, configured to provide a pulse signal to the backlight BL in a first display mode and perform overshoot driving on the plurality of display partitions A0, wherein the overshoot rate of the first display partition A01 is different from the overshoot rate of the second display partition A02, and the overshoot rate is the proportion of the actual driving value of the display partition A0 deviating from the target driving value.

[0077] Overshoot includes overshoot and undershoot. As shown in Figure 3, overshoot occurs when a pixel changes from a darker grayscale to a brighter grayscale, and the actual driving value provided to the pixel is greater than the target driving value, thus reducing the response time during the rising phase. Overshoot rate = (actual driving value - target driving value) / target driving value. Undershoot occurs when a pixel changes from a brighter grayscale to a darker grayscale, and the actual driving value provided to the pixel is less than the target driving value, thus reducing the response time during the falling phase. Undershoot rate = (target driving value - actual driving value) / target driving value. It should be noted that both overshoot rate and undershoot rate are positive values, i.e., overshoot rate / undershoot rate = |target driving value - actual driving value| / target driving value.

[0078] Figure 4 exemplarily illustrates the actual driving value lookup table and the target driving value lookup table. As shown in Figure 4a, the first row of the actual driving value lookup table represents the grayscale data of the current frame, and the first column represents the grayscale data of the previous frame. The actual driving value lookup table records the actual driving value corresponding to the change from the grayscale data of the previous frame to the grayscale data of the current frame. Each actual driving value is related to the grayscale data of the previous frame and the grayscale data of the current frame, and can be obtained through calculation or experimentation. For example, for a certain pixel, if the grayscale data of the previous frame is L1 and the grayscale data of the current frame is L254, the intersection of row L1 and column L254 in the actual driving value lookup table can be found to obtain the actual driving value a(1,254) corresponding to the change from grayscale L1 to grayscale L254.

[0079] As shown in Figure 4b, the first row of the target driving value lookup table represents the grayscale data of the current frame, and the first column represents the grayscale data of the previous frame. The target driving value lookup table records the target driving value corresponding to the change from the grayscale data of the previous frame to the grayscale data of the current frame. Each target driving value is related to the grayscale data of the previous frame and the grayscale data of the current frame, and can be obtained through calculation or experimentation. For example, for a certain pixel, if the grayscale data of the previous frame is L1 and the grayscale data of the current frame is L254, the intersection of row L1 and column L254 in the target driving value lookup table can be found to obtain the target driving value b(1,254) corresponding to the change from grayscale L1 to grayscale L254.

[0080] It should be noted that the actual driving value and the target driving value can be driving voltage value, grayscale value, or display brightness value, etc.

[0081] For each display partition A0, the overshoot rate and undershoot rate corresponding to multiple gray-to-gray (G2G) values ​​can be calculated. The overshoot rate of display partition A0 can be, for example, the average of multiple overshoot rates and multiple undershoot rates. It can be understood that the larger the overshoot rate, the shorter the response time, and the smaller the overshoot rate, the longer the response time.

[0082] In this disclosure, since a pulse signal is provided to the backlight BL in the first display mode, and the first display partition A01 and the second display partition A02 have different overshoot rates, the overshoot rate of the first display partition A01 and the overshoot rate of the second display partition A02 can be adjusted according to the position of the effective pulse in the pulse signal, thereby adjusting the response time of the first display partition A01 and the second display partition A02 respectively. This helps to reduce the trailing problem of high refresh rate models and improve the display image quality.

[0083] In addition, by providing pulse signals to the backlight BL, it is beneficial to eliminate motion blur caused by residual images of objects on the eyes. Backlight flicker further reduces the trailing problem of high refresh rate models and improves the display quality.

[0084] For example, a display panel PNL may include 20 or fewer display zones A0, such as 10. Each display zone A0 may include the same number of pixel rows, such as 160 pixel rows. Of course, different display zones A0 may also include different numbers of pixel rows. For example, each display zone A0 may include 200 or fewer pixel rows.

[0085] For example, the overshoot rate of display partition A0 can be greater than or equal to 5% and less than or equal to 100%. It should be noted that the overshoot rate of each display partition A0 can be adjusted according to the actual display effect, and this disclosure does not specifically limit the overshoot rate value of each display partition A0.

[0086] For each display partition A0, the absolute value of the difference between the average of the multiple overshoot rates and the average of the multiple undershoot rates can be, for example, less than or equal to 10% or 5%.

[0087] For example, the first display mode may be a game mode or a video playback mode, in which the user hopes to be able to accurately locate the target and reduce ghosting.

[0088] In some implementations, as shown in Figure 1 or Figure 2, the first display partition A01 and the second display partition A02 are arranged sequentially along the scanning direction fs, and the overshoot rate of the second display partition A02 is greater than the overshoot rate of the first display partition A01.

[0089] As shown in Figure 1 or Figure 2, the first display partition A01 and the second display partition A02 are arranged sequentially along the scanning direction fs and the overshoot rate increases sequentially.

[0090] For example, along the scanning direction fs, the overshoot rates of multiple display partitions A0 in the display panel PNL increase sequentially, for example, from 20% to 100%. In some embodiments, as shown in FIG1, the multiple display partitions A0 further include: a third display partition A03, located on the side of the second display partition A02 away from the first display partition A01, and the overshoot rate of the third display partition A03 is less than the overshoot rate of the second display partition A02.

[0091] As shown in Figure 1, the first display partition A01, the second display partition A02, and the third display partition A03 are arranged sequentially along the scanning direction fs, with the overshoot increasing first and then decreasing.

[0092] In some implementations, as shown in FIG2, the plurality of display partitions A0 further includes: a fourth display partition A04, located on the side of the first display partition A01 away from the second display partition A02, wherein the overshoot rate of the fourth display partition A04 is greater than the overshoot rate of the first display partition A01.

[0093] As shown in Figure 2, the fourth display partition A04, the first display partition A01, and the second display partition A02 are arranged sequentially along the scanning direction fs, with the overshoot decreasing first and then increasing.

[0094] In some implementations, as shown in FIG1, a display cycle of the display panel PNL includes a refresh phase and a hold phase, and the effective pulse of the pulse signal is located within the time range of the hold phase; and along the scanning direction fs, the overshoot rate of multiple display zones A0 in the display panel PNL increases sequentially, for example from 20% to 100%.

[0095] In this context, the effective pulse of the pulse signal being within the hold phase time range means that the backlight is only turned on during the hold phase. As shown in Figure 1, the scanning direction fs is from top to bottom, meaning that multiple pixel rows in the display panel PNL are sequentially opened and refreshed from top to bottom. The deflection time of each pixel row is from the time it finishes refreshing until the backlight is turned on. Since the backlight is only turned on during the hold phase, that is, after the last pixel row finishes refreshing, the deflection time of the topmost pixel row is the longest, and the deflection time of the last pixel row is the shortest. This means that the first display partition A0 has more time for the liquid crystal to reach the target position. By setting the overshoot rate of multiple display partitions A0 to increase sequentially along the scanning direction fs, the response time of multiple display partitions A0 is sequentially decreased along the scanning direction fs. This ensures that the liquid crystal of each display partition A0 has reached the target position when the backlight is turned on, thereby reducing or eliminating the display trailing problem in high refresh rate models.

[0096] In some embodiments, as shown in FIG2, the plurality of display partitions A0 further include a fifth display partition A05 and a sixth display partition A06 arranged sequentially along the scanning direction fs. The effective pulse of the pulse signal overlaps with the refresh of the fifth display partition A05, but does not overlap with the refresh of the sixth display partition A06. In order to reduce or eliminate the display trailing problem of high refresh rate models, the overshoot rate of the fifth display partition A05 is greater than that of the sixth display partition A06, and along the scanning direction fs, the overshoot rate of the sixth display partition A06 and at least one display partition A0 located on the side of the sixth display partition A06 away from the fifth display partition A05 increases sequentially.

[0097] As shown in Figure 2, when at least one display partition A0 is provided on the side of the fifth display partition A05 away from the sixth display partition A06, in order to further reduce or eliminate the display trailing problem of high refresh rate models, the overshoot rate of at least one display partition A0 located on the side of the fifth display partition A05 away from the sixth display partition A06 and the overshoot rate of the fifth display partition A05 are increased sequentially.

[0098] In some implementations, as shown in FIG9, the display panel PNL includes multiple display units UN, and different display units UN include the same number of display partitions A0 (5 as shown in FIG9). The multiple display partitions A0 in each display unit UN are sorted along the scanning direction fs, and the overshoot rates of display partitions A0 with the same sequence number in different display units UN are approximately the same.

[0099] As shown in Figure 9, the multiple display partitions A0 in each display unit UN are sorted along the scanning direction fs, with the serial numbers s0, s1, s2, s3, and s4 respectively. In display units UN1 and UN2, the overshoot rates of the two display partitions A0 with serial number s0 are approximately the same, the overshoot rates of the two display partitions A0 with serial number s1 are approximately the same, the overshoot rates of the two display partitions A0 with serial number s2 are approximately the same, the overshoot rates of the two display partitions A0 with serial number s3 are approximately the same, and the overshoot rates of the two display partitions A0 with serial number s4 are approximately the same.

[0100] In some implementations, as shown in Figures 5 to 8, when the refresh frequency of the display panel PNL is a first refresh frequency f1 (f1 = 240Hz as shown in Figures 5 to 7, and f1 = 360Hz as shown in Figure 8), one display cycle of the display panel PNL includes a first refresh phase SX1 and a first hold phase BC1. The pulse signal includes a first pulse signal PWM1, and the duty cycle of the first pulse signal PWM1 is less than or equal to the duration of the first hold phase BC1 in one display cycle.

[0101] For example, when the first refresh frequency f1 is the highest refresh frequency of the display panel PNL, the duty cycle of the first pulse signal PWM1 is equal to the proportion of the duration of the first hold phase BC1 in one display cycle. When the first refresh frequency f1 is less than the highest refresh frequency of the display panel PNL, the duty cycle of the first pulse signal PWM1 is less than the proportion of the duration of the first hold phase BC1 in one display cycle.

[0102] As shown in Figures 5 to 7, the first refresh frequency f1 is 240Hz, the duration of the first hold phase BC1 in one display cycle is 25%, and the duty cycle of the first pulse signal PWM1 is equal to the duration of the first hold phase BC1 in one display cycle, that is, the duty cycle of the first pulse signal PWM1 is 25%. Furthermore, the effective pulses of the first pulse signal PWM1 completely overlap with the first hold phase BC1.

[0103] As shown in Figure 8, the first refresh rate f1 is 360Hz, and the display panel PNL includes, for example, 1600 pixel rows. The duration of the first hold phase BC1 is the sum of the refresh times of 600 pixel rows. The duration of the first hold phase BC1 in one display cycle accounts for 27%. The duty cycle of the first pulse signal PWM1 is less than the duration of the first hold phase BC1 in one display cycle, and the duty cycle of the first pulse signal PWM1 is 25%. Furthermore, the effective pulse of the first pulse signal PWM1 is within the time range of the first hold phase BC1.

[0104] In some implementations, as shown in FIG7, when the refresh frequency of the display panel PNL is a third refresh frequency f3 (120Hz as shown in FIG7), one display cycle of the display panel PNL includes a third refresh phase SX3 and a third hold phase BC3. The pulse signal also includes a third pulse signal PWM3, and the duty cycle of the third pulse signal PWM3 is equal to the proportion of the duration of the third hold phase BC3 in one display cycle. Specifically, the third refresh frequency f3 is different from the first refresh frequency f1, the duration of the third refresh phase SX3 is the same as that of the first refresh phase SX1, and the duration of the third hold phase BC3 is different from that of the first hold phase BC1.

[0105] When the frequency conversion function is enabled, the refresh frequency of the display panel PNL changes. The refresh frequency includes, for example, a first refresh frequency f1 and a third refresh frequency f3. As shown in Figure 7, at the first refresh frequency f1, a first pulse signal PWM1 is provided to the backlight BL, and the duty cycle of the first pulse signal PWM1 is equal to the proportion of the duration of the first hold phase BC1 in one display cycle, as shown in Figure 7 (25%). At the third refresh frequency f3, a third pulse signal PWM3 is provided to the backlight BL, and the duty cycle of the third pulse signal PWM3 is equal to the proportion of the duration of the third hold phase BC3 in one display cycle, as shown in Figure 7 (62.5%). When the frequency conversion function is enabled, the refresh frequency continuously changes. The different proportions of the hold phase in one display cycle at different refresh frequencies cause the duty cycle of the pulse signal to constantly change, which can easily lead to flickering.

[0106] For example, as shown in Figure 10, the driving circuit DR includes a timing controller TCON and a light source driver LED Driver. In a specific implementation, the timing controller TCON can determine the corresponding backlight current based on the duty cycle of the pulse signal, and control the light source driver LED Driver to output the backlight current corresponding to the duty cycle via I2C commands.

[0107] To ensure that the backlight brightness remains constant under different modes, the backlight current I under pulse drive can be calculated using the following formula. ED = I0*(1 / PWM DUTY), where PWM DUTY is the duty cycle of the pulse signal driving the backlight, I0 is the backlight current corresponding to the DC drive, and I ED This is the backlight current corresponding to the pulse drive.

[0108] With the duty cycle of the first pulse signal PWM1 being 25%, the backlight current corresponding to the first pulse signal PWM1 can be determined to be 4 times the DC drive backlight current I0. Assuming the DC drive backlight current I0 is 6mA, then the amplitude of the backlight current (I1 as shown in Figure 7) corresponding to the first pulse signal PWM1 is 24mA.

[0109] With the duty cycle of the third pulse signal PWM3 at 62.5%, the backlight current corresponding to the third pulse signal PWM3 can be determined to be 1.6 times the DC drive backlight current I0. Assuming the DC drive backlight current I0 is 6mA, the amplitude of the backlight current (I3 as shown in Figure 7) corresponding to the third pulse signal PWM3 is 9.6mA.

[0110] For example, as shown in FIG7, the effective pulse of the third pulse signal PWM3 completely overlaps with the third hold phase BC3.

[0111] For example, the duration of the third holding phase BC3 can be greater than (as shown in Figure 7) or less than the duration of the first holding phase BC1.

[0112] To address the flickering issue, in some implementations, as shown in Figure 5 or Figure 6, when the refresh frequency of the display panel PNL is a second refresh frequency f2 and the second refresh frequency f2 is less than the first refresh frequency f1, the pulse signal further includes: a second pulse signal PWM2, the second pulse signal PWM2 including a second effective pulse PL2, the first pulse signal PWM1 including a first effective pulse PL1, the duty cycle of the second effective pulse PL2 being the same as the duty cycle of the first effective pulse PL1, and the duration of one second effective pulse PL2 being the same as the duration of one first effective pulse PL1.

[0113] In this embodiment, since the duty cycle of the second effective pulse PL2 is the same as that of the first effective pulse PL1, the duty cycles of the second effective pulse PL2 and the first effective pulse PL1 will not change with the refresh frequency, and the corresponding backlight current will not change with the refresh frequency, thereby eliminating the flicker problem.

[0114] To finely adjust the duty cycle of the second pulse signal PWM2, in some embodiments, as shown in Figure 5 or Figure 6, the second pulse signal PWM2 further includes a third effective pulse PL3. The duty cycle of the third effective pulse PL3 is the same as that of the first effective pulse PL1, and the duration of the third effective pulse PL3 is less than the duration of the first effective pulse PL1.

[0115] For example, as shown in Figure 5 or Figure 6, the duty cycles of the first effective pulse PL1, the second effective pulse PL2, and the third effective pulse PL3 are all 25%. The durations of the first effective pulse PL1 and the second effective pulse PL2 are the same, while the duration of the third effective pulse PL3 is shorter than that of the first effective pulse PL1 and the second effective pulse PL2. This allows for a more precise adjustment of the output quantity of the third effective pulse PL3 based on the duration of the second hold phase BC2, making the effective duty cycle of the second pulse signal PWM2 closer to that of the first pulse signal PWM1.

[0116] For example, as shown in Figure 5 or Figure 6, the first effective pulse PL1 overlaps with the first display period T1, and the start time of the first effective pulse PL1 is delayed by a first preset duration t1 relative to the start time of the first display period T1. The first preset duration t1 is, for example, greater than or equal to 0. The start time of the first display period T1 is, for example, the time point at which the first pixel row begins to refresh within the first display period T1 or the output time point of the frame start signal.

[0117] As shown in Figure 5, the first preset duration t1 is greater than 0 and less than the duration of the first refresh phase SX1. As shown in Figure 6, the first preset duration t1 is equal to the duration of the first refresh phase SX1.

[0118] For example, as shown in Figure 5 or Figure 6, the second effective pulse PL2 overlaps with the second display period T2, and the start time of the second effective pulse PL2 is also delayed by a first preset time t1 relative to the start time of the second display period T2. The start time of the second display period T2 is, for example, the time point at which the first pixel row begins to refresh within the second display period T2 or the output time point of the frame start signal.

[0119] For example, as shown in Figure 5 or Figure 6, the start time of the third effective pulse PL3 adjacent to the second effective pulse PL2 is delayed by a second preset duration t2 relative to the start time of the second effective pulse PL2. The second preset duration t2 is equal to the duration of the first refresh phase SX1.

[0120] As shown in Figure 5 or Figure 6, when the refresh frequency of the display panel PNL is the second refresh frequency f2, within one display cycle (such as the second display cycle T2), the second pulse signal PWM2 first outputs a second valid pulse PL2, and then outputs one or more third valid pulses PL3 until the end of the display cycle.

[0121] For example, the duration of the third effective pulse PL3 and the center interval duration of two adjacent third effective pulses PL3 can be calculated in units of pixel rows. For example, the center interval duration of two adjacent third effective pulses PL3 is the sum of the refresh duration of 32 pixel rows, and the duration of the third effective pulse PL3 is the sum of the refresh duration of 8 pixel rows.

[0122] Since the duty cycles of the first effective pulse PL1, the second effective pulse PL2, and the third effective pulse PL3 are the same, the amplitudes of the first effective pulse PL1, the second effective pulse PL2, and the third effective pulse PL3 can be set to be the same, that is, the backlight current corresponding to the first effective pulse PL1, the second effective pulse PL2, and the third effective pulse PL3 is the same.

[0123] In some implementations, as shown in FIG5, the first effective pulse PL1 overlaps with the first refresh phase SX1 but does not overlap with the first hold phase BC1.

[0124] In some implementations, as shown in FIG5, the second display period T2 includes a second refresh phase SX2 and a second hold phase BC2, the second effective pulse PL2 overlaps with the second refresh phase SX2, and the third effective pulse PL3 overlaps with the second hold phase BC2.

[0125] For example, as shown in FIG5, the second effective pulse PL2 does not overlap with the second hold phase BC2, and the third effective pulse PL3 does not overlap with the second refresh phase SX2.

[0126] For example, as shown in Figure 5, the second refresh phase SX2 has the same duration as the first refresh phase SX1, and the second hold phase BC2 has a longer duration than the first hold phase BC1.

[0127] In some implementations, as shown in FIG6, the first effective pulse PL1 overlaps with the first hold phase BC1. Further, as shown in FIG6, the first effective pulse PL1 is within the time range of the first hold phase BC1.

[0128] In some implementations, as shown in FIG6, the second display period T2 includes a second refresh phase SX2 and a second hold phase BC2, and the second effective pulse PL2 and the third effective pulse PL3 overlap with the second hold phase BC2. Further, as shown in FIG6, both the second effective pulse PL2 and the third effective pulse PL3 are within the time range of the second hold phase BC2.

[0129] For example, the frequency of the third effective pulse PL3 is greater than or equal to 0.5KHz and less than or equal to 100KHz or 25KHz.

[0130] For example, the frequency of the first effective pulse PL1 is greater than or equal to the first refresh frequency f1, and less than or equal to ten times the first refresh frequency f1, such as the frequency of the first effective pulse PL1 being equal to twice the first refresh frequency f1.

[0131] For example, as shown in Figure 7, the effective pulse frequency of the third pulse signal PWM3 is equal to the third refresh frequency f3.

[0132] In some implementations, as shown in FIG8, the first pulse signal PWM1 includes a first effective pulse PL1, the first effective pulse PL1 is within the time range of the first hold phase BC1, the duration of the first effective pulse PL1 is less than the duration of the first hold phase BC1, and the end time of the first effective pulse PL1 is the same as the end time of the first hold phase BC1.

[0133] In this embodiment, the liquid crystal can continue to deflect during the time between the end of the first refresh phase SX1 and the start of the first effective pulse PL1, so that the liquid crystal can be better deflected to the target position, further reducing the trailing problem and improving the display effect.

[0134] For example, when the first refresh frequency f1 is greater than or equal to the first threshold, the frequency of the first pulse signal PWM1 is equal to the first refresh frequency f1. The first threshold is, for example, greater than or equal to 100Hz, such as 120Hz or 200Hz.

[0135] As shown in Figures 5 to 7, since the first refresh frequency f1 is 240Hz, which is greater than the first threshold of 200Hz, the effective pulse frequency of the first pulse signal PWM1 is equal to the first refresh frequency f1.

[0136] To avoid flickering, in some implementations, when the first refresh frequency f1 is less than a first threshold, the frequency of the first pulse signal PWM1 is greater than the first refresh frequency f1, but less than or equal to ten times the first refresh frequency f1. As shown in Figure 9, the frequency of the first pulse signal PWM1 is equal to twice the first refresh frequency f1, that is, two first valid pulses PL1 are output within the first display period T1.

[0137] For example, the frequency of the third effective pulse PL3 is greater than or equal to 200Hz.

[0138] As shown in Figure 9, the display panel PNL includes two display units UN. In one display cycle, the first pulse signal PWM1 includes two first effective pulses PL1. One first effective pulse PL1 is located in the first refresh stage SX1, and the other first effective pulse PL1 is located in the first hold stage BC1. The first effective pulse PL1 located in the first refresh stage SX1 overlaps with the refresh at the junction of the two display units UN.

[0139] For example, for each display unit UN, the overshoot rate of multiple display partitions A0 can be increased sequentially along the scanning direction fs, for example from 40% to 100%.

[0140] For example, the frequency of the pulse signal is greater than or equal to 200 Hz and less than or equal to 25 kHz.

[0141] In some embodiments, the backlight BL includes a light-emitting element, which comprises a light-emitting diode (LED) chip and a color conversion unit. The inventors have discovered that when the LED uses fluoride (KSF) phosphor as the color conversion unit, there is afterglow when the LED is turned off, and a red flicker occurs when the backlight is driven by a pulse signal. To solve this red flicker problem, for example, the color conversion unit of the light-emitting element uses a non-KSF phosphor with a response time of less than 1 ms, thereby reducing the response time of the color conversion unit to less than 1 ms.

[0142] The structure of the light-emitting element will be described in detail below with reference to Figures 11 and 12.

[0143] Figure 11 illustrates an exemplary structural schematic diagram of a light-emitting element. As shown in Figure 11, the light-emitting element 100 includes an LED chip 10 and a color conversion unit 20, with the color conversion unit 20 located at least on the light-emitting side of the LED chip 10. The LED chip 10 emits blue light or a mixture of blue and green light. The color conversion unit 20 is used to convert the light emitted by the LED chip 10 into white light.

[0144] The response time of the color conversion unit 20 is less than 1ms. Response time refers to the time required for the luminous intensity of the color conversion unit to decay to a set percentage of its initial intensity after the light-emitting element is powered off (or the LED chip stops emitting light), with the set percentage being 10%. In other words, when the LED chip is turned off, the color conversion unit 20 can be considered to stop emitting light within this response time. Because the response time of the color conversion unit 20 is short, less than 1ms, the aforementioned flickering red problem can be solved.

[0145] The response time can be tested as follows: Excite the sample in the color conversion unit 20 to saturation using a short-pulse light source (the wavelength can be the same as the wavelength of the blue light emitted by the LED chip), and immediately turn off the excitation source; then, use a detector to record the decay curve of the sample's luminous intensity over time; finally, perform exponential fitting on the decay curve to determine the response time. The first two steps of this test can be performed in a darkroom environment.

[0146] Optionally, the color conversion section 20 is a photoluminescent layer. For example, the color conversion section 20 includes color conversion particles 22. The response time of the color conversion particles 22 is less than 1 ms. Optionally, the type of color conversion particles includes phosphors or quantum dots, etc. When the color conversion particles are phosphors, the response time of the color conversion section 20 is the afterglow time of the phosphor.

[0147] Optionally, the color conversion section 20 further includes a matrix 21 in which color conversion particles 22 are distributed. Exemplarily, the material of the matrix 21 includes at least one of silicone resin, epoxy resin, and polyurethane.

[0148] As mentioned above, when the color conversion unit 20 contains KFS phosphor, a red flash problem is likely to occur. Therefore, in this embodiment of the present disclosure, the color conversion unit 20 does not contain KSF phosphor.

[0149] In some examples, the LED chip 10 is a blue light chip, and the color conversion unit 20 is used to convert the blue light emitted by the LED chip 10 into white light. Exemplarily, the color conversion unit 20 can emit red and green light when excited by a portion of the blue light emitted by the LED chip 10, and the resulting red and green light, along with another portion of the blue light emitted by the LED chip 10, mix to produce white light.

[0150] For example, the color conversion particles in the color conversion unit 20 include color conversion particles for emitting red light and color conversion particles for emitting green light. The material of the color conversion particles for emitting red light includes one or more of nitride phosphors (e.g., silicon-based nitride phosphors), rare earth silicate phosphors, and yttrium aluminum garnet (YAG) phosphors. The material of the color conversion particles for emitting green light includes one or more of silicate phosphors and nitride phosphors.

[0151] Nitride phosphors possess high electron mobility and short carrier lifetime, achieving response times in the nanosecond range (approximately 20 μs), thus accelerating the switching speed of the light-emitting element and resolving the red flashing issue. Silicate phosphors have response times of approximately 2 μs, and aluminate phosphors have response times of approximately 30 μs, both reaching the nanosecond level. Therefore, the response time of the color conversion unit 20 is less than 1 ms.

[0152] For example, the color conversion particles include red quantum dots and green quantum dots. The response time of red quantum dots and green quantum dots can both reach the nanosecond level. Therefore, the response time of the color conversion unit 20 is less than 1 ms.

[0153] In other examples, LED chip 10 is a blue-green LED chip. The color conversion unit 20 can emit red light when excited by a portion of the blue light emitted by LED chip 10. The resulting red light, along with the green light emitted by the LED chip and another portion of the blue light, mix to produce white light.

[0154] For example, the color conversion particles in the color conversion unit 20 include color conversion particles for emitting red light. The material of the color conversion particles for emitting red light includes one or more of nitride phosphors (e.g., silicon-based nitride phosphors), rare earth silicate phosphors, and YAG phosphors, or the color conversion particles for emitting red light include red quantum dots.

[0155] In some other examples, LED chip 10 is a blue-red LED chip. The color conversion unit 20 can emit green light when excited by a portion of the blue light emitted by LED chip 10. The green light produced, along with the red light emitted by LED chip and another portion of blue light, mix to produce white light.

[0156] For example, the color conversion particles in the color conversion unit 20 include color conversion particles for emitting green light. The material of the color conversion particles for emitting green light includes one or more of silicate phosphors and nitride phosphors. As another example, the color conversion particles for emitting green light include green quantum dots.

[0157] Optionally, in the three examples described above, the color conversion particles in the color conversion unit 20 may further include color conversion particles for emitting yellow light. The material of the color conversion particles for emitting yellow light includes one or more of nitride phosphors, silicate phosphors, and YAG phosphors; or includes yellow quantum dots.

[0158] In some other examples, LED chip 10 is a blue LED chip. The color conversion unit 20 can emit yellow light when excited by a portion of the blue light emitted by LED chip 10. The generated yellow light mixes with another portion of the blue light emitted by LED chip to produce white light.

[0159] It should be noted that the embodiments disclosed herein do not limit the emission color of the phosphor contained in the color conversion unit 20, as long as it can cooperate with the LED chip 20 to produce white light and the response time is less than 1ms.

[0160] Table 1 lists the specific types of phosphors that emit red, green, and yellow light.

[0161] The specific types of phosphors with different emitting colors can be found in Table 1 above. The response times of the phosphors in Table 1 are all less than 1ms, which can solve the aforementioned red flickering problem. Therefore, in this embodiment, using a blue LED chip in conjunction with the color conversion unit 20 can improve the color gamut while solving the red flickering problem.

[0162] The structure of the blue-green LED chip is illustrated below with reference to Figure 12.

[0163] Figure 12 illustrates an exemplary structural schematic diagram of an LED chip. As shown in Figure 12, the LED chip 10 includes an electroluminescent layer 1 and a first photoluminescent layer 2.

[0164] For example, when the LED chip is a blue-green LED chip, the electroluminescent layer 1 is used to emit blue light under the action of the charge provided by the current when a current is applied; the first photoluminescent layer 2 is used to emit green light when excited by a portion of the blue light emitted by the electroluminescent layer 1. In this case, the aforementioned color conversion section 20 is a second photoluminescent layer, used to emit red light when excited by another portion of the blue light emitted by the electroluminescent layer 1.

[0165] For example, the electroluminescent layer 1 has a multi-quantum-well structure. Under the influence of the charge provided by the current, the multi-quantum-well structure acts as an active region of electron traps, capable of emitting blue light. For example, the material of the multi-quantum-well structure includes indium gallium nitride / gallium nitride, wherein the proportions of indium gallium in indium gallium nitride and gallium nitride are 0.15 and 0.85, respectively (which can be written as In). 0.15 Ga 0.85 N / GaN).

[0166] For example, the first photoluminescent layer 2 has a multiple quantum well structure. It emits green light when excited by blue light emitted from the electroluminescent layer 1. For instance, the material of the multiple quantum well structure includes indium gallium nitride / gallium nitride, wherein the proportions of indium gallium in indium gallium nitride and gallium nitride are 0.15 and 0.85, respectively (which can be written as In...). 0.15 Ga 0.85 N / GaN).

[0167] It should be noted that the proportion of indium gallium in indium gallium nitride in electroluminescent layer 1 and first photoluminescent layer 2 can be adjusted as needed, as long as electroluminescent layer 1 emits blue light under current drive and first photoluminescent layer 2 emits green light under blue light excitation.

[0168] In this embodiment, the electroluminescent layer 1 includes an electroluminescent wafer layer, and the first photoluminescent layer 2 includes a photoluminescent wafer layer. In some examples, the electroluminescent layer 1 and the first photoluminescent layer 2 can be disposed in the same crystal structure, such as the LED chip 10 shown in FIG. 12. Alternatively, the electroluminescent layer 1 and the first photoluminescent layer 2 can be an integral structure. For example, the LED chip 10 has two separate multiple quantum wells (MQWs) light-emitting regions, one of which is used to form the electroluminescent layer 1, and the other MQW is used to form the first photoluminescent layer 2.

[0169] As shown in Figure 12, in some optional embodiments, the electroluminescent layer 1 and the first photoluminescent layer 2 are stacked, and the second photoluminescent layer covers the first photoluminescent layer 2 and the electroluminescent layer 1.

[0170] In this embodiment, the LED chip 10 further includes a first electrode 3 and a second electrode 4. The first electrode 3 is connected to one side of the electroluminescent layer 1, and the second electrode 4 is connected to the opposite side of the electroluminescent layer 1. Exemplarily, the first electrode is connected to one side of the electroluminescent layer 1 along its thickness direction, and the first electrode 3 is connected to the opposite side of the electroluminescent layer 1 along its thickness direction.

[0171] As shown in Figure 12, in some optional embodiments, the LED chip 10 further includes a first semiconductor layer 11 and a second semiconductor layer 9.

[0172] In this embodiment, a first semiconductor layer 11, a first photoluminescent layer 2, an electroluminescent layer 1, and a second semiconductor layer 9 are sequentially stacked, with the color conversion unit 20 at least partially located on the side of the second semiconductor layer 9 away from the electroluminescent layer 1. The electroluminescent layer 1 includes a first multiple quantum well layer, and the first photoluminescent layer 2 includes a second multiple quantum well layer. The first electrode 3 is electrically connected to the second semiconductor layer 9, and the second electrode 4 is electrically connected to the first semiconductor layer 11.

[0173] Through the above embodiments, the structural design of the light-emitting element 100 is realized by utilizing the stacked arrangement of the electroluminescent layer 1, the first photoluminescent layer 2 and the color conversion unit 20, and the power supply requirements of the electroluminescence process and the radiation requirements of blue light on the first photoluminescent layer 2 and the color conversion unit 20 during the photoluminescence process are better met.

[0174] In some optional embodiments, the material of the first semiconductor layer 11 includes one of N-GaN and P-GaN, and the material of the second semiconductor layer 9 includes the other of N-GaN and P-GaN.

[0175] In some optional embodiments, the second semiconductor layer 9 includes a P-type semiconductor layer, and the first semiconductor layer 11 includes an N-type semiconductor layer. Exemplarily, the material of the second semiconductor layer 9 includes gallium nitride, and the material of the first semiconductor layer 11 includes gallium nitride.

[0176] For example, as shown in FIG12, the second semiconductor layer 9 includes a P++ type semiconductor layer 91 and a P type semiconductor layer 92. For example, the P++ type semiconductor layer 91 is a P++ type gallium nitride layer, and the P type semiconductor layer 92 is a P type gallium nitride layer.

[0177] For example, the N-type semiconductor layer is an N-type gallium nitride layer.

[0178] In some examples, the first electrode 3 is located on the side of the second semiconductor layer 9 away from the electroluminescent layer 1 and is in contact with the first semiconductor layer 11, which is in contact with the electroluminescent layer 1. Thus, the first electrode 3 is connected to the electroluminescent layer 1 through the first semiconductor layer 11.

[0179] In some examples, the second electrode 4 is disposed on the side of the first semiconductor layer 1 away from the substrate 6, and the thickness of the first semiconductor layer 11 located between the first photoluminescent layer 2 and the substrate 6 is greater than the thickness of the first semiconductor layer 11 located between the second electrode 4 and the substrate 6. For example, the first semiconductor layer 11 has a substrate structure close to the substrate 6 and a protrusion structure away from the substrate 6, the first photoluminescent layer 2 is disposed on the protrusion structure, and the second electrode 4 is disposed in the same layer as the protrusion structure and is spaced apart.

[0180] In some optional embodiments, the first electrode 3 is a P-type electrode and the second electrode 4 is an N-type electrode.

[0181] As shown in FIG12, in some optional embodiments, the light-emitting element 100 further includes an isolation layer 5 located between the first photoluminescent layer 2 and the electroluminescent layer 1.

[0182] Through the above embodiments, the isolation layer 5 can be used to block the transmission of charge carriers output from the second semiconductor layer 9 to the first photoluminescent layer 2.

[0183] For example, when the second semiconductor layer 9 is a P-type semiconductor layer, the material of the isolation layer 5 can be an N-type semiconductor, such as N-GaN.

[0184] For example, when the second semiconductor layer 9 is an N-type semiconductor layer, the material of the isolation layer 5 can be a P-type semiconductor, such as P-GaN.

[0185] In this configuration, a trace (not shown) can be provided in the LED chip 10, penetrating the first photoluminescent layer 2 and the insulating layer 5, allowing the second electrode 4 to be electrically connected to the electroluminescent layer 1 via the trace. In practice, vias can be formed in the first photoluminescent layer 2 and the insulating layer 5, with the trace located within the via and its two ends connected to the first semiconductor layer 11 and the electroluminescent layer 1, respectively. An insulating layer can be provided on the sidewalls of the via to prevent the trace from being energized by other structural layers.

[0186] As shown in Figure 12, in some optional embodiments, the LED chip 10 further includes a first reflective layer 7 located on the side of the first semiconductor layer 11 away from the second semiconductor layer 9.

[0187] For example, the first reflective layer 7 can be a distributed Bragg reflector (DBR).

[0188] Through the above embodiments, the high electron mobility and high saturation drift velocity of gallium nitride material are utilized to reduce losses in the electro-optical conversion process and improve the electroluminescence efficiency of LED chip 10. In addition, the first reflective layer 7 is used to reflect blue light, thereby improving the photoluminescence efficiency.

[0189] In an alternative embodiment, the LED chip 10 further includes a substrate 6. An electroluminescent layer 1 and a first photoluminescent layer 2 are stacked on the substrate 6.

[0190] In some alternative embodiments, the electroluminescent layer 1 is disposed on the side of the first photoluminescent layer 2 away from the substrate 6.

[0191] In some examples, the second semiconductor layer 9 is disposed on the side of the electroluminescent layer 1 away from the first photoluminescent layer 2, and the first semiconductor layer 11 is disposed between the first photoluminescent layer 2 and the substrate 6.

[0192] In some examples, substrate 6 can be a silicon substrate.

[0193] In one alternative implementation, the LED chip 10 further includes a second reflective layer 8. In some examples, the first reflective layer 7 is located on the side of the substrate 6 away from the first photoluminescent layer 2, and the second reflective layer 8 is located on the side of the second semiconductor layer 9 away from the electroluminescent layer 1.

[0194] For example, the second reflective layer 8 can be an indium tin oxide (ITO) layer.

[0195] Optionally, the LED chip 10 may further include a protective layer (not shown) located on the side of the second reflective layer 8 away from the second semiconductor layer 9. In some examples, the protective layer also extends to the side of the second semiconductor layer 9, the side of the electroluminescent layer 1, the side of the insulating layer 5, the side of the first photoluminescent layer 2, the side of the protrusion structure, and the side of the second electrode 4, and also extends to the surface of the substrate structure away from the substrate 6. Thus, the protective layer can appropriately isolate the chip structure, including the electroluminescent layer 1 and the first photoluminescent layer 2, from the color conversion section 20, thereby protecting the chip structure and improving the reflection capability of blue light, thereby enhancing the excitation efficiency of green light.

[0196] Optionally, the LED chip 10 also includes a buffer layer 12. The buffer layer 12 is located between the substrate 6 and the first semiconductor layer 11 and serves as a buffer.

[0197] Figure 13 exemplarily illustrates the emission spectrum of the LED chip shown in Figure 12. In Figure 13, the dashed box represents the wavelength of light emitted by the LED chip when driven by a current of 20mA. As can be seen from Figure 13, the LED chip can emit blue and green light when driven by a current of 20mA.

[0198] Referring to Figure 11, at least part of the color conversion section 20 is located on the side of the electroluminescent layer 1 away from the first photoluminescent layer 2 in Figure 12. That is, the light-emitting side of the LED chip 10 is located on the side of the electroluminescent layer 1 away from the first photoluminescent layer 2.

[0199] As shown in Figure 11, in some optional embodiments, the light-emitting element 100 further includes a support 33, which includes a receiving groove. The color conversion part 20 and the LED chip 10 are located within the receiving groove.

[0200] In some examples, the support 33 can be bowl-shaped. The support 33 is disposed on the side of the first reflective layer 7 away from the substrate 6, and the support 33 also extends along the thickness direction of the substrate 6 to the side of the LED chip 10 and the color conversion part 20, thereby protecting the LED chip 10 and the color conversion part 20.

[0201] In this embodiment, the color conversion unit 20 is also located on the periphery of the stacked structure composed of the first semiconductor layer 11, the first photoluminescent layer 2, the electroluminescent layer 1, and the second semiconductor layer 9.

[0202] The above embodiments further improve the structural design of the light-emitting element 100 and enhance its luminous efficiency.

[0203] In some examples, a gap exists between the support 33 extending along the thickness direction of the substrate 6 and the LED chip 10, and the color conversion section 20 extends into this gap and wraps around the side of the LED chip 10. For example, the color conversion section 20 is sealed to both the side of the LED chip 10 and the inner side of the support 33, thereby improving the structural stability of the light-emitting element 100. Thus, the color conversion section 20 indirectly wraps around at least a portion of the surface of the electroluminescent layer 1, enabling it to better receive blue light, thereby being excited by blue light and improving the luminous efficiency of red light.

[0204] It should be noted that the structure of blue-red LED chips is similar to that of blue-green LED chips. The only difference is that the material of the first photoluminescent layer used to emit green light is replaced with the material of the first photoluminescent layer used to emit red light.

[0205] As shown in Figure 11, the light-emitting element 100 also includes a third electrode 31, a fourth electrode 32, a first metal line 34, and a second metal line 35.

[0206] In some examples, the third electrode 31 and the fourth electrode 32 can be mounted on the bracket 33 and connected to the power supply via wiring within the bracket 33. For example, the third electrode 31 is the positive electrode and the fourth electrode 32 is the negative electrode.

[0207] In some other examples, the third electrode 31 and the fourth electrode 32 may be mounted on different supports 33, and an insulating bridge may be provided between the support 33 where the third electrode 31 is located and the support 33 where the fourth electrode 32 is located, with the insulating bridge serving as an insulating protection.

[0208] In some examples, a first metal line 34 and a second metal line 35 are disposed in the fluorescent layer. The two ends of the first metal line 34 are connected to the first electrode 3 and the third electrode 31, respectively, and the two ends of the second metal line 35 are connected to the second electrode 4 and the fourth electrode 32, respectively.

[0209] For example, the first metal wire 34 and the second metal wire 35 can be gold wire or the like.

[0210] In other embodiments, the electroluminescent layer 1 may also be disposed between the first photoluminescent layer 2 and the substrate 6, or in other words, the electroluminescent layer 1 may be disposed on the side of the first photoluminescent layer 2 closer to the substrate 6. Exemplarily, the color conversion section 20 is located on the side of the first photoluminescent layer 2 away from the electroluminescent layer 1.

[0211] Through the above embodiments, the structural design of the LED chip is realized by utilizing the stacked arrangement of the electroluminescent layer 1, the first photoluminescent layer 2 and the color conversion unit 20, and the power supply requirements of the electroluminescence process and the blue light radiation requirements of the photoluminescence process are better met.

[0212] In one example provided in this disclosure, the first reflective layer 7 is located on one side of the bracket 33.

[0213] In this example, substrate 6 is located on the side of the first reflective layer 7 away from the support 33. Buffer layer 12 is located on the side of substrate 6 away from the first reflective layer 7.

[0214] In this example, the first semiconductor layer 11 is located on the side of the buffer layer 12 away from the substrate 6. The first semiconductor layer 11 includes a first semiconductor region and a second semiconductor region along the laying direction.

[0215] In this example, the thickness of the second semiconductor region is greater than the thickness of the first semiconductor region.

[0216] In this example, the second electrode 4 is located on the side of the first semiconductor region away from the buffer layer 12, and is connected to the electroluminescent layer 1 through the first semiconductor region, the second semiconductor region, the first photoluminescent layer 2, and the isolation layer 5.

[0217] In this example, the first photoluminescent layer 2 is located on the side of the second semiconductor region away from the buffer layer 12. The isolation layer 5 is located on the side of the first photoluminescent layer 2 away from the second semiconductor region. The second semiconductor layer 9 is located on the side of the electroluminescent layer 1 away from the isolation layer 5. The first semiconductor layer 11 and the second semiconductor layer 9 have different conductivity types. The second reflective layer 8 is located on the side of the second semiconductor layer 9 away from the electroluminescent layer 1.

[0218] In this example, the first electrode 3 is located on the side of the second reflective layer 8 away from the second semiconductor layer 9, and is connected to the electroluminescent layer 1 through the second reflective layer 8 and the second semiconductor layer 9.

[0219] The above example further improves the structural design of LED chip 10.

[0220] To achieve high brightness display, the light-emitting element is, for example, a dual-crystal LED lamp. A dual-crystal LED lamp is an LED lighting product that uses dual-chip packaging technology. By integrating two independent light-emitting chips (usually with different color temperatures or colors) in the same package structure, it achieves more flexible light efficiency control and performance improvement.

[0221] For example, the light-emitting element can achieve a brightness of 1000 nits while realizing 100% DCI-P3 color gamut.

[0222] In some optional embodiments, the backlight BL includes a light source, which can be strip-shaped or surface-shaped. For example, each or multiple light-emitting elements constitute a lamp bead, and the lamp beads are arranged in one or more rows along the substrate to form a light source.

[0223] In some examples, the backlight is a direct-lit backlight, in which case the light source emits light in a planar manner. Exemplarily, the light source includes a substrate and a plurality of the aforementioned light-emitting elements, with the plurality of light-emitting elements arrayed on the substrate.

[0224] Optionally, the backlight also includes an optical film layer located on the light-emitting surface of the light source for uniform light distribution. Optionally, the optical film layer includes one or more of a diffusion layer, a uniform light distribution layer, and a brightness enhancement layer.

[0225] Figure 14 illustrates an exemplary schematic diagram of a direct-lit backlight. As shown in Figure 14, the backlight BL includes a substrate 130, a plurality of light-emitting elements 100, and an optical film layer. The plurality of light-emitting elements 100 are arranged in an array on the substrate 130. The light-emitting surfaces of the light-emitting elements 100 are disposed opposite to the display panel (not shown), and the optical film layer is located between the light-emitting elements 100 and the display panel.

[0226] In some examples, as shown in FIG14, the optical film layer includes: a first diffusion layer 131, a light-diffusing layer 132, a brightness-enhancing layer 133, and a second diffusion layer 134. The first diffusion layer 131 is stacked on the side of the light-emitting element 100 away from the substrate 130; the light-diffusing layer 132 is stacked on the side of the first diffusion layer 131 away from the substrate 130; the brightness-enhancing layer 133 is stacked on the side of the light-diffusing layer 132 away from the first diffusion layer; and the second diffusion layer 134 is stacked on the side of the brightness-enhancing layer 133 away from the light-diffusing layer 132, and the second diffusion layer 134 is located between the brightness-enhancing layer 133 and the display panel.

[0227] In other examples, the backlight is a side-lit backlight, in which case the light source emits light in a strip shape. Exemplarily, the light source includes a substrate (i.e., a light strip), and the light-emitting elements are disposed on the substrate.

[0228] The side-lit backlight also includes a reflective layer, a light guide plate, and an optical film layer. The light guide plate is stacked on one side of the reflective layer. The optical film layer is stacked on the side of the light guide plate away from the reflective layer. The light source is located on one side of the light guide plate along its light-guiding direction, and the light-emitting element is located between the substrate and the light guide plate.

[0229] Optionally, the optical film layer includes one or more of a diffusion layer and a brightness enhancement layer.

[0230] Figure 15 illustrates a schematic diagram of a side-lit backlight. As shown in Figure 15, the backlight BL includes a light-emitting element 100, a reflective layer 141, a light guide plate 142, and an optical film layer.

[0231] Exemplarily, the optical film layer includes a first diffusion layer 143, a brightness enhancement layer 144, and a second diffusion layer 145. The first diffusion layer 143 is stacked on the side of the light guide plate 142 away from the reflective layer 141. The brightness enhancement layer 144 is stacked on the side of the first diffusion layer 143 away from the light guide plate 142. The second diffusion layer 145 is stacked on the side of the brightness enhancement layer 143 away from the first diffusion layer 143 and is located between the display panel (not shown) and the brightness enhancement layer 144.

[0232] For example, the driving circuit DR includes a timing controller TCON, which is configured to receive a display command. If the command indicates entering a first display mode, a pulse signal is provided to the backlight BL, and overshoot driving is performed on the display partition A0. The overshoot rate of the first display partition A01 is different from that of the second display partition A02. If the display command indicates entering a second display mode, a DC signal is provided to the backlight BL, and overshoot driving is performed on multiple display partitions A0. The overshoot rates of the different display partitions are the same.

[0233] For example, as shown in Figure 10, the driving circuit DR also includes a light source driver (LED Driver). In a specific implementation, the timing controller (TCON) can determine the corresponding backlight current based on the duty cycle of the pulse signal, and control the light source driver (LED Driver) to output a backlight driving signal corresponding to the duty cycle and backlight current to the backlight source BL via I2C commands.

[0234] For example, the display panel PNL includes two display modes, namely a first display mode and a second display mode. The first display mode can be used for video playback or playing games, while the second display mode can be used for regular browsing or office work.

[0235] For example, a user cannot enter the second display mode at a refresh rate of 100Hz. To improve the display effect, the user can enter the second display mode at a refresh rate of 200Hz or higher.

[0236] As shown in Figure 10a, the first display mode and the second display mode can be switched by controlling the BOOST pin. In this case, the display command is the BOOST command input by the BOOST pin. When the BOOST command switches from low level to high level, it indicates that the first display mode is switched to the second display mode.

[0237] As shown in Figure 10b, the first display mode and the second display mode can also be switched using AUX commands. In this case, the AUX commands include the AUX-P command and the AUX-N command. The AUX-P command indicates entering the first display mode, and the AUX-N command indicates entering the second display mode.

[0238] This disclosure provides a display device, including any of the aforementioned display modules.

[0239] Those skilled in the art will understand that the display device provided in this disclosure has the advantages of the above-described display module.

[0240] The display device disclosed herein can be any product or component with display function, such as a game console, mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, in-vehicle display device, smartwatch, fitness wristband, personal digital assistant, etc.

[0241] In some examples, the display device is a laptop, game console, or monitor. In practice, game consoles, monitors, or laptops often require high refresh rates during operation, making the aforementioned display module particularly suitable.

[0242] This disclosure provides a display driving method applicable to any of the aforementioned display modules. As shown in Figure 10, the display module includes a display panel PNL and a backlight BL. The display panel PNL includes multiple display partitions A0 arranged along the scanning direction fs, and the multiple display partitions A0 include a first display partition A01 and a second display partition A02. The display driving method includes:

[0243] Step S01: Obtain the display command.

[0244] Step S02: If the display command indicates to enter the first display mode, a pulse signal is provided to the backlight BL, and overshoot driving is performed on multiple display zones A0. The overshoot rate of the first display zone A01 is different from the overshoot rate of the second display zone A02. The overshoot rate is the proportion of the actual driving value of the display zone A0 deviating from the target driving value.

[0245] The execution entity of the display driving method provided in this embodiment can be, for example, the driving circuit DR in the aforementioned display module.

[0246] In some embodiments, after step S01, the display driving method further includes:

[0247] Step S03: If the display command indicates that the second display mode is entered, a DC signal is provided to the backlight BL, and overshoot drive is performed on multiple display zones A0, and the overshoot rate of different display zones A0 is the same.

[0248] In the second display mode, since the backlight driving signal is a DC signal, the backlight remains constantly on throughout the display process. Therefore, to improve the display effect, for example, the overshoot rate of each display zone A0 can be between 12% and 20%. If the overshoot rate is too high, ghosting (i.e., shadows with reversed colors) will be seen; if the overshoot rate is too low, motion blur (i.e., shadows of the same color but lighter) will appear.

[0249] For example, the display panel PNL has two display modes, namely a first display mode and a second display mode. The first display mode can be used for video playback or playing games, while the second display mode can be used for regular browsing or office work.

[0250] For example, users cannot enter the second display mode when the refresh rate is below 100Hz. To improve the display effect, users can enter the second display mode when the refresh rate is above 200Hz.

[0251] As shown in Figure 10a, the first display mode and the second display mode can be switched by controlling the BOOST pin. In this case, the display command is the BOOST command input by the BOOST pin. When the BOOST command switches from low level to high level, it indicates that the display mode is switched from the first display mode to the second display mode.

[0252] As shown in Figure 10b, the first display mode and the second display mode can also be switched using AUX commands. In this case, the AUX commands include the AUX-P command and the AUX-N command. The AUX-P command indicates entering the first display mode, and the AUX-N command indicates entering the second display mode.

[0253] As shown in Figure 16, when switching from the first display mode to the second display mode, the BOOST instruction switches from low level to high level. The effective pulse of the pulse signal PWM is delayed by about 1.6ms relative to the switching time of the BOOST instruction. This delay causes the backlight to dim briefly, which can cover the brightness change that occurs during the process of switching the backlight from DC drive to pulse drive.

[0254] In embodiments of this disclosure, relational terms such as first and second are used merely to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0255] In the embodiments of this disclosure, "electrical connection" and "coupling" include situations where constituent elements are connected together by a component having some electrical function. There are no particular limitations on the "component having some electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0256] In this disclosure, "multiple" means two or more, and "at least one" means one or more, unless otherwise explicitly specified. "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C," both including the following combinations of A, B, and C: A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C. "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0257] The use of “for” or “configured to” in this disclosure implies an open and inclusive language that does not preclude applicability to or configuration to devices for performing additional tasks or steps.

[0258] As used in this disclosure, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0259] As used in this disclosure, "parallel," "perpendicular," "equal," and "flush" include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the error associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein an acceptable deviation range for approximate parallelism may be, for example, within 10° or 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein an acceptable deviation range for approximate perpendicularity may also be, for example, within 10° or 5°. "Equal" includes absolute equality and approximate equality, wherein an acceptable deviation range for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one. "Flush" includes absolute flush and approximate flush, wherein an acceptable deviation range for approximate flush may be, for example, a distance between the flushes being less than or equal to 5% of either one's dimension.

[0260] The above description is merely an optional embodiment of this disclosure and is not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A display module, comprising: The display panel includes multiple display zones arranged along the scanning direction, wherein the multiple display zones include a first display zone and a second display zone; A backlight source, located on the backlight side of the display panel, is configured to provide backlight to the display panel. The backlight source includes a light-emitting element, which includes a light-emitting diode chip and a color conversion section located at least on the light-emitting side of the light-emitting diode chip. The light-emitting color of the light-emitting diode chip is blue light, a mixture of blue and green light, or a mixture of blue and red light. as well as The driving circuit, which is connected to the plurality of display zones and the backlight respectively, is configured to provide a pulse signal to the backlight in a first display mode and perform overshoot driving on the plurality of display zones, wherein the overshoot rate of the first display zone is different from the overshoot rate of the second display zone, and the overshoot rate is the proportion of the actual driving value of the display zone deviating from the target driving value. The response time of the color conversion unit is less than 1ms.

2. The display module according to claim 1, wherein, The first display partition and the second display partition are arranged sequentially along the scanning direction, and the overshoot rate of the second display partition is greater than that of the first display partition.

3. The display module according to claim 2, wherein, Along the scanning direction, the overshoot rate of multiple display zones in the display panel increases sequentially.

4. The display module according to claim 2, wherein, The plurality of display partitions further includes: a third display partition located on the side of the second display partition away from the first display partition, wherein the overshoot rate of the third display partition is less than the overshoot rate of the second display partition; or The fourth display partition is located on the side of the first display partition that is far from the second display partition, and the overshoot rate of the fourth display partition is greater than that of the first display partition.

5. The display module according to claim 1, wherein, One display cycle of the display panel includes a refresh phase and a hold phase, and the effective pulse of the pulse signal is located within the time range of the hold phase; and Along the scanning direction, the overshoot rate of multiple display zones in the display panel increases sequentially.

6. The display module according to claim 1, wherein, The plurality of display zones also includes a fifth display zone and a sixth display zone arranged sequentially along the scanning direction. The effective pulse of the pulse signal overlaps with the refresh of the fifth display zone but does not overlap with the refresh of the sixth display zone. and The overshoot rate of the fifth display partition is greater than that of the sixth display partition, and along the scanning direction, the overshoot rate of the sixth display partition and at least one display partition located on the side of the sixth display partition away from the fifth display partition increases sequentially.

7. The display module according to claim 1, wherein, The display panel includes multiple display units, and different display units include the same number of display partitions. The multiple display partitions in each display unit are sorted along the scanning direction, and the overshoot rates of display partitions with the same sequence number in different display units are approximately the same.

8. The display module according to claim 1, wherein, A display cycle of the display panel includes a refresh phase and a hold phase. When the refresh frequency of the display panel is a first refresh frequency, a display cycle of the display panel includes a first refresh phase and a first hold phase. The pulse signal includes a first pulse signal, and the duty cycle of the first pulse signal is less than or equal to the duration of the first hold phase in a display cycle.

9. The display module according to claim 8, wherein, When the refresh rate of the display panel is a second refresh rate and the second refresh rate is less than the first refresh rate, the pulse signal further includes: The second pulse signal includes a second effective pulse, the first pulse signal includes a first effective pulse, the duty cycle of the second effective pulse is the same as the duty cycle of the first effective pulse, and the duration of one second effective pulse is the same as the duration of one first effective pulse.

10. The display module according to claim 9, wherein, The second pulse signal also includes a third effective pulse, the duty cycle of which is the same as that of the first effective pulse, and the duration of one third effective pulse is less than the duration of one first effective pulse.

11. The display module according to claim 10, wherein, The first effective pulse overlaps with the first display cycle, and the start time of the first effective pulse is delayed by a first preset time relative to the start time of the first display cycle; The second valid pulse overlaps with the second display cycle, and the start time of the second valid pulse is delayed by the first preset duration relative to the start time of the second display cycle; The start time of the third effective pulse adjacent to the second effective pulse is delayed by a second preset duration relative to the start time of the second effective pulse, and the second preset duration is equal to the duration of the first display cycle.

12. The display module according to claim 11, wherein, The first valid pulse overlaps with the first refresh phase; The second display cycle includes a second refresh phase and a second hold phase, the second valid pulse overlaps with the second refresh phase, and the third valid pulse overlaps with the second hold phase.

13. The display module according to claim 11, wherein, The first effective pulse overlaps with the first hold phase; The second display cycle includes a second refresh phase and a second hold phase, and the second effective pulse and the third effective pulse overlap with the second hold phase.

14. The display module according to claim 13, wherein, The first valid pulse is within the time range of the first hold phase, and the second valid pulse and the third valid pulse are both within the time range of the second hold phase.

15. The display module according to claim 8, wherein, The duty cycle of the first pulse signal is equal to the proportion of the duration of the first hold phase in a display cycle; When the refresh frequency of the display panel is the third refresh frequency, one display cycle of the display panel includes a third refresh phase and a third hold phase. The pulse signal also includes a third pulse signal, and the duty cycle of the third pulse signal is equal to the duration of the third hold phase in one display cycle. and The third refresh frequency is different from the first refresh frequency, the third refresh phase has the same duration as the first refresh phase, and the third hold phase has a different duration than the first hold phase.

16. The display module according to claim 8, wherein, The duty cycle of the first pulse signal is less than the duration of the first hold phase in a display cycle; The first pulse signal includes a first valid pulse, which is located within the time range of the first hold phase. The duration of the first valid pulse is less than the duration of the first hold phase, and the end time of the first valid pulse is the same as the end time of the first hold phase.

17. The display module according to claim 8, wherein, When the first refresh frequency is greater than or equal to the first threshold, the frequency of the first pulse signal is equal to the first refresh frequency; when the first refresh frequency is less than the first threshold, the frequency of the first pulse signal is greater than the first refresh frequency and less than or equal to ten times the first refresh frequency.

18. The display module according to claim 1, wherein, The frequency of the pulse signal is greater than or equal to 200Hz and less than or equal to 25KHz.

19. The display module according to claim 1, wherein, The backlight is a side-lit backlight, which includes a light strip and a light guide plate. The light-emitting elements are arranged on the light strip, and the light-emitting surfaces of the light-emitting elements are opposite to the side of the light guide plate. The backlight is a direct-lit backlight, which includes an optical film layer and a plurality of light-emitting elements arranged in an array. The light-emitting surface of the light-emitting elements is disposed opposite to the display panel, and the optical film layer is located between the light-emitting elements and the display panel.

20. The display module according to any one of claims 1 to 19, wherein, The color conversion unit includes color conversion particles; The color conversion particles are made of one or more of nitride phosphors, silicate phosphors, and yttrium aluminum garnet phosphors, or the color conversion particles are made of quantum dots.

21. The display module according to any one of claims 1 to 19, wherein, The light-emitting diode chip emits blue light, and the color conversion unit includes phosphors for emitting red light and phosphors for emitting green light; or, the light-emitting diode chip emits a mixture of blue and green light, and the color conversion particles include phosphors for emitting red light; or, the light-emitting diode chip emits a mixture of blue and red light, and the color conversion particles include phosphors for emitting green light. The phosphor used to emit red light includes one or more of nitride phosphors and silicate phosphors, and the phosphor used to emit green light includes one or more of nitride phosphors and silicate phosphors.

22. The display module according to claim 21, wherein, The nitride phosphor used to emit red light includes one or more of the following: CaAlSiN3, (Sr,Ca)AlSiN3, CaAlSi(ON)3, Sr2SiN8; The silicate phosphor used to emit red light includes: Y2SiO5; The nitride phosphor used to emit green light includes one or more of the following: La3Si6N 11 (La,Y)3Si6N 11 The silicate phosphors used to emit green light include one or more of the following: BaSi2O2N2, (Si,Al)6(ON)8, β-SiAlON; 23. The display module according to any one of claims 1 to 19, wherein, The color conversion unit includes phosphors for emitting yellow light, wherein the phosphors for emitting yellow light include one or more of nitride phosphors, silicate phosphors, and yttrium aluminum garnet.

24. The display module according to claim 20, wherein, The color conversion section does not contain fluoride phosphors.

25. The display module according to claim 20, wherein, The color conversion section further includes a matrix, in which the color conversion particles are distributed, and the matrix material includes at least one of silicone resin, epoxy resin and polyurethane.

26. The display module according to any one of claims 1 to 19, wherein, The light-emitting diode chip includes: An electroluminescent layer is used to emit blue light when an electric current is applied. The first photoluminescent layer is used to emit green light when excited by a portion of the blue light; The color conversion section is a second photoluminescent layer, which is used to emit red light when excited by another portion of the blue light; The electroluminescent layer is stacked with the first photoluminescent layer, and the second photoluminescent layer covers the first photoluminescent layer and the electroluminescent layer.

27. The display module according to claim 26, wherein, The light-emitting diode chip further includes a first semiconductor layer, a second semiconductor layer, a first electrode, and a second electrode. The first semiconductor layer, the first photoluminescent layer, the electroluminescent layer and the second semiconductor layer are stacked sequentially, and the second photoluminescent layer is at least partially located on the side of the second semiconductor layer away from the electroluminescent layer; The electroluminescent layer includes a first multiple quantum well layer, and the first photoluminescent layer includes a second multiple quantum well layer; The first electrode is electrically connected to the second semiconductor layer, and the second electrode is electrically connected to the first semiconductor layer.

28. The display module according to claim 27, wherein, The light-emitting diode chip also includes an isolation layer located between the first photoluminescent layer and the electroluminescent layer.

29. The display module according to claim 27, wherein, The material of the first semiconductor layer includes one of N-GaN and P-GaN, and the material of the second semiconductor layer includes the other of N-GaN and P-GaN; The light-emitting diode chip also includes a first reflective layer located on the side of the first semiconductor layer away from the second semiconductor layer.

30. The display module according to any one of claims 27 to 29, wherein, The light-emitting element further includes a support, the support including a receiving groove, wherein the first semiconductor layer, the first photoluminescent layer, the electroluminescent layer, the second semiconductor layer and the second photoluminescent layer are located within the receiving groove; The second photoluminescent layer is also located on the periphery of the stacked structure formed by the first semiconductor layer, the second semiconductor layer, the first semiconductor layer, the first photoluminescent layer, the electroluminescent layer and the second semiconductor layer.

31. The display module according to any one of claims 1 to 19, claim 22, claims 24 to 25, and 27 to 29, wherein, The driving circuit includes a timing controller configured to receive a display command. If the command indicates entry into the first display mode, a pulse signal is provided to the backlight, and overshoot driving is performed on multiple display zones, wherein the overshoot rate of the first display zone is different from that of the second display zone. If the display command indicates entry into the second display mode, a DC signal is provided to the backlight, and overshoot driving is performed on multiple display zones, wherein the overshoot rate of different display zones is the same.

32. A display device comprising a display module as described in any one of claims 1 to 31, wherein the display device is a laptop computer, a game console, or a monitor.

33. A display driving method applied to a display module, the display module including a display panel and a backlight, the display panel including a plurality of display zones arranged along a scanning direction, the plurality of display zones including a first display zone and a second display zone, the backlight including a light-emitting element, the light-emitting element including a light-emitting diode chip and a color conversion section at least located on the light-emitting side of the light-emitting diode chip, the light-emitting color of the light-emitting diode chip being blue light or a mixture of blue and green light or a mixture of blue and red light; wherein, The response time of the color conversion unit is less than 1ms; The display driving method includes: Get the display command; If the display command indicates entry into the first display mode, a pulse signal is provided to the backlight and overshoot driving is performed on the multiple display zones. The overshoot rate of the first display zone is different from the overshoot rate of the second display zone. The overshoot rate is the proportion of the actual driving value of the display zone deviating from the target driving value.

34. The display driving method according to claim 33, wherein, After the step of obtaining the display instruction, the display driving method further includes: If the display command indicates entry into the second display mode, a DC signal is provided to the backlight and overshoot drive is performed on multiple display zones, with the overshoot rate being the same for different display zones.

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