Signal processing circuit, chip and electronic device

Abstract

Provided in the embodiments of the present application are a signal processing circuit, a chip and an electronic device. The signal processing circuit comprises: an analog-to-digital conversion module and a signal amplification module; a first chopping switch module, the first chopping switch module being used for modulating a differential input signal to a high frequency under the control of a preset clock signal and inputting same to the signal amplification module; and a second chopping switch module, the second chopping switch module being used for modulating, under the control of a preset control signal, a differential output signal output by the signal amplification module to a low frequency and inputting same to the analog-to-digital conversion module, wherein under the control of the preset control signal, the second chopping switch module further enables the analog-to-digital conversion module to establish sampling. In the present application, the second chopping switch module is multiplexed as a sampling switch of the analog-to-digital conversion module, thus avoiding the problem of an increase in on resistance caused by providing both a chopping demodulation switch and a sampling switch.

Description

Signal processing circuits, chips and electronic devices

[0001] This application claims priority to Chinese Patent Application No. 202510191441.2, filed on February 20, 2025, entitled “Signal Processing Circuit, Chip and Electronic Device”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to the field of integrated circuit technology, specifically to a signal processing circuit, chip, and electronic device. Background Technology

[0003] Currently, programmable gain amplifiers (PGAs) are commonly used as pre-amplifiers in analog-to-digital converters (ADCs) to amplify input signals and improve the signal-to-noise ratio (SNR) of signal processing systems. In related technologies, PGAs often incorporate chopping techniques to eliminate the effects of operational amplifier offset voltage and flicker noise. By placing chopper switches at both the input and output terminals of the PGA, the input chopper modulates the input signal to a high frequency, while the output chopper demodulates the high-frequency signal back to a low frequency. This modulates the operational amplifier's offset voltage and flicker noise to a high frequency, which is then eliminated by subsequent filtering circuitry.

[0004] However, after adopting chopper technology, the on-resistance between the output of the programmable gain amplifier and the sampling capacitor in the analog-to-digital converter includes the on-resistance of the chopper switch and the sampling switch. This will cause the setup error of the sampling capacitor in the analog-to-digital converter to increase due to the increased on-resistance. Technical solutions

[0005] In view of the above problems, embodiments of this application provide a signal processing circuit, chip, and electronic device to solve the above technical problems.

[0006] In a first aspect, embodiments of this application provide a signal processing circuit, including:

[0007] Analog-to-digital conversion module and signal amplification module;

[0008] The first chopper switch module is used to modulate the differential input signal to a high frequency and input it to the signal amplification module under the control of a preset clock signal.

[0009] The second chopper switch module is used to modulate the differential output signal output by the signal amplification module to a low frequency and input it into the analog-to-digital conversion module under the control of a preset control signal.

[0010] The second chopper switch module also enables the analog-to-digital converter module to establish sampling under the control of a preset control signal.

[0011] Secondly, embodiments of this application also provide a chip including the signal processing circuit described above.

[0012] Thirdly, embodiments of this application also provide an electronic device, including the aforementioned chip or signal processing circuit.

[0013] These or other aspects of this application will become more apparent in the following description of the embodiments. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 shows a schematic diagram of a signal processing circuit in the related technology.

[0016] Figure 2 shows a schematic diagram of a signal processing circuit in the related art.

[0017] Figure 3 shows a schematic diagram of a signal processing circuit in an embodiment of this application.

[0018] Figure 4 shows another schematic diagram of the signal processing circuit in an embodiment of this application.

[0019] Figure 5 shows another schematic diagram of the signal processing circuit in an embodiment of this application.

[0020] Figure 6 shows another schematic diagram of the signal processing circuit in an embodiment of this application.

[0021] Figure 7 shows a signal schematic diagram of a signal processing circuit in an embodiment of this application.

[0022] The system includes: 10 analog-to-digital conversion module, 101 first sampling input terminal, 102 second sampling input terminal; 20 signal amplification module, 201 first input terminal, 202 second input terminal, 203 first output terminal, 204 second output terminal; 30 first chopper switch module, 40 second chopper switch module; first differential signal VIP, second differential signal VIN, operational amplifier OP, first capacitor C1, second capacitor C2, third capacitor C3, fourth capacitor C4, first resistor R1, second resistor R2, third resistor R3, fourth resistor R4, first differential amplified signal VOP, second differential amplified signal VON, sampling capacitors CS1, CS2, reset switch SI; first switch S1, second switch S2, third switch S3, fourth switch S4, fifth switch S5, sixth switch S6, seventh switch S7, eighth switch S8, first clock signal CLK1, second clock signal CLK2, reset clock signal CLKI, first control signal CLKS1, second control signal CLKS2.

[0023] Implementation methods of this application

[0024] The embodiments of this application are described in detail below. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0025] To enable those skilled in the art to better understand the solutions of this application, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0026] In the embodiments of this application, it should be noted that, in this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations.

[0027] Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0028] In the description of the embodiments of this application, the words "example" or "for example" are used to indicate exemplification, illustration, or description. Any embodiment or design described as "example" or "for example" in the embodiments of this application is not to be construed as being more preferred or having more advantages than another embodiment or design. The use of the words "example" or "for example" is intended to present relative concepts in a clear manner.

[0029] Furthermore, in the embodiments of this application, "multiple" refers to two or more. Therefore, in the embodiments of this application, "multiple" can also be understood as "at least two". "At least one" can be understood as one or more, such as one, two, or more. For example, including at least one means including one, two, or more, and is not limited to which ones are included. For example, including at least one of A, B, and C, then it could include A, B, C, A and B, A and C, B and C, or A and B and C.

[0030] It should be noted that in the embodiments of this application, "and / or" describes the relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after it are in an "or" relationship.

[0031] It should be noted that in the embodiments of this application, "connection" can be understood as electrical connection. The connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be a direct connection between A and B, or an indirect connection between A and B through one or more other electrical components.

[0032] In the circuit structure provided by the embodiments of this application, nodes such as the first node and the second node do not represent actual existing components, but rather represent the junction points of related couplings in the circuit diagram. In other words, these nodes are equivalent to the junction points of related couplings in the circuit diagram.

[0033] Currently, programmable gain amplifiers are often combined with chopping technology to eliminate the effects of operational amplifier offset voltage and flicker noise. Referring to Figures 1 and 2, Figure 1 shows a schematic diagram of a signal processing circuit in the related art, and Figure 2 shows a signal schematic diagram of a signal processing circuit in the related art. The signal processing circuit includes a chopper modulation switch, an amplifier circuit, a chopper demodulation switch, and an analog-to-digital converter (ADC).

[0034] Specifically, the chopper modulation switch includes four switches, two of which are controlled by clock signal CLK1 and the other two by clock signal CLK2. Clock signals CLK1 and CLK2 do not overlap, so the two differential signals VIP and VIN can be alternately input to the negative and positive input terminals of the amplifier circuit, and the differential signals VIP and VIN can be modulated into high-frequency signals for input to the amplifier circuit.

[0035] The amplifier circuit includes an operational amplifier OP, two input capacitors C1, and two feedback capacitors C2. The operational amplifier OP, the two input capacitors C1, and the two feedback capacitors C2 form a capacitive amplifier circuit. The amplification factor of the amplifier circuit is the ratio of the capacitances of capacitors C2 and C1. Finally, it can output differential amplified signals VOP and VON at the inverting output terminal and the non-inverting output terminal of the operational amplifier OP, respectively.

[0036] The chopper demodulation switch includes four switches, two of which are controlled by clock signal CLK1 and the other two by clock signal CLK2. Since clock signals CLK1 and CLK2 do not overlap, the high-frequency differential amplified signals VOP and VON output by the operational amplifier OP can be converted into low-frequency differential output signals VOUTP and VOUTN.

[0037] The analog-to-digital converter (ADC) includes two sampling capacitors CS, two sampling switches, and a reset switch. The two sampling switches are controlled by the sampling clock signal CLKS, and the reset switch is controlled by the reset clock signal CLKI. When the sampling switch is closed and the reset switch is open, the two sampling capacitors CS can be charged based on the differential output signals VOUTP and VOUTN, respectively, thereby acquiring voltage information and performing analog-to-digital conversion.

[0038] It can be seen that the chopper modulation switch changes the polarity of the amplifier circuit input, while the chopper demodulation switch restores the polarity of the differential output signals VOUTP and VOUTN. This allows the sampling capacitor CS to be charged based on the differential output signals VOUTP and VOUTN, thus completing signal measurement. Simultaneously, since the chopper modulation switch modulates the differential signals VOP and VON to a high frequency, and the chopper demodulation switch converts the high-frequency differential amplifier signals VOP and VON into low-frequency differential output signals VOUTP and VOUTN, the operational amplifier's offset voltage and flicker noise are modulated to a high frequency by the chopper demodulation switch. Therefore, the effects of the operational amplifier's offset voltage and flicker noise can be eliminated by the subsequent filtering circuit.

[0039] However, in Figure 1, a chopper demodulation switch and a sampling switch are set between the sampling capacitor CS and the output terminal of the operational amplifier OP. Therefore, the setup error of the sampling capacitor CS in the analog-to-digital converter will be affected by the on-resistance of both the chopper demodulation switch and the sampling switch. If the on-resistance is not reduced, the accuracy of the analog-to-digital converter will decrease. If a larger area transistor is used as the sampling switch to reduce the on-resistance, the parasitic capacitance of the sampling switch will increase, thus affecting the sampling setup speed.

[0040] Therefore, this application provides a signal processing circuit, a chip, and an electronic device, which will be described in detail below.

[0041] First, referring to Figure 3, Figure 3 shows a schematic diagram of a signal processing circuit in an embodiment of this application, wherein the signal processing circuit includes an analog-to-digital conversion module 10, a signal amplification module 20, a first chopper switch module 30, and a second chopper switch module 40.

[0042] Specifically, the analog-to-digital conversion module 10 has a first sampling input terminal 101 and a second sampling input terminal 102. The analog-to-digital conversion module 10 can perform analog-to-digital conversion on the differential signals input to the first sampling input terminal 101 and the second sampling input terminal 102, and finally output a digital signal corresponding to the voltage difference between the first sampling input terminal 101 and the second sampling input terminal 102, thereby realizing the voltage measurement process.

[0043] For example, the analog-to-digital conversion module 10 may include, but is not limited to, a successive approximation register ADC (SAR ADC), a Σ-Δ ADC, or a hybrid ADC consisting of a SAR ADC and a Sigma-Delta ADC.

[0044] It should be noted that the analog-to-digital conversion module 10 includes sampling capacitors CS1 and CS2 and a reset switch SI. One end of the reset switch SI is connected to the first sampling input terminal 101, and the other end is connected to the second sampling input terminal 102. The sampling capacitors CS1 and CS2 can be charged by the voltage signals input to the first sampling input terminal 101 and the second sampling input terminal 102, thereby storing charge signals related to the input voltage. When the reset switch SI is closed, the charge stored in the sampling capacitors CS1 and CS2 can be cleared so that the sampling capacitors CS1 and CS2 can perform sampling during the sampling phase.

[0045] Understandably, the analog-to-digital converter module 10 may include other circuit structures in addition to the sampling capacitors CS1 and CS2 and the reset switch SI. For example, when the analog-to-digital converter module 10 includes a SAR ADC, it may also include a comparator and a successive approximation logic module; or, for example, when the analog-to-digital converter module 10 includes a Sigma-Delta ADC, it may also include a digital-to-analog converter, an integrator, and a quantizer.

[0046] The signal amplification module 20 has a first input terminal 201, a second input terminal 202, a first output terminal 203 and a second output terminal 204. The signal amplification module 20 can amplify the signals input to the first input terminal 201 and the second input terminal 202, and output the amplified signals at the first output terminal 203 and the second output terminal 204 to improve the signal-to-noise ratio of the signal processing circuit.

[0047] In some embodiments of this application, the signal amplification module 20 may include a PGA amplifier. In this case, voltage signals are input to the first input terminal 201 and the second input terminal 202, and amplified voltage signals are output to the first output terminal 203 and the second output terminal 204, so that the analog-to-digital conversion module 10 can perform analog-to-digital conversion on the amplified voltage signals. In some embodiments of this application, the signal amplification module 20 may include a TIA amplifier. In this case, current signals are input to the first input terminal 201 and the second input terminal 202, and amplified voltage signals can be output to the first output terminal 203 and the second output terminal 204, so that the analog-to-digital conversion module 10 can perform analog-to-digital conversion on the amplified voltage signals.

[0048] In some embodiments of this application, the signal amplification module 20 includes an operational amplifier OP, a first impedance element, a second impedance element, a third impedance element, and a fourth impedance element; the first end of the first impedance element is connected to the first chopper switch module 30, and the second end of the first impedance element is connected to the non-inverting input terminal of the operational amplifier OP; the first end of the second impedance element is connected to the first chopper switch module 30, and the second end of the second impedance element is connected to the inverting input terminal of the operational amplifier OP; the first end of the third impedance element is connected to the non-inverting input terminal of the operational amplifier OP, and the second end of the third impedance element is connected to the inverting output terminal of the operational amplifier OP; the first end of the fourth impedance element is connected to the inverting input terminal of the operational amplifier OP, and the second end of the fourth impedance element is connected to the non-inverting output terminal of the operational amplifier OP.

[0049] It should be noted that the first impedance element, the second impedance element, the third impedance element, and the fourth impedance element may include resistors and / or capacitors. For example, referring to Figure 4, Figure 4 shows another schematic diagram of the signal processing circuit in an embodiment of this application. In this case, the first impedance element includes a first capacitor C1, the second impedance element includes a second capacitor C2, the third impedance element includes a third capacitor C3, and the fourth impedance element includes a fourth capacitor C4. In this case, the operational amplifier OP, the first capacitor C1, the second capacitor C2, the third capacitor C3, and the fourth capacitor C4 form a PGA amplifier circuit with a capacitor architecture. Therefore, the voltage signals input at the first input terminal 201 and the second input terminal 202 can be amplified, thereby outputting the first differential amplified signal VOP and the second differential amplified signal VON at the first output terminal 203 and the second output terminal 204, respectively.

[0050] For example, referring to Figure 5, which shows another schematic diagram of the signal processing circuit in an embodiment of this application, the first impedance element includes a first resistor R1, the second impedance element includes a second resistor R2, the third impedance element includes a third resistor R3, and the fourth impedance element includes a fourth resistor R4. In this case, the operational amplifier OP, the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 form a PGA amplifier circuit with a resistor architecture. Therefore, the voltage signals input at the first input terminal 201 and the second input terminal 202 can be amplified, thereby outputting the differential amplified signal VOP and the differential amplified signal VON at the first output terminal 203 and the second output terminal 204, respectively.

[0051] Understandably, in some possible embodiments, the first impedance element, the second impedance element, the third impedance element, and the fourth impedance element may simultaneously include resistors and capacitors. For example, the first impedance element includes a first resistor R1 and a first capacitor C1, the second impedance element includes a second resistor R2 and a second capacitor C2, the third impedance element includes a third resistor R3 and a third capacitor C3, and the fourth impedance element includes a fourth resistor R4 and a fourth capacitor C4. The first capacitor C1 and the first resistor R1 are connected in parallel as the first impedance element, and the second impedance element, the third impedance element, and the fourth impedance element are similarly described, and will not be repeated here.

[0052] The first chopper switch module 30 can modulate the differential input signal to a high frequency and input it to the signal amplification module 20 under the control of a preset clock signal. For example, during the high level of the preset clock signal, the first chopper switch module 30 controls the first input terminal 201 of the signal amplification module 20 to input the first differential signal VIP of the differential input signal, and the second input terminal 202 of the signal amplification module 20 to input the second differential signal VIN of the differential input signal; while during the low level of the preset clock signal, the first chopper switch module 30 controls the first input terminal 201 of the signal amplification module 20 to input the second differential signal VIN of the differential input signal, and the second input terminal 202 of the signal amplification module 20 to input the first differential signal VIP of the differential input signal. The above process is executed alternately, thereby modulating the differential input signal to a high frequency and inputting it to the signal amplification module 20.

[0053] In some embodiments of this application, referring to FIG6, FIG6 shows another schematic diagram of the signal processing circuit in an embodiment of this application, wherein the first chopper switch module 30 includes a first switch S1, a second switch S2, a third switch S3 and a fourth switch S4; the first end of the first switch S1 is used to connect to the first differential signal VIP, and the second end of the first switch S1 is connected to the first input terminal 201; the first end of the second switch S2 is used to connect to the first differential signal VIP, and the second end of the second switch S2 is connected to the second input terminal 202; the first end of the third switch S3 is used to connect to the second differential signal VIN, and the second end of the third switch S3 is connected to the first input terminal 201; the first end of the fourth switch S4 is used to connect to the second differential signal VIN, and the second end of the fourth switch S4 is connected to the second input terminal 202.

[0054] Specifically, when the first switch S1 and the fourth switch S4 are closed, and the second switch S2 and the third switch S3 are open, the first differential signal VIP can be continuously input to the first input terminal 201 of the signal amplifier circuit, and the second differential signal VIN can be continuously input to the second input terminal 202 of the signal amplifier circuit. Conversely, when the first switch S1 and the fourth switch S4 are open, and the second switch S2 and the third switch S3 are closed, the first differential signal VIP can be continuously input to the second input terminal 202 of the signal amplifier circuit, and the second differential signal VIN can be continuously input to the first input terminal 201 of the signal amplifier circuit. The above process is executed alternately, which can modulate the differential input signal to a high frequency and input it to the signal amplification module 20.

[0055] The second chopper switch module 40 can be used to modulate the differential output signal of the signal amplification module 20 to a low frequency and input it to the analog-to-digital converter module 10 under the control of a preset control signal. For example, during one time period, the second chopper switch module 40 can control the first output terminal 203 of the signal amplification module 20 to be connected to the first sampling input terminal 101 of the analog-to-digital converter, and control the second output terminal 204 of the signal amplification module 20 to be connected to the second sampling input terminal 102 of the analog-to-digital converter; during another time period, the second chopper switch module 40 can control the second output terminal 204 of the signal amplification module 20 to be connected to the first sampling input terminal 101 of the analog-to-digital converter, and control the first output terminal 203 of the signal amplification module 20 to be connected to the second sampling input terminal 102 of the analog-to-digital converter.

[0056] In some embodiments of this application, referring to FIG6, the second chopper switch module 40 includes a fifth switch S5, a sixth switch S6, a seventh switch S7, and an eighth switch S8; the first end of the fifth switch S5 is connected to the first output terminal 203, and the second end of the fifth switch S5 is connected to the first sampling input terminal 101; the first end of the sixth switch S6 is connected to the first output terminal 203, and the second end of the sixth switch S6 is connected to the second sampling input terminal 102; the first end of the seventh switch S7 is connected to the second output terminal 204, and the second end of the seventh switch S7 is connected to the first sampling input terminal 101; the first end of the eighth switch S8 is connected to the second output terminal 204, and the second end of the eighth switch S8 is connected to the second sampling input terminal 102.

[0057] Specifically, when the fifth switch S5 and the eighth switch S8 are closed, and the sixth switch S6 and the seventh switch S7 are open, the first sampling input terminal 101 of the analog-to-digital converter module 10 is connected to the first differential amplified signal VOP of the differential output signal, and the second sampling input terminal 102 of the analog-to-digital converter module 10 is connected to the second differential amplified signal VON of the differential output signal; conversely, when the fifth switch S5 and the eighth switch S8 are open, and the sixth switch S6 and the seventh switch S7 are closed, the first sampling input terminal 101 of the analog-to-digital converter module 10 is connected to the second differential amplified signal VON of the differential output signal, and the second sampling input terminal 102 of the analog-to-digital converter module 10 is connected to the first differential amplified signal VOP of the differential output signal.

[0058] It should be noted that when the first chopper switch module 30 controls the first input terminal 201 of the signal amplification module 20 to input the first differential signal VIP, and the second input terminal 202 of the signal amplification module 20 to input the second differential signal VIN, the second chopper switch module 40 can control the first output terminal 203 of the signal amplification module 20 to connect with the first sampling input terminal 101 of the analog-to-digital converter, and control the second output terminal 204 of the signal amplification module 20 to connect with the second sampling input terminal 102 of the analog-to-digital converter; while when the first chopper switch module 30 controls the first input terminal 201 of the signal amplification module 20 to input the second differential signal VIN, and the second input terminal 202 of the signal amplification module 20 to input the first differential signal VIP, the second chopper switch module 40 can control the first output terminal 203 of the signal amplification module 20 to connect with the second sampling input terminal 102 of the analog-to-digital converter, and control the second output terminal 204 of the signal amplification module 20 to connect with the first sampling input terminal 101 of the analog-to-digital converter.

[0059] In the two processes described above, although the first chopper switch module 30 changes the polarity of the input signals at the first input terminal 201 and the second input terminal 202, the second chopper switch module 40 also changes the polarity of the output signals at the first output terminal 203 and the second output terminal 204. Therefore, the polarity of the input signals at the first sampling input terminal 101 and the second conversion input terminal will not change. This ensures that the analog-to-digital conversion module 10 can measure the signal while performing signal chopping.

[0060] In this embodiment, the second chopper switch module 40 also enables the analog-to-digital converter module 10 to establish sampling under the control of the preset control signal. For example, when the second chopper switch module 40 controls the first output terminal 203 of the signal amplification module 20 to connect with the first sampling input terminal 101 of the analog-to-digital converter, and controls the second output terminal 204 of the signal amplification module 20 to connect with the second sampling input terminal 102 of the analog-to-digital converter, the sampling capacitors CS1 and CS2 can be charged for sampling; when the second chopper switch module 40 controls the second output terminal 204 of the signal amplification module 20 to connect with the first sampling input terminal 101 of the analog-to-digital converter, and controls the first output terminal 203 of the signal amplification module 20 to connect with the second sampling input terminal 102 of the analog-to-digital converter, the sampling capacitors CS1 and CS2 can also be charged for sampling.

[0061] As can be seen, this application reuses the second chopper switch module 40 as the sampling switch of the analog-to-digital conversion module 10. The second chopper switch module 40 can not only realize the chopper demodulation function, but also realize the sampling switch function of sampling capacitors CS1 and CS2. In the end, there is no need to set a sampling switch between sampling capacitors CS1 and CS2 and the second chopper switch module 40, thereby avoiding the problem of increased on-resistance caused by setting both chopper demodulation switch and sampling switch at the same time.

[0062] In some embodiments of this application, referring to Figures 6 and 7, the preset clock signal includes a first clock signal CLK1 and a second clock signal CLK2, and the preset control signal includes a first control signal CLKS1 and a second control signal CLKS1. The first clock signal CLK1 and the second clock signal CLK2 do not overlap. The first control signal CLKS1 has multiple high levels only during the first level (e.g., high level) of the first clock signal CLK1, and the second control signal CLKS2 has multiple high levels only during the second level (e.g., low level) of the first clock signal CLK1.

[0063] For example, the first switch S1 and the fourth switch S4 of the first chopper switch module 30 change their switching states based on the first clock signal CLK1, the second switch S2 and the third switch S3 change their switching states based on the second clock signal CLK2, the fifth switch S5 and the eighth switch S8 of the second chopper switch module 40 change their switching states based on the first control signal CLKS1, and the sixth switch S6 and the seventh switch S7 change their switching states based on the second control signal CLKS2. The example is given with NMOS transistors as the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7, and the eighth switch S8.

[0064] During the high level of the first clock signal CLK1, the first switch S1 and the fourth switch S4 are closed, and the second switch S2 and the third switch S3 are open. Therefore, the first chopper switch module 30 can control the first differential signal VIP to continuously input to the first input terminal 201 of the signal amplifier circuit, and the second differential signal VIN to continuously input to the second input terminal 202 of the signal amplifier circuit. At the same time, since the first control signal CLKS1 has multiple high levels only during the first level (e.g., high level) of the first clock signal CLK1, the second control signal CLKS2 only has multiple high levels during the second level of the first clock signal CLK1. During the (e.g., low level) period, there are multiple high levels, so the fifth switch S5 and the eighth switch S8 switch back and forth between the closed state and the open state, while the sixth switch S6 and the seventh switch S7 remain in the open state. Therefore, the second chopper switch module 40 can control the first output terminal 203 of the signal amplification module 20 to be intermittently connected to the first sampling input terminal 101, and control the second output terminal 204 of the signal amplification module 20 to be intermittently connected to the second sampling input terminal 102. At this time, the fifth switch S5 and the eighth switch S8 act as sampling switches for the analog-to-digital conversion module 10, enabling the analog-to-digital conversion module 10 to establish sampling.

[0065] During the low level of the first clock signal CLK1, the first switch S1 and the fourth switch S4 are open, and the second switch S2 and the third switch S3 are closed. Therefore, the first chopper switch module 30 can control the first differential signal VIP to continuously input to the second input terminal 202 of the signal amplifier circuit, and the second differential signal VIN to continuously input to the first input terminal 201 of the signal amplifier circuit. At the same time, since the first control signal CLKS1 has multiple high levels only during the first level (e.g., high level) of the first clock signal CLK1, the second control signal CLKS2 only has multiple high levels during the second level of the first clock signal CLK1. During the (e.g., low level) period, there are multiple high levels, so the sixth switch S6 and the seventh switch S7 switch back and forth between the closed state and the open state, while the fifth switch S5 and the eighth switch S8 remain in the open state. Therefore, the second chopper switch module 40 can control the second output terminal 204 of the signal amplification module 20 to be intermittently connected to the first sampling input terminal 101, and control the first output terminal 203 of the signal amplification module 20 to be intermittently connected to the second sampling input terminal 102. At this time, the sixth switch S6 and the seventh switch S7 act as sampling switches for the analog-to-digital conversion module 10, enabling the analog-to-digital conversion module 10 to establish sampling.

[0066] It can be seen that during the high level of the first clock signal CLK1, the fifth switch S5 and the eighth switch S8 are multiplexed as sampling switches of the analog-to-digital converter module 10; during the low level of the first clock signal CLK1, the sixth switch S6 and the seventh switch S7 are multiplexed as sampling switches of the analog-to-digital converter module 10. Therefore, under the control of the first control signal CLKS1 and the second control signal CLKS2, the second chopper switch module 40 can not only modulate the differential output signal output by the signal amplification module 20 to a low frequency and input it into the analog-to-digital converter module 10, but also enable the analog-to-digital converter module 10 to establish sampling.

[0067] In some embodiments of this application, the first control signal CLKS1 is generated based on the first clock signal CLK1 and the reset clock signal CLKI of the analog-to-digital converter module 10, and the second control signal CLKS2 is generated based on the second clock signal CLK2 and the reset clock signal CLKI of the analog-to-digital converter module 10, and the frequencies of the first clock signal CLK1 and the second clock signal CLK2 are less than the frequency of the reset clock signal CLKI.

[0068] It should be noted that the reset clock signal CLKI refers to the clock signal that controls the reset switch SI in the analog-to-digital converter module 10. The first clock signal CLK1 and the reset clock signal CLKI can generate the first control signal CLKS1 through logic gate circuits. The second clock signal CLK2 and the reset clock signal CLKI can also generate the first control signal CLKS1 through logic gate circuits.

[0069] For example, referring to Figure 6, the first clock signal CLK1 and the reset clock signal CLKI can be used to generate the first control signal CLKS1 through a logic gate circuit composed of NOT gates and AND gates. The reset clock signal CLKI is output as an inverted reset clock signal CLKI through a NOT gate. Then, the first clock signal CLK1 and the inverted reset clock signal CLKI are passed through an AND gate to output the first control signal CLKS1. Similarly, the second clock signal CLK2 and the reset clock signal CLKI can be used to generate the second control signal CLKS2 through a logic gate circuit composed of NOT gates and AND gates. The reset clock signal CLKI is output as an inverted reset clock signal CLKI through a NOT gate. Then, the second clock signal CLK2 and the inverted reset clock signal CLKI are passed through an AND gate to output the second control signal CLKS2.

[0070] Since the first clock signal CLK1 and the second clock signal CLK2 do not overlap, and the frequencies of the first clock signal CLK1 and the second clock signal CLK2 are less than the frequency of the reset clock signal CLKI, during the high level of the first clock signal CLK1 and the low level of the second clock signal CLK2, as shown in Figure 7, the first control signal CLKS1 has multiple high levels and multiple low levels, while the second control signal CLKS2 remains at a low level; conversely, during the low level of the first clock signal CLK1 and the high level of the second clock signal CLK2, the second control signal CLKS2 has multiple high levels and multiple low levels, while the first control signal CLKS1 remains at a low level.

[0071] For example, if the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7, and the eighth switch S8 are NMOS transistors, during the high level of the first clock signal CLK1 and the low level of the second clock signal CLK2, the first switch S1 and the fourth switch S4 remain in the closed state, and the second switch S2 and the third switch S3 remain in the open state. At the same time, since the first control signal CLKS1 has multiple high levels and multiple low levels, while the second control signal CLKS2 remains at a low level, the fifth switch S5 and the eighth switch S8 switch back and forth between the closed and open states, while the sixth switch S6 and the seventh switch S7 remain in the open state.

[0072] Conversely, during the low level of the first clock signal CLK1 and the high level of the second clock signal CLK2, the first switch S1 and the fourth switch S4 remain in the open state, the second switch S2 and the third switch S3 remain in the closed state, and since the second control signal CLKS2 has multiple high levels and multiple low levels, while the first control signal CLKS1 remains in the low level, the sixth switch S6 and the seventh switch S7 switch back and forth between the closed and open states, while the fifth switch S5 and the eighth switch S8 remain in the open state.

[0073] As can be seen, by controlling the first switch S1 and the fourth switch S4 through the first clock signal CLK1, controlling the second switch S2 and the third switch S3 through the second clock signal CLK2, controlling the fifth switch S5 and the eighth switch S8 through the first control signal CLKS1, and controlling the sixth switch S6 and the seventh switch S7 through the second control signal CLKS2, not only can signal chopping modulation and signal chopping demodulation be realized, but the fifth switch S5, the sixth switch S6, the seventh switch S7, and the eighth switch S8 can also be multiplexed as sampling switches of the analog-to-digital conversion module 10.

[0074] It should be noted that the above description of the signal processing circuit is intended to clearly illustrate the implementation and verification process of this application. Those skilled in the art can make equivalent modifications under the guidance of this application. For example, the first switch S1, the second switch S2, the third switch S3, the fourth switch S4, the fifth switch S5, the sixth switch S6, the seventh switch S7, and the eighth switch S8 can also be transistors with switching functions such as PMOS transistors, triodes, or JEFT transistors.

[0075] This application also provides a chip that includes the signal processing circuit described above. A chip (Integrated Circuit, IC) is also called a chip, and this chip can be, but is not limited to, a System on Chip (SOC) chip or a System in Package (SIP) chip. Since the chip of this application possesses the signal processing circuit described in the above embodiments, it has all the beneficial effects of the signal processing circuit in the above embodiments, and will not be repeated here.

[0076] This application also provides an electronic device, which includes a device body and a chip as described above disposed within the device body. The electronic device may be, but is not limited to, a weight scale, body fat scale, nutrition scale, infrared electronic thermometer, pulse oximeter, body composition analyzer, power bank, wireless charger, fast charger, car charger, adapter, display, USB (Universal Serial Bus) docking station, stylus, true wireless earphones, car center console screen, automobile, smart wearable device, mobile terminal, and smart home device. Smart wearable devices include, but are not limited to, smartwatches, smart bracelets, and neck massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablets, and POS (point of sales terminal) machines. Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart robot vacuums, and smart lights.

[0077] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.

Claims

1. A signal processing circuit, characterized in that, include: Analog-to-digital conversion module and signal amplification module; The first chopper switch module is used to modulate the differential input signal to a high frequency and input it to the signal amplification module under the control of a preset clock signal. The second chopper switch module is used to modulate the differential output signal output by the signal amplification module to a low frequency and input it into the analog-to-digital conversion module under the control of a preset control signal. The second chopper switch module also enables the analog-to-digital conversion module to establish sampling under the control of the preset control signal.

2. The signal processing circuit as described in claim 1, characterized in that, The preset clock signal includes a first clock signal and a second clock signal, and the preset control signal includes a first control signal and a second control signal; The first clock signal and the second clock signal do not overlap. The first control signal has multiple high levels only during the first level of the first clock signal, and the second control signal has multiple high levels only during the second level of the first clock signal.

3. The signal processing circuit as described in claim 2, characterized in that, The first control signal is generated based on the first clock signal and the reset clock signal of the analog-to-digital converter module, and the second control signal is generated based on the second clock signal and the reset clock signal of the analog-to-digital converter module. The frequencies of the first clock signal and the second clock signal are lower than the frequency of the reset clock signal.

4. The signal processing circuit as described in claim 2, characterized in that, The analog-to-digital conversion module has a first sampling input terminal and a second sampling input terminal, and the signal amplification module has a first input terminal, a second input terminal, a first output terminal, and a second output terminal; During the first level of the first clock signal, the first chopper switch module controls the first input terminal to continuously receive the first differential signal and controls the second input terminal to continuously receive the second differential signal; the second chopper switch module controls the first output terminal to intermittently connect with the first sampling input terminal and controls the second output terminal to intermittently connect with the second sampling input terminal. During the second level of the first clock signal, the first chopper switch module controls the first input terminal to continuously receive the second differential signal, and controls the second input terminal to continuously receive the first differential signal; The second chopper switch module controls the second output terminal to be intermittently connected to the first sampling input terminal, and also controls the first output terminal to be intermittently connected to the second sampling input terminal.

5. The signal processing circuit as described in claim 4, characterized in that, The first chopper switch module includes a first switch, a second switch, a third switch, and a fourth switch; The first terminal of the first switch is used to receive the first differential signal, and the second terminal of the first switch is connected to the first input terminal; The first terminal of the second switch is used to receive the first differential signal, and the second terminal of the second switch is connected to the second input terminal; The first terminal of the third switch is used to receive the second differential signal, and the second terminal of the third switch is connected to the first input terminal; The first terminal of the fourth switch is used to receive the second differential signal, and the second terminal of the fourth switch is connected to the second input terminal; The first switch and the fourth switch change their switch states based on the first clock signal, and the second switch and the third switch change their switch states based on the second clock signal.

6. The signal processing circuit as described in claim 4, characterized in that, The second chopper switch module includes a fifth switch, a sixth switch, a seventh switch, and an eighth switch; The first end of the fifth switch is connected to the first output end, and the second end of the fifth switch is connected to the first sampling input end; The first end of the sixth switch is connected to the first output end, and the second end of the sixth switch is connected to the second sampling input end; The first end of the seventh switch is connected to the second output end, and the second end of the seventh switch is connected to the first sampling input end; The first terminal of the eighth switch is connected to the second output terminal, and the second terminal of the eighth switch is connected to the second sampling input terminal; The fifth and eighth switches change their states based on the first control signal, while the sixth and seventh switches change their states based on the second control signal.

7. The signal processing circuit as described in claim 1, characterized in that, The signal amplification module includes an operational amplifier, a first impedance element, a second impedance element, a third impedance element, and a fourth impedance element; The first end of the first impedance element is connected to the first chopper switch module, and the second end of the first impedance element is connected to the non-inverting input of the operational amplifier. The first end of the second impedance element is connected to the first chopper switch module, and the second end of the second impedance element is connected to the inverting input terminal of the operational amplifier. The first end of the third impedance element is connected to the non-inverting input terminal of the operational amplifier, and the second end of the third impedance element is connected to the inverting output terminal of the operational amplifier. The first end of the fourth impedance element is connected to the inverting input of the operational amplifier, and the second end of the fourth impedance element is connected to the non-inverting output of the operational amplifier.

8. The signal processing circuit as described in claim 7, characterized in that, The first impedance element includes a first resistor and / or a first capacitor, and the second impedance element includes a second resistor and / or a second capacitor; The third impedance element includes a third resistor and / or a third capacitor, and the fourth impedance element includes a fourth resistor and / or a fourth capacitor.

9. A chip, characterized in that, Includes the signal processing circuit as described in any one of claims 1 to 8.

10. An electronic device, characterized in that, It includes a device body and a chip as described in claim 9 disposed on the device body.

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