CPLD configuration information power-on loading method and system based on dynamic voltage regulation

Abstract

The present invention relates to the technical field of CPLD management, and provides a CPLD configuration information power-on loading method and system based on dynamic voltage regulation. The method comprises: step S1, a CPU generating offset sub-addresses of byte data in configuration information on the basis of an offset address; step S2, sending a protection identifier, a first piece of byte data, and a corresponding offset sub-address to an I2C slave controller so as to respectively write into a protection register, a data register, and an address register; step S3, after verifying the protection identifier written into the protection register, a logic controller controlling an I2C master controller to read the byte data and the offset sub-address from the corresponding registers, so as to write the byte data into an EEPROM on the basis of the offset sub-address, and performing writing of the next byte data until all writing is completed; and step S4, when a CPLD is powered on, the I2C master controller automatically loading the byte data stored in the EEPROM into a configuration register. The present invention has the following advantages: the convenience, flexibility, security, and reliability of CPLD configuration information loading are significantly improved.

Description

A CPLD configuration information power-on loading method and system based on dynamic voltage regulation TECHNICAL FIELD

[0001] The present application relates to the technical field of CPLD management, and particularly relates to a CPLD configuration information power-on loading method and system based on dynamic voltage regulation. BACKGROUND

[0002] A CPLD (Complex Programmable Logic Device) is a programmable logic device, and a user can construct a logic function according to a need. The CPLD is composed of a plurality of programmable logic units (PLD), and the logic units are connected through programmable global interconnection resources. The operation of the CPLD depends on configuration information, that is, the CPLD can normally operate only when the configuration information is correctly loaded. For the loading of the configuration information of the CPLD, the following methods exist traditionally.

[0003] Method one is to solidify the configuration information in firmware burned in the CPLD, so as to automatically load the configuration information when the CPLD is powered on. However, the method cannot flexibly modify the configuration information, and the configuration information must be re-burned in the firmware, which causes many risks in the management of the firmware version, and the firmware version is easily fragmented.

[0004] Method two is to load the configuration information through high and low levels of IO pins. However, the method cannot flexibly modify the configuration information, and the configuration information must be adjusted through a jumper resistor on a circuit board. In addition, in a scenario where the configuration information is large, a large number of IO pins need to be occupied, and the configuration information needs to be modified by opening a case.

[0005] In summary, the traditional method is poor in convenience and flexibility of the loading of the CPLD configuration information. In addition, no corresponding safety measures are taken for the reading and writing of the configuration information, and there is a certain security risk. In the configuration information loading process of the traditional method, the loading often fails due to fluctuations in electrical variables, for example, unstable voltage causes the configuration information to fail to be loaded. Therefore, how to provide a CPLD configuration information power-on loading method and system based on dynamic voltage regulation, and realize the convenience, flexibility, safety and reliability of the loading of the CPLD configuration information, has become a technical problem to be solved. TECHNICAL PROBLEM

[0006] The technical problem to be solved by the present application is to provide a CPLD configuration information power-on loading method and system based on dynamic voltage regulation, and realize the convenience, flexibility, safety and reliability of the loading of the CPLD configuration information. TECHNICAL SOLUTION

[0007] The application provides a CPLD configuration information power-on loading method based on dynamic voltage regulation.

[0008] In step S1, the CPU acquires the configuration information to be loaded by the CPLD and the offset address corresponding to the configuration information, and generates offset sub-addresses of byte data in the configuration information based on the offset address.

[0009] In step S2, the CPU respectively encrypts the byte data and the offset sub-addresses into encrypted byte data and encrypted offset sub-addresses.

[0010] In step S3, the CPU sends a preset protection identifier, the first encrypted byte data and the encrypted offset sub-address corresponding to the encrypted byte data to the I2C slave controller of the CPLD through the I2C bus.

[0011] In step S4, the I2C slave controller writes the received protection identifier, encrypted byte data and encrypted offset sub-address into a protection register, a data register and an address register respectively.

[0012] In step S5, after the logic controller of the CPLD verifies the protection identifier written in the protection register, the logic controller controls the I2C master controller to read the encrypted byte data and the encrypted offset sub-address from the data register and the address register respectively.

[0013] In step S6, the I2C master controller decrypts the encrypted byte data and the encrypted offset sub-address to obtain corresponding byte data and offset sub-addresses, and writes the byte data into an EEPROM based on the offset sub-addresses.

[0014] In step S7, the logic controller forwards the write completion feedback sent by the I2C master controller to the CPU, so as to execute the writing of the next byte data until the writing of all the byte data is completed, and the protection register is emptied.

[0015] In step S8, when the CPLD is powered on or the control register is set, the voltage sensor is used to monitor the power supply voltage in real time, the voltage regulator is used to dynamically regulate the power supply voltage so that the power supply voltage is within a preset voltage interval, the logic controller automatically sends a continuous reading command to the I2C master controller, and the I2C master controller loads the byte data stored in the EEPROM into a configuration register based on the received continuous reading command, so as to complete the power-on automatic loading of the configuration information.

[0016] Further, the step S2 is specifically as follows.

[0017] The CPU converts each byte of data into first binary data, divides each first binary data in a 2:6 ratio and swaps their order to obtain first intermediate data, and then shifts each character of each first intermediate data cyclically to the right by 3 bits to obtain encrypted byte data.

[0018] The CPU converts each offset sub-address into second binary data, divides each second binary data in a 3:5 ratio and swaps their order to obtain second intermediate data, and then shifts each character of each second intermediate data cyclically to the left by 2 bits to obtain the encrypted offset sub-address.

[0019] Furthermore, step S4 specifically includes:

[0020] The I2C slave controller, based on the write command sent by the CPU, writes the received encrypted byte data and encrypted offset sub-address into the data register and address register in real time, respectively. It also writes each character carried by the received protection identifier into the protection register in a preset standard writing order and records the actual writing order.

[0021] Step S5 specifically involves:

[0022] The CPLD's logic controller monitors the setting status of the protection register in real time. When the protection register is set, it performs a first-level verification on the actual writing order based on the preset standard writing order, and then performs a second-level verification on the protection identifier written to the protection register through the locally pre-stored protection identifier. Finally, it controls the I2C master controller to read the encrypted byte data and the encrypted offset sub-address from the data register and the address register, respectively.

[0023] Furthermore, step S6 specifically includes:

[0024] The I2C main controller shifts each character of the encrypted byte data cyclically 3 bits to the left to obtain the first intermediate data. It then divides the first intermediate data in a 6:2 ratio and rearranges the order to obtain the first binary data. The first binary data is then converted to plaintext to obtain the byte data, thus completing the decryption of the encrypted byte data. Next, it shifts each character of the encrypted offset sub-address cyclically 2 bits to the right to obtain the second intermediate data. This second intermediate data is then divided in a 5:3 ratio and rearranged to obtain the second binary data. The second binary data is then converted to plaintext to obtain the offset sub-address, thus completing the decryption of the encrypted offset sub-address.

[0025] The I2C master controller writes one byte of data into the EEPROM in real time based on the offset sub-address.

[0026] Furthermore, step S7 specifically includes:

[0027] After the I2C master controller writes the byte data, it sends a write completion feedback to the logic controller in real time. The logic controller forwards the write completion feedback to the CPU in real time. The CPU executes the writing of the next byte data based on the write completion feedback until all the byte data is written. Then, it sends a write end notification to the logic controller through the I2C slave controller.

[0028] The logic controller clears the protection register based on the received end write notification, reads the configuration information written to the EEPROM through the I2C master controller and calculates the CRC8 check value, and sends the CRC8 check value to the CPU.

[0029] The CPU performs integrity verification on the configuration information written based on the received CRC8 check value to obtain the verification result. Based on the verification result, writing time, configuration information, offset address, and CPLD serial number, it generates a write log and stores and backs up the write log.

[0030] Secondly, the present invention provides a CPLD configuration information power-on loading system based on dynamic voltage regulation, comprising the following modules:

[0031] The configuration information preprocessing module is used by the CPU to obtain the configuration information to be loaded by the CPLD and the offset address corresponding to the configuration information, and to generate the offset sub-address of each byte of data in the configuration information based on the offset address.

[0032] An encryption module is used by the CPU to encrypt each byte data and the offset sub-address into encrypted byte data and encrypted offset sub-address, respectively.

[0033] The data transmission module is used by the CPU to send a preset protection identifier, the first encrypted byte data, and the encrypted offset sub-address corresponding to the encrypted byte data to the CPLD's I2C slave controller via the I2C bus.

[0034] The data storage module is used to write the received protection identifier, encrypted byte data, and encrypted offset sub-address from the I2C slave controller into the protection register, data register, and address register, respectively.

[0035] The protection identifier verification module is used by the CPLD's logic controller to verify the protection identifier written in the protection register, and then control the I2C master controller to read the encrypted byte data and the encrypted offset sub-address from the data register and the address register, respectively.

[0036] The first byte data writing module is used by the I2C host controller to decrypt the encrypted byte data and the encrypted offset sub-address to obtain the corresponding byte data and offset sub-address, and write the byte data into the EEPROM based on the offset sub-address;

[0037] The second byte data writing module is used by the logic controller to forward the write completion feedback sent by the I2C master controller to the CPU to execute the writing of the next byte of data until all the bytes of data are written and the protection register is cleared.

[0038] The configuration information power-on loading module is used to monitor the power supply voltage in real time through a voltage sensor when the CPLD is powered on or the control register is set. The voltage regulator dynamically adjusts the power supply voltage to keep it within a preset voltage range. The logic controller automatically sends a continuous read command to the I2C master controller. Based on the received continuous read command, the I2C master controller loads each byte of data stored in the EEPROM into the configuration register to complete the automatic power-on loading of the configuration information.

[0039] Furthermore, the encryption module is specifically used for:

[0040] The CPU converts each byte of data into first binary data, divides each first binary data in a 2:6 ratio and swaps their order to obtain first intermediate data, and then shifts each character of each first intermediate data cyclically to the right by 3 bits to obtain encrypted byte data.

[0041] The CPU converts each offset sub-address into second binary data, divides each second binary data in a 3:5 ratio and swaps their order to obtain second intermediate data, and then shifts each character of each second intermediate data cyclically to the left by 2 bits to obtain the encrypted offset sub-address.

[0042] Furthermore, the data storage module is specifically used for:

[0043] The I2C slave controller, based on the write command sent by the CPU, writes the received encrypted byte data and encrypted offset sub-address into the data register and address register in real time, respectively. It also writes each character carried by the received protection identifier into the protection register in a preset standard writing order and records the actual writing order.

[0044] The protection identifier verification module is specifically used for:

[0045] The CPLD's logic controller monitors the setting status of the protection register in real time. When the protection register is set, it performs a first-level verification on the actual writing order based on the preset standard writing order, and then performs a second-level verification on the protection identifier written to the protection register through the locally pre-stored protection identifier. Finally, it controls the I2C master controller to read the encrypted byte data and the encrypted offset sub-address from the data register and the address register, respectively.

[0046] Furthermore, the first byte data writing module is specifically used for:

[0047] The I2C main controller shifts each character of the encrypted byte data cyclically 3 bits to the left to obtain the first intermediate data. It then divides the first intermediate data in a 6:2 ratio and rearranges the order to obtain the first binary data. The first binary data is then converted to plaintext to obtain the byte data, thus completing the decryption of the encrypted byte data. Next, it shifts each character of the encrypted offset sub-address cyclically 2 bits to the right to obtain the second intermediate data. This second intermediate data is then divided in a 5:3 ratio and rearranged to obtain the second binary data. The second binary data is then converted to plaintext to obtain the offset sub-address, thus completing the decryption of the encrypted offset sub-address.

[0048] The I2C master controller writes one byte of data into the EEPROM in real time based on the offset sub-address.

[0049] Furthermore, the second byte data writing module is specifically used for:

[0050] After the I2C master controller writes the byte data, it sends a write completion feedback to the logic controller in real time. The logic controller forwards the write completion feedback to the CPU in real time. The CPU executes the writing of the next byte data based on the write completion feedback until all the byte data is written. Then, it sends a write end notification to the logic controller through the I2C slave controller.

[0051] The logic controller clears the protection register based on the received end write notification, reads the configuration information written to the EEPROM through the I2C master controller and calculates the CRC8 check value, and sends the CRC8 check value to the CPU.

[0052] The CPU performs integrity verification on the configuration information written based on the received CRC8 check value to obtain the verification result. Based on the verification result, writing time, configuration information, offset address, and CPLD serial number, it generates a write log and stores and backs up the write log. Beneficial effects

[0053] 1. The CPU obtains the configuration information to be loaded by the CPLD and the corresponding offset address. Based on the offset address, it generates the offset sub-address of each byte of data in the configuration information. Then, the CPU encrypts each byte of data and the offset sub-address into encrypted byte data and encrypted offset sub-address, respectively, and sends a preset protection flag, the first encrypted byte data, and the corresponding encrypted offset sub-address to the CPLD's I2C slave controller. Next, the I2C slave controller writes the protection flag, encrypted byte data, and encrypted offset sub-address into the protection register, data register, and address register, respectively. After verifying the protection flag written to the protection register, the CPLD's logic controller controls the I2C master controller to read the encrypted byte data and encrypted offset sub-address from the data register and address register, respectively. The I2C master controller decrypts the encrypted byte data and encrypted offset sub-address to obtain the corresponding byte data and offset sub-address, and writes the byte data into the EEPROM based on the offset sub-address. Then, the logic controller forwards the write completion feedback sent by the I2C master controller to the CPU to execute the next step. The process involves writing byte data until all bytes are written and the protection register is cleared. When the CPLD powers on or the control register is set, the logic controller automatically sends a continuous read command to the I2C master controller. The I2C master controller loads the bytes of data stored in the EEPROM into the configuration register based on the continuous read command, thus completing the automatic loading of configuration information upon power-on. In other words, the CPLD connects to the CPU and EEPROM via the I2C bus. The CPU interacts with the CPLD through the register group set by the CPLD to write configuration information into the EEPROM. When the CPLD powers on or the control register is set, the configuration information stored in the EEPROM is automatically loaded into the configuration register. Compared with the traditional method, it does not require managing a large number of firmware versions or occupying a large number of IO pins. The writing and updating of configuration information can be achieved solely through the register group. Furthermore, during the configuration information writing process, security measures such as encryption of byte data and offset sub-addresses, verification of protection identifiers, and integrity verification are combined, ultimately greatly improving the convenience, flexibility, and security of CPLD configuration information loading.

[0054] 2. The CPU converts each byte of data into first binary data. This first binary data is then divided in a 2:6 ratio and its order is reversed to obtain first intermediate data. Each character in the first intermediate data is then cyclically shifted 3 bits to the right to obtain encrypted byte data. Each offset sub-address is converted into second binary data. This second binary data is then divided in a 3:5 ratio and its order is reversed to obtain second intermediate data. Each character in the second intermediate data is then cyclically shifted 2 bits to the left to obtain encrypted offset sub-addresses. In other words, the byte data and offset sub-addresses are encrypted using preset data transformation rules. Without knowing the corresponding data transformation rules, the encrypted byte data and encrypted offset sub-addresses cannot be cracked. Furthermore, the different data transformation rules used for the byte data and offset sub-addresses further increase the difficulty of cracking. At least six security measures are employed (first division ratio, first displacement direction, first displacement distance, second division ratio, second displacement direction, second displacement distance), greatly improving the security of byte data and offset sub-address transmission and storage, and consequently, significantly enhancing the security of CPLD configuration information loading.

[0055] 3. By writing each character carried by the protection identifier into the protection register in a preset standard writing order and recording the actual writing order, when the logic controller detects that the protection register is set, it performs a first-level verification on the actual writing order based on the standard writing order, and then performs a second-level verification on the protection identifier written to the protection register using the locally pre-stored protection identifier. Only when both verifications pass can the I2C master controller be controlled to read the encrypted byte data and the encrypted offset sub-address from the data register and the address register, respectively. That is, before reading the encrypted byte data and the encrypted offset sub-address, not only must the protection register store the correct protection identifier, but the protection identifier must also be written in the standard writing order. For example, if the protection identifier is set to 0xA5 / 0xA4 / 0xA3 / 0xA2 / 0xB0 / 0xB1 / 0xB2 / 0xB3 (8 bytes), these 8 bytes must be written one by one in the set standard writing order. Otherwise, the verification will fail. Two security measures are taken (the value of the protection identifier and the writing order of the protection identifier) ​​to prevent the contents stored in the data register and the address register from being read illegally, thereby further improving the security of CPLD configuration information loading.

[0056] 4. After writing byte data via the I2C master controller, a write completion feedback is sent to the logic controller in real time. The logic controller forwards the write completion feedback to the CPU in real time. The CPU executes the writing of the next byte of data based on the file number until all byte data is written. Then, it sends a write end notification to the logic controller via the I2C slave controller. The logic controller clears the protection register based on the write end notification, reads the configuration information written to the EEPROM via the I2C master controller, calculates the CRC8 check value, and sends the CRC8 check value to the CPU. The CPU performs integrity verification of the configuration information writing based on the CRC8 check value. In other words, during the configuration information writing process, the CPU and CPLD interact in real time with the write progress through write completion feedback and write end notification. When all writing is completed, the protection register is cleared in time to avoid illegal writing. The CRC8 check value is also used to verify whether the configuration information written to the EEPROM is complete, thereby greatly improving the reliability of CPLD configuration information writing.

[0057] 5. Generate write logs that include verification results, write time, configuration information, offset address, and CPLD serial number, and store and back up the write logs to facilitate later traceability.

[0058] 6. By encrypting byte data and offset sub-addresses (first segmentation ratio, first displacement direction, first displacement distance, second segmentation ratio, second displacement direction, second displacement distance), verifying protection identifiers (value of protection identifier, writing order of protection identifier), verifying integrity (CRC8 check value of configuration information), clearing protection registers in a timely manner, and isolating the CPU and EEPROM through CPLD, the security of CPLD configuration information loading is greatly improved.

[0059] 7. By monitoring the power supply voltage in real time through a voltage sensor when the CPLD is powered on or the control register is set, and dynamically adjusting the power supply voltage through a voltage regulator to keep it within a preset voltage range, the reliability of CPLD configuration information loading is greatly improved, avoiding configuration information loading failure caused by unstable power supply voltage. Attached Figure Description

[0060] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0061] Figure 1 is a flowchart of a power-on loading method for CPLD configuration information based on dynamic voltage regulation according to the present invention.

[0062] Figure 2 is a schematic diagram of the CPLD configuration information power-on loading system based on dynamic voltage regulation according to the present invention.

[0063] Figure 3 is a hardware architecture diagram of the present invention. Embodiments of the present invention

[0064] The overall concept of the technical solution in this application embodiment is as follows: The CPLD is connected to the CPU and EEPROM via the I2C bus. The CPU interacts with the CPLD through the register group (control register, protection register, data register, address register, and configuration register) set by the CPLD to write configuration information into the EEPROM. When the CPLD is powered on or the control register is set, the configuration information stored in the EEPROM is automatically loaded into the configuration register, and the power supply voltage is dynamically adjusted to be within a preset voltage range. Compared with the traditional method, there is no need to manage a large number of firmware versions or occupy a large number of IO pins. The writing and updating of configuration information can be realized only through the register group. In addition, during the configuration information writing process, security measures such as encryption of byte data and offset sub-address, verification of protection identifier, and integrity verification are combined. It also avoids configuration information loading failure due to unstable power supply voltage, thereby improving the convenience, flexibility, security, and reliability of CPLD configuration information loading.

[0065] Referring to Figures 1 to 3, a preferred embodiment of the CPLD configuration information power-on loading method based on dynamic voltage regulation of the present invention includes the following steps:

[0066] Step S1: The CPU obtains the configuration information to be loaded by the CPLD and the offset address corresponding to the configuration information, and generates the offset sub-address of each byte of data in the configuration information based on the offset address;

[0067] Step S2: The CPU encrypts each byte data and offset sub-address into encrypted byte data and encrypted offset sub-address, respectively;

[0068] Step S3: The CPU sends a preset protection identifier, the first encrypted byte data, and the encrypted offset sub-address corresponding to the encrypted byte data to the CPLD's I2C slave controller via the I2C bus.

[0069] Step S4: The I2C slave controller writes the received protection identifier, encrypted byte data, and encrypted offset sub-address into the protection register, data register, and address register, respectively.

[0070] Step S5: After verifying the protection identifier written to the protection register, the logic controller of the CPLD controls the I2C master controller to read the encrypted byte data and the encrypted offset sub-address from the data register and the address register, respectively.

[0071] Step S6: The I2C master controller decrypts the encrypted byte data and the encrypted offset sub-address to obtain the corresponding byte data and offset sub-address, and writes the byte data into the EEPROM based on the offset sub-address;

[0072] Step S7: The logic controller forwards the write completion feedback sent by the I2C master controller to the CPU to execute the writing of the next byte of data until all the bytes of data have been written, and clears the protection register.

[0073] In step S8, when the CPLD is powered on or the control register is set, the power supply voltage is monitored in real time by a voltage sensor, and the power supply voltage is dynamically adjusted by a voltage regulator to keep the power supply voltage within a preset voltage range. The logic controller automatically sends a continuous read command to the I2C master controller. Based on the received continuous read command, the I2C master controller loads each byte of data stored in the EEPROM into the configuration register to complete the automatic loading of the configuration information upon power-on.

[0074] The CPLD includes a logic controller, an I2C slave controller, an I2C master controller, and a register group. The register group includes a control register, a protection register, a data register, an address register, and a configuration register. The logic controller is connected to the I2C slave controller, the I2C master controller, and the register group. One end of the I2C slave controller is connected to the CPU via an I2C bus, and the other end is connected to the register group. One end of the I2C master controller is connected to the EEPROM via an I2C bus, and the other end is connected to the register group.

[0075] The logic controller controls the operation of the CPLD and automatically sends continuous read commands to the I2C master controller based on a preset script when the CPLD is powered on or the control register is set. The I2C slave controller communicates with the CPU, using a communication format similar to EEPROM 24C02A, supporting 256-byte random reads and byte writes. The I2C master controller writes single-byte data to the EEPROM and reads multi-byte data (configuration information) from the EEPROM. The control register triggers the loading of configuration information. The protection register initiates the writing of configuration information. The data register stores encrypted byte data. The address register stores encrypted offset sub-addresses. The configuration register stores the configuration information loaded by the CPLD from the EEPROM. The register group occupies 256 bytes of space.

[0076] Step S2 specifically involves:

[0077] The CPU converts each byte of data into first binary data, divides each first binary data in a 2:6 ratio and swaps their order to obtain first intermediate data, and then shifts each character of each first intermediate data cyclically to the right by 3 bits to obtain encrypted byte data.

[0078] The CPU converts each offset sub-address into second binary data, divides each second binary data in a 3:5 ratio and swaps their order to obtain second intermediate data, and then shifts each character of each second intermediate data cyclically to the left by 2 bits to obtain the encrypted offset sub-address.

[0079] The CPU converts each byte of data into first binary data. This first binary data is then divided in a 2:6 ratio and its order is reversed to obtain first intermediate data. Each character in the first intermediate data is then cyclically shifted 3 bits to the right to obtain encrypted byte data. Each offset sub-address is converted into second binary data. This second binary data is then divided in a 3:5 ratio and its order is reversed to obtain second intermediate data. Each character in the second intermediate data is then cyclically shifted 2 bits to the left to obtain encrypted offset sub-addresses. In other words, the byte data and offset sub-addresses are encrypted using a preset data transformation rule. Without knowing the corresponding data transformation rule, the encrypted byte data and encrypted offset sub-addresses cannot be cracked. Furthermore, the use of different data transformation rules for the byte data and offset sub-addresses further increases the difficulty of cracking. At least six security measures are employed (first division ratio, first displacement direction, first displacement distance, second division ratio, second displacement direction, and second displacement distance), greatly improving the security of byte data and offset sub-address transmission and storage, and consequently, significantly enhancing the security of CPLD configuration information loading.

[0080] Step S4 specifically involves:

[0081] The I2C slave controller, based on the write command sent by the CPU, writes the received encrypted byte data and encrypted offset sub-address into the data register and address register in real time, respectively. It also writes each character carried by the received protection identifier into the protection register in a preset standard writing order and records the actual writing order.

[0082] Step S5 specifically involves:

[0083] The CPLD's logic controller monitors the setting status of the protection register in real time. When the protection register is set, it performs a first-level verification on the actual writing order based on the preset standard writing order, and then performs a second-level verification on the protection identifier written to the protection register through the locally pre-stored protection identifier. Finally, it controls the I2C master controller to read the encrypted byte data and the encrypted offset sub-address from the data register and the address register, respectively.

[0084] By writing each character carried by the protection identifier into the protection register in a preset standard writing order and recording the actual writing order, when the logic controller detects that the protection register is set, it performs a first-level verification on the actual writing order based on the standard writing order, and then performs a second-level verification on the protection identifier written to the protection register using the locally pre-stored protection identifier. Only when both verifications pass can the I2C master controller be controlled to read the encrypted byte data and the encrypted offset sub-address from the data register and the address register, respectively. That is, before reading the encrypted byte data and the encrypted offset sub-address, not only must the protection register store the correct protection identifier, but the protection identifier must also be written in the standard writing order. For example, if the protection identifier is set to 0xA5 / 0xA4 / 0xA3 / 0xA2 / 0xB0 / 0xB1 / 0xB2 / 0xB3 (8 bytes), these 8 bytes must be written one by one in the set standard writing order. Otherwise, the verification will fail. Two security measures are taken (the value of the protection identifier and the writing order of the protection identifier) ​​to prevent the contents stored in the data register and the address register from being read illegally, thereby further improving the security of CPLD configuration information loading.

[0085] Step S6 specifically involves:

[0086] The I2C main controller shifts each character of the encrypted byte data cyclically 3 bits to the left to obtain the first intermediate data. It then divides the first intermediate data in a 6:2 ratio and rearranges the order to obtain the first binary data. The first binary data is then converted to plaintext to obtain the byte data, thus completing the decryption of the encrypted byte data. Next, it shifts each character of the encrypted offset sub-address cyclically 2 bits to the right to obtain the second intermediate data. This second intermediate data is then divided in a 5:3 ratio and rearranged to obtain the second binary data. The second binary data is then converted to plaintext to obtain the offset sub-address, thus completing the decryption of the encrypted offset sub-address.

[0087] The I2C master controller writes one byte of data into the EEPROM in real time based on the offset sub-address.

[0088] Step S7 specifically involves:

[0089] After the I2C master controller writes the byte data, it sends a write completion feedback to the logic controller in real time. The logic controller forwards the write completion feedback to the CPU in real time. The CPU executes the writing of the next byte data based on the write completion feedback until all the byte data is written. Then, it sends a write end notification to the logic controller through the I2C slave controller.

[0090] The logic controller clears the protection register based on the received end write notification, prohibits write operations, reads the configuration information written to the EEPROM through the I2C master controller and calculates the CRC8 check value, and sends the CRC8 check value to the CPU.

[0091] After writing byte data via the I2C master controller, a write completion feedback is sent to the logic controller in real time. The logic controller forwards the write completion feedback to the CPU in real time. The CPU executes the writing of the next byte of data based on the file number until all bytes of data are written. Then, it sends a write end notification to the logic controller via the I2C slave controller. Based on the write end notification, the logic controller clears the protection register, reads the configuration information written to the EEPROM via the I2C master controller, calculates the CRC8 check value, and sends the CRC8 check value to the CPU. The CPU uses the CRC8 check value to verify the integrity of the configuration information written. In other words, during the configuration information writing process, the CPU and CPLD interact in real time with the write progress through write completion feedback and write end notification. When all writing is completed, the protection register is cleared in time to avoid illegal writing. The CRC8 check value is also used to verify whether the configuration information written to the EEPROM is complete, thereby greatly improving the reliability of CPLD configuration information writing.

[0092] The CPU performs integrity verification on the configuration information written based on the received CRC8 check value to obtain the verification result. Based on the verification result, writing time, configuration information, offset address, and CPLD serial number, it generates a write log and stores and backs up the write log.

[0093] By generating write logs that include verification results, write time, configuration information, offset address, and CPLD serial number, and storing and backing up the write logs, it is easy to trace the source later.

[0094] By encrypting byte data and offset sub-addresses (first segmentation ratio, first displacement direction, first displacement distance, second segmentation ratio, second displacement direction, second displacement distance), verifying protection identifiers (value of protection identifier, writing order of protection identifier), verifying integrity (CRC8 check value of configuration information), clearing protection registers in a timely manner, and isolating the CPU and EEPROM through CPLD, the security of CPLD configuration information loading is greatly improved.

[0095] A preferred embodiment of the CPLD configuration information power-on loading system based on dynamic voltage regulation of the present invention includes the following modules:

[0096] The configuration information preprocessing module is used by the CPU to obtain the configuration information to be loaded by the CPLD and the offset address corresponding to the configuration information, and to generate the offset sub-address of each byte of data in the configuration information based on the offset address.

[0097] An encryption module is used by the CPU to encrypt each byte data and the offset sub-address into encrypted byte data and encrypted offset sub-address, respectively.

[0098] The data transmission module is used by the CPU to send a preset protection identifier, the first encrypted byte data, and the encrypted offset sub-address corresponding to the encrypted byte data to the CPLD's I2C slave controller via the I2C bus.

[0099] The data storage module is used to write the received protection identifier, encrypted byte data, and encrypted offset sub-address from the I2C slave controller into the protection register, data register, and address register, respectively.

[0100] The protection identifier verification module is used by the CPLD's logic controller to verify the protection identifier written in the protection register, and then control the I2C master controller to read the encrypted byte data and the encrypted offset sub-address from the data register and the address register, respectively.

[0101] The first byte data writing module is used by the I2C host controller to decrypt the encrypted byte data and the encrypted offset sub-address to obtain the corresponding byte data and offset sub-address, and write the byte data into the EEPROM based on the offset sub-address;

[0102] The second byte data writing module is used by the logic controller to forward the write completion feedback sent by the I2C master controller to the CPU to execute the writing of the next byte of data until all the bytes of data are written and the protection register is cleared.

[0103] The configuration information power-on loading module is used to monitor the power supply voltage in real time through a voltage sensor when the CPLD is powered on or the control register is set. The voltage regulator dynamically adjusts the power supply voltage to keep it within a preset voltage range. The logic controller automatically sends a continuous read command to the I2C master controller. Based on the received continuous read command, the I2C master controller loads each byte of data stored in the EEPROM into the configuration register to complete the automatic power-on loading of the configuration information.

[0104] The CPLD includes a logic controller, an I2C slave controller, an I2C master controller, and a register group. The register group includes a control register, a protection register, a data register, an address register, and a configuration register. The logic controller is connected to the I2C slave controller, the I2C master controller, and the register group. One end of the I2C slave controller is connected to the CPU via an I2C bus, and the other end is connected to the register group. One end of the I2C master controller is connected to the EEPROM via an I2C bus, and the other end is connected to the register group.

[0105] The logic controller controls the operation of the CPLD and automatically sends continuous read commands to the I2C master controller based on a preset script when the CPLD is powered on or the control register is set. The I2C slave controller communicates with the CPU, using a communication format similar to EEPROM 24C02A, supporting 256-byte random reads and byte writes. The I2C master controller writes single-byte data to the EEPROM and reads multi-byte data (configuration information) from the EEPROM. The control register triggers the loading of configuration information. The protection register initiates the writing of configuration information. The data register stores encrypted byte data. The address register stores encrypted offset sub-addresses. The configuration register stores the configuration information loaded by the CPLD from the EEPROM. The register group occupies 256 bytes of space.

[0106] The encryption module is specifically used for:

[0107] The CPU converts each byte of data into first binary data, divides each first binary data in a 2:6 ratio and swaps their order to obtain first intermediate data, and then shifts each character of each first intermediate data cyclically to the right by 3 bits to obtain encrypted byte data.

[0108] The CPU converts each offset sub-address into second binary data, divides each second binary data in a 3:5 ratio and swaps their order to obtain second intermediate data, and then shifts each character of each second intermediate data cyclically to the left by 2 bits to obtain the encrypted offset sub-address.

[0109] The CPU converts each byte of data into first binary data. This first binary data is then divided in a 2:6 ratio and its order is reversed to obtain first intermediate data. Each character in the first intermediate data is then cyclically shifted 3 bits to the right to obtain encrypted byte data. Each offset sub-address is converted into second binary data. This second binary data is then divided in a 3:5 ratio and its order is reversed to obtain second intermediate data. Each character in the second intermediate data is then cyclically shifted 2 bits to the left to obtain encrypted offset sub-addresses. In other words, the byte data and offset sub-addresses are encrypted using a preset data transformation rule. Without knowing the corresponding data transformation rule, the encrypted byte data and encrypted offset sub-addresses cannot be cracked. Furthermore, the use of different data transformation rules for the byte data and offset sub-addresses further increases the difficulty of cracking. At least six security measures are employed (first division ratio, first displacement direction, first displacement distance, second division ratio, second displacement direction, and second displacement distance), greatly improving the security of byte data and offset sub-address transmission and storage, and consequently, significantly enhancing the security of CPLD configuration information loading.

[0110] The data storage module is specifically used for:

[0111] The I2C slave controller, based on the write command sent by the CPU, writes the received encrypted byte data and encrypted offset sub-address into the data register and address register in real time, respectively. It also writes each character carried by the received protection identifier into the protection register in a preset standard writing order and records the actual writing order.

[0112] The protection identifier verification module is specifically used for:

[0113] The CPLD's logic controller monitors the setting status of the protection register in real time. When the protection register is set, it performs a first-level verification on the actual writing order based on the preset standard writing order, and then performs a second-level verification on the protection identifier written to the protection register through the locally pre-stored protection identifier. Finally, it controls the I2C master controller to read the encrypted byte data and the encrypted offset sub-address from the data register and the address register, respectively.

[0114] By writing each character carried by the protection identifier into the protection register in a preset standard writing order and recording the actual writing order, when the logic controller detects that the protection register is set, it performs a first-level verification on the actual writing order based on the standard writing order, and then performs a second-level verification on the protection identifier written to the protection register using the locally pre-stored protection identifier. Only when both verifications pass can the I2C master controller be controlled to read the encrypted byte data and the encrypted offset sub-address from the data register and the address register, respectively. That is, before reading the encrypted byte data and the encrypted offset sub-address, not only must the protection register store the correct protection identifier, but the protection identifier must also be written in the standard writing order. For example, if the protection identifier is set to 0xA5 / 0xA4 / 0xA3 / 0xA2 / 0xB0 / 0xB1 / 0xB2 / 0xB3 (8 bytes), these 8 bytes must be written one by one in the set standard writing order. Otherwise, the verification will fail. Two security measures are taken (the value of the protection identifier and the writing order of the protection identifier) ​​to prevent the contents stored in the data register and the address register from being read illegally, thereby further improving the security of CPLD configuration information loading.

[0115] The first byte data writing module is specifically used for:

[0116] The I2C main controller shifts each character of the encrypted byte data cyclically 3 bits to the left to obtain the first intermediate data. It then divides the first intermediate data in a 6:2 ratio and rearranges the order to obtain the first binary data. The first binary data is then converted to plaintext to obtain the byte data, thus completing the decryption of the encrypted byte data. Next, it shifts each character of the encrypted offset sub-address cyclically 2 bits to the right to obtain the second intermediate data. This second intermediate data is then divided in a 5:3 ratio and rearranged to obtain the second binary data. The second binary data is then converted to plaintext to obtain the offset sub-address, thus completing the decryption of the encrypted offset sub-address.

[0117] The I2C master controller writes one byte of data into the EEPROM in real time based on the offset sub-address.

[0118] The second byte data writing module is specifically used for:

[0119] After the I2C master controller writes the byte data, it sends a write completion feedback to the logic controller in real time. The logic controller forwards the write completion feedback to the CPU in real time. The CPU executes the writing of the next byte data based on the write completion feedback until all the byte data is written. Then, it sends a write end notification to the logic controller through the I2C slave controller.

[0120] The logic controller clears the protection register based on the received end write notification, prohibits write operations, reads the configuration information written to the EEPROM through the I2C master controller and calculates the CRC8 check value, and sends the CRC8 check value to the CPU.

[0121] After writing byte data via the I2C master controller, a write completion feedback is sent to the logic controller in real time. The logic controller forwards the write completion feedback to the CPU in real time. The CPU executes the writing of the next byte of data based on the file number until all bytes of data are written. Then, it sends a write end notification to the logic controller via the I2C slave controller. Based on the write end notification, the logic controller clears the protection register, reads the configuration information written to the EEPROM via the I2C master controller, calculates the CRC8 check value, and sends the CRC8 check value to the CPU. The CPU uses the CRC8 check value to verify the integrity of the configuration information written. In other words, during the configuration information writing process, the CPU and CPLD interact in real time with the write progress through write completion feedback and write end notification. When all writing is completed, the protection register is cleared in time to avoid illegal writing. The CRC8 check value is also used to verify whether the configuration information written to the EEPROM is complete, thereby greatly improving the reliability of CPLD configuration information writing.

[0122] The CPU performs integrity verification on the configuration information written based on the received CRC8 check value to obtain the verification result. Based on the verification result, writing time, configuration information, offset address, and CPLD serial number, it generates a write log and stores and backs up the write log.

[0123] By generating write logs that include verification results, write time, configuration information, offset address, and CPLD serial number, and storing and backing up the write logs, it is easy to trace the source later.

[0124] By encrypting byte data and offset sub-addresses (first segmentation ratio, first displacement direction, first displacement distance, second segmentation ratio, second displacement direction, second displacement distance), verifying protection identifiers (value of protection identifier, writing order of protection identifier), verifying integrity (CRC8 check value of configuration information), clearing protection registers in a timely manner, and isolating the CPU and EEPROM through CPLD, the security of CPLD configuration information loading is greatly improved.

[0125] In summary, the advantages of this invention are as follows:

[0126] 1. The CPU obtains the configuration information to be loaded by the CPLD and the corresponding offset address. Based on the offset address, it generates the offset sub-address of each byte of data in the configuration information. Then, the CPU encrypts each byte of data and the offset sub-address into encrypted byte data and encrypted offset sub-address, respectively, and sends a preset protection flag, the first encrypted byte data, and the corresponding encrypted offset sub-address to the CPLD's I2C slave controller. Next, the I2C slave controller writes the protection flag, encrypted byte data, and encrypted offset sub-address into the protection register, data register, and address register, respectively. After verifying the protection flag written to the protection register, the CPLD's logic controller controls the I2C master controller to read the encrypted byte data and encrypted offset sub-address from the data register and address register, respectively. The I2C master controller decrypts the encrypted byte data and encrypted offset sub-address to obtain the corresponding byte data and offset sub-address, and writes the byte data into the EEPROM based on the offset sub-address. Then, the logic controller forwards the write completion feedback sent by the I2C master controller to the CPU to execute the next step. The process involves writing byte data until all bytes are written and the protection register is cleared. When the CPLD powers on or the control register is set, the logic controller automatically sends a continuous read command to the I2C master controller. The I2C master controller loads the bytes of data stored in the EEPROM into the configuration register based on the continuous read command, thus completing the automatic loading of configuration information upon power-on. In other words, the CPLD connects to the CPU and EEPROM via the I2C bus. The CPU interacts with the CPLD through the register group set by the CPLD to write configuration information into the EEPROM. When the CPLD powers on or the control register is set, the configuration information stored in the EEPROM is automatically loaded into the configuration register. Compared with the traditional method, it does not require managing a large number of firmware versions or occupying a large number of IO pins. The writing and updating of configuration information can be achieved solely through the register group. Furthermore, during the configuration information writing process, security measures such as encryption of byte data and offset sub-addresses, verification of protection identifiers, and integrity verification are combined, ultimately greatly improving the convenience, flexibility, and security of CPLD configuration information loading.

[0127] 2. The CPU converts each byte of data into first binary data. This first binary data is then divided in a 2:6 ratio and its order is reversed to obtain first intermediate data. Each character in the first intermediate data is then cyclically shifted 3 bits to the right to obtain encrypted byte data. Each offset sub-address is converted into second binary data. This second binary data is then divided in a 3:5 ratio and its order is reversed to obtain second intermediate data. Each character in the second intermediate data is then cyclically shifted 2 bits to the left to obtain encrypted offset sub-addresses. In other words, the byte data and offset sub-addresses are encrypted using preset data transformation rules. Without knowing the corresponding data transformation rules, the encrypted byte data and encrypted offset sub-addresses cannot be cracked. Furthermore, the different data transformation rules used for the byte data and offset sub-addresses further increase the difficulty of cracking. At least six security measures are employed (first division ratio, first displacement direction, first displacement distance, second division ratio, second displacement direction, second displacement distance), greatly improving the security of byte data and offset sub-address transmission and storage, and consequently, significantly enhancing the security of CPLD configuration information loading.

[0128] 3. By writing each character carried by the protection identifier into the protection register in a preset standard writing order and recording the actual writing order, when the logic controller detects that the protection register is set, it performs a first-level verification on the actual writing order based on the standard writing order, and then performs a second-level verification on the protection identifier written to the protection register using the locally pre-stored protection identifier. Only when both verifications pass can the I2C master controller be controlled to read the encrypted byte data and the encrypted offset sub-address from the data register and the address register, respectively. That is, before reading the encrypted byte data and the encrypted offset sub-address, not only must the protection register store the correct protection identifier, but the protection identifier must also be written in the standard writing order. For example, if the protection identifier is set to 0xA5 / 0xA4 / 0xA3 / 0xA2 / 0xB0 / 0xB1 / 0xB2 / 0xB3 (8 bytes), these 8 bytes must be written one by one in the set standard writing order. Otherwise, the verification will fail. Two security measures are taken (the value of the protection identifier and the writing order of the protection identifier) ​​to prevent the contents stored in the data register and the address register from being read illegally, thereby further improving the security of CPLD configuration information loading.

[0129] 4. After writing byte data via the I2C master controller, a write completion feedback is sent to the logic controller in real time. The logic controller forwards the write completion feedback to the CPU in real time. The CPU executes the writing of the next byte of data based on the file number until all byte data is written. Then, it sends a write end notification to the logic controller via the I2C slave controller. The logic controller clears the protection register based on the write end notification, reads the configuration information written to the EEPROM via the I2C master controller, calculates the CRC8 check value, and sends the CRC8 check value to the CPU. The CPU performs integrity verification of the configuration information writing based on the CRC8 check value. In other words, during the configuration information writing process, the CPU and CPLD interact in real time with the write progress through write completion feedback and write end notification. When all writing is completed, the protection register is cleared in time to avoid illegal writing. The CRC8 check value is also used to verify whether the configuration information written to the EEPROM is complete, thereby greatly improving the reliability of CPLD configuration information writing.

[0130] 5. Generate write logs that include verification results, write time, configuration information, offset address, and CPLD serial number, and store and back up the write logs to facilitate later traceability.

[0131] 6. By encrypting byte data and offset sub-addresses (first segmentation ratio, first displacement direction, first displacement distance, second segmentation ratio, second displacement direction, second displacement distance), verifying protection identifiers (value of protection identifier, writing order of protection identifier), verifying integrity (CRC8 check value of configuration information), clearing protection registers in a timely manner, and isolating the CPU and EEPROM through CPLD, the security of CPLD configuration information loading is greatly improved.

[0132] 7. By monitoring the power supply voltage in real time through a voltage sensor when the CPLD is powered on or the control register is set, and dynamically adjusting the power supply voltage through a voltage regulator to keep it within a preset voltage range, the reliability of CPLD configuration information loading is greatly improved, avoiding configuration information loading failure caused by unstable power supply voltage.

[0133] While specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and not intended to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should be covered within the scope of protection of the claims of the present invention.

Claims

1. A method for power-on loading of CPLD configuration information based on dynamic voltage regulation, characterized in that: Includes the following steps: Step S1: The CPU obtains the configuration information to be loaded by the CPLD and the offset address corresponding to the configuration information, and generates the offset sub-address of each byte of data in the configuration information based on the offset address; Step S2: The CPU encrypts each byte data and offset sub-address into encrypted byte data and encrypted offset sub-address, respectively; Step S3: The CPU sends a preset protection identifier, the first encrypted byte data, and the encrypted offset sub-address corresponding to the encrypted byte data to the CPLD's I2C slave controller via the I2C bus. Step S4: The I2C slave controller writes the received protection identifier, encrypted byte data, and encrypted offset sub-address into the protection register, data register, and address register, respectively. Step S5: After verifying the protection identifier written to the protection register, the logic controller of the CPLD controls the I2C master controller to read the encrypted byte data and the encrypted offset sub-address from the data register and the address register, respectively. Step S6: The I2C master controller decrypts the encrypted byte data and the encrypted offset sub-address to obtain the corresponding byte data and offset sub-address, and writes the byte data into the EEPROM based on the offset sub-address; Step S7: The logic controller forwards the write completion feedback sent by the I2C master controller to the CPU to execute the writing of the next byte of data until all the bytes of data have been written, and then clears the protection register. In step S8, when the CPLD is powered on or the control register is set, the power supply voltage is monitored in real time by a voltage sensor, and the power supply voltage is dynamically adjusted by a voltage regulator to keep the power supply voltage within a preset voltage range. The logic controller automatically sends a continuous read command to the I2C master controller. Based on the received continuous read command, the I2C master controller loads each byte of data stored in the EEPROM into the configuration register to complete the automatic loading of the configuration information upon power-on.

2. The power-on loading method for CPLD configuration information based on dynamic voltage regulation as described in claim 1, characterized in that: Step S2 specifically involves: The CPU converts each byte of data into first binary data, divides each first binary data in a 2:6 ratio and swaps their order to obtain first intermediate data, and then shifts each character of each first intermediate data cyclically to the right by 3 bits to obtain encrypted byte data. The CPU converts each offset sub-address into second binary data, divides each second binary data in a 3:5 ratio and swaps their order to obtain second intermediate data, and then shifts each character of each second intermediate data cyclically to the left by 2 bits to obtain the encrypted offset sub-address.

3. The power-on loading method for CPLD configuration information based on dynamic voltage regulation as described in claim 1, characterized in that: Step S4 specifically involves: The I2C slave controller, based on the write command sent by the CPU, writes the received encrypted byte data and encrypted offset sub-address into the data register and address register in real time, respectively. It also writes each character carried by the received protection identifier into the protection register in a preset standard writing order and records the actual writing order. Step S5 specifically involves: The CPLD's logic controller monitors the setting status of the protection register in real time. When the protection register is set, it performs a first-level verification on the actual writing order based on the preset standard writing order, and then performs a second-level verification on the protection identifier written to the protection register through the locally pre-stored protection identifier. Finally, it controls the I2C master controller to read the encrypted byte data and the encrypted offset sub-address from the data register and the address register, respectively.

4. The power-on loading method for CPLD configuration information based on dynamic voltage regulation as described in claim 1, characterized in that: Step S6 specifically involves: The I2C main controller shifts each character of the encrypted byte data cyclically 3 bits to the left to obtain the first intermediate data. It then divides the first intermediate data in a 6:2 ratio and rearranges the order to obtain the first binary data. The first binary data is then converted to plaintext to obtain the byte data, thus completing the decryption of the encrypted byte data. Next, it shifts each character of the encrypted offset sub-address cyclically 2 bits to the right to obtain the second intermediate data. This second intermediate data is then divided in a 5:3 ratio and rearranged to obtain the second binary data. The second binary data is then converted to plaintext to obtain the offset sub-address, thus completing the decryption of the encrypted offset sub-address. The I2C master controller writes one byte of data into the EEPROM in real time based on the offset sub-address.

5. The power-on loading method for CPLD configuration information based on dynamic voltage regulation as described in claim 1, characterized in that: Step S7 specifically involves: After the I2C master controller writes the byte data, it sends a write completion feedback to the logic controller in real time. The logic controller forwards the write completion feedback to the CPU in real time. The CPU executes the writing of the next byte data based on the write completion feedback until all the byte data is written. Then, it sends a write end notification to the logic controller through the I2C slave controller. The logic controller clears the protection register based on the received end write notification, reads the configuration information written to the EEPROM through the I2C master controller and calculates the CRC8 check value, and sends the CRC8 check value to the CPU. The CPU performs integrity verification on the configuration information written based on the received CRC8 check value to obtain the verification result. Based on the verification result, writing time, configuration information, offset address, and CPLD serial number, it generates a write log and stores and backs up the write log.

6. A CPLD configuration information power-on loading system based on dynamic voltage regulation, characterized in that: Includes the following modules: The configuration information preprocessing module is used by the CPU to obtain the configuration information to be loaded by the CPLD and the offset address corresponding to the configuration information, and to generate the offset sub-address of each byte of data in the configuration information based on the offset address. An encryption module is used by the CPU to encrypt each byte data and the offset sub-address into encrypted byte data and encrypted offset sub-address, respectively. The data transmission module is used by the CPU to send a preset protection identifier, the first encrypted byte data, and the encrypted offset sub-address corresponding to the encrypted byte data to the CPLD's I2C slave controller via the I2C bus. The data storage module is used to write the received protection identifier, encrypted byte data, and encrypted offset sub-address from the I2C slave controller into the protection register, data register, and address register, respectively. The protection identifier verification module is used by the CPLD's logic controller to verify the protection identifier written in the protection register, and then control the I2C master controller to read the encrypted byte data and the encrypted offset sub-address from the data register and the address register, respectively. The first byte data writing module is used by the I2C host controller to decrypt the encrypted byte data and the encrypted offset sub-address to obtain the corresponding byte data and offset sub-address, and write the byte data into the EEPROM based on the offset sub-address; The second byte data writing module is used by the logic controller to forward the write completion feedback sent by the I2C master controller to the CPU to execute the writing of the next byte of data until all the bytes of data are written and the protection register is cleared. The configuration information power-on loading module is used to monitor the power supply voltage in real time through a voltage sensor when the CPLD is powered on or the control register is set. The voltage regulator dynamically adjusts the power supply voltage to keep it within a preset voltage range. The logic controller automatically sends a continuous read command to the I2C master controller. Based on the received continuous read command, the I2C master controller loads each byte of data stored in the EEPROM into the configuration register to complete the automatic power-on loading of the configuration information.

7. The CPLD configuration information power-on loading system based on dynamic voltage regulation as described in claim 6, characterized in that: The encryption module is specifically used for: The CPU converts each byte of data into first binary data, divides each first binary data in a 2:6 ratio and swaps their order to obtain first intermediate data, and then shifts each character of each first intermediate data cyclically to the right by 3 bits to obtain encrypted byte data. The CPU converts each offset sub-address into second binary data, divides each second binary data in a 3:5 ratio and swaps their order to obtain second intermediate data, and then shifts each character of each second intermediate data cyclically to the left by 2 bits to obtain the encrypted offset sub-address.

8. The CPLD configuration information power-on loading system based on dynamic voltage regulation as described in claim 6, characterized in that: The data storage module is specifically used for: The I2C slave controller, based on the write command sent by the CPU, writes the received encrypted byte data and encrypted offset sub-address into the data register and address register in real time, respectively. It also writes each character carried by the received protection identifier into the protection register in a preset standard writing order and records the actual writing order. The protection identifier verification module is specifically used for: The CPLD's logic controller monitors the setting status of the protection register in real time. When the protection register is set, it performs a first-level verification on the actual writing order based on the preset standard writing order, and then performs a second-level verification on the protection identifier written to the protection register through the locally pre-stored protection identifier. Finally, it controls the I2C master controller to read the encrypted byte data and the encrypted offset sub-address from the data register and the address register, respectively.

9. The CPLD configuration information power-on loading system based on dynamic voltage regulation as described in claim 6, characterized in that: The first byte data writing module is specifically used for: The I2C main controller shifts each character of the encrypted byte data cyclically 3 bits to the left to obtain the first intermediate data. It then divides the first intermediate data in a 6:2 ratio and rearranges the order to obtain the first binary data. The first binary data is then converted to plaintext to obtain the byte data, thus completing the decryption of the encrypted byte data. Next, it shifts each character of the encrypted offset sub-address cyclically 2 bits to the right to obtain the second intermediate data. This second intermediate data is then divided in a 5:3 ratio and rearranged to obtain the second binary data. The second binary data is then converted to plaintext to obtain the offset sub-address, thus completing the decryption of the encrypted offset sub-address. The I2C master controller writes one byte of data into the EEPROM in real time based on the offset sub-address.

10. The CPLD configuration information power-on loading system based on dynamic voltage regulation as described in claim 6, characterized in that: The second byte data writing module is specifically used for: After the I2C master controller writes the byte data, it sends a write completion feedback to the logic controller in real time. The logic controller forwards the write completion feedback to the CPU in real time. The CPU executes the writing of the next byte data based on the write completion feedback until all the byte data is written. Then, it sends a write end notification to the logic controller through the I2C slave controller. The logic controller clears the protection register based on the received end write notification, reads the configuration information written to the EEPROM through the I2C master controller and calculates the CRC8 check value, and sends the CRC8 check value to the CPU. The CPU performs integrity verification on the configuration information written based on the received CRC8 check value to obtain the verification result. Based on the verification result, writing time, configuration information, offset address, and CPLD serial number, it generates a write log and stores and backs up the write log.

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