Display substrate and display device

Abstract

Disclosed in the present invention are a display substrate and a display device. The display substrate comprises: M trace groups, wherein at least one trace group among the M trace groups comprises a gate line and a first trace extending in a first direction, and the first trace and the gate line are electrically connected at at least one end position; N second traces extending in a second direction and arranged in the first direction, wherein an n-th second trace is electrically connected to the first trace in an n-th trace group at an intersection position, n≤N, n≤M, and M, N, and n are positive integers; and a first gate drive circuit located in an opposite bonding region, wherein one end of each second trace is electrically connected to the first gate drive circuit, to provide a signal of the first gate drive circuit to the gate lines.

Description

Display substrate and display device

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202510191926.1, filed on February 20, 2025, entitled "Display Substrate and Display Device," the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to the field of display technology, and more particularly to a display substrate and a display device. Background Technology

[0004] Active-matrix organic light-emitting diode (AMOLED) displays have advantages such as active light emission without the need for a backlight, high contrast, and flexibility, making them highly likely to become the next-generation display technology. Gate Driver On Array (GOA) technology is a technique that integrates the gate driving circuitry of a display device onto an array substrate. Using GOA technology can reduce the number of ICs used, thereby lowering production costs and power consumption. Furthermore, GOA technology can also enable narrower bezels in display devices. Summary of the Invention

[0005] This invention provides a display substrate and a display device. The display substrate has a display area, a bonding area located on one side of the display area, and a bonding opposite area located on the other side of the display area and opposite to the bonding area; wherein, the display substrate includes:

[0006] Substrate;

[0007] M routing groups, the M routing groups extending along a first direction and arranged along a second direction, at least one of the M routing groups includes: a gate line extending along the first direction and a first routing line; the first routing line and the gate line are electrically connected at at least one end position;

[0008] N second traces, the N second traces extending along the second direction and arranged along the first direction; wherein, the nth second trace is electrically connected to the first trace in the nth trace group at the intersection position, n≤N, n≤M, and M, N, n are positive integers;

[0009] A first gate drive circuit is located in the bonding opposite region; one end of the second trace is electrically connected to the first gate drive circuit to provide the signal of the first gate drive circuit to the gate line.

[0010] In one possible implementation, the first trace includes: a first trace main portion extending along the first direction, and a first protrusion connected to the first trace main portion; the width of the first protrusion perpendicular to the first direction is greater than the width of the first trace main portion perpendicular to the first direction.

[0011] The second trace includes: a second trace main portion extending along the second direction, and a second protrusion connected to the second trace main portion; the width of the second protrusion perpendicular to the second direction is greater than the width of the second trace main portion perpendicular to the second direction.

[0012] The orthographic projection of the second protrusion on the substrate overlaps with the orthographic projection of the first protrusion on the substrate, and a hole is drilled at the overlapping position for electrical connection.

[0013] In one possible implementation, the first trace and the gate line are electrically connected at both ends in the extension direction.

[0014] In one possible implementation, the first trace further includes: a third protrusion connected to the end of the main portion of the first trace; the width of the third protrusion in the direction perpendicular to the first direction is greater than the width of the main portion of the first trace in the direction perpendicular to the first direction.

[0015] The gate line includes: a gate line main portion extending along the first direction, and a gate line protrusion connected to the end of the gate line main portion; the width of the gate line protrusion perpendicular to the first direction is greater than the width of the gate line main portion perpendicular to the first direction.

[0016] The orthographic projection of the third protrusion on the substrate overlaps with the orthographic projection of the gate line protrusion on the substrate, and a hole is drilled at the overlapping position for connection.

[0017] In one possible implementation, the third protrusion includes: a first sub-protrusion and a second sub-protrusion arranged and connected along the second direction;

[0018] The first sub-protrusion is connected to the first main trace portion; the orthographic projection of the second sub-protrusion on the substrate covers the orthographic projection of the gate line protrusion on the substrate.

[0019] In one possible implementation, the display substrate further includes: a plurality of data lines extending along the second direction and arranged along the first direction;

[0020] The second trace is on the same layer and made of the same material as the data line.

[0021] In one possible implementation, the data line is located on the side of the gate line opposite to the substrate; the first trace is located on the side of the data line opposite to the gate line.

[0022] In one possible implementation, the first gate driving circuit includes: a plurality of M gate driving units arranged sequentially and cascaded along the first direction.

[0023] One end of the nth second trace is electrically connected to the nth gate driving unit to provide the signal of the nth gate driving unit to the gate line in the nth trace group.

[0024] In one possible implementation, the first gate driving circuit includes: a first sub-gate driving circuit, and a second sub-gate driving circuit located on the side of the first sub-gate driving circuit away from the display area; the first sub-gate driving circuit and the second sub-gate driving circuit extend along the first direction and are arranged along the second direction;

[0025] The first sub-gate driving circuit includes: a plurality of M first sub-gate driving units arranged sequentially along the first direction and cascaded sequentially from the first end to the second end; the second sub-gate driving circuit includes: a plurality of M second sub-gate driving units arranged sequentially along the first direction and cascaded sequentially from the second end to the first end.

[0026] In one possible implementation, the display substrate further includes: P third traces, which extend along the second direction and are arranged along the first direction; wherein the nth third trace is electrically connected to the first trace in the M-(n-1)th trace group at the intersection position, n≤P, and P is a positive integer.

[0027] In one possible implementation, one end of the nth second trace is electrically connected to the nth first sub-gate driving unit from the first end to the second end, so as to provide the signal of the nth first sub-gate driving unit to the gate line in the nth trace group.

[0028] One end of the third trace of the nth term is electrically connected to the M-(n-1)th second sub-gate driving unit from the first end to the second end, so as to provide the signal of the M-(n-1)th second sub-gate driving unit from the first end to the second end to the gate line in the M-(n-1)th trace group.

[0029] In one possible implementation, the third trace is in the same layer and made of the same material as the second trace.

[0030] In one possible implementation, the display substrate further has a first side area connecting one end of the bonding area and one end of the bonding opposite side area, and a second side area connecting the other end of the bonding area and the other end of the bonding opposite side area.

[0031] The display substrate further includes: a plurality of first signal lines; the first signal lines extend from one end of the bonding area, through the first side area, the bonding opposite side area, and the second side area to the other end of the bonding area.

[0032] In one possible implementation, the first signal line includes: a trigger signal line, and / or a first clock signal line, and / or a second clock signal line.

[0033] This disclosure also provides a display device, which includes the display substrate as described in this disclosure. Attached Figure Description

[0034] Figure 1 is a schematic diagram of a display substrate provided in an embodiment of the present invention;

[0035] Figure 2A can be a magnified schematic diagram of a sub-pixel in Figure 1;

[0036] Figure 2B can be a schematic diagram of Figure 2A that only includes the first trace G1 and the second trace G2;

[0037] Figure 3A can be a magnified schematic diagram of the end of the pixel row in Figure 1;

[0038] Figure 3B can be a schematic diagram of Figure 3A at the position indicated by the dashed line, including only the first trace G1 and the gate line G0;

[0039] Figure 3C can be a schematic diagram of Figure 3A including only the first trace G1;

[0040] Figure 4 is a second schematic diagram of the display substrate provided in an embodiment of the present invention;

[0041] Figure 5 is a third schematic diagram of the display substrate provided in an embodiment of the present invention;

[0042] Figure 6 is a fourth schematic diagram of the display substrate provided in an embodiment of the present invention. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0044] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as “comprising” or “including” mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as “connected” or “linked” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as “upper,” “lower,” “left,” and “right” are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0045] As used herein, “approximately” or “substantially the same” includes the stated value and means within an acceptable range of deviations from the specific value, as determined by a person skilled in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., limitations of the measurement system). For example, “substantially the same” may mean a difference relative to the stated value within one or more standard deviations, or within ±30%, 20%, 10%, or 5%.

[0046] In the accompanying drawings, the thicknesses of layers, films, panels, regions, etc., are enlarged for clarity. Exemplary embodiments are described herein with reference to cross-sectional views that are schematic diagrams of idealized embodiments. Thus, deviations from the shapes shown in the drawings will be expected as a result of, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes of the regions shown herein, but rather include deviations in shape caused, for example, by manufacturing processes. For example, regions illustrated or described as flat may typically have rough and / or non-linear characteristics. Furthermore, sharp corners illustrated may be rounded. Thus, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, nor are they intended to limit the scope of the claims.

[0047] To keep the following description of the embodiments of this disclosure clear and concise, detailed descriptions of known functions and known components are omitted.

[0048] As AMOLED products mature and market demand for ultra-narrow bezels intensifies, achieving narrow bezel designs without compromising image quality (especially with some single-sided driving) has become increasingly important. The main challenges of narrow bezels lie in the left, right, and bottom bezels, while the top bezel is often designed to be larger simply to maintain a similar size to the left, right, and bottom bezels, even though it doesn't actually require that much space. One of the main factors limiting the left and right bezels is the GOA (Graphics On-Grid) circuitry. Due to increasing demands for display quality, all GOAs are generally required to be dual-sided driven, and to optimize display, more GOA signals are often introduced, for example, requiring five GOAs. Therefore, the space on the top bezel can be used to house the GOAs, thus reducing the size of the left and right bezels.

[0049] In related technologies, when the GOA portion is set on the top bezel of the display substrate, the position of the brightest (or darkest) sub-pixel of the GOA signal in each row of pixels will be different. For example, in the first pixel row, the brightest sub-pixel is the first column of sub-pixels, while in the second pixel row, the brightest sub-pixel may be the second or fourth column of sub-pixels. The mura of the entire display panel has no regularity, making grayscale compensation (Demura) difficult to perform.

[0050] Referring to Figure 1, an embodiment of the present invention provides a display substrate having a display area AA, a bonding area BB1 located on one side of the display area AA, a bonding opposite side area BB2 located on the other side of the display area AA and opposite to the bonding area BB1, a first side area BB3 connecting one end of the bonding area BB1 and one end of the bonding opposite side area BB2, and a second side area BB4 connecting the other end of the bonding area BB1 and the other end of the bonding opposite side area BB2; wherein, the display substrate includes:

[0051] Substrate;

[0052] M trace groups G, which extend along a first direction X and are arranged along a second direction Y. At least one of the trace groups G includes: a gate line G0 extending along the first direction X and a first trace G1; the first trace G1 and the gate line G0 are electrically connected at at least one end position (as shown by the large black dot in Figure 1).

[0053] N second traces G2, extending along the second direction Y and arranged along the first direction X; wherein, the nth second trace G2 is electrically connected to the first trace G1 in the nth trace group G at the intersection position (as shown by the small black dot in Figure 1), n≤N, n≤M, and M, N, and n are positive integers; for example, as shown in Figure 1, the second second trace G2 in the direction from the first side area BB3 to the second side area BB4 (that is, from left to right in Figure 1) is electrically connected to the first trace G1 in the second grid line group G2 in the direction from the binding opposite side area BB2 to the binding area BB1 (that is, from top to bottom in Figure 1) at the intersection position; M and N can be equal, or, or not equal;

[0054] The first gate drive circuit GOA is located in the bonding opposite region BB2; one end of the second trace G2 is electrically connected to the first gate drive circuit GOA to provide the signal of the first gate drive circuit GOA to the gate line G0.

[0055] In this embodiment, the display substrate includes a first gate driving circuit GOA located in the bonding opposite side region BB2, which can narrow the width of the left and right bezels of the display substrate, thereby achieving a narrow bezel display panel. Furthermore, the display substrate also includes a second trace G2 connected to the first gate driving circuit GOA and extending along the second direction Y, and a first trace G1 connected to the second trace G2 and extending along the first direction X. The first trace G1 is electrically connected to the gate line G0 at its end position. Thus, the signal output by the first gate driving circuit GOA can be transmitted to the end portion of the gate line G0 through the second trace G2 and the first trace G1. The signal is transmitted from the end of the gate line G0 into the display area. This ensures that the point from the strongest to the weakest driving force in each row of pixels is at the end and then to the center of the display area AA. In other words, the brightest to the darkest sub-pixel in each row of pixels is at the end and then to the center of the display area AA. This facilitates subsequent grayscale compensation, achieves uniform display of the display panel, and improves the problem in related technologies where the gate driving circuit is placed on the upper bezel of the display substrate. In this case, the position of the brightest (or darkest) sub-pixel in each row of pixels is different, resulting in no regularity of the mura of the entire display panel and making grayscale compensation (Demura) difficult.

[0056] In this embodiment, each second trace G2 can extend from the bonding opposite region BB2 to the bonding region BB1, and the extension length of each second trace G2 can be equal, thus simplifying the manufacturing process. The second trace G2 can intersect with multiple first traces G1, but only when it is necessary to transmit the signal of the first gate drive circuit to the gate line G0 corresponding to the pixel in that row, the first trace G1 located in the same trace group G as the gate line G0 will be electrically connected. That is, multiple first traces G1 are connected to each second trace G2 one by one.

[0057] In one possible implementation, the number of gate lines on the display substrate can be the same as the number of gate lines G0 in the wiring group G. That is, a first wiring G1 and a second wiring G2 can be provided at each gate line position in the display substrate. In other words, all gate driving circuits of the display substrate can be located in the bonding opposite side region BB2, and the scan signal of each gate line is provided by the first gate driving circuit GOA located in the bonding opposite side region BB2. In another possible implementation, the number of gate lines on the display substrate can be greater than the number of gate lines G0 in the wiring group G. That is, the first wiring G1 and the second wiring G2 can be provided at only some gate line positions in the display substrate. In other words, the display substrate can also have other gate driving circuits located in the first side region BB1 and / or the second side region BB2. The scan signals of the remaining gate lines without the first wiring G1 can be directly provided by the other gate driving circuits located in the first side region BB1 and / or the second side region BB2.

[0058] It should be noted that, in the embodiments of this disclosure, the gate line G0 extends along the first direction X, which may be the entire gate line G0 extending along the first direction X, but may be bent at some local locations; similarly, the first trace G1 extends along the first direction X, which may be the entire first trace G1 extending along the first direction X, but may be bent at some local locations; similarly, the second trace G2 extends along the second direction Y, which may be the entire second trace G2 extending along the second direction Y, but may be bent at some local locations.

[0059] In one possible implementation, referring to Figures 2A and 2B, Figure 2A can be an enlarged schematic diagram of a sub-pixel in Figure 1, and Figure 2B can be a schematic diagram of Figure 2A including only the first trace G1 and the second trace G2. The first trace G1 includes: a first trace main portion G11 extending along the first direction X, and a first protrusion G12 (which can serve as an overlap pad) connected to the first trace main portion G11; the width b1 of the first protrusion G12 in the direction perpendicular to the first direction X is greater than the width b2 of the first trace main portion G11 in the direction perpendicular to the first direction X.

[0060] The second trace G2 includes: a second trace main portion G21 extending along the second direction Y, and a second protrusion G22 (which can serve as an overlap pad) connected to the second trace main portion G21; the width b3 of the second protrusion G22 in the direction perpendicular to the second direction Y is greater than the width b4 of the second trace main portion G21 in the direction perpendicular to the second direction Y.

[0061] The orthographic projection of the second protrusion G22 onto the substrate overlaps with the orthographic projection of the first protrusion G12 onto the substrate, and an electrical connection is made by drilling a hole at the overlapping position. For example, as shown in FIG2B, the second protrusion G22 and the first protrusion G12 are electrically connected at the overlapping position through a first via K1.

[0062] In this embodiment, the first trace G1 is further provided with a wider first protrusion G12, and the second trace G2 is further provided with a wider second protrusion G22. In this way, when making electrical connections through holes, it can have a better contact and conduction effect, avoiding the problem that the second trace G2 and the first trace G1 are too thin at the intersection, resulting in poor conduction or no conduction effect.

[0063] In one possible implementation, as shown in Figures 2A and 2B, the size of the second protrusion G22 can be larger than the size of the first protrusion G12. That is, the orthographic projection of the second protrusion G22 onto the substrate can overlap with the orthographic projection of the first protrusion G12 onto the substrate.

[0064] In one possible implementation, the second protrusion G22 and the first protrusion G12 may be provided only at the position where the second trace G2 and the first trace G1 are connected; in another possible implementation, the second protrusion G22 and the first protrusion G12 may be provided at the position where the second trace G2 and the first trace G1 intersect.

[0065] In one possible implementation, referring to Figure 1, the first trace G1 and the gate line G0 are electrically connected at both ends in the extending direction. That is, as shown in Figure 1, the first trace G1 and the gate line G0 are electrically connected at both the left and right ends. In this way, the point of strongest to weakest driving force in each row of pixels is located from the left or right edge to the center of the display area AA.

[0066] In one possible implementation, the first trace G1 and the gate line G0 may be electrically connected at one end of the extension direction. For example, they may be electrically connected only at the position near the first side area BB3, or they may be electrically connected only at the position near the second side area BB4.

[0067] In one possible implementation, referring to Figures 3A, 3B, and 3C, Figure 3A can be an enlarged schematic diagram of the pixel row end in Figure 1, Figure 3B can be a schematic diagram of Figure 3A including only the first trace G1 and the gate line G0, and Figure 3C can be a schematic diagram of Figure 3A including only the first trace G1. The first trace G1 further includes: a third protrusion G13 connected to the end of the main portion G11 of the first trace; the width b5 of the third protrusion G13 in the direction perpendicular to the first direction X is greater than the width b2 of the main portion G11 of the first trace in the direction perpendicular to the first direction X.

[0068] The gate line G0 includes: a gate line main portion G01 extending along a first direction X, and a gate line protrusion G02 connected to the end of the gate line main portion G01; the width b6 of the gate line protrusion G02 in the direction perpendicular to the first direction X is greater than the width b7 of the gate line main portion G01 in the direction perpendicular to the first direction X.

[0069] The orthographic projection of the third protrusion G13 onto the substrate overlaps with the orthographic projection of the gate protrusion G02 onto the substrate, and a hole is drilled at the overlapping position for connection.

[0070] In this embodiment, the first trace G1 is provided with a wider third protrusion G13 at its end position, and the gate trace G0 is provided with a gate protrusion G02 at its end position. In this way, when making electrical connections through holes, it can have a better contact conduction effect, avoiding the problem that the gate trace G0 and the first trace G1 are too thin at the intersection position, resulting in poor conduction or no conduction effect.

[0071] In one possible implementation, referring to FIG3C, the third protrusion G13 includes: a first sub-protrusion G131 and a second sub-protrusion G132 arranged and connected along the second direction Y; the first sub-protrusion G131 is connected to the first trace main portion G11; the orthographic projection of the second sub-protrusion G132 on the substrate covers the orthographic projection of the gate line protrusion G02 on the substrate.

[0072] In one possible implementation, referring to FIG2A, the display substrate further includes: a plurality of data lines D extending along the second direction Y and arranged along the first direction X; and a second trace G2 being on the same layer and made of the same material as the data lines D. In this embodiment of the present disclosure, the second trace G2 being on the same layer and made of the same material as the data lines D allows the second trace G2 to be formed simultaneously with the data lines D, thereby simplifying the manufacturing process of the display panel and reducing costs.

[0073] In another possible implementation, the second trace G2 may also be on a different layer than the data trace D.

[0074] In one possible implementation, the data line D is located on the side of the gate line G0 facing away from the substrate; the first trace G1 is located on the side of the data line D facing away from the gate line G0. Specifically, the display substrate may include: a first source / drain layer (SD1 layer), and a second source / drain layer (SD2 layer) located on the side of the first source / drain layer facing away from the substrate; the first source / drain layer may include the data line and the second trace G2; the first trace G1 may be located in the second source / drain layer. Thus, the first trace G1 can be formed when the second source / drain layer is formed, thereby simplifying the manufacturing process of the display panel and reducing costs.

[0075] In one possible implementation, the display substrate may further include multiple pixel circuits. Referring to FIG2A, the pixel circuit may include: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T7, and an eighth transistor T8; the connection relationship of each transistor may be the same as the connection method of a pixel circuit in a display substrate that conventionally includes eight transistors.

[0076] In one possible implementation, referring to FIG1, the first gate drive circuit GOA includes: a plurality of M gate drive units (GO1, GO2...GOM as shown in FIG1) arranged sequentially and cascaded along a first direction X; one end of the nth second trace G2 is electrically connected to the nth gate drive unit to provide the signal of the nth gate drive unit to the gate line G0 in the nth trace group G. For example, referring to FIG1, the second second trace G2 in the direction from the first side area BB3 to the second side area BB4 (that is, from left to right in FIG1) is electrically connected to the second gate drive unit in the direction from the first side area BB3 to the second side area BB4 (that is, from left to right in FIG1) to provide the signal of the second gate drive unit (GO2) to the gate line G0 in the second trace group G.

[0077] In one possible implementation, referring to FIG4, the first gate driving circuit GOA includes: a first sub-gate driving circuit GO11, and a second sub-gate driving circuit GO12 located on the side of the first sub-gate driving circuit GO11 away from the display area AA; the first sub-gate driving circuit GO11 and the second sub-gate driving circuit GO11 extend along the first direction X and are arranged along the second direction Y.

[0078] The first sub-gate driving circuit GO11 includes: a plurality of M first sub-gate driving units (GO1, GO2...GOM as shown in Figure 1) arranged sequentially along the first direction X and cascaded sequentially from the first end H1 to the second end H2; the second sub-gate driving circuit GO12 includes: a plurality of M second sub-gate driving units (GOM, GOM-1...GO1 as shown in Figure 1) arranged sequentially along the first direction X and cascaded sequentially from the second end H2 to the first end H1.

[0079] In this embodiment, the first gate driving circuit GOA includes a first sub-gate driving circuit GO11 and a second sub-gate driving circuit GO12, which can enhance the driving force of GOA on the display substrate. Two rows of GOA units are designed on the bonding side area BB2 (i.e., the upper frame). One row of GOA units is arranged from left to right, and the other row of GOA units is arranged from right to left. Then, each row of pixels in the AA area will have two GOA output signals that pass through the second trace G2 and then into the first trace G1. Finally, they are connected to the gate line G0 of the same row on the left and right sides of each row of pixels. With this design, the driving force of GOA on the display substrate is twice that of conventional design.

[0080] In one possible implementation, referring to FIG4, the display substrate further includes: P third traces G3, which extend along the second direction Y and are arranged along the first direction X; wherein the nth third trace G3 is electrically connected to the first trace G1 in the M-(n-1)th trace group G at the intersection position, n≤P, and P is a positive integer. For example, referring to FIG4, the second third trace G3 in the direction from the first side area BB3 to the second side area BB4 (that is, from left to right in FIG4) is electrically connected to the first trace G1 in the M-(2-1)th gate line group G2 in the direction from the bonding opposite side area BB2 to the bonding area BB1 (that is, from top to bottom in FIG4) at the intersection position.

[0081] In one possible implementation, referring to FIG4, one end of the nth second trace G2 is electrically connected to the nth first sub-gate driving unit from the first end H1 to the second end H2, so as to provide the signal of the nth first sub-gate driving unit to the gate line G0 in the nth trace group; for example, referring to FIG4, the second second trace G2 in the direction from the first side area BB3 to the second side area BB4 (that is, from left to right in FIG4) is electrically connected to the second first sub-gate driving unit (GO2 in the first sub-gate driving circuit GO11) in the direction from the first end H1 to the second end H2 (that is, from left to right in FIG1), so as to provide the signal of the second first sub-gate driving unit (GO2 in the first sub-gate driving circuit GO11) to the gate line G0 in the second trace group G;

[0082] One end of the nth third trace G3 is electrically connected to the M-(n-1)th second sub-gate driving unit from the first end H1 to the second end H2, so as to provide the signal of the M-(n-1)th second sub-gate driving unit from the first end H1 to the second end H2 to the gate line G0 in the M-(n-1)th trace group. For example, referring to FIG4, the second third trace G3 in the direction from the first side area BB3 to the second side area BB4 (that is, from left to right in FIG4) is electrically connected to the M-(2-1)th second sub-gate driving unit (GOM-1 in the second sub-gate driving circuit GO12) in the direction from the first end H1 to the second end H2 (that is, from left to right in FIG4), so as to provide the signal of the M-(2-1)th second sub-gate driving unit (GOM-1 in the second sub-gate driving circuit GO12) to the gate line G0 in the M-(2-1)th trace group G.

[0083] In one possible implementation, the third trace G3 is in the same layer and made of the same material as the second trace G2. In this embodiment of the present disclosure, the third trace G3 is in the same layer and made of the same material as the second trace G2, while the second trace G2 is in the same layer and made of the same material as the data line D. The second trace G2 and the third trace G3 can be formed at the same time as the data line D, thereby simplifying the manufacturing process of the display panel and reducing costs.

[0084] In one possible implementation, as shown in Figure 1 or Figure 4, the display substrate further includes: a plurality of first signal lines; the first signal lines extend from one end of the bonding area BB1, through the first side area BB3, the bonding opposite side area BB2, and the second side area BB4 to the other end of the bonding area BB1.

[0085] In one possible implementation, as shown in Figure 1 or Figure 4, the first signal line includes: a trigger signal line gstv, and / or a first clock signal line ck, and / or a second clock signal line cb.

[0086] In one possible implementation, referring to Figure 1 or Figure 4, the trigger signal line gstv can be electrically connected to the first-stage gate drive unit (GO1 in Figure 1, or GO1 in the first sub-gate drive circuit GO11 in Figure 4, or GO1 in the second sub-gate drive circuit GO12 in Figure 4) in the first gate drive circuit GOA.

[0087] In one possible implementation, referring to Figure 1 or Figure 4, the first clock signal line ck and the second clock signal line cb can be alternately connected to the stage gate driving units in the first gate driving circuit GOA. For example, referring to Figure 1, the first clock signal line ck can be connected to the first stage gate driving unit (GO1), the third stage gate driving unit (GO2), the fifth stage gate driving unit (GO5), etc. in the first gate driving circuit GOA, and the second clock signal line cb can be connected to the second stage gate driving unit (GO2), the fourth stage gate driving unit (GO4), the sixth stage gate driving unit (GO6), etc. in the first gate driving circuit GOA.

[0088] In one possible implementation, as shown in Figure 5 or Figure 6, the display substrate may not have the first trace G1, and the second trace G2 may be directly connected to the gate G0. In this way, the signal in the first gate drive circuit GOA set in the bonded opposite side region BB2 can be transmitted to the gate line G0, and the display panel can also be made narrower.

[0089] Based on the same inventive concept, this disclosure also provides a display device, which includes a display substrate as provided in the embodiments of this disclosure. Implementation of this display device can refer to the embodiments of the display panel described above, and repeated details will not be repeated.

[0090] In specific implementations, in the embodiments of this disclosure, the display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. Other essential components of the display device are those that should be understood by those skilled in the art, and will not be described in detail here, nor should they be construed as limiting this disclosure.

[0091] Although preferred embodiments of this disclosure have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this disclosure.

[0092] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A display substrate having a display area, a bonding area located on one side of the display area, and a bonding opposing area located on the other side of the display area and opposite to the bonding area; wherein, The display substrate includes: Substrate; M routing groups, the M routing groups extending along a first direction and arranged along a second direction, at least one of the M routing groups includes: a gate line extending along the first direction and a first routing line; the first routing line and the gate line are electrically connected at at least one end position; N second traces, the N second traces extending along the second direction and arranged along the first direction; wherein, the nth second trace is electrically connected to the first trace in the nth trace group at the intersection position, n≤N, n≤M, and M, N, n are positive integers; A first gate drive circuit is located in the bonding opposite region; one end of the second trace is electrically connected to the first gate drive circuit to provide the signal of the first gate drive circuit to the gate line.

2. The display substrate as claimed in claim 1, wherein, The first trace includes: a first trace main portion extending along the first direction, and a first protrusion connected to the first trace main portion; the width of the first protrusion perpendicular to the first direction is greater than the width of the first trace main portion perpendicular to the first direction. The second trace includes: a second trace main portion extending along the second direction, and a second protrusion connected to the second trace main portion; the width of the second protrusion perpendicular to the second direction is greater than the width of the second trace main portion perpendicular to the second direction. The orthographic projection of the second protrusion on the substrate overlaps with the orthographic projection of the first protrusion on the substrate, and a hole is drilled at the overlapping position for electrical connection.

3. The display substrate as described in claim 2, wherein, The first trace and the gate line are electrically connected at both ends in the extension direction.

4. The display substrate as described in claim 3, wherein, The first trace further includes: a third protrusion connected to the end of the main portion of the first trace; the width of the third protrusion in the direction perpendicular to the first direction is greater than the width of the main portion of the first trace in the direction perpendicular to the first direction; The gate line includes: a gate line main portion extending along the first direction, and a gate line protrusion connected to the end of the gate line main portion; the width of the gate line protrusion perpendicular to the first direction is greater than the width of the gate line main portion perpendicular to the first direction. The orthographic projection of the third protrusion on the substrate overlaps with the orthographic projection of the gate line protrusion on the substrate, and a hole is drilled at the overlapping position for connection.

5. The display substrate as claimed in claim 4, wherein, The third protrusion includes: a first sub-protrusion and a second sub-protrusion arranged and connected along the second direction; The first sub-protrusion is connected to the first main trace portion; the orthographic projection of the second sub-protrusion on the substrate covers the orthographic projection of the gate line protrusion on the substrate.

6. The display substrate according to any one of claims 1-5, wherein, The display substrate further includes: a plurality of data lines extending along the second direction and arranged along the first direction; The second trace is on the same layer and made of the same material as the data line.

7. The display substrate as claimed in claim 6, wherein, The data line is located on the side of the gate line away from the substrate; the first trace is located on the side of the data line away from the gate line.

8. The display substrate according to any one of claims 1-7, wherein, The first gate driving circuit includes: a plurality of M gate driving units arranged sequentially and cascaded along the first direction; One end of the nth second trace is electrically connected to the nth gate driving unit to provide the signal of the nth gate driving unit to the gate line in the nth trace group.

9. The display substrate according to any one of claims 1-8, wherein, The first gate driving circuit includes: a first sub-gate driving circuit, and a second sub-gate driving circuit located on the side of the first sub-gate driving circuit away from the display area; the first sub-gate driving circuit and the second sub-gate driving circuit extend along the first direction and are arranged along the second direction; The first sub-gate driving circuit includes: a plurality of M first sub-gate driving units arranged sequentially along the first direction and cascaded sequentially from the first end to the second end; the second sub-gate driving circuit includes: a plurality of M second sub-gate driving units arranged sequentially along the first direction and cascaded sequentially from the second end to the first end.

10. The display substrate as claimed in claim 9, wherein, The display substrate further includes: P third traces, which extend along the second direction and are arranged along the first direction; wherein the nth third trace is electrically connected to the first trace in the M-(n-1)th trace group at the intersection position, n≤P, and P is a positive integer.

11. The display substrate as claimed in claim 10, wherein, One end of the nth second trace is electrically connected to the nth first sub-gate driving unit from the first end to the second end, so as to provide the signal of the nth first sub-gate driving unit to the gate line in the nth trace group; One end of the third trace of the nth term is electrically connected to the M-(n-1)th second sub-gate driving unit from the first end to the second end, so as to provide the signal of the M-(n-1)th second sub-gate driving unit from the first end to the second end to the gate line in the M-(n-1)th trace group.

12. The display substrate as claimed in claim 10 or 11, wherein, The third trace is in the same layer and made of the same material as the second trace.

13. The display substrate according to any one of claims 1-12, wherein, The display substrate further has a first side area connecting one end of the bonding area and one end of the bonding opposite side area, and a second side area connecting the other end of the bonding area and the other end of the bonding opposite side area; The display substrate further includes: a plurality of first signal lines; the first signal lines extend from one end of the bonding area, through the first side area, the bonding opposite side area, and the second side area to the other end of the bonding area.

14. The display substrate as claimed in claim 13, wherein, The first signal line includes: a trigger signal line, and / or a first clock signal line, and / or a second clock signal line.

15. A display device, wherein, Includes the display substrate as described in any one of claims 1-14.

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