Modular multiplication compressor circuit
Patent Information
- Application Number
- PCT/CN2026/073472
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-02-19
- Filing Date
- 2026-01-19
- Publication Date
- 2026-08-27
Smart Images
Figure CN2026073472_27082026_PF_FP_ABST
Abstract
Description
A modular compressor circuit Technical Field
[0001] This application relates to the field of analog multiplier and compressor design technology, and in particular to an analog multiplier compressor circuit. Background Technology
[0002] To combat the quantum threat, research on quantum-resistant cryptography has received widespread attention. Crystals-Kyber is a NIST-standardized quantum-resistant encryption algorithm. Quantum-resistant encryption algorithms often involve computations over many prime fields, involving a series of modular multiplication and compression operations. However, existing modular multipliers and compressors are implemented using two discrete circuits, resulting in large data transmission delays, high hardware overhead, and poor flexibility. They cannot be configured with compression and modular multiplication parameters according to requirements. Summary of the Invention
[0003] Based on the above analysis, the embodiments of this application aim to provide a modular multiplier compressor circuit to solve the problems of large data transmission delay, large hardware overhead, and poor flexibility in existing discrete modular multipliers and compressors.
[0004] This application provides a modular multiplication compressor circuit, including an input configuration unit, a data initial processing unit, a switching unit, a compression processing unit, and a modular multiplication processing unit;
[0005] The input configuration unit is used to generate first data to be processed, first initial processing parameters, second initial processing parameters, and third initial processing parameters based on the received first raw data to be processed, switching parameters, and modulus.
[0006] The data initial processing unit is used to process the received first data to be processed and the second raw data to be processed based on the received first initial processing parameters, second initial processing parameters and third initial processing parameters, and generate initial processing output data and quotient output data.
[0007] The switching unit is used to send the received initial processing output data to the compression processing unit or the modular multiplication processing unit according to the received switching parameters.
[0008] The compression processing unit is used to generate and output compressed data based on the received initial processing output data, quotient output data, and modulus.
[0009] The modular multiplication processing unit is used to generate and output modular multiplication data based on the received initial processing output data, the third initial processing parameters, and the modulus.
[0010] Furthermore, in the input configuration unit, the first data to be processed, y1, is represented as:
[0011] In the formula, y represents the first raw data to be processed, c represents the switching parameter, c1 represents the first switching value set, and c2 represents the second switching value set.
[0012] The first initial processing parameter k satisfies the following formula:
[0013] Where s = log2(q+1);
[0014] In the formula, Let q represent the set of integers, and q represent the modulus.
[0015] The second initial processing parameter m is expressed as:
[0016] In the formula, Indicates rounding down;
[0017] The third initial processing parameter q1 is expressed as: q1 = -q.
[0018] Furthermore, the data initial processing unit includes a first multiplier, a second multiplier, a third multiplier, a shifter, and a first adder;
[0019] The first and second input terminals of the first multiplier serve as the first and second input terminals of the data initial processing unit, respectively, for receiving the first data to be processed and the second raw data to be processed. The output terminal of the first multiplier is connected to the first input terminal of the second multiplier. The second input terminal of the second multiplier serves as the third input terminal of the data initial processing unit, for receiving the second initial processing parameter. The output terminal of the second multiplier is connected to the data input terminal of the shifter. The shift input terminal of the shifter serves as the fourth input terminal of the data initial processing unit, for receiving the first initial processing parameter. The output terminal of the shifter is connected to the first input terminal of the third multiplier. The second input terminal of the third multiplier serves as the fifth input terminal of the data initial processing unit, for receiving the third initial processing parameter, and the output terminal of the third multiplier is connected to the first input terminal of the first adder. The second input terminal of the first adder is connected to the output terminal of the first multiplier, and its output terminal serves as the first output terminal of the data initial processing unit, for outputting the initial processing output data. The output terminal of the shifter also serves as the second output terminal of the data initial processing unit, for outputting the quotient output data.
[0020] Furthermore, the shifter is a right-shift shifter.
[0021] Further, the switching unit is a first multiplexer; the first input terminal of the first multiplexer serves as the first input terminal of the switching unit, used to receive initial processing output data; the second input terminal of the first multiplexer serves as the second input terminal of the switching unit, used to receive switching parameters; the first output terminal of the first multiplexer serves as the first output terminal of the switching unit, used to output initial processing output data to the analog-multiplication processing unit; the second output terminal of the first multiplexer serves as the second output terminal of the switching unit, used to output initial processing output data to the compression processing unit.
[0022] Furthermore, in the first multiplexer, when the switching parameter received at the second input is the set first switching parameter value, the initial processing output data received at the first input is sent to the analog-multiplication processing unit through the first output; when the switching parameter received at the second input is the set second switching parameter value, the initial processing output data received at the first input is sent to the compression processing unit through the second output.
[0023] Furthermore, the modular multiplication processing unit includes a second multiplexer and a second adder;
[0024] The first input terminal of the second multiplexer serves as the first input terminal of the modular multiplication processing unit, used to receive the initial processing output data; the first output terminal of the second multiplexer is connected to the first input terminal of the second adder; the second input terminal of the second adder serves as the second input terminal of the modular multiplication processing unit, used to receive the third initial processing parameter; the third input terminal of the second multiplexer serves as the third input terminal of the modular multiplication processing unit, used to receive the modulus; the output terminal of the second adder is connected to the second output terminal of the second multiplexer and serves as the output terminal of the modular multiplication processing unit.
[0025] Furthermore, in the second multiplexer, when the initial processing output data received at the first input terminal is greater than or equal to the modulus received at the second input terminal, the received initial processing output data is output at the first output terminal; otherwise, the second multiplexer outputs the initial processing output data received at the first input terminal at the second output terminal.
[0026] Furthermore, the compression processing unit includes a fourth multiplier, a third multiplexer, a third adder, a fourth adder, and a first fixed value source, a second fixed value source, and a third fixed value source;
[0027] The first input terminal of the fourth multiplier serves as the first input terminal of the compression processing unit, used to receive initial processing output data; the second input terminal of the fourth multiplier is connected to the first fixed value source, and its output terminal is connected to the first input terminal of the third multiplexer; the second input terminal of the third multiplexer serves as the second input terminal of the compression processing unit, used to receive the modulus; the third input terminal of the third multiplexer serves as the third input terminal of the compression processing unit, used to receive quotient output data; the first output terminal of the third multiplexer is connected to the first input terminal of the third adder; the second input terminal of the third adder is connected to the second fixed value source; the second output terminal of the third multiplexer is connected to the first input terminal of the fourth adder; the second input terminal of the fourth adder is connected to the third fixed value source; the third output terminal of the third multiplexer, after being connected to the output terminals of the third adder and the fourth adder, serves as the output terminal of the compression processing unit.
[0028] Furthermore, in the third multiplexer, when the data received at the first input terminal is less than the modulus received at the second input terminal, the quotient output data received at the third input terminal is output at the third output terminal.
[0029] When the data received by the first input terminal is greater than or equal to the modulus received by the second input terminal by a set multiple, the quotient output data received by the third input terminal will be output by the second output terminal.
[0030] Otherwise, the quotient output data received at the third input terminal will be output at the first output terminal.
[0031] Compared with the prior art, this application can achieve at least one of the following beneficial effects:
[0032] This application provides an analog-to-digital multiplication and compression circuit. A data initial processing unit performs the same data initial processing as the analog-to-digital multiplier and compressor. A switching unit then selects which analog-to-digital multiplication and compression processing is performed later, integrating analog-to-digital multiplication and compression into a single circuit. This eliminates the problems of large data transmission delays and high hardware overhead. Furthermore, the circuit allows for arbitrary settings of the number of bits, the modulus, and the compression bits, offering good flexibility. In addition, the circuit can shorten the critical path of analog-to-digital multiplication processing, increasing the circuit's operating frequency. The circuit completes compression through integer judgment, avoiding floating-point operations and simplifying the operation.
[0033] In this application, the above-described technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of this application will be set forth in the following description, and some advantages may become apparent from the description or be learned by practicing this application. The objectives and other advantages of this application can be realized and obtained from the specific points highlighted in the description and accompanying drawings. Attached Figure Description
[0034] The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Throughout the drawings, the same reference numerals denote the same parts.
[0035] Figure 1 is a structural connection diagram of the modular compressor circuit provided in an embodiment of this application;
[0036] Figure 2 is a detailed connection diagram of a portion of the structure of the analog-multiplexer compressor circuit provided in an embodiment of this application. Detailed Implementation
[0037] The preferred embodiments of this application are described in detail below with reference to the accompanying drawings, which constitute a part of this application and are used together with the embodiments of this application to illustrate the principles of this application, but are not intended to limit the scope of this application.
[0038] A specific embodiment of this application discloses a modular multiplication compressor circuit, as shown in FIG1, including an input configuration unit, a data initial processing unit, a switching unit, a compression processing unit, and a modular multiplication processing unit;
[0039] The input configuration unit is used to generate first data to be processed, first initial processing parameters, second initial processing parameters, and third initial processing parameters based on the received first raw data to be processed, switching parameters, and modulus.
[0040] The data initial processing unit is used to process the received first data to be processed and the second raw data to be processed based on the received first initial processing parameters, second initial processing parameters and third initial processing parameters, and generate initial processing output data and quotient output data.
[0041] The switching unit is used to send the received initial processing output data to the compression processing unit or the modular multiplication processing unit according to the received switching parameters.
[0042] The compression processing unit is used to generate and output compressed data based on the received initial processing output data, quotient output data, and modulus.
[0043] The modular multiplication processing unit is used to generate and output modular multiplication data based on the received initial processing output data, the third initial processing parameters, and the modulus.
[0044] In implementation, in the input configuration unit, the first data to be processed, y1, is represented as:
[0045] In the formula, y represents the first raw data to be processed, c represents the switching parameter, c1 represents the first switching value set, and c2 represents the second switching value set.
[0046] The first initial processing parameter k satisfies the following formula:
[0047] Where s = log2(q+1);
[0048] In the formula, Let q represent the set of integers, and q represent the modulus.
[0049] The second initial processing parameter m is expressed as:
[0050] In the formula, Indicates rounding down;
[0051] The third initial processing parameter q1 is expressed as: q1 = -q.
[0052] Specifically, c1 represents the first switching value set to indicate that the subsequent processing is modular multiplication; c2 represents the second switching value set to indicate that the subsequent processing is compression. The first and second switching values can be set according to requirements.
[0053] It should be noted that the inputs of the analog-multiplication compressor circuit include the first raw data to be processed, the second raw data to be processed, the modulus, and the switching parameters. The first raw data to be processed, the first initial processing parameters, the second initial processing parameters, and the third initial processing parameters generated in the input configuration unit can be obtained through hardware circuitry or through programming of a digital signal processor or microcontroller, and then sent to the corresponding receiving end.
[0054] It is understood that if the circuit in this embodiment is used for data compression, it can input any bit variable x, any modulus q, and any compression bit y, which is highly flexible.
[0055] In practice, as shown in Figure 2, the data initial processing unit includes a first multiplier, a second multiplier, a third multiplier, a shifter, and a first adder.
[0056] The first and second input terminals of the first multiplier serve as the first and second input terminals of the data initial processing unit, respectively, for receiving the first data to be processed and the second raw data to be processed. The output terminal of the first multiplier is connected to the first input terminal of the second multiplier. The second input terminal of the second multiplier serves as the third input terminal of the data initial processing unit, for receiving the second initial processing parameter. The output terminal of the second multiplier is connected to the data input terminal of the shifter. The shift input terminal of the shifter serves as the fourth input terminal of the data initial processing unit, for receiving the first initial processing parameter. The output terminal of the shifter is connected to the first input terminal of the third multiplier. The second input terminal of the third multiplier serves as the fifth input terminal of the data initial processing unit, for receiving the third initial processing parameter, and the output terminal of the third multiplier is connected to the first input terminal of the first adder. The second input terminal of the first adder is connected to the output terminal of the first multiplier, and its output terminal serves as the first output terminal of the data initial processing unit, for outputting the initial processing output data. The output terminal of the shifter also serves as the second output terminal of the data initial processing unit, for outputting the quotient output data.
[0057] Specifically, the shifter is a right-shift shifter.
[0058] It should be noted that the inputs to the data initial processing unit include the first initial processing parameter k, the second initial processing parameter m, the third initial processing parameter q1, the first data to be processed y1, and the second original data to be processed x. The data initial processing unit completes the initial processing of the data as follows:
[0059] S11, a = x·y1;
[0060] S12, t1 = a·m;
[0061] S13
[0062] S14, t3 = t2·q1;
[0063] S15, z = a + t3;
[0064] In the formula, a and t3 are intermediate variables, z represents the initial processing output data, and t2 represents the quotient output data.
[0065] Understandably, by implementing the same data preprocessing process as the analog multiplier and compressor through the data preprocessing unit, the problems of large data transmission latency and high hardware overhead are eliminated.
[0066] In implementation, the switching unit is a first multiplexer; the first input terminal of the first multiplexer serves as the first input terminal of the switching unit, used to receive initial processing output data; the second input terminal of the first multiplexer serves as the second input terminal of the switching unit, used to receive switching parameters; the first output terminal of the first multiplexer serves as the first output terminal of the switching unit, used to output initial processing output data to the modular multiplication processing unit; the second output terminal of the first multiplexer serves as the second output terminal of the switching unit, used to output initial processing output data to the compression processing unit.
[0067] Specifically, in the first multiplexer, when the switching parameter received by the second input terminal is the set first switching parameter value, the initial processing output data received by the first input terminal is sent to the analog-multiplication processing unit through the first output terminal; when the switching parameter received by the second input terminal is the set second switching parameter value, the initial processing output data received by the first input terminal is sent to the compression processing unit through the second output terminal.
[0068] Understandably, the first multiplexer enables the selection of analog multiplication and compression processing, which can be switched by changing parameters, thus integrating analog multiplication and compression into a single circuit.
[0069] In implementation, the modular multiplication processing unit includes a second multiplexer and a second adder;
[0070] The first input terminal of the second multiplexer serves as the first input terminal of the modular multiplication processing unit, used to receive the initial processing output data; the first output terminal of the second multiplexer is connected to the first input terminal of the second adder; the second input terminal of the second adder serves as the second input terminal of the modular multiplication processing unit, used to receive the third initial processing parameter; the third input terminal of the second multiplexer serves as the third input terminal of the modular multiplication processing unit, used to receive the modulus; the output terminal of the second adder is connected to the second output terminal of the second multiplexer and serves as the output terminal of the modular multiplication processing unit.
[0071] Specifically, in the second multiplexer, when the initial processing output data received at the first input is greater than or equal to the modulus received at the second input, the received initial processing output data is output at the first output; otherwise, the second multiplexer outputs the initial processing output data received at the first input at the second output.
[0072] It should be noted that the inputs to the modular multiplication processing unit include the modulus q, the initial processing output data z, and the third initial processing parameter q1. The modular multiplication processing unit completes the modular multiplication process as follows:
[0073] In the formula, z1 represents the output data of the modular multiplication processing unit, i.e., the modular multiplication result.
[0074] It is understandable that the modular multiplication process described above can obtain the final modular multiplication result with at most one modular subtraction, so that the delay of the modular multiplication process can be matched with the higher-level operations (such as NTT (number theory transformation) operations in quantum-resistant cryptographic algorithms), and the critical path of the modular multiplication process can be shortened, thereby increasing the circuit operating frequency.
[0075] In implementation, the compression processing unit includes a fourth multiplier, a third multiplexer, a third adder, a fourth adder, a first fixed value source, a second fixed value source, and a third fixed value source;
[0076] The first input terminal of the fourth multiplier serves as the first input terminal of the compression processing unit, used to receive initial processing output data; the second input terminal of the fourth multiplier is connected to the first fixed value source, and its output terminal is connected to the first input terminal of the third multiplexer; the second input terminal of the third multiplexer serves as the second input terminal of the compression processing unit, used to receive the modulus; the third input terminal of the third multiplexer serves as the third input terminal of the compression processing unit, used to receive quotient output data; the first output terminal of the third multiplexer is connected to the first input terminal of the third adder; the second input terminal of the third adder is connected to the second fixed value source; the second output terminal of the third multiplexer is connected to the first input terminal of the fourth adder; the second input terminal of the fourth adder is connected to the third fixed value source; the third output terminal of the third multiplexer, after being connected to the output terminals of the third adder and the fourth adder, serves as the output terminal of the compression processing unit.
[0077] Specifically, in the third multiplexer, when the data received at the first input terminal is less than the modulus received at the second input terminal, the quotient output data received at the third input terminal is output at the third output terminal.
[0078] When the data received by the first input terminal is greater than or equal to the modulus received by the second input terminal by a set multiple, the quotient output data received by the third input terminal will be output by the second output terminal.
[0079] Otherwise, the quotient output data received at the third input terminal will be output at the first output terminal.
[0080] Specifically, the first fixed value source, the second fixed value source, and the third fixed value source are preset constants; more specifically, the first fixed value is 2, the second fixed value is 2, and the third fixed value is 1.
[0081] Specifically, the multiplier is set to 3.
[0082] It should be noted that the inputs to the modular multiplication processing unit include the modulus q, the initial processing output data z, and the quotient output data t2. The compression processing unit completes the compression process as follows:
[0083] S31, z2 = 2z;
[0084] S32,
[0085] In the formula, z out z1 represents the output data of the compression processing unit, i.e., the compression result; z2 represents the intermediate variable.
[0086] Understandably, this compression process simplifies the hardware structure, enabling the compression of arbitrary bits, arbitrary modulo, and arbitrary compressed bits, allowing the FPGA implementation of the circuit to output results within 5 clock cycles.
[0087] It should be noted that the first initial processing parameter k and the second initial processing parameter m in the modular multiplier compressor circuit of this embodiment are based on the following derivation:
[0088] Define q as exactly s bits, that is, 2^s. s-1 <q<2 s Pre-calculation but
[0089] Therefore, when 2s-k=0, that is, 2s=k, there exists z<2q. So, based on the number of bits s of the modulus q, we can obtain the range of values for the first initial processing parameter k, and thus obtain the second initial processing parameter m.
[0090] Compared with existing technologies, the modular multiplication and compression circuit provided in this embodiment implements the same data initial processing process for both the modular multiplier and the compressor through a data initial processing unit. Then, a switching unit selects the subsequent modular multiplication and compression processing, integrating modular multiplication and compression into a single circuit. This eliminates the problems of large data transmission latency and high hardware overhead. Furthermore, the circuit allows for arbitrary settings of the number of bits, modulus, and compression bits, offering high flexibility. In addition, the circuit can shorten the critical path of the modular multiplication process, increasing the circuit's operating frequency. The circuit completes compression through integer judgment, avoiding floating-point operations and simplifying operation.
[0091] Those skilled in the art will understand that all or part of the processes of the methods described in the above embodiments can be implemented by a computer program instructing related hardware, and the program can be stored in a computer-readable storage medium. The computer-readable storage medium may be a disk, optical disk, read-only memory, or random access memory, etc.
[0092] The above description is merely a preferred embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application.
Claims
1. A modular multiplier compressor circuit, characterized in that, It includes an input configuration unit, a data initial processing unit, a switching unit, a compression processing unit, and a modular multiplication processing unit; The input configuration unit is used to generate first data to be processed, first initial processing parameters, second initial processing parameters, and third initial processing parameters based on the received first raw data to be processed, switching parameters, and modulus. The data initial processing unit is used to process the received first data to be processed and the second raw data to be processed based on the received first initial processing parameters, second initial processing parameters and third initial processing parameters, and generate initial processing output data and quotient output data. The switching unit is used to send the received initial processing output data to the compression processing unit or the modular multiplication processing unit according to the received switching parameters. The compression processing unit is used to generate and output compressed data based on the received initial processing output data, quotient output data, and modulus. The modular multiplication processing unit is used to generate and output modular multiplication data based on the received initial processing output data, the third initial processing parameters, and the modulus.
2. The analog-multiplexer compressor circuit according to claim 1, characterized in that, In the input configuration unit, the first data to be processed, y1, is represented as: In the formula, y represents the first raw data to be processed, c represents the switching parameter, c1 represents the first switching value set, and c2 represents the second switching value set. The first initial processing parameter k satisfies the following formula: Where s = log2(q+1); In the formula, Let q represent the set of integers, and q represent the modulus. The second initial processing parameter m is expressed as: In the formula, Indicates rounding down; The third initial processing parameter q1 is expressed as: q1 = -q.
3. The analog-multiplexer compressor circuit according to claim 1, characterized in that, The data initial processing unit includes a first multiplier, a second multiplier, a third multiplier, a shifter, and a first adder; The first and second input terminals of the first multiplier serve as the first and second input terminals of the data initial processing unit, respectively, for receiving the first data to be processed and the second raw data to be processed. The output terminal of the first multiplier is connected to the first input terminal of the second multiplier. The second input terminal of the second multiplier serves as the third input terminal of the data initial processing unit, for receiving the second initial processing parameter. The output terminal of the second multiplier is connected to the data input terminal of the shifter. The shift input terminal of the shifter serves as the fourth input terminal of the data initial processing unit, for receiving the first initial processing parameter. The output terminal of the shifter is connected to the first input terminal of the third multiplier. The second input terminal of the third multiplier serves as the fifth input terminal of the data initial processing unit, for receiving the third initial processing parameter, and the output terminal of the third multiplier is connected to the first input terminal of the first adder. The second input terminal of the first adder is connected to the output terminal of the first multiplier, and its output terminal serves as the first output terminal of the data initial processing unit, for outputting the initial processing output data. The output terminal of the shifter also serves as the second output terminal of the data initial processing unit, for outputting the quotient output data.
4. The analog-multiplicative compressor circuit according to claim 3, characterized in that, The shifter is a right-shift shifter.
5. The analog-multiplexer compressor circuit according to claim 1, characterized in that, The switching unit is a first multiplexer; the first input terminal of the first multiplexer serves as the first input terminal of the switching unit, used to receive the initial processed output data; The second input terminal of the first multiplexer serves as the second input terminal of the switching unit, used to receive switching parameters; The first output terminal of the first multiplexer serves as the first output terminal of the switching unit, and is used to output the initial processed output data to the modular multiplication processing unit. The second output terminal of the first multiplexer serves as the second output terminal of the switching unit, and is used to output the initial processed output data to the compression processing unit.
6. The analog-multiplicative compressor circuit according to claim 5, characterized in that, In the first multiplexer, when the switching parameter received at the second input is the set first switching parameter value, the initial processing output data received at the first input is sent to the modular multiplication processing unit through the first output. When the switching parameter received by the second input terminal is the set second switching parameter value, the initial processing output data received by the first input terminal is sent to the compression processing unit through the second output terminal.
7. The analog-multiplexer compressor circuit according to claim 1, characterized in that, The modular multiplication processing unit includes a second multiplexer and a second adder; The first input terminal of the second multiplexer serves as the first input terminal of the modular multiplication processing unit, used to receive the initial processing output data; The first output terminal of the second multiplexer is connected to the first input terminal of the second adder; the second input terminal of the second adder serves as the second input terminal of the modular multiplication processing unit, used to receive the third initial processing parameters; the third input terminal of the second multiplexer serves as the third input terminal of the modular multiplication processing unit, used to receive the modulus; the output terminal of the second adder is connected to the second output terminal of the second multiplexer and serves as the output terminal of the modular multiplication processing unit.
8. The analog-multiplexer compressor circuit according to claim 1, characterized in that, In the second multiplexer, when the initial processing output data received at the first input terminal is greater than or equal to the modulus received at the second input terminal, the received initial processing output data is output at the first output terminal. Otherwise, the second multiplexer will output the initial processed output data received at the first input terminal at the second output terminal.
9. The analog-multiplexer compressor circuit according to claim 1, characterized in that, The compression processing unit includes a fourth multiplier, a third multiplexer, a third adder, a fourth adder, a first fixed value source, a second fixed value source, and a third fixed value source; The first input terminal of the fourth multiplier serves as the first input terminal of the compression processing unit, used to receive the initial processing output data; the second input terminal of the fourth multiplier is connected to the first fixed value source, and the output terminal is connected to the first input terminal of the third multiplexer. The second input terminal of the third multiplexer serves as the second input terminal of the compression processing unit, used to receive the modulus; the third input terminal of the third multiplexer serves as the third input terminal of the compression processing unit, used to receive the quotient output data; the first output terminal of the third multiplexer is connected to the first input terminal of the third adder; the second input terminal of the third adder is connected to the second fixed value source; the second output terminal of the third multiplexer is connected to the first input terminal of the fourth adder; the second input terminal of the fourth adder is connected to the third fixed value source; the third output terminal of the third multiplexer, after being connected to the output terminals of the third adder and the fourth adder, serves as the output terminal of the compression processing unit.
10. The analog-multiplexer compressor circuit according to claim 9, characterized in that, In the third multiplexer, when the data received at the first input terminal is less than the modulus received at the second input terminal, the quotient output data received at the third input terminal is output at the third output terminal. When the data received by the first input terminal is greater than or equal to the modulus received by the second input terminal by a set multiple, the quotient output data received by the third input terminal will be output by the second output terminal. Otherwise, the quotient output data received at the third input terminal will be output at the first output terminal.