Memory structure and method for manufacturing memory structure

Abstract

The present disclosure provides a memory structure and a method for manufacturing the memory structure. The structure comprises: a semiconductor substrate, wherein the semiconductor substrate comprises an array region and a logic region that are adjacent to each other, the array region comprises a first conductive channel and a memory cell, and the logic region comprises a second conductive channel; a protective layer that is located on the side of the semiconductor substrate provided with the memory cell and covers the sidewall of the memory cell; a first insulating dielectric layer, located on the side of the semiconductor substrate provided with the protective layer; an etch stop layer, located on the side of the first insulating dielectric layer away from the protective layer; a second insulating dielectric layer, located on the side of the etch stop layer away from the semiconductor substrate; and a top metal interconnection structure that is located on the side of the semiconductor substrate provided with the memory cell and comprises a first metal connection portion and a second metal connection portion electrically connected to each other, wherein the first metal connection portion is located on the array region and is disposed in contact with the memory cell, and the second metal connection portion is located on the logic region and is disposed in contact with the second conductive channel.

Description

Memory structure and its fabrication methods

[0001] This disclosure claims priority to Chinese Patent Application No. 202510205245.6, filed on February 24, 2025, entitled “Memory Structure and Method for Manufacturing Memory Structure”, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This disclosure relates to the field of semiconductor memory technology, and more specifically, to a memory structure and a method for manufacturing the memory structure. Background Technology

[0003] MRAM memory, as a novel type of memory, offers significant advantages over traditional Flash memory in terms of read / write speed and device reliability. Currently, to fabricate MRAM memory, the array region and logic region are typically fabricated separately. That is, after fabricating the bottom vias and memory cells of the memory array region, the bottom vias of the logic region are fabricated, and then the top metal interconnect structure is formed on both the array and logic regions. Therefore, fabricating the array and logic regions requires two photolithography etching processes, making the fabrication process complex and costly. Furthermore, when fabricating the memory cells in the array region and the top interconnect, a chemical mechanical polishing (CMP) process is usually required to open the top surface of the memory cells. This process demands extremely high surface uniformity in the array region. During the fabrication of large-capacity arrays, problems such as insufficient polishing leading to open circuits or excessive polishing leading to short circuits can easily occur. Summary of the Invention

[0004] The main objective of this disclosure is to provide a memory structure and a method for manufacturing the memory structure, so as to solve the problem of low memory reliability caused by oxidation of memory cells during the fabrication of the logic area in the prior art.

[0005] To achieve the above objectives, according to one aspect of this disclosure, a memory structure is provided, comprising: a semiconductor substrate, the semiconductor substrate including an adjacent array region and a logic region, the array region including a first conductive channel located in the substrate and a memory cell stacked and contacted with the first conductive channel, the logic region including a second conductive channel located in the substrate, the first conductive channel and the second conductive channel being spaced apart; a protective layer located on the side of the semiconductor substrate having the memory cell and covering the sidewall of the memory cell; a first insulating dielectric layer located on the side of the semiconductor substrate having the protective layer; an etch stop layer located on the side of the first insulating dielectric layer away from the protective layer; a second insulating dielectric layer located on the side of the etch stop layer away from the semiconductor substrate; and a top metal interconnect structure located on the side of the semiconductor substrate having the memory cell, the top metal interconnect structure including an electrically connected first metal connection portion and a second metal connection portion, the first metal connection portion being located on the array region and contacting the memory cell, and the second metal connection portion being located on the logic region and contacting the second conductive channel.

[0006] Optionally, a second insulating dielectric layer and an etching barrier layer surround the first metal connection.

[0007] Optionally, the second insulating dielectric layer and the first insulating dielectric layer surround the second metal connection.

[0008] Optionally, the surface of the first insulating dielectric layer away from the semiconductor substrate is flush with the surface of the memory cell away from the first conductive channel.

[0009] Optionally, the surface of the first insulating dielectric layer on the side away from the semiconductor substrate is higher than the surface of the memory cell on the side away from the first conductive channel.

[0010] According to another aspect of this disclosure, a method for fabricating a memory structure is provided, comprising a semiconductor substrate including an adjacent array region and a logic region, the array region including a first conductive channel located in the substrate and memory cells stacked and contacted with the first conductive channel, the logic region including a second conductive channel located in the substrate, the first conductive channel and the second conductive channel being spaced apart; a protective layer is conformally formed on the side of the semiconductor substrate having the memory cells; a first insulating dielectric layer and an etch barrier layer are sequentially formed on the side of the semiconductor substrate having the protective layer; a portion of the etch barrier material and a portion of the first insulating material are removed, and then a second insulating dielectric layer is formed on the side of the semiconductor substrate having the etch barrier layer and the first insulating dielectric layer, wherein the portion of the etch barrier material is at least a portion of the etch barrier material located on the logic region in the etch barrier layer, and the portion of the first insulating material is at least a portion of the first insulating material located on the logic region in the first insulating dielectric layer; a top metal interconnect structure is formed on the side of the semiconductor substrate having the memory cells, the top metal interconnect structure including a first metal connection portion and a second metal connection portion electrically connected, the first metal connection portion being located on the array region and contacting the memory cells, and the second metal connection portion being located on the logic region and contacting the second conductive channel.

[0011] Optionally, the step of forming the first insulating dielectric layer includes: depositing a first insulating material layer on the side of the semiconductor substrate having a protective layer, such that the first insulating material layer covers the protective layer; planarizing the first insulating material layer until the surface of the protective layer on the side away from the memory cell is exposed, thereby forming the first insulating dielectric layer.

[0012] Optionally, the first insulating material located on the logic region in the first insulating dielectric layer includes a first portion covering the protective layer and a second portion located on the side of the first portion away from the protective layer. The step of removing part of the etch barrier material and part of the first insulating material includes: sequentially removing all of the etch barrier material located on the logic region in the etch barrier layer and the second portion in the first insulating dielectric layer using a patterned process.

[0013] Optionally, the first insulating material located on the logic region in the first insulating dielectric layer includes a first portion covering the protective layer and a second portion located on the side of the first portion away from the protective layer. The etch barrier material located on the array region in the etch barrier layer includes a first portion located on the side of the protective layer away from the memory cell and communicating with the etch barrier material located on the logic region, and a second portion other than the first portion. The step of removing part of the etch barrier material and part of the first insulating material includes: sequentially removing all the etch barrier material located on the logic region in the etch barrier layer, the second portion in the first insulating dielectric layer, and the first portion of the etch barrier material using a patterning process.

[0014] Optionally, the step of forming the second insulating dielectric layer includes: forming a second insulating material layer on one side of the semiconductor substrate having an etch stop layer and a first insulating dielectric layer; planarizing the second insulating material layer to form the second insulating dielectric layer, wherein the second insulating dielectric layer covers the etch stop layer.

[0015] Optionally, the step of forming the top metal interconnect structure includes: etching a second insulating material in the second insulating dielectric layer located on the array region, etching an etching barrier layer on the array region, a protective material in the protective layer located on the array region, and a first insulating material in the first insulating dielectric layer located on the array region until the memory cell is exposed; simultaneously, etching the second insulating material in the second insulating dielectric layer located on the logic region and the first insulating material in the first insulating dielectric layer located on the logic region until the second conductive channel is exposed, so as to form a trench on the surface of the second insulating dielectric layer, the trench including a first trench and a second trench that are connected, the first trench being located on the array region and connected to the memory cell, and the second trench being located on the logic region and connected to the second conductive channel; filling the trench with metal material to form the top metal interconnect structure.

[0016] Optionally, the step of forming the top metal interconnect structure includes: etching the second insulating material located on the array region in the second insulating dielectric layer, the etching barrier material located on the array region in the etching barrier layer, and the protective material located on the array region in the protective layer using a single damask process until the memory cell is exposed; simultaneously, etching the second insulating material located on the logic region in the second insulating dielectric layer and the first insulating material located on the logic region in the first insulating dielectric layer until the second conductive channel is exposed, so as to form a trench on the surface of the second insulating dielectric layer, the trench including a first trench and a second trench that are connected, the first trench being located on the array region and connected to the memory cell, and the second trench being located on the logic region and connected to the second conductive channel; filling the trench with metal material to form the top metal interconnect structure.

[0017] This disclosure provides a method for fabricating a memory structure. The method first provides a semiconductor substrate comprising an adjacent array region and a logic region, and then forms a protective layer on one side of the semiconductor substrate. The array region of the provided semiconductor substrate includes a first conductive channel located in the substrate and a memory cell disposed in contact with the first conductive channel. The logic region includes a second conductive channel located in the substrate and spaced apart from the first conductive channel. Notably, the first and second conductive channels in the semiconductor substrate are formed in the same semiconductor process, and the memory cell is formed after the formation of the first and second conductive channels. Therefore, the formation of the protective layer immediately follows the formation of the memory cell. Furthermore, since the protective layer can conformally cover the side of the semiconductor substrate with the memory cell, it effectively isolates the memory cell from the external environment, preventing oxidation of the memory cell surface during subsequent processing and maintaining the original electrical characteristics of the memory cell.

[0018] Furthermore, in order to form a top metal interconnect structure on the side of the semiconductor substrate with memory cells and to prevent damage to the memory cells during subsequent etching, a first insulating dielectric layer and an etch barrier layer are sequentially formed on the side of the semiconductor substrate with a protective layer. Then, by removing a portion of the etch barrier material and a portion of the first insulating material, at least a portion of the etch barrier material located on the logic region in the etch barrier layer and at least a portion of the first insulating material located on the logic region in the first insulating dielectric layer are removed. It is worth noting that after this step, the memory cells are still covered by the protective layer; therefore, the surface of the memory cells will not be oxidized in this step. Next, a second insulating dielectric layer is formed on the side of the semiconductor substrate with the etch barrier layer and the first insulating dielectric layer. Then, a top metal interconnect structure is formed on the side of the semiconductor substrate with memory cells. The first metal connection portion of the top metal interconnect structure is located on the array region and is in contact with the memory cells, while the second metal connection portion of the top metal interconnect structure is located on the logic region and is in contact with the second conductive channel. Therefore, the top metal interconnect structure is formed by directly etching the second insulating dielectric layer, the first insulating dielectric layer, and the protective layer to create and fill the grooves. Thus, during the formation of the top metal interconnect structure, the surface of the memory cell is not directly exposed to the etching environment, thereby avoiding the possibility of oxidation. Furthermore, it eliminates the need for chemical mechanical polishing to open the surface of the memory cell away from the first conductive channel, preventing either an unpolished or over-polished surface on that side. This avoids the problems of open circuits due to unpolished memory cells or short circuits due to over-polishing.

[0019] In summary, this application solves the problem of low memory reliability caused by oxidation of memory cells during the fabrication of the logic area in the prior art. Attached Figure Description

[0020] The accompanying drawings, which form part of this disclosure, are used to provide a further understanding of this disclosure. The illustrative embodiments of this disclosure and their descriptions are used to explain this disclosure and do not constitute an undue limitation of this disclosure. In the drawings:

[0021] Figure 1 shows a cross-sectional view of the structure after the formation of the memory cell film layer in a method for manufacturing a memory structure according to an embodiment of the present disclosure.

[0022] Figure 2 shows a cross-sectional view of the structure after the storage cells are formed on the basis of the structure shown in Figure 1, and after the protective layer is formed.

[0023] Figure 3 shows a cross-sectional schematic diagram of the structure after the first insulating dielectric layer and the etching barrier layer are formed on the basis of the structure shown in Figure 2.

[0024] Figure 4 shows a cross-sectional view of the structure after removing part of the etching barrier material and the first insulating material located on the logic region in the etching barrier layer, based on the structure shown in Figure 3.

[0025] Figure 5 shows a cross-sectional schematic diagram of the structure after the second insulating dielectric layer is formed based on the structure shown in Figure 4.

[0026] Figure 6 shows a cross-sectional structural diagram of a memory structure fabricated according to the first embodiment of the present disclosure, based on the structure shown in Figure 5.

[0027] Figure 7 shows a cross-sectional structure diagram of a memory structure fabricated according to a second embodiment of the present disclosure, based on the structure shown in Figure 5.

[0028] The above figures include the following reference numerals: 100, array area; 200, logic area; 10, first conductive channel; 20, second conductive channel; 30, memory cell; 301, memory cell film layer; 40, protective layer; 50, first insulating dielectric layer; 60, etching barrier layer; 70, second insulating dielectric layer; 80, top metal interconnect structure. Detailed Implementation

[0029] It should be noted that, unless otherwise specified, the embodiments and features described in this disclosure can be combined with each other. This disclosure will now be described in detail with reference to the accompanying drawings and embodiments.

[0030] To enable those skilled in the art to better understand the present disclosure, the technical solutions of the present disclosure will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present disclosure, and not all embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present disclosure.

[0031] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0032] As described in the background section, existing MRAM memory fabrication processes are complex and costly due to the need for two photolithography etching processes to fabricate the array region and logic region. Furthermore, when fabricating the array region memory cells and their interconnects, a chemical mechanical polishing (CMP) process is typically required to open the top surface of the memory cells. This process demands extremely high surface uniformity in the array region, and in large-capacity array fabrication, it can easily lead to problems such as open circuits due to insufficient polishing or short circuits due to excessive polishing. Therefore, this application aims to address the problem of low memory reliability caused by oxidation of memory cells during the logic region fabrication process in existing technologies by providing a memory structure and a method for fabricating the memory structure.

[0033] According to one aspect of this application, a method for fabricating a memory structure is provided, comprising:

[0034] A semiconductor substrate is provided, including an adjacent array region and a logic region. The array region includes a first conductive channel located in the substrate and a memory cell stacked and contacted with the first conductive channel. The logic region includes a second conductive channel located in the substrate. The first conductive channel and the second conductive channel are spaced apart.

[0035] It should be noted that for the semiconductor substrate provided above, the first conductive channel in the array region and the second conductive channel in the logic region are formed using the same semiconductor process.

[0036] It is understandable that when the first conductive channel of the array region and the second conductive channel of the logic region are fabricated in the same semiconductor process, the memory structure of the array region is formed after the first conductive channel and the second conductive channel.

[0037] Specifically, as shown in Figure 1, both the first conductive channel 10 and the second conductive channel 20 extend from one side surface of the substrate (not labeled in the figure) to the other surface opposite to that side surface.

[0038] Specifically, the steps for forming the aforementioned memory cell include: as shown in FIG1, depositing a memory cell film layer 301 on one side surface of a substrate. More specifically, when the substrate has a bottom metal interconnect structure on one side surface, the memory cell film layer 301 is located on the side of the first conductive channel 10 and the second conductive channel 20 away from the bottom metal interconnect structure, and the first conductive channel 10 and the second conductive channel 20 are equidistant from the bottom metal interconnect structure. The memory cell film layer 301 may include a lower electrode material layer, a memory material layer, and an upper electrode material layer stacked together.

[0039] Optionally, the lower electrode material layer and the upper electrode material layer may include, but are not limited to, metal layers such as Ti, TiN, Ta, TaN, and W. Optionally, a hard mask material layer may also be included on the upper electrode material layer, which may include, but is not limited to, metal layers such as Ti, TiN, Ta, TaN, and W, or dielectric layers such as silicon oxide and silicon nitride. Optionally, the storage material layer may include a free layer, a barrier layer, and a reference layer stacked sequentially, with the free layer in contact with the lower electrode material layer and the reference layer in contact with the upper electrode material layer.

[0040] Specifically, to form a memory cell, a patterning process can be used to etch the memory cell film layer to form the memory cell. Optionally, the hard mask material layer, the upper electrode material layer, the memory material layer, and the lower electrode material layer can be etched sequentially, thereby forming the memory cell based on a preset pattern in the patterning process.

[0041] Optionally, as shown in FIG2, the vertical projection shape of the storage cell 30 on the substrate is circular.

[0042] In addition, the shape of the vertical projection of the storage cell 30 onto the substrate can also be elliptical, elongated, or other shapes.

[0043] Furthermore, as shown in Figure 2, in order to prevent the memory cell 30 from being oxidized in subsequent fabrication processes, a protective layer 40 can be conformally formed on the side of the semiconductor substrate (not shown in the figure) where the memory cell 30 is located.

[0044] It should be noted that since the memory cells 30 are only located in the array region 100, the memory cells 30 in the array region 100 significantly protrude from the surface of the substrate. Therefore, in the step of forming the protective layer 40 on the side of the semiconductor substrate with the memory cells 30, the protective layer 40 can uniformly cover the surface of the substrate and the entire surface of the memory cells 30. Thus, after the protective layer 40 is formed on the side of the semiconductor substrate with the memory cells 30, the protective material covering the memory cells 30 in the protective layer 40 significantly protrudes from the protective material covering the surface of the substrate in the protective layer 40. Based on this, it is considered that the protective layer 40 is conformally located on the side of the semiconductor substrate with the memory cells 30.

[0045] Next, as shown in FIG3, in order to avoid oxidation of the surface of the memory cell 30 away from the semiconductor substrate during the step of fabricating the groove for forming the top metal interconnect structure on the array region 100 and the logic region 200 using the same etching process, a first insulating dielectric layer 50 and an etch barrier layer 60 are sequentially formed on the side of the semiconductor substrate with the protective layer 40; a portion of the etch barrier material and a portion of the first insulating material are removed, as shown in FIG4. Then, as shown in FIG5, a second insulating dielectric layer 70 is formed on the side of the semiconductor substrate with the etch barrier layer 60 and the first insulating dielectric layer 50. The portion of the etch barrier material is at least a portion of the etch barrier material located on the logic region 200 in the etch barrier layer 60, and the portion of the first insulating material is at least a portion of the first insulating material located on the logic region 200 in the first insulating dielectric layer 50.

[0046] In some optional embodiments, the step of forming the first insulating dielectric layer includes: depositing a first insulating material layer on the side of the semiconductor substrate having a protective layer, so that the first insulating material layer covers the protective layer; planarizing the first insulating material layer until the surface of the protective layer on the side away from the memory cell is exposed, thereby forming the first insulating dielectric layer.

[0047] Specifically, the minimum vertical distance between the surface of the first insulating material layer away from the semiconductor substrate and the substrate is greater than the maximum vertical distance between the protective layer and the substrate.

[0048] It is understandable that, as shown in Figure 3, after the first insulating dielectric layer 50 is formed, the surface of the first insulating dielectric layer 50 away from the semiconductor substrate can be flush with the surface of the protective layer 40 away from the memory cell 30.

[0049] Specifically, as shown in FIG3, the etching barrier material of the etching barrier layer 60 may include the portion located on the array region 100 covering the first insulating dielectric layer 50 and the protective layer 40, and the portion located on the logic region 200 covering the first insulating dielectric layer 50.

[0050] Optionally, the etching barrier material includes, but is not limited to, one or more combinations of silicon nitride, silicon carbonitride, aluminum oxide, and other non-conductive metal oxide materials such as magnetic insulating layers.

[0051] Furthermore, in order to fabricate the grooves for forming the top metal interconnect structure on both the array region 100 and the logic region 200 using the same etching process, all the etch-blocking material in the etch-blocking layer 60 located on the logic region 200 can be removed first, as shown in Figure 4. That is, after this step, the etch-blocking material in the etch-blocking layer 60 located on the array region 100 can be completely retained, while all the etch-blocking material in the etch-blocking layer 60 located on the logic region 200 is removed.

[0052] Of course, in some alternative implementations, a portion of the etch barrier material located on the logic region in the etch barrier layer may be removed, and the position of this portion of the etch barrier material corresponds to the position of the subsequent top metal interconnect structure located on the logic region.

[0053] As shown in Figure 4, when removing at least a portion of the etch-blocking material located on the logic region 200 in the etch-blocking layer 60, in order to completely remove all the etch-blocking material located on the logic region 200 in the etch-blocking layer 60, all the etch-blocking material located on the logic region 200 in the etch-blocking layer 60 can be over-etched. That is, if the first insulating material located on the logic region 200 in the first insulating dielectric layer 50 includes a first portion (not shown in the figure) covering the protective layer 40 and a second portion (not shown in the figure) located on the side of the first portion away from the protective layer 40, the second portion of the first insulating material can also be removed.

[0054] Of course, in some alternative embodiments, the etch barrier material located on the array region in the etch barrier layer includes a first portion located on the side of the protective layer away from the memory cell and communicating with the etch barrier material located on the logic region, and a second portion other than the first portion. The step of removing part of the etch barrier material and part of the first insulating material includes: sequentially removing all the etch barrier material located on the logic region in the etch barrier layer, the second portion in the first insulating dielectric layer, and the first portion of the etch barrier material using a patterning process.

[0055] That is, a portion of the etch stop material on the array region can be retained. In this case, only a portion of the etch stop material located on the array region in the etch stop layer is removed. The first etch stop material on the array region in the etch stop layer is patterned into a strip shape along a direction parallel to the substrate surface. It can be understood that the positions on the array region corresponding to the removed portion of the etch stop material are used to form the portions of the top metal interconnect structure that are electrically connected to the memory cells.

[0056] As shown in Figure 4, it should be noted that after the steps of removing part of the etching barrier material and removing part of the first insulating material, the protective layer 40 still covers the entire surface of the storage cell 30. That is, the protective layer 40 can still be used to isolate the storage cell 30 from the external environment and prevent the storage cell 30 from being oxidized.

[0057] Furthermore, as shown in FIG5, in some alternative embodiments, in order to provide mechanical support for the top metal interconnect structure and to avoid damage to the underlying structure during the etching process, a second insulating dielectric layer 70 is formed on the side of the etching barrier layer 60 away from the semiconductor substrate and the first insulating dielectric layer 50 away from the semiconductor substrate.

[0058] Specifically, the step of forming the second insulating dielectric layer includes: forming a second insulating material layer on one side of the semiconductor substrate having an etch stop layer and a first insulating dielectric layer; planarizing the second insulating material layer to form the second insulating dielectric layer, wherein the second insulating dielectric layer covers the etch stop layer.

[0059] It should be noted that, as shown in Figure 5, the planarized second insulating dielectric layer 70 has a certain vertical distance on the etching barrier layer 60.

[0060] Finally, a top metal interconnect structure can be formed on the side of the semiconductor substrate with the memory cell, and the top metal interconnect structure includes a first metal connection portion and a second metal connection portion electrically connected. The first metal connection portion is located on the array region and is in contact with the memory cell, and the second metal connection portion is located on the logic region and is in contact with the second conductive channel.

[0061] Understandably, during the formation of the first and second metal connections, a portion of the material covering the memory cell and the second conductive channel in the second insulating material layer is removed, as is a portion of the material covering the memory cell and the second conductive channel in the etching barrier layer. Additionally, a portion of the material covering the surface of the memory cell away from the first conductive channel and a portion of the first insulating material covering the second conductive channel in the protective layer are also removed. Thus, after the formation of the first metal connection that contacts the memory cell, the second insulating dielectric layer and the etching barrier layer surround the first metal connection; after the formation of the second metal connection that contacts the second conductive channel, the second insulating dielectric layer and the first insulating dielectric layer surround the second metal connection. Furthermore, a portion of the etching barrier material may remain on the logic region; in this case, the second insulating dielectric layer, the etching barrier layer, and the first insulating dielectric layer surround the second metal connection.

[0062] As can be seen from the above, before forming the top metal interconnect structure, the surface of the first insulating dielectric layer away from the semiconductor substrate is flush with the surface of the protective layer away from the memory cell. Therefore, in some optional embodiments, the step of forming the top metal interconnect structure includes: as shown in FIG5 and FIG6, etching the second insulating material in the second insulating dielectric layer 70 located on the array region 100, the etching barrier material in the etching barrier layer 60 located on the array region 100, the protective material in the protective layer 40 located on the array region 100, and the first insulating material in the first insulating dielectric layer 50 located on the array region 100 until the memory cell 30 is exposed. Meanwhile, as shown in Figures 5 and 6, the second insulating material located on the logic region 200 in the second insulating dielectric layer 70 and the first insulating material located on the logic region 200 in the first insulating dielectric layer 50 are etched until the second conductive channel 20 is exposed, so as to form a trench (not shown in the figure) on the surface of the second insulating dielectric layer. The trench includes a first trench (not shown in the figure) and a second trench (not shown in the figure) that are connected. The first trench is located on the array region 100 and is connected to the memory cell 30, and the second trench is located on the logic region 200 and is connected to the second conductive channel 20. Metal material is filled in the trench to form a top metal interconnect structure 80.

[0063] As can be understood, as shown in FIG6, in this embodiment, after the top metal interconnect structure 80 is formed, the metal material located on the array region 100 in the top metal interconnect structure 80 has contact surfaces with the first insulating dielectric layer 50 and the memory cell 30, respectively, and the contact surface between the metal material located on the array region 100 in the top metal interconnect structure 80 and the first insulating dielectric layer 50 is flush with the contact surface between the metal material located on the array region 100 in the top metal interconnect structure 80 and the memory cell 30.

[0064] In some alternative embodiments, to form a low-resistance metal interconnect and reduce process steps, the step of forming the top metal interconnect structure includes: as shown in Figures 5 and 7, etching the second insulating material in the second insulating dielectric layer 70 located on the array region 100, the etching barrier material in the etching barrier layer 60 located on the array region 100, and the protective material in the protective layer 40 located on the array region 100 using a single damask process until the memory cell 30 is exposed. Simultaneously, as shown in Figures 5 and 7, etching the second insulating material in the second insulating dielectric layer 70 located on the logic region 200 and the first insulating material in the first insulating dielectric layer 50 located on the logic region 200 until the second conductive channel 20 is exposed to form a trench (not shown) on the surface of the second insulating dielectric layer. The trench includes a first trench (not shown) and a second trench (not shown), which are connected. The first trench is located on the array region 100 and connected to the memory cell 30, and the second trench is located on the logic region 200 and connected to the second conductive channel 20. The trench is then filled with metal material to form the top metal interconnect structure 80.

[0065] As can be seen, the memory cell is covered by a protective layer before the first trench for filling the metal material is etched. Thus, this application can solve the problem of low memory reliability caused by oxidation of the memory cell during the fabrication of the logic area in the prior art.

[0066] This disclosure provides a method for fabricating a memory structure. The method first provides a semiconductor substrate comprising an adjacent array region and a logic region, and then forms a protective layer on one side of the semiconductor substrate. The array region of the provided semiconductor substrate includes a first conductive channel located in the substrate and a memory cell disposed in contact with the first conductive channel. The logic region includes a second conductive channel located in the substrate and spaced apart from the first conductive channel. Notably, the first and second conductive channels in the semiconductor substrate are formed in the same semiconductor process, and the memory cell is formed after the formation of the first and second conductive channels. Therefore, the formation of the protective layer immediately follows the formation of the memory cell. Furthermore, since the protective layer can conformally cover the side of the semiconductor substrate with the memory cell, it effectively isolates the memory cell from the external environment, preventing oxidation of the memory cell surface during subsequent processing and maintaining the original electrical characteristics of the memory cell.

[0067] Furthermore, in order to form a top metal interconnect structure on the side of the semiconductor substrate with memory cells and to prevent damage to the memory cells during subsequent etching, a first insulating dielectric layer and an etch barrier layer are sequentially formed on the side of the semiconductor substrate with a protective layer. Then, by removing a portion of the etch barrier material and a portion of the first insulating material, at least a portion of the etch barrier material located on the logic region in the etch barrier layer and at least a portion of the first insulating material located on the logic region in the first insulating dielectric layer are removed. It is worth noting that after this step, the memory cells are still covered by the protective layer; therefore, the surface of the memory cells will not be oxidized in this step. Next, a second insulating dielectric layer is formed on the side of the semiconductor substrate with the etch barrier layer and the first insulating dielectric layer. Then, a top metal interconnect structure is formed on the side of the semiconductor substrate with memory cells. The first metal connection portion of the top metal interconnect structure is located on the array region and is in contact with the memory cells, while the second metal connection portion of the top metal interconnect structure is located on the logic region and is in contact with the second conductive channel. Therefore, the top metal interconnect structure is formed by directly etching the second insulating dielectric layer, the first insulating dielectric layer, and the protective layer to create and fill the grooves. Thus, during the formation of the top metal interconnect structure, the surface of the memory cell is not directly exposed to the etching environment, thereby avoiding the possibility of oxidation. Furthermore, it eliminates the need for chemical mechanical polishing to open the surface of the memory cell away from the first conductive channel, preventing either an unpolished or over-polished surface on that side. This avoids the problems of open circuits due to unpolished memory cells or short circuits due to over-polishing.

[0068] In summary, this application solves the problem of low memory reliability caused by oxidation of memory cells during the fabrication of the logic area in the prior art.

[0069] According to another aspect of this disclosure, a memory structure is provided, which is fabricated using any of the memory structure fabrication methods described above. As shown in Figures 6 and 7, the memory structure includes: a semiconductor substrate, the semiconductor substrate including adjacent array region 100 and logic region 200, the array region 100 including a first conductive channel 10 located in the substrate and memory cells 30 stacked and contacted with the first conductive channel 10, the logic region 200 including a second conductive channel 20 located in the substrate, the first conductive channel 10 and the second conductive channel 20 being spaced apart; a protective layer 40 located on the side of the semiconductor substrate having the memory cells 30 and covering the sidewall of the memory cells 30; the first... An insulating dielectric layer 50 is located on the side of the semiconductor substrate having a protective layer 40; an etch stop layer (not shown in the figure) is located on the side of the first insulating dielectric layer 50 away from the protective layer 40; a second insulating dielectric layer (not shown in the figure) is located on the side of the etch stop layer away from the semiconductor substrate; a top metal interconnect structure 80 is located on the side of the semiconductor substrate having a memory cell 30, the top metal interconnect structure 80 includes an electrically connected first metal connection portion (not labeled in the figure) and a second metal connection portion (not shown in the figure), the first metal connection portion is located on the array region 100 and is in contact with the memory cell 30, and the second metal connection portion is located on the logic region 200 and is in contact with the second conductive channel 20.

[0070] As shown in Figures 6 and 7, in the above embodiments, since the memory structure is fabricated using the above-described memory structure fabrication method, there is good electrical contact between the memory cell 30 and the top metal interconnect structure 80, thereby improving the reliability of the memory.

[0071] In some alternative embodiments, a second insulating dielectric layer and an etch barrier layer surround the first metal connection, thereby enabling the first metal connection to contact the memory cell.

[0072] Similarly, in some alternative embodiments, the second insulating dielectric layer and the first insulating dielectric layer surround the second metal connection, thereby enabling the second metal connection to contact the second conductive channel.

[0073] In some alternative embodiments, as shown in FIG6, in order to enable good electrical contact between the top metal interconnect structure 80 and the memory cell 30, the surface of the first insulating dielectric layer 50 away from the semiconductor substrate is flush with the surface of the memory cell 30 away from the first conductive channel 10.

[0074] In some alternative embodiments, as shown in FIG7, in order to reduce the contact resistance between the top metal interconnect structure 80 and the memory cell 30, the surface of the first insulating dielectric layer 50 away from the semiconductor substrate is higher than the surface of the memory cell 30 away from the first conductive channel 10.

[0075] As can be seen from the above description, the embodiments of this disclosure achieve the following technical effects:

[0076] This disclosure provides a method for fabricating a memory structure. The method first provides a semiconductor substrate comprising an adjacent array region and a logic region, and then forms a protective layer on one side of the semiconductor substrate. The array region of the provided semiconductor substrate includes a first conductive channel located in the substrate and a memory cell disposed in contact with the first conductive channel. The logic region includes a second conductive channel located in the substrate and spaced apart from the first conductive channel. Notably, the first and second conductive channels in the semiconductor substrate are formed in the same semiconductor process, and the memory cell is formed after the formation of the first and second conductive channels. Therefore, the formation of the protective layer immediately follows the formation of the memory cell. Furthermore, since the protective layer can conformally cover the side of the semiconductor substrate with the memory cell, it effectively isolates the memory cell from the external environment, preventing oxidation of the memory cell surface during subsequent processing and maintaining the original electrical characteristics of the memory cell.

[0077] Furthermore, in order to form a top metal interconnect structure on the side of the semiconductor substrate with memory cells and to prevent damage to the memory cells during subsequent etching, a first insulating dielectric layer and an etch barrier layer are sequentially formed on the side of the semiconductor substrate with a protective layer. Then, by removing a portion of the etch barrier material and a portion of the first insulating material, at least a portion of the etch barrier material located on the logic region in the etch barrier layer and at least a portion of the first insulating material located on the logic region in the first insulating dielectric layer are removed. It is worth noting that after this step, the memory cells are still covered by the protective layer; therefore, the surface of the memory cells will not be oxidized in this step. Next, a second insulating dielectric layer is formed on the side of the semiconductor substrate with the etch barrier layer and the first insulating dielectric layer. Then, a top metal interconnect structure is formed on the side of the semiconductor substrate with memory cells. The first metal connection portion of the top metal interconnect structure is located on the array region and is in contact with the memory cells, while the second metal connection portion of the top metal interconnect structure is located on the logic region and is in contact with the second conductive channel. Therefore, the top metal interconnect structure is formed by directly etching the second insulating dielectric layer, the first insulating dielectric layer, and the protective layer to create and fill the grooves. Thus, during the formation of the top metal interconnect structure, the surface of the memory cell is not directly exposed to the etching environment, thereby avoiding the possibility of oxidation. Furthermore, it eliminates the need for chemical mechanical polishing to open the surface of the memory cell away from the first conductive channel, preventing either an unpolished or over-polished surface on that side. This avoids the problems of open circuits due to unpolished memory cells or short circuits due to over-polishing.

[0078] In summary, this application solves the problem of low memory reliability caused by oxidation of memory cells during the fabrication of the logic area in the prior art.

[0079] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A memory structure, the memory structure comprising: A semiconductor substrate, the semiconductor substrate including an adjacent array region and a logic region, the array region including a first conductive channel located in the substrate and a memory cell stacked and contacted with the first conductive channel, the logic region including a second conductive channel located in the substrate, the first conductive channel and the second conductive channel being spaced apart; A protective layer is located on the side of the semiconductor substrate having the memory cell and covers the sidewall of the memory cell; A first insulating dielectric layer is located on the side of the semiconductor substrate having the protective layer; An etching barrier layer is located on the side of the first insulating dielectric layer away from the protective layer; The second insulating dielectric layer is located on the side of the etch barrier layer away from the semiconductor substrate; A top metal interconnect structure is located on the side of the semiconductor substrate having the memory cell. The top metal interconnect structure includes a first metal connection portion and a second metal connection portion electrically connected. The first metal connection portion is located on the array region and is in contact with the memory cell. The second metal connection portion is located on the logic region and is in contact with the second conductive channel.

2. The memory structure according to claim 1, wherein, The second insulating dielectric layer and the etching barrier layer surround the first metal connection.

3. The memory structure according to claim 1, wherein, The second insulating dielectric layer and the first insulating dielectric layer surround the second metal connection portion.

4. The memory structure according to claim 1, wherein, The surface of the first insulating dielectric layer away from the semiconductor substrate is flush with the surface of the memory cell away from the first conductive channel.

5. The memory structure according to claim 1, wherein, The surface of the first insulating dielectric layer on the side away from the semiconductor substrate is higher than the surface of the memory cell on the side away from the first conductive channel.

6. The memory structure according to claim 1, wherein, Both the first conductive channel and the second conductive channel extend from one side surface of the substrate to another surface opposite to one side surface of the substrate.

7. A method for fabricating a memory structure, comprising: A semiconductor substrate is provided, including an adjacent array region and a logic region. The array region includes a first conductive channel located in the substrate and a memory cell stacked and contacted with the first conductive channel. The logic region includes a second conductive channel located in the substrate. The first conductive channel and the second conductive channel are spaced apart. A protective layer is conformally formed on one side of the semiconductor substrate having the memory cell; A first insulating dielectric layer and an etch barrier layer are sequentially formed on the side of the semiconductor substrate having the protective layer; A portion of the etch-blocking material and a portion of the first insulating material are removed, and then a second insulating dielectric layer is formed on the side of the semiconductor substrate having the etch-blocking layer and the first insulating dielectric layer. The portion of the etch-blocking material is at least a portion of the etch-blocking material located on the logic region in the etch-blocking layer, and the portion of the first insulating material is at least a portion of the first insulating material located on the logic region in the first insulating dielectric layer. A top metal interconnect structure is formed on one side of the semiconductor substrate having the memory cell. The top metal interconnect structure includes a first metal connection portion and a second metal connection portion electrically connected. The first metal connection portion is located on the array region and is in contact with the memory cell. The second metal connection portion is located on the logic region and is in contact with the second conductive channel.

8. The manufacturing method according to claim 7, wherein, The steps for forming the first insulating dielectric layer include: A first insulating material layer is deposited on the side of the semiconductor substrate having the protective layer, such that the first insulating material layer covers the protective layer; The first insulating material layer is planarized until the surface of the protective layer on the side away from the storage cell is exposed to form the first insulating dielectric layer.

9. The manufacturing method according to claim 8, wherein, The minimum vertical distance of the surface of the first insulating material layer away from the semiconductor substrate from the substrate is greater than the maximum vertical distance of the protective layer from the substrate.

10. The manufacturing method according to claim 7, wherein, The first insulating material located on the logic region in the first insulating dielectric layer includes a first portion covering the protective layer and a second portion located on the side of the first portion away from the protective layer. The step of removing part of the etching barrier material and part of the first insulating material includes: A patterned process is used to sequentially remove all the etch-blocking material located on the logic region in the etch-blocking layer and the second portion in the first insulating dielectric layer.

11. The manufacturing method according to claim 7, wherein, The first insulating material in the first insulating dielectric layer located on the logic region includes a first portion covering the protective layer and a second portion located on the side of the first portion away from the protective layer. The etch barrier layer located on the array region includes an etch barrier material located on the side of the protective layer away from the memory cell and communicating with the etch barrier material located on the logic region, and a second portion other than the first portion. The step of removing part of the etch barrier material and part of the first insulating material includes: A patterned process is used to sequentially remove all etch-blocking material located on the logic region in the etch-blocking layer, the second portion in the first insulating dielectric layer, and the first portion of the etch-blocking material.

12. The manufacturing method according to claim 7, wherein, The steps for forming the second insulating dielectric layer include: A second insulating material layer is formed on one side of the semiconductor substrate having the etch barrier layer and the first insulating dielectric layer; The second insulating material layer is planarized to form the second insulating dielectric layer, and the second insulating dielectric layer covers the etching barrier layer.

13. The manufacturing method according to any one of claims 7 to 12, wherein, The steps for forming the top metal interconnect structure include: The second insulating material in the second insulating dielectric layer located on the array region, the etching barrier material in the etching barrier layer located on the array region, the protective material in the protective layer located on the array region, and the first insulating material in the first insulating dielectric layer located on the array region are etched until the memory cell is exposed. At the same time, the second insulating material in the second insulating dielectric layer located on the logic region and the first insulating material in the first insulating dielectric layer located on the logic region are etched until the second conductive channel is exposed, so as to form a trench on the surface of the second insulating dielectric layer. The trench includes a first trench and a second trench that are connected. The first trench is located on the array region and is connected to the memory cell, and the second trench is located on the logic region and is connected to the second conductive channel. The trench is filled with a metallic material to form the top metal interconnect structure.

14. The manufacturing method according to any one of claims 7 to 12, wherein, The steps for forming the top metal interconnect structure include: The second insulating material located on the array region in the second insulating dielectric layer, the etching barrier material located on the array region in the etching barrier layer, and the protective material located on the array region in the protective layer are etched using a single damascus etching process until the memory cell is exposed. Simultaneously, the second insulating material located on the logic region in the second insulating dielectric layer and the first insulating material located on the logic region in the first insulating dielectric layer are etched until the second conductive channel is exposed, thereby forming a trench on the surface of the second insulating dielectric layer. The trench includes a first trench and a second trench that are connected. The first trench is located on the array region and is connected to the memory cell, and the second trench is located on the logic region and is connected to the second conductive channel. The trench is filled with a metallic material to form the top metal interconnect structure.

15. The manufacturing method according to any one of claims 7 to 12, wherein, The first conductive channel in the array region and the second conductive channel in the logic region are formed using the same semiconductor process.

16. The manufacturing method according to any one of claims 7 to 12, wherein, The first conductive channel in the array region and the second conductive channel in the logic region are formed using the same semiconductor process.

17. The manufacturing method according to any one of claims 7 to 12, wherein, The storage unit comprises: A memory cell film layer is deposited on one side surface of the substrate to obtain the memory cell. The memory cell film layer includes a lower electrode material layer, a memory material layer, and an upper electrode material layer stacked together.

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