Data processing method, apparatus, and system

Abstract

A data processing method, an apparatus, and a system, relating to the technical field of optical communications, and used for improving the error correction performance of an overall concatenated FEC scheme. In embodiments of the present application, two data streams having undergone outer code encoding undergo block distribution, cyclic shift, and inner code encoding, and then undergo bit-pair interleaving (or bit-pair interleaving and bit-pair multiplexing) to form one data stream, so that symbols processed by FEC outer code encoding can be scattered into more inner code codewords, and thus the concatenated codes have better anti-colored noise capability, so as to improve the error correction performance of the overall concatenated FEC.

Description

A data processing method, apparatus and system

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202510207489.8, filed on February 22, 2025, entitled "A Data Processing Method, Apparatus and System", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of communication technology, and in particular to a data processing method, apparatus and system. Background Technology

[0004] Driven by 5G, cloud computing, big data, and artificial intelligence, optical communication systems and optical transport networks (OTNs) are developing towards higher capacity and ultra-high speed. Using forward error correction (FEC) to correct errors in transmitted data can resolve transmission errors and recover the original data sent by the transmitter from the received data.

[0005] A cascaded FEC transmission scheme is proposed, where the transmitting device and the transmitting processing module are connected via an attachment unit interface (AUI). The transmitting device performs a first FEC encoding on the data to be transmitted and sends the first FEC-encoded data to the transmitting processing module. The transmitting processing module then performs a second FEC encoding on the first FEC-encoded data, modulates and maps the second FEC-encoded data to generate a corresponding modulation symbol sequence, and finally generates an optical signal based on the modulation symbol sequence and transmits it to the receiving end via optical fiber. The first FEC encoding is also called external code encoding, and the second FEC encoding is also called internal code encoding.

[0006] Typically, the transmitting processing module performs interleaving before and after the second FEC encoding to shuffle the data order, thereby enhancing the error correction and burst resistance performance of the cascaded FEC scheme. For direct detection transmission scenarios, a cascaded FEC scheme for 200G / lane transmission is currently provided, but not for 400G / lane. Existing cascaded FEC schemes for 200G / lane transmission cannot be directly applied to 400G / lane or higher transmission rate scenarios. Specifically, as the transmission rate of each channel increases, the amount of data allocated to each channel for the external code codewords increases, causing the interleaver in existing cascaded FEC to be unable to distribute the external code codewords into more internal codewords, thus affecting the overall error correction performance of the cascaded FEC scheme. Summary of the Invention

[0007] This application provides a data processing method, apparatus, and system to improve the error correction performance of the overall cascaded FEC scheme.

[0008] In a first aspect, embodiments of this application provide a data processing method. This method can be implemented by a sending device integrating a sending-end processing module, or executed by the sending-end processing module itself. The method includes: performing first data processing on two first data streams respectively to obtain 2*S second data streams; where S is an integer greater than 1, both first data streams are encoded using an external code, the first data processing includes block distribution, and each first data stream is distributed into S second data streams; performing second data processing on the 2*S second data streams respectively to obtain 2*S third data streams, the second data processing including cyclic shifting and internal code encoding; and interleaving the bit pairs of the 2*S third data streams into a fourth data stream.

[0009] Using the scheme provided in the embodiments of this application, two 200G data streams are distributed in blocks, cyclically shifted, and then encoded with internal codes. After interleaving bit pairs, they become a 400G data stream. The external codewords can be scattered into more internal codewords, so that the concatenated code has a better ability to resist colored noise, that is, improve the error correction performance of the overall concatenated FEC.

[0010] In one possible implementation, the outer code encoding can employ RS(544, 514) code. A specific implementation of the outer code encoding is provided, enabling this scheme to have good resistance to colored noise.

[0011] In one possible implementation, S = 4 or S = 8. A specific implementation of block distribution is provided, allowing for the adoption of a specific block distribution scheme according to requirements. Furthermore, the block distribution method described above enables this scheme to achieve good practical results.

[0012] In one possible implementation, the method further includes: performing pad sequence insertion on the fourth data stream to obtain a data stream with pad insertion.

[0013] In one possible implementation, the pad sequence comprises f groups, each of the f groups comprising N bits, where f = 2*S, and N > 1.

[0014] In one possible implementation, each packet may include a first part and a second part. The first part includes at least one bit pair, and the sequence of the first parts of the f packets arranged sequentially according to the packet order, in units of bit pairs, includes a frame-aligned sequence. The above provides a specific form of the pad sequence before bit pair mapping, enabling the f packets to obtain a frame-aligned sequence after bit pair multiplexing, thus giving this scheme good practical performance.

[0015] In one possible implementation, the second part includes a first sub-part and a second sub-part, the second sub-part being NK bit check information, and the first sub-part being a scrambled sequence of all zeros.

[0016] In one possible implementation, the codeword length of the internal code encoding is N bits, where N = 128, and the information length of the codeword is 120 bits.

[0017] In one possible implementation, pad sequence insertion is performed on the fourth data stream, including: inserting the pad sequence after every H internal codewords in the fourth data stream; where f = 8, H = 8704, or f = 16, H = 17408. The above provides two possible pad insertion methods.

[0018] In one possible implementation, S = 4, and the values ​​of pad_cw_i<127:122> in the f groups are:

[0019] Where 0≤i<8, pad_cw_i<127:122> represents bits 122 to 127 of group i in the f groups. pad_cw_i<127:122> can also be understood as the first part of the pad sequence.

[0020] The above provides a specific method for generating f groups, which enables the first part of the f groups to obtain a frame-aligned sequence after bit-pair multiplexing, and has good practical effect.

[0021] In one possible implementation, S = 8, and the pad_cw_i of the f groups <n-1:x>The value can be:

[0022] Where 0 ≤ i < 16, and when 0 ≤ i < 8, x = 124, and when 8 ≤ i < 16, x = 126, pad_cw_i <n-1:x>Let f represent bits x to N-1 of group i in the f groups.

[0023] In one possible implementation, pad_cw_i <n-1:x>It can also be understood as the first part of the pad sequence.

[0024] The above provides another specific method for generating f groups, which enables the first part of the f groups to obtain a frame alignment sequence after bit pair multiplexing. This allows the receiving end to quickly complete the internal codeword synchronization using the frame alignment sequence, resulting in good practical performance.

[0025] In one possible implementation, the method further includes: performing third data processing on the two fifth data streams to obtain the two first data streams, wherein the third data processing includes alignment flag locking; wherein the two fifth data streams are both encoded with external codes.

[0026] In one possible implementation, third data processing is performed on the two fifth data streams, including:

[0027] Symbol demultiplexing is performed on each of the two fifth data streams to obtain 2*t demultiplexed data streams. Each fifth data stream is demultiplexed into t demultiplexed data streams.

[0028] Alignment identifier locking is performed on the 2*t demultiplexed data streams respectively to obtain 2*t channel data streams with alignment identifier locking;

[0029] Deskipation processing is performed on 2*t channel data streams;

[0030] Symbol multiplexing is performed on each t channel data stream in the 2*t channel data streams after deskipation to obtain 2 first data streams; each t channel data stream comes from the same fifth data stream.

[0031] By employing the above scheme, aligning and locking before de-skewing can further improve the performance of concatenated codes.

[0032] Symbol demultiplexing can be performed with one symbol, two symbols (or symbol pair demultiplexing), or four symbols (or quad symbol demultiplexing). Symbol pair demultiplexing uses a round-robin method, distributing 20 bits (i.e., two symbols) at a time. Quad symbol demultiplexing uses a round-robin method, distributing 40 bits (i.e., four symbols) at a time.

[0033] In one possible implementation, the two first data streams undergo first data processing, including:

[0034] The first data processing is performed on every two first data streams in the obtained p first data streams, where p is an integer multiple of 2.

[0035] Through the above solution, the present application can be applied to higher-rate transmission scenarios, such as 800G, 1.6T, 3.2T, etc.

[0036] In a possible implementation, p = 8 or p = 16, t = 2, and four-symbol demultiplexing is used for symbol demultiplexing, and four-symbol multiplexing is used for symbol multiplexing.

[0037] In a possible implementation, the method further includes:

[0038] Before symbol multiplexing the 2*t channel data streams after de-skewing processing, delay the odd-channel data streams in the 2*t channel data streams after de-skewing processing by g symbols; when p = 2, g = 69, or when p = 4, g = 1.

[0039] In a possible implementation, the start positions of the alignment flags between any two of the 2*t channel data streams after de-skewing processing are skewed by D*136 symbols, where D is an integer greater than or equal to 0.

[0040] In some implementation scenarios, the above channel data streams can also be understood as PCS channel (PCSL) data streams.

[0041] In a possible implementation, p = 2 or p = 4, t = 8, and symbol-pair demultiplexing is used for symbol demultiplexing, and symbol-pair multiplexing is used for symbol multiplexing.

[0042] In a possible implementation, the first data processing further includes convolutional interleaving.

[0043] In a possible implementation, the number of symbols by which the nth second data stream from different first data streams is circularly shifted is the same, 0 ≤ n <S, and the number of symbols by which the S second data streams from the same first data stream are circularly shifted is different. It can make the 2 bit pairs from the same RS codeword in the fourth data be at least S symbols apart, improving the burst resistance performance of the concatenated code.

[0044] In a possible implementation, the number of symbols by which any two of the 2*S second data streams are circularly shifted is different, and S = 4.

[0045] In a possible implementation, S = 8, and the circular shift of the 2*S second data streams adopts the method described in any row of the following table:

[0046] Wherein, the second data stream m represents the m-th data stream among 16 second data streams, m = {0, 1, 2, ..., 15}, and the data c in the y-th column represents the right circular shift of c symbols for every consecutive 12 symbols in the corresponding second data stream m, or the data c in the y-th column represents the left circular shift of 12-c symbols for every consecutive 12 symbols in the corresponding second data stream m, where 1 ≤ y ≤ 16.

[0047] By using the cyclic shifting method described above, two bit pairs from the same RS codeword in the fourth data stream can be spaced at least S symbols apart, thus improving the burst resistance of the concatenated code.

[0048] In one possible implementation, S = 4, and the cyclic shift of the 2*S second data streams can be performed as described in any row of the following table:

[0049] Wherein, the second data stream m represents the m-th data stream among the 8 second data streams, m = {0, 1, 2, ..., 7}, and the data c in the y-th column represents the right circular shift of c symbols for every consecutive 12 symbols in the corresponding second data stream m, or the data c in the y-th column represents the left circular shift of 12-c symbols for every consecutive 12 symbols in the corresponding second data stream m, where 1 ≤ y ≤ 8.

[0050] By employing the cyclic shifting method described above, the concatenated code can have better resistance to colored noise.

[0051] Secondly, embodiments of this application provide a data processing method, which can be implemented by a sending device integrating a sending-end processing module, or executed by the sending-end processing module. The method includes: performing first data processing on two first data streams to obtain 2*S second data streams; where S is an integer greater than 1, all first data streams are encoded using an external code, and the first data processing includes block distribution, with each first data stream being block-distributed into S second data streams; performing second data processing on the 2*S second data streams respectively to obtain 2*S third data streams, where the second data processing includes cyclic shifting and internal code encoding; interleaving the bit pairs of the 2*S third data streams into two sixth data streams; and multiplexing the bit pairs of the two sixth data streams into a seventh data stream.

[0052] Using the scheme provided in the embodiments of this application, two 200G data streams are distributed in blocks, cyclically shifted, and then encoded with internal codes. After interleaving bit pairs, they become a 400G data stream. The external codewords can be scattered into more internal codewords, which improves the ability of the concatenated code to resist colored noise, that is, improves the error correction performance of the overall concatenated FEC.

[0053] In one possible implementation, the outer code encoding can employ RS(544, 514) code. A specific implementation of the outer code encoding is provided, enabling this scheme to have good resistance to colored noise.

[0054] In one possible implementation, S = 4 or S = 8. A specific implementation of block distribution is provided, allowing for the adoption of a specific block distribution scheme according to requirements. Furthermore, the block distribution method described above enables this scheme to achieve good practical results.

[0055] In one possible implementation, the method further includes:

[0056] Before bit multiplexing the two sixth data streams, pad sequence insertion is performed on the two sixth data streams.

[0057] In one possible implementation, the pad sequence comprises f groups, each of the f groups comprising N bits, where f = S and N > 1.

[0058] In one possible implementation, each group includes a first part and a second part, the first part including at least one bit pair, and the sequence of the first parts of the f groups arranged in the order of the groups by bit pairs includes a frame-aligned sequence.

[0059] In one possible implementation, the second part includes a first sub-part and a second sub-part, the second sub-part being NK bit check information, and the first sub-part being a sequence including an all-zero sequence after scrambling.

[0060] In one possible implementation, the codeword length of the internal code encoding is N bits, where N = 128, and the information length of the codeword is 120 bits.

[0061] In one possible implementation, pad sequence insertion is performed on the sixth data stream, including:

[0062] The pad sequence is inserted after every H internal codewords in the sixth data stream;

[0063] Where f = 8, H = 8704, or f = 4, H = 4352.

[0064] In one possible implementation, S = 4, and the values ​​of pad_cw_i<127:116> for the f groups are:

[0065] Where 0≤i<4, pad_cw_i<127:116> represents bits 116 to 127 of group i in the f groups.

[0066] In one possible implementation, S = 8, and the values ​​of pad_cw_i<127:122> for the f groups are:

[0067] Where 0≤i<8, pad_cw_i<127:122> represents bits 122 to 127 of group i in the f groups.

[0068] In one possible implementation, each of the two sixth data streams contains α consecutive bit pairs that are consecutive in the seventh data stream, where α ≥ 1.

[0069] In one possible implementation,

[0070] α = β × S, where the consecutive β × S bit pairs in the sixth data stream are obtained by bit-pair interleaving of consecutive β bit pairs from each of the S third data streams; where β ≥ 1 and β is divisible by N / 2.

[0071] In one possible implementation, α = 1, 4, 8, 32, 64, 128, 256, or 512. Adopting these implementation methods facilitates hardware implementation and improves practical performance.

[0072] In one possible implementation, the method further includes:

[0073] The two fifth data streams are subjected to third data processing to obtain the two first data streams. The third data processing includes alignment flag locking. Both fifth data streams are encoded with external codes.

[0074] In one possible implementation, third data processing is performed on the two fifth data streams, including:

[0075] Symbol demultiplexing is performed on each of the two fifth data streams to obtain 2*t demultiplexed data streams. Each fifth data stream is demultiplexed into t demultiplexed data streams.

[0076] Alignment identifier locking is performed on the 2*t demultiplexed data streams respectively to obtain 2*t channel data streams with alignment identifier locking;

[0077] Deskipation processing is performed on 2*t channel data streams;

[0078] Symbol multiplexing is performed on each of the 2*t channel data streams after deskipation to obtain the two first data streams; wherein each t channel data stream comes from the same fifth data stream.

[0079] In a possible implementation, performing first data processing on two first data streams includes:

[0080] Performing the first data processing on each pair of the p obtained first data streams respectively, where p is an integer multiple of 2.

[0081] In a possible implementation, p = 8 or p = 16, and t = 2; the symbol demultiplexing adopts four-symbol demultiplexing, and the symbol multiplexing adopts four-symbol multiplexing.

[0082] In a possible implementation, p = 2 or p = 4, and t = 8; the symbol demultiplexing adopts symbol-pair demultiplexing, and the symbol multiplexing adopts symbol-pair multiplexing.

[0083] In a possible implementation, the method further includes:

[0084] Before performing symbol-pair multiplexing on every 2*t channel data streams after de-skewing processing, delaying the odd-channel data streams among the 2*t channel data streams after de-skewing processing by g symbols, where when p = 2, g = 69, or when p = 4, g = 1.

[0085] In a possible implementation, the skew between the start positions of the alignment flags of any two channel data streams among the 2*t channel data streams after de-skewing processing is D * 136 symbols, where D is an integer greater than or equal to 0. [[ID=१९]] [[ID=२०]]

[0086] In a possible implementation, the first data processing further includes convolutional interleaving.

[0087] In a possible implementation, the number of symbols for cyclic shift of the nth second data stream from different first data streams is the same, 0 ≤ n < S, and the number of symbols for cyclic shift of the S second data streams from the same first data stream is different.

[0088] In a possible implementation, the number of symbols for cyclic shift of any two of the 2*S second data streams is different, and S = 4. <아이디 =

[0089] [[ID=3०]]In a possible implementation, S = 8, α = S, and the cyclic shift of the 2*S second data streams adopts the method described in any row of the following table:

[0090] Among them, the second data stream m represents the mth data stream among the 16 second data streams, m = {0, 1, 2,..., 15}, the data c in the yth column represents that every consecutive 12 symbols in the corresponding second data stream m are right-cycled by c symbols, or the data c in the yth column represents that every consecutive 12 symbols in the corresponding second data stream m are left-cycled by 12 - c symbols, where 1 ≤ y ≤ 16.

[0091] In one possible implementation, S = 8, α = 1, and the cyclic shift of the 2*S second data streams is performed in the manner described in any row of the following table:

[0092] Wherein, the second data stream m represents the m-th data stream among 16 second data streams, m = {0, 1, 2, ..., 15}, and the data c in the y-th column represents the right circular shift of c symbols for every consecutive 12 symbols in the corresponding second data stream m, or the data c in the y-th column represents the left circular shift of 12-c symbols for every consecutive 12 symbols in the corresponding second data stream m, where 1 ≤ y ≤ 16.

[0093] In one possible implementation, S = 4, α = S, and the cyclic shift of the 2*S second data streams is performed in the manner described in any row of the following table:

[0094] Wherein, the second data stream m represents the m-th data stream among the 8 second data streams, m = {0, 1, 2, ..., 7}, and the data c in the y-th column represents the right circular shift of c symbols for every consecutive 12 symbols in the corresponding second data stream m, or the data c in the y-th column represents the left circular shift of 12-c symbols for every consecutive 12 symbols in the corresponding second data stream m, where 1 ≤ y ≤ 8.

[0095] In one possible implementation, S = 4, α = 1, and the cyclic shift of the 2*S second data streams is performed in the manner described in any row of the following table:

[0096] Wherein, the second data stream m represents the m-th data stream among the 8 second data streams, m = {0, 1, 2, ..., 7}, and the data c in the y-th column represents the right circular shift of c symbols for every consecutive 12 symbols in the corresponding second data stream m, or the data c in the y-th column represents the left circular shift of 12-c symbols for every consecutive 12 symbols in the corresponding second data stream m, where 1 ≤ y ≤ 8.

[0097] Thirdly, this application provides a data processing method, which can be implemented by a receiving device integrating the function of a receiving end processing module, or executed by the receiving end processing module.

[0098] In one possible implementation, the method includes: obtaining a fourth data stream, which is obtained by bit-pair interleaving 2*S third data streams, where S is an integer greater than 1; the 2*S third data streams are obtained by performing second data processing on 2*S second data streams respectively, the second data processing including internal code encoding and cyclic shifting; the 2*S second data streams are obtained by performing first data processing on 2 first data streams, where both first data streams are external code encoded; the first data processing includes block distribution, wherein each first data stream is block-distributed into S second data streams.

[0099] In one possible implementation, the method includes: demultiplexing a fourth data stream bit-to-bit to obtain 2*S third data streams; performing a second data inverse process on each of the 2*S third data streams to obtain 2*S second data streams; the second data inverse process includes internal code decoding and cyclic shifting; performing a first data inverse process on the 2*S second data streams to obtain 2 first data streams, wherein both first data streams are encoded with external codes, and the first data inverse process includes block merging, wherein every S second data stream blocks in the 2*S second data streams are merged into one first data stream.

[0100] In one possible implementation, S = 4 or S = 8.

[0101] In one possible implementation, the method further includes: deleting the pad sequence from the data stream that has been pad-inserted to obtain the fourth data stream.

[0102] In one possible implementation, the pad sequence comprises f groups, each of the f groups comprising N bits, where f = 2*S, and N > 1.

[0103] In one possible implementation, each group includes a first part and a second part, the first part including at least one bit pair, and the sequence of the first parts of the f groups arranged in the order of the groups by bit pairs includes a frame-aligned sequence.

[0104] In one possible implementation, the second part includes a first sub-part and a second sub-part, the second sub-part being NK bit check information, and the first sub-part being a scrambled sequence of all zeros.

[0105] In one possible implementation, the codeword length of the internal code decoding is N bits, where N = 128, and the information length of the codeword of the internal code decoding is 120 bits.

[0106] In one possible implementation, deleting the pad sequence from the data stream that has been padded includes:

[0107] Delete the pad sequence after every H internal codewords in the data stream inserted by pad;

[0108] Where f = 8, H = 8704, or f = 16, H = 17408.

[0109] In one possible implementation, S = 4, and the values ​​of pad_cw_i<127:122> for the f groups are:

[0110] Where 0≤i<8, pad_cw_i<127:122> represents bits 122 to 127 of group i in the f groups.

[0111] In one possible implementation, S = 8, and the pad_cw_i of the f groups <n-1:x>The value can be:

[0112] Where 0 ≤ i < 16, and when 0 ≤ i < 8, x = 124, and when 8 ≤ i < 16, x = 126, pad_cw_i <n-1:x>Denote bits x to bit N - 1 of packet i in f packets.

[0113] In a possible implementation, bit - pair demultiplexing of the fourth data stream includes:

[0114] Performing the bit - pair demultiplexing on p / 2 fourth data streams respectively, where p is an integer multiple of 2.

[0115] In a possible implementation, the second data inverse processing further includes convolutional de - interleaving.

[0116] In a possible implementation, the number of symbols of the cyclic shift of the n - th third data stream merged into different first data streams is the same, 0 ≤ n < S, and the number of symbols of the cyclic shift of the S third data streams merged into the same first data stream is different.

[0117] In a possible implementation, S = 4, and the number of symbols of the cyclic shift of any two of the 2*S third data streams is different.

[0118] In a possible implementation, S = 8, and the cyclic shift of the 2*S third data streams adopts the method described in any row of the following table:

[0119] Among them, the third data stream m represents the m - th data stream among 16 third data streams, m = {0, 1, 2, ……, 15}, the data c in the y - th column means that each consecutive 12 symbols in the corresponding third data stream m are circularly shifted to the left by c symbols, or the data c in the y - th column means that each consecutive 12 symbols in the corresponding third data stream m are circularly shifted to the right by 12 - c symbols, where 1 ≤ y ≤ 8.

[0120] In a possible implementation, S = 4, and the cyclic shift of the 2*S third data streams adopts the method described in any row of the following table:

[0121] Among them, the third data stream m represents the m - th data stream among 8 third data streams, m = {0, 1, 2, ……, 7}, the data c in the y - th column means that each consecutive 12 symbols in the corresponding third data stream m are circularly shifted to the left by c symbols, or the data c in the y - th column means that each consecutive 12 symbols in the corresponding third data stream m are circularly shifted to the right by 12 - c symbols, where 1 ≤ y ≤ 8.

[0122] Fourthly, an embodiment of the present application provides a data processing method, which can be implemented by a receiving - end device integrating the functions of a receiving - end processing module, or executed by a receiving - end processing module.

[0123] In one possible implementation, the method includes: receiving a seventh data stream, which is obtained by multiplexing two sixth data streams bit pairs, the two sixth data streams being obtained by interleaving two*S third data streams bit pairs, the two*S third data streams being obtained by performing second data processing on two*S second data streams respectively, the second data processing including cyclic shifting and internal code encoding, the two*S second data streams being obtained by performing first data processing on two first data streams respectively, the first data streams being external code encoded.

[0124] In another possible implementation, the method includes: demultiplexing the seventh data stream bit-to-bit to obtain two sixth data streams; deinterleaving the two sixth data streams bit-to-bit to obtain 2*S third data streams, each sixth data stream being deinterleaved into S third data streams; performing a second data processing inverse process on the 2*S third data streams to obtain 2*S second data streams, the second data inverse process including internal code decoding and cyclic shifting; performing a first data inverse process on the 2*S second data streams to obtain two first data streams; both first data streams are encoded using external codes, the first data inverse process including block merging, whereby the S second data streams from the same sixth data stream are quickly merged into one first data stream.

[0125] In one possible implementation, the external code encoding adopts RS(544, 514) code.

[0126] In one possible implementation, S = 4 or S = 8.

[0127] In one possible implementation, the method further includes: performing pad sequence deletion on the two sixth data streams before performing bit-pair deinterleaving on the two sixth data streams to obtain 2*S third data streams.

[0128] In one possible implementation, the pad sequence comprises f groups, each of the f groups comprising N bits, where f = S and N > 1.

[0129] In one possible implementation, each group includes a first part and a second part, the first part including at least one bit pair, and the sequence of the first parts of the f groups arranged in the order of the groups by bit pairs includes a frame-aligned sequence.

[0130] In one possible implementation, the second part includes a first sub-part and a second sub-part, the second sub-part being NK bit check information, and the first sub-part being a sequence including an all-zero sequence after scrambling.

[0131] In a possible implementation, the codeword length of the inner code encoding is N bits, N = 128, and the information length of the codeword of the inner code encoding is 120 bits.

[0132] In a possible implementation, deleting the pad sequence from the two sixth data streams includes:

[0133] Deleting the pad sequence after every H inner codewords in the sixth data stream;

[0134] where f = 8, H = 8704, or f = 4, H = 4352.

[0135] In a possible implementation, S = 4, and the values of pad_cw_i<127:116> of the f groups are:

[0136] where 0 ≤ i < 4, and pad_cw_i<127:116> represents bits 116 to 127 of group i in the f groups.

[0137] In a possible implementation, S = 8, and the values of pad_cw_i<127:122> of the f groups are:

[0138] where 0 ≤ i < 8, and pad_cw_i<127:122> represents bits 122 to 127 of group i in the f groups.

[0139] In a possible implementation, each consecutive α bits of the two sixth data streams are consecutive in the seventh data stream, α ≥ 1.

[0140] In a possible implementation,

[0141] α = β × S, and each consecutive β bits of the S third data streams are deinterleaved from the consecutive β × S bits of one sixth data stream; where β ≥ 1 and β is divisible by N / 2. <​​​​​​​​

[0145] In one possible implementation, the sign number of any two third data streams in the 2*S third data streams is different, and S = 4.

[0146] In one possible implementation, S = 8, α = S, and the cyclic shift of the 2*S third data streams is performed in the manner described in any row of the following table:

[0147] Wherein, the third data stream m represents the m-th data stream among 16 third data streams, m = {0, 1, 2, ..., 15}, and the data c in the y-th column represents the left circular shift of c symbols for every 12 consecutive symbols in the corresponding third data stream m, or the data c in the y-th column represents the right circular shift of 12-c symbols for every 12 consecutive symbols in the corresponding third data stream m, where 1 ≤ y ≤ 16.

[0148] In one possible implementation, S = 8, α = 1, and the cyclic shift of the 2*S third data streams is performed in the manner described in any row of the following table:

[0149] Wherein, the third data stream m represents the m-th data stream among 16 third data streams, m = {0, 1, 2, ..., 15}, and the data c in the y-th column represents the left circular shift of c symbols for every 12 consecutive symbols in the corresponding third data stream m, or the data c in the y-th column represents the right circular shift of 12-c symbols for every 12 consecutive symbols in the corresponding third data stream m, where 1 ≤ y ≤ 16.

[0150] In one possible implementation, S = 4, α = β × S, and the cyclic shift of the 2*S third data streams is performed in the manner described in any row of the following table:

[0151] Wherein, the third data stream m represents the m-th data stream among the 8 third data streams, m = {0, 1, 2, ..., 7}, and the data c in the y-th column represents the left circular shift of c symbols for every consecutive 12 symbols in the corresponding third data stream m, or the data c in the y-th column represents the right circular shift of 12-c symbols for every consecutive 12 symbols in the corresponding third data stream m, where 1 ≤ y ≤ 8.

[0152] In one possible implementation, S = 4, α = 1, and the cyclic shift of the 2*S third data streams is performed in the manner described in any row of the following table:

[0153] Wherein, the third data stream m represents the m-th data stream among the 8 third data streams, m = {0, 1, 2, ..., 7}, and the data c in the y-th column represents the left circular shift of c symbols for every consecutive 12 symbols in the corresponding third data stream m, or the data c in the y-th column represents the right circular shift of 12-c symbols for every consecutive 12 symbols in the corresponding third data stream m, where 1 ≤ y ≤ 8.

[0154] Fifthly, embodiments of this application provide a data processing apparatus, which includes modules or units for implementing the method described in the first aspect or any implementation thereof.

[0155] In one possible implementation, the device includes a first processing unit, a second processing unit, and a bit-pair interleaving unit. The first processing unit performs first data processing on two first data streams to obtain 2*S second data streams, where S is an integer greater than 1. Both first data streams are encoded using an outer code, and the first data processing includes block distribution, where each first data stream is distributed into S second data streams. The second processing unit performs second data processing on the 2*S second data streams to obtain 2*S third data streams, where the second data processing includes cyclic shifting and inner code encoding. The bit-pair interleaving unit interleaves the 2*S third data streams bit pairs into a fourth data stream.

[0156] Using the scheme provided in the embodiments of this application, two 200G data streams are distributed in blocks, cyclically shifted, and then encoded with internal codes. After interleaving bit pairs, they become a 400G data stream. The external codewords can be scattered into more internal codewords, which improves the ability of the concatenated code to resist colored noise, that is, improves the error correction performance of the overall concatenated FEC.

[0157] In one possible implementation, the outer code encoding can employ RS(544, 514) code. A specific implementation of the outer code encoding is provided, enabling this scheme to have good resistance to colored noise.

[0158] In one possible implementation, S = 4 or S = 8. A specific implementation of block distribution is provided, allowing for the adoption of a specific block distribution scheme according to requirements. Furthermore, the block distribution method described above enables this scheme to achieve good practical results.

[0159] One possible implementation also includes:

[0160] The pad insertion unit is used to perform pad sequence insertion on the fourth data stream to obtain a data stream with pad insertion.

[0161] In one possible implementation, the pad insertion unit is specifically used to: insert the pad sequence into the fourth data stream every H internal codewords; where f = 8, H = 8704, or f = 16, H = 17408. The above provides two possible pad insertion methods.

[0162] In one possible implementation, it further includes: a third processing unit, used to perform third data processing on the two fifth data streams to obtain the two first data streams, wherein the third data processing includes alignment flag locking; wherein the two fifth data streams are both encoded with external codes.

[0163] In one possible implementation, the third processing unit is specifically used for:

[0164] Symbol demultiplexing is performed on each of the two fifth data streams to obtain 2*t demultiplexed data streams. Each fifth data stream is demultiplexed into t demultiplexed data streams.

[0165] Alignment identifier locking is performed on the 2*t demultiplexed data streams respectively to obtain 2*t channel data streams with alignment identifier locking;

[0166] Deskipation processing is performed on 2*t channel data streams;

[0167] Symbol multiplexing is performed on each of the 2*t channel data streams after deskipation to obtain the two first data streams; wherein each t channel data stream comes from the same fifth data stream.

[0168] By employing the above scheme, aligning and locking before de-skewing can further improve the performance of concatenated codes.

[0169] In one possible implementation, the first processing unit is specifically used for:

[0170] The first data processing is performed on every two first data streams of the obtained p first data streams, where p is an integer multiple of 2.

[0171] The above solution enables this application to be applied to higher-speed transmission scenarios, such as 800G, 1.6T, and 3.2T.

[0172] In one possible implementation, the third processing unit is further configured to:

[0173] Before multiplexing the 2*t channel data streams after deskewing, delay the odd-numbered channel data streams by g symbols; when p=2, g=69, or when p=4, g=1.

[0174] For a description of the first, second, and third data processing steps mentioned above, please refer to the first aspect; they will not be repeated here.

[0175] In a sixth aspect, embodiments of this application provide a data processing apparatus, which includes modules or units for implementing the method described in the second aspect or any implementation thereof.

[0176] In one possible implementation, the device includes a first processing unit, a second processing unit, a bit-pair interleaving unit, and a bit-pair multiplexing unit. The first processing unit performs first data processing on two first data streams to obtain 2*S second data streams; where S is an integer greater than 1. All first data streams are encoded using an external code, and the first data processing includes block distribution, with each first data stream being distributed into S second data streams. The second processing unit performs second data processing on the 2*S second data streams respectively to obtain 2*S third data streams; the second data processing includes cyclic shifting and internal code encoding. The bit-pair interleaving unit interleaves the bit pairs of the 2*S third data streams into two sixth data streams. The bit-pair multiplexing unit multiplexes the bit pairs of the two sixth data streams into a seventh data stream.

[0177] In one possible implementation, it further includes a pad insertion unit for inserting a pad sequence into the two sixth data streams before bit multiplexing them.

[0178] In one possible implementation, the pad insertion unit is specifically used to: insert the pad sequence into the sixth data stream every H internal codewords;

[0179] Where f = 8, H = 8704, or f = 4, H = 4352.

[0180] In one possible implementation, a third processing unit is also included, for:

[0181] The two fifth data streams are subjected to third data processing to obtain the two first data streams. The third data processing includes alignment flag locking. Both fifth data streams are encoded with external codes.

[0182] In one possible implementation, the third processing unit is specifically used for:

[0183] Symbol demultiplexing is performed on each of the two fifth data streams to obtain 2*t demultiplexed data streams. Each fifth data stream is demultiplexed into t demultiplexed data streams.

[0184] Alignment identifier locking is performed on the 2*t demultiplexed data streams respectively to obtain 2*t channel data streams with alignment identifier locking;

[0185] Deskipation processing is performed on 2*t channel data streams;

[0186] Symbol multiplexing is performed on each t channel data stream in the 2*t channel data streams after deskipation to obtain the two first data streams; each t channel data stream comes from the same fifth data stream.

[0187] In one possible implementation, the first processing unit is specifically used to: perform the first data processing on every 2 first data streams of the obtained p first data streams, where p is an integer multiple of 2.

[0188] In one possible implementation, the third processing unit is further configured to:

[0189] Before multiplexing the 2*t channel data streams after deskewing, delay the odd-numbered channel data streams by g symbols, when p=2, g=69, or when p=4, g=1.

[0190] For descriptions of the first data processing, second data processing, third data processing, bit pair interleaving, bit pair multiplexing, etc., please refer to the first aspect, which will not be repeated here.

[0191] In a seventh aspect, this application provides a data processing apparatus, which includes modules or units for implementing the method described in the third aspect or any implementation thereof.

[0192] In one possible implementation, the apparatus includes: a bit-pair demultiplexing unit for demultiplexing a fourth data stream to obtain 2*S third data streams; a second inverse processing unit for performing second data inverse processing on each of the 2*S third data streams to obtain 2*S second data streams; the second data inverse processing includes internal code decoding and cyclic shifting; and a first inverse processing unit for performing first data inverse processing on the 2*S second data streams to obtain two first data streams, both of which are encoded using external codes, the first data inverse processing including block merging, wherein every S blocks of the 2*S second data streams are merged into one first data stream.

[0193] In one possible implementation, it further includes a pad sequence deletion unit for deleting the pad sequence in the data stream that has been inserted by pads to obtain the fourth data stream.

[0194] In one possible implementation, the pad sequence deletion unit is specifically used for:

[0195] Delete the pad sequence after every H internal codewords in the data stream inserted by pad;

[0196] Where f = 8, H = 8704, or f = 16, H = 17408.

[0197] In one possible implementation, the bit-pair demultiplexing unit is specifically used for:

[0198] The bit pairs are demultiplexed for each of the p / 2 fourth data streams, where p is an integer multiple of 2.

[0199] For a description of the first data inverse processing, the second data inverse processing, and bit pair demultiplexing, please refer to the third aspect, which will not be repeated here.

[0200] Eighthly, embodiments of this application provide a data processing apparatus, which includes modules or units for implementing the method described in the fourth aspect or any implementation thereof.

[0201] In one possible implementation, the device includes: a bit-to-demultiplexing unit for demultiplexing a seventh data stream to obtain two sixth data streams; a bit-to-deinterleaving unit for deinterleaving the two sixth data streams to obtain 2*S third data streams, each sixth data stream being deinterleaved into S third data streams; a second inverse processing unit for performing a second data processing inverse process on the 2*S third data streams to obtain 2*S second data streams, the second data inverse process including internal code decoding and cyclic shifting; and a first inverse processing unit for performing a first data inverse process on the 2*S second data streams to obtain two first data streams; both first data streams are encoded using an external code, the first data inverse process including block merging, whereby the S second data streams from the same sixth data stream are quickly merged into one first data stream.

[0202] In one possible implementation, it further includes a pad sequence deletion unit, used to perform pad sequence deletion on the two sixth data streams before performing bit pair deinterleaving on the two sixth data streams to obtain 2*S third data streams.

[0203] In one possible implementation, the pad sequence deletion unit is specifically used for:

[0204] Delete the pad sequence after every H internal codewords in the sixth data stream;

[0205] Where f = 8, H = 8704, or f = 4, H = 4352.

[0206] For a description of the first data inverse processing, the second data inverse processing, bit pair demultiplexing, and bit pair demultiplexing, please refer to the fourth aspect, which will not be repeated here.

[0207] Ninthly, a data processing apparatus is provided. This data processing apparatus can be a transmitting or receiving device in an optical communication network, or a part of a transmitting or receiving device (such as a circuit or chip). It includes a processor, a memory, and a communication interface, which are interconnected. The communication interface is used to receive and transmit data, the memory is used to store the aforementioned program, and the processor is used to call the program stored in the memory. When the program is executed by a computer, it causes the computer to execute the data processing method of the first aspect and any possible implementation thereof, or execute the data processing method of the second aspect and any possible implementation thereof, or execute the data processing method of the third aspect and any possible implementation thereof, or execute the data processing method of the fourth aspect and any possible implementation thereof. The processor and memory can be physically independent units, or the memory can be integrated with the processor.

[0208] In a tenth aspect, a computer-readable medium is provided, which stores instructions that, when executed on a computer, cause the computer to perform the data processing method of the first aspect and any possible implementation thereof, or to perform the data processing method of the second aspect and any possible implementation thereof, or to perform the data processing method of the third aspect and any possible implementation thereof, or to perform the data processing method of the fourth aspect and any possible implementation thereof.

[0209] Eleventhly, a computer program product is provided, comprising: computer program code, which, when executed on a computer, causes the computer to execute the data processing method in the first aspect and any possible implementation thereof, or to execute the data processing method in the second aspect and any possible implementation thereof, or to execute the data processing method in the third aspect and any possible implementation thereof, or to execute the data processing method in the fourth aspect and any possible implementation thereof.

[0210] In a twelfth aspect, a chip is provided, the chip being used to perform the data processing method provided by the first aspect or any alternative implementation thereof, or the data processing method of the second aspect and any possible implementation thereof, or the data processing method of the third aspect and any possible implementation thereof, or the data processing method of the fourth aspect and any possible implementation thereof.

[0211] In a thirteenth aspect, an optical module is provided, the optical module including a processor and an interface, the interface being used for transmitting and receiving signals, and the processor being used for executing a data processing method as provided in the first aspect or any optional implementation thereof, or a data processing method in the second aspect and any possible implementation thereof, or a data processing method in the third aspect and any possible implementation thereof, or a data processing method in the fourth aspect and any possible implementation thereof.

[0212] In a fourteenth aspect, a network device is provided, the network device comprising a host-side device and the optical module described in the thirteenth aspect; the optical module is configured to convert an electrical signal from the host-side device into an optical signal and transmit the optical signal, or the optical module is configured to convert a received optical signal into an electrical signal and transmit the electrical signal to the host-side device.

[0213] In a fifteenth aspect, a communication system is provided, comprising a plurality of network devices as described in the fourteenth aspect, wherein the plurality of network devices are configured to transmit optical signals to each other. Attached Figure Description

[0214] Figure 1 is a schematic diagram of a communication system applied in an embodiment of this application;

[0215] Figure 2 is a schematic diagram of a data transmission process in the communication system shown in Figure 1;

[0216] Figure 3 is a schematic diagram of another communication system applied in the embodiments of this application;

[0217] Figures 4A and 4B are schematic flowcharts of the first data processing method provided in the embodiments of this application;

[0218] Figure 5A is a schematic diagram of the first structure of convolutional interleaving processing in an embodiment of this application;

[0219] Figure 5B is a schematic diagram of the second structure of convolutional interleaving in an embodiment of this application;

[0220] Figure 6 is a schematic diagram of the block distribution method provided in an embodiment of this application;

[0221] Figure 7A is a schematic diagram of a processing scheme provided by an embodiment of this application, which involves first performing cyclic shifting and then encoding the internal code.

[0222] Figure 7B is a schematic diagram of a processing scheme provided in an embodiment of this application, which involves first encoding the internal code and then performing cyclic shifting.

[0223] Figure 8A is a schematic diagram of a cyclic shift implementation method provided in an embodiment of this application;

[0224] Figure 8B is a schematic diagram of another implementation of cyclic shifting provided in the embodiments of this application;

[0225] Figure 8C is a schematic diagram of another implementation of cyclic shifting provided in the embodiments of this application;

[0226] Figure 8D is a schematic diagram of another implementation of cyclic shifting provided in the embodiments of this application;

[0227] Figure 9 is a schematic diagram of a bit pair interleaving implementation method provided in an embodiment of this application;

[0228] Figure 10 is a schematic diagram of a pad sequence generation method provided in an embodiment of this application;

[0229] Figure 11 is a schematic diagram of pad sequence insertion provided in an embodiment of this application;

[0230] Figures 12A and 12B are schematic flowcharts of the first data processing method provided in the embodiments of this application;

[0231] Figure 13 is a schematic diagram of a bit pair multiplexing implementation method provided in an embodiment of this application;

[0232] Figure 14A is a schematic diagram of a third data processing flow provided in an embodiment of this application;

[0233] Figure 14B is a schematic diagram of another third data processing flow provided in an embodiment of this application;

[0234] Figure 14C is a schematic diagram of another third data processing flow provided in an embodiment of this application;

[0235] Figure 14D is a schematic diagram of another third data processing flow provided in an embodiment of this application;

[0236] Figure 14E is a schematic diagram of another third data processing flow provided in an embodiment of this application;

[0237] Figure 14F is a schematic diagram of another third data processing flow provided in an embodiment of this application;

[0238] Figure 15 is a schematic flowchart of another data processing method according to an embodiment of this application;

[0239] Figure 16 is a schematic flowchart of another data processing method according to an embodiment of this application;

[0240] Figure 17 is a schematic diagram of a data processing device provided in an embodiment of this application;

[0241] Figure 18 is a schematic diagram of a data processing device provided in an embodiment of this application;

[0242] Figure 19 is a schematic diagram of a data processing device provided in an embodiment of this application;

[0243] Figure 20 is a schematic diagram of a data processing device provided in an embodiment of this application;

[0244] Figure 21 is a schematic diagram of a structure of an optical module in an embodiment of this application;

[0245] Figure 22 is a schematic diagram of a communication device in an embodiment of this application. Detailed Implementation

[0246] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0247] It should be noted that the terms "first," "second," etc., in this application specification, claims, and the accompanying drawings are used to distinguish similar objects, not to limit a specific order or sequence. It should be understood that the above terms can be interchanged where appropriate so that the embodiments described in this application can be implemented in a sequence other than that described in this application. In this application, the multiplication sign can be represented by "*" or "×". Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices.

[0248] Figure 1 is a schematic diagram of a communication system applied in an embodiment of this application. As shown in Figure 1, the communication system includes a transmitting device 01, a transmitting processing module 02, a channel transmission medium 03, a receiving processing module 04, and a receiving device 05. Taking a data center network as an example, the transmitting device 01 and the receiving device 05 can be devices such as switches, routers, or servers. The transmitting device 01 is also called a client device located at the transmitting end, and the receiving device 05 is also called a client device located at the receiving end. The channel transmission medium 03 can be an optical fiber. The client device is sometimes also called a host device. The client device includes a client chip and an interface. The client chip is also called a host chip. The connection interface between the transmitting device 01 and the transmitting processing module 02 can be connected through an attachment unit interface (AUI), and the connection interface between the receiving device 05 and the receiving processing module 04 can be connected through an AUI. The transmitting end processing module 02 and the receiving end processing module 04 can be optical modules, electrical modules, connectors, or other modules that process data during data transmission. For example, the processing module can be a DR optical module, FR optical module, or LR optical module. The optical module can be an 800G optical module, a 400G optical module, or a 200G optical module.

[0249] Examples include 800G FR4 optical modules, 800G LR4 optical modules, 800G DR4-2 optical modules, 400G FR2 optical modules, 400G LR2 optical modules, 400G DR2-2 optical modules, 200G LR1 optical modules, 200G DR1-2 optical modules, and 200G FR1 optical modules. Of course, it can also be an optical module supporting higher speeds, or other types of optical modules; this application does not limit this. Furthermore, the transmitting device 01, transmitting processing module 02, channel transmission medium 03, receiving processing module 04, and receiving device 05 in this communication system can all support bidirectional transmission or unidirectional transmission; specific details are not limited here.

[0250] Figure 2 is a schematic diagram of a data transmission process in the communication system shown in Figure 1. As shown in Figure 2, during the data transmission process from the transmitting device 01 to the receiving device 05, the transmitting device 01 performs external code encoding on the data and then transmits the externally encoded data to the transmitting processing module 02. The transmitting processing module 02 performs internal code encoding on the externally encoded data to obtain data with both external and internal code encoding, and transmits the data with both external and internal code encoding to the channel transmission medium 03. The channel transmission medium 03 transmits the data with both external and internal code encoding to the receiving processing module 04. The receiving processing module 04 performs internal code decoding on the data with both external and internal code encoding and transmits the internally decoded data to the receiving device 05. The receiving device 05 performs external code decoding on the data with internal code decoding.

[0251] It should be understood that the distinction between "internal" in internal code and "external" in external code is based solely on the distance between the entity performing the data operation and the channel transmission medium 03. The entity operating on the internal code is closer to the channel transmission medium, while the entity operating on the external code is farther away. In this embodiment, after data is sent from the transmitting device 01, it is transmitted to the channel transmission medium 03 via the transmitting processing module 02, and then from the channel transmission medium 03 via the receiving processing module 04 to the receiving device 05. The data encoded by the transmitting device 01 is farther from the channel transmission medium 03 than the data encoded by the transmitting processing module 02, and the data decoded by the receiving device 05 is farther from the channel transmission medium 03 than the data decoded by the receiving processing module 04. Therefore, the data encoded by the transmitting device 01 is called data encoded with external code, the data encoded by the transmitting processing module 02 is called data encoded with internal code, the data decoded by the receiving device 05 is called data decoded with external code, and the data decoded by the receiving processing module 04 is called data decoded with internal code. In one possible implementation, both the internal and external encoding methods described above employ FEC encoding, thus forming a cascaded FEC transmission scheme. For example, the transmitting device 01 can use Reed-Solomon (RS) code for external encoding, and the transmitting processing module 02 can use Hamming code for internal encoding. Alternatively, the transmitting device 01 can use RS code for external encoding, and the transmitting processing module 02 can use Bose-Chaudhuri-Hocquenghem (BCH) code for internal encoding. A BCH code correcting a single error is equivalent to a Hamming code. Another example is that the transmitting device 01 can use RS code for external encoding, and the transmitting processing module 02 can also use Polar code for internal encoding. In some specific application scenarios, the transmitting device 01 can use RS(544,514) code, also known as KP4 code, for external encoding.

[0252] Figure 3 is a schematic diagram of another communication system applied in an embodiment of this application. As shown in Figure 3, the communication system includes a transmitting device 01, a channel transmission medium 03, and a receiving device 05. The transmitting device 01 performs external code encoding and internal code encoding on the data. The data after external code encoding and internal code encoding is sent to the channel transmission medium 03. The receiving device 05 decodes the internal code and external code of the data received from the channel transmission medium 03. Taking a data center network as an example, the transmitting device 01 and the receiving device 05 can be devices such as switches, routers, or servers. The transmitting device 01 is also called a client device or host device located at the transmitting end, and the receiving device 05 is also called a client chip located at the receiving end. The channel transmission medium 03 can be an optical fiber. The client device includes a client chip and an interface. The client chip is also called a host chip. The transmitting device 01, the channel transmission medium 03, and the receiving device 05 in this communication system can all support bidirectional transmission or unidirectional transmission, which is not limited here. In other words, the transmitting device 01 shown in Figure 3 also integrates the functions of the transmitting processing module 02 shown in Figure 2, and the receiving device 05 shown in Figure 3 also integrates the functions of the receiving processing module 04 shown in Figure 2. In this case, the transmitting device 01 can also employ linear pluggable optics (LPO), co-packaged optics (CPO), or near packaged optics (NPO) technology.

[0253] It should also be noted that the above content is an exemplary description of the application scenarios of the data processing method provided in the embodiments of this application, and does not constitute a limitation on the application scenarios of the data processing method. As those skilled in the art will know, as business needs change, the application scenarios can be adjusted according to the application needs, and the embodiments of this application do not list them one by one.

[0254] The aforementioned transmission scheme employing cascaded FEC currently only addresses 200G / lane transmission scenarios. For higher-speed transmission scenarios, such as 400G / lane or even higher, the current cascaded FEC scheme for 200G / lane cannot be directly applied to 400G / lane transmission scenarios. Therefore, developing a low-latency, high-performance coding scheme for transmission scenarios of 400G / lane or higher is an urgent problem to be solved.

[0255] This application designs a data processing scheme including bit-pair interleaving to achieve better overall performance and lower latency in the cascaded FEC scheme. The data processing is implemented through the aforementioned sending-end processing module 02.

[0256] The data processing scheme provided in the embodiments of this application will be described in detail below.

[0257] Figures 4A and 4B show schematic diagrams of the first data processing method provided in this application embodiment. As shown in Figures 4A and 4B, the sending processing module performs first data processing on every two data streams in the p-th data streams that have already been encoded with external codes. The following example uses two first data streams. The first data processing includes block distribution. In some possible implementation scenarios, the first data processing may also include convolutional interleaving. For ease of explanation, the following description uses RS(544,514) code as the external code encoding example. In practical applications, other encoding methods can also be used for external code encoding. RS code can also be called RS FEC code.

[0258] S401, perform first data processing on the two first data streams respectively to obtain 2*S second data streams. The first data processing includes block distribution, whereby each first data stream is distributed into S second data streams. The first data streams are encoded using RS-FEC, and each first data stream contains four consecutive RS-FEC symbols derived from four RS-FEC codewords. These four consecutive RS-FEC symbols are referred to as an RS-FEC 4-symbol quartet.

[0259] S402, perform second data processing on the 2*S second data streams respectively to obtain 2*S third data streams. The second data processing includes cyclic shifting and internal code encoding.

[0260] Considering that the length of the information data encoded by the internal code is K bits, that is, K information bits in the second data stream are encoded by the internal code to generate P' check bits, thus obtaining an internal codeword including N = K + P' bits, where 1 < K < N, P' > 0, K > 0. To achieve optimal performance of the concatenated code, and taking RS(544, 514) as an example for the external code encoding, K can be set to an integer multiple of 10, that is, K is an integer multiple of the length of the external codeword. Furthermore, by adding interleaving processing between the internal code encodings, the K information bits of each internal codeword correspond to K / 10 external code RS FEC symbols, that is, one symbol is taken from each of the K / 10 external code RS FEC symbols to form the information data of an internal code. For example, the internal code uses BCH(126,110), where K = 110 information bits in each internal codeword correspond to K / 10 = 11 external code symbols, and these K / 10 = 11 external code symbols come from K / 10 = 11 external codewords (RS). Another example is a linear block code with N = 128 and K = 120, where K = 120 information bits in each internal codeword correspond to K / 10 = 12 external code symbols, and these K / 10 = 12 external code symbols come from K / 10 = 12 different external codewords (RS).

[0261] S403, interleave the 2*S third data stream bit pairs into a fourth data stream.

[0262] In some embodiments, the first data processing method executed by the originating processing module may further include pad sequence insertion. That is, in S404, pad sequence insertion is performed on the fourth data stream to obtain a pad-inserted data stream.

[0263] To ensure that the K information bits in each internal codeword correspond to K / 10 different external codewords (RS codewords) and simultaneously improve tolerance to colored noise, this embodiment of the application performs 1:S block distribution on each of the two first data streams to obtain S second data streams, resulting in a total of f = 2 × S second data streams. Figure 4B shows two first data streams, first data stream 0 and first data stream 1, as an example. The 1:S processing involved in this embodiment refers to inputting one data stream and outputting S data streams. The second data stream can also be called the distribution data stream, or other names can be used; this embodiment of the application does not limit this. Then, each consecutive K bits of data in each second data stream undergoes second data processing including cyclic shifting and internal code encoding to obtain an internal codeword of N bits, thus obtaining f third data streams. The third data stream can also be called the internal code data stream, or other names can be used; this embodiment of the application does not limit this. Furthermore, the f third data streams are bit-pair interleaved to obtain a fourth data stream. The fourth data stream can also be called an interleaved data stream, or other names may be used; this application does not limit this. Finally, a pad sequence is inserted into the fourth data stream to obtain a pad-inserted data stream.

[0264] In one possible implementation, the first data processing may further include convolutional interleaving (or convolutional interleaving processing). Referring to Figure 4B, convolutional interleaving can be performed in block processing. Each of the two first data streams is subjected to convolutional interleaving to obtain two convolutionally interleaved data streams. Then, the two convolutionally interleaved data streams are distributed in a 1:S block ratio to obtain S second data streams, resulting in a total of f = 2 × S second data streams.

[0265] The specific implementation of each of the above processes is described in detail below.

[0266] Convolutional interleaving:

[0267] The convolutional interleaver for the convolutional interleaving process includes r delay lines, each with a different number of storage units. The delay line with the fewest storage units has 0 storage units. The difference in the number of storage units between any two adjacent delay lines is Q, where r is an integer greater than 1 and Q is an integer greater than or equal to 1. Each storage unit stores d bits, where d is an integer greater than or equal to 1. Bits from the input data stream of the convolutional interleaver are sequentially input to the r delay lines according to their indices. Each input consists of d bits to and from each delay line at a time. In some specific applications, d bits are input to the convolutional interleaver at a time, and these d bits are input to one delay line of the convolutional interleaver. In other specific applications, r × d bits are input to the convolutional interleaver at a time, and these r × d bits are input to the r delay lines of the convolutional interleaver. The data input to each delay line consists of d consecutive bits from the r × d bits. The continuous r×d bits in the data stream output by the convolutional interleaver include the d bits output by each delay line.

[0268] It should be understood that the r delay lines each comprise 0, Q, 2×Q, ..., (r-1)×Q storage units, with each storage unit storing d bits. The r delay lines correspond to r delay values, which include 0 bits, Q×d bits, 2×Q×d bits, ..., (r-1)×Q×d bits. The more bits a delay line includes in its delay values, the longer the delay (also called latency) to the data stream. It should be understood that when a delay line contains no storage units, its delay is 0 bits, which is called zero-latency pass-through. It should be understood that the aforementioned storage units are also called delay elements.

[0269] Figure 5A is a schematic diagram of the first structure of convolutional interleaving in this embodiment. As shown in Figure 5A, the number of storage units in the r delay lines decreases sequentially according to the sequence number of the r delay lines. That is, delay line 0 has (r-1)Q storage units, each delay line decreases by Q storage units sequentially, and delay line r-1 has 0 storage units. Figure 5B is a schematic diagram of the second structure of convolutional interleaving in this embodiment. As shown in Figure 5B, the number of storage units in the r delay lines increases sequentially according to the sequence number of the r delay lines. That is, delay line 0 has 0 storage units, each delay line increases by Q storage units sequentially, and delay line r-1 has (r-1)Q storage units. In Figures 5A and 5B, the boxes with 'd' represent delay units with a delay of 'd' bits. It should be understood that in the convolutional interleaver shown in Figure 5A, delay line 0 delays the input data by (r-1)×Q×d bits, delay line 1 delays the input data by (r-2)×Q×d bits, and so on, with delay line r-2 delaying the input data by Q×d bits, while delay line r-1 does not delay the input data. Similarly, in the convolutional interleaver shown in Figure 5B, delay line 0 does not delay the input data, delay line 1 delays the input data by Q×d bits, and so on, with delay line r-2 delaying the input data by (r-1)×Q×d bits, and delay line r-1 delaying the input data by (r-1)×Q×d bits.

[0270] It should be noted that at any given moment, the input and output switches of the convolutional interleaver are located on the same delay line. After the current delay line receives and outputs d bits in a single input, the switch is switched to the next delay line. This ensures that the bits in the input data stream are sequentially input to the r delay lines according to their sequence numbers, and that the consecutive r×d bits in the output data stream include the d bits output from each delay line. The specific data read / write operations are as follows: d bits are read from the memory cell closest to the output port of the current delay line; the d bits stored in each memory cell of the current delay line are transferred to the next memory cell; then, d bits are written to the memory cell closest to the input port of the current delay line. Afterward, the switch is moved to the next delay line, and the above operations are repeated, and so on.

[0271] It should be understood that when the same parameters r, Q, and d are used, the convolutional interleaving process in Figure 5A and the convolutional interleaving process in Figure 5B are the inverse operations of each other. That is, when the sending-end processing module uses the convolutional interleaving structure shown in Figure 5A, the corresponding convolutional deinterleaving in its receiving-end processing module uses the structure shown in Figure 5B. Similarly, when the sending-end processing module uses the convolutional interleaving structure shown in Figure 5B, the corresponding convolutional deinterleaving in its receiving-end processing module uses the structure shown in Figure 5A.

[0272] Since four consecutive RS FEC symbols in the first data stream come from four RS FEC codewords, to reduce the latency of the convolutional interleaver, the typical number of delay lines r = 3, and the number of bits stored in each storage unit d = a × 10 = 40. That is, the 40 bits stored in each storage unit come from 40 consecutive bits in a second data stream, corresponding to four RS FEC symbols. These four RS FEC symbols, coming from four RS FEC codewords, are called an RS FEC quartet. An RS FEC quartet can also be called an RS FEC 4-symbol, RS FEC quartet, or RS-FEC quartet, or simply 4-symbol or quartet. With a suitable Q value, twelve consecutive RS FEC symbols in the convolutional interleaver stream can come from twelve RS FEC codewords.

[0273] Block distribution processing:

[0274] Figure 6 is a schematic diagram of the block distribution method provided in the embodiment of this application. It can be understood that one implementation of the block distribution processing in Figure 4B, as shown in Figure 6, performs a 1:S block distribution on each convolutional interleaved stream to obtain S second data streams. Specifically, it adopts a round-robin method, distributing 3 consecutive RS FEC 4-symbol quartets at a time. That is, distributing 12 consecutive RS FEC symbols each time. Figure 6A... i B i C i Three consecutive RS FEC quad symbols in the convolutionally interleaved data stream k are output from the three delay lines of the convolutional interleaver. During block distribution, these three RS FEC quad symbols, totaling 12 RS symbols, are distributed to a second data stream. As shown in Figure 6, A0, B0, and C0 are distributed to second data stream 0, A1, B1, and C1 to second data stream 1, A2, B2, and C2 to second data stream 2, and so on. s-1 B s-1 C s-1 Distribute to the second data stream S-1. Where S = 4 or S = 8, i ≥ 0.

[0275] Circular shift and internal code encoding processing:

[0276] One implementation of the cyclic shift and internal code encoding process in Figure 4B involves performing cyclic shift first, followed by internal code encoding. Specifically, for every K / 10 consecutive RS symbols in each second data stream, a left cyclic shift of δ symbols or a right cyclic shift of Δ symbols is performed. Then, the K / 10 RS FEC symbols after the shift are encoded using internal code, and NK bits of check information are added to obtain an internal codeword with a code length of N bits. Taking K=120 and N=128 as an example, Figure 7A shows a processing scheme that involves performing cyclic shift first and then internal code encoding. In Figure 7A, the 12 RS FEC symbols are right-circularly shifted by Δ RS FEC symbols, that is, the i-th RS FEC symbol is right-circularly shifted to the (i+Δ)%12th symbol; or the 12 symbols are left-circularly shifted by δ RS FEC symbols, that is, the i-th RS FEC symbol is left-circularly shifted to the (i+12-δ)%12th symbol, where 0≤i<12, 0≤δ<12, 0≤Δ<12. The scheme shown in Figure 7A can represent a right-circular shift Δ=4 or a left-circular shift δ=8.

[0277] Another implementation of the cyclic shift and internal code encoding process in Figure 4B involves performing internal code encoding first, followed by cyclic shift. Specifically, for each second data stream, internal code encoding is performed on every K / 10 consecutive RS FEC symbols, adding NK bits of check information to obtain an internal codeword with a code length of N bits. Then, cyclic shift is performed on K / 10 RS FEC symbols of the information data in each internal codeword, while the check data remains unchanged. For example, K / 10 RS FEC symbols of the information data can be cyclically shifted left by δ symbols or cyclically shifted right by Δ symbols. A left cyclic shift of δ symbols can also be described as a left cyclic shift of δ symbols. A right cyclic shift of Δ symbols can also be described as a right cyclic shift of Δ symbols. Taking K=120 and N=128 as an example, Figure 7B shows one processing scheme corresponding to internal code encoding followed by cyclic shift. In Figure 7B, the 12 RS FEC symbols are cyclically shifted right by Δ RS FEC symbols, that is, the i-th RS FEC symbol is cyclically shifted right to the (i+Δ)%12th symbol; or the 12 symbols are cyclically shifted left by δ RS FEC symbols, that is, the i-th RS FEC symbol is cyclically shifted left to the (i+12-δ)%12th symbol, where 0≤i<12, 0≤δ<12, 0≤Δ<12. The scheme shown in Figure 7A can represent a right cyclic shift of Δ=4 or a left cyclic shift of δ=8. Figure 7A only uses Δ=4 or δ=8 as examples and does not specify the values ​​of Δ and δ. It should be noted that, in order to improve the burst resistance of the concatenated code, the number of symbols δ and Δ for the cyclic shift corresponding to each second data stream may be different.

[0278] It should be understood that when the cyclic shift in the transmitting end processing module is a left cyclic shift of δ symbols, the corresponding reverse operation in the receiving end processing module is a right cyclic shift of δ symbols; when the cyclic shift in the transmitting end processing module is a right cyclic shift of Δ symbols, the corresponding reverse operation in the receiving end processing module is a left cyclic shift of Δ symbols.

[0279] In some embodiments, the number of symbols for cyclic shift of the nth second data stream from different first data streams is the same, where 0 ≤ n < S, and the number of symbols for cyclic shift of the S second data streams from the same first data stream is different. Specifically, for example, in FIG. 4B, the first data stream 0 distributes to obtain S second data streams denoted as the second data stream 0 to the second data stream S - 1, and the first data stream 1 distributes to obtain S second data streams denoted as the second data stream S to the second data stream 2×S - 1. Then, the number of symbols for cyclic shift of any two data streams among the second data stream 0 to the second data stream S - 1 is different; the number of symbols for cyclic shift of any two second data streams among the second data stream S to the second data stream 2×S - 1 is different; the number of cyclic shifts of the second data stream n and the second data stream S + n is the same. Through cyclic shift and subsequent bit pair interleaving processing, multiple consecutive PAM4 symbol errors introduced in channel transmission can be dispersed to multiple inner code words and multiple RS code words, improving the burst resistance performance of the concatenated code.

[0280] In some other embodiments, the number of symbols for cyclic shift of the 2*S second data streams from two data streams is different, for example, S = 4.

[0281] In some other embodiments, the number of symbols for cyclic shift of the S second data streams from the same first data stream is different. It can make at least S symbols separate between two bit pairs from the same RS code word in the fourth data stream, improving the burst resistance performance of the concatenated code.

[0282] As an example, when S = 8, the cyclic shift of the 2*S second data streams can adopt any one of the ways 1 to 17 in Table 1 below. It should be noted that Table 1 is only for example and does not constitute a specific limitation on the way of cyclic shift. By adopting the example way of cyclic shift, it can make at least 8 symbols separate between two bit pairs from the same RS code word in the fourth data stream, improving the burst resistance performance of the concatenated code.

[0283] Table 1<00006​​​Among them, the second data stream m represents the m-th data stream among 16 second data streams, m = {0, 1, 2,..., 15}, and the data c in the y-th column represents that each consecutive 12 symbols in the corresponding second data stream m are circularly shifted to the right by c symbols. Here, 1 ≤ y ≤ 16, which can also be understood as each consecutive 12 symbols in the corresponding second data stream m are circularly shifted to the left by 12 - c symbols. The above-mentioned y-th column represents a data column, and the value of y satisfies 1 ≤ y ≤ 16, excluding the column of the mode names corresponding to Modes 1 - Mode 17.

[0285] As another example, S = 4, and the circular shift of the 2*S (8) second data streams adopts any one of Modes 1 to Mode 6 in Table 2 below:

[0286] Table 2

[0287] Among them, the second data stream m represents the m-th data stream among 8 second data streams, m = {0, 1, 2,..., 7}, and the data c in the y-th column represents that each consecutive 12 symbols in the corresponding second data stream m are circularly shifted to the right by c symbols, which can also be understood as each consecutive 12 symbols in the corresponding second data stream m are circularly shifted to the left by 12 - c symbols, where 1 ≤ y ≤ 8. The above-mentioned y-th column represents a data column, and the value of y satisfies 1 ≤ y ≤ 8, excluding the column of the mode names corresponding to Modes 1 - Mode 6.

[0288] The implementation method of the circular shift corresponding to Mode 1 in Table 1 above can be seen in Figure 8A. Figure 8A satisfies that the number of symbols circularly shifted for the n-th second data stream from different first data streams is the same, 0 ≤ n < S, and the number of symbols circularly shifted for the S second data streams from the same first data stream is different. That is, the number of symbols circularly shifted for the second data stream n and the second data stream n + 8 is the same, and the number of symbols circularly shifted for the second data streams from 0 to 7 is different from each other, and the number of symbols circularly shifted for the second data streams from 8 to 15 is different from each other. Among them, CS(a) in Figure 8A represents a circular shift to the right by a RS FEC symbols (or simply referred to as RS symbols), 0 ≤ i < 8. The second data streams from 0 to 7 are 8 second data streams obtained by 1:8 block distribution of the convolutional interleaved data stream 0, and the second data streams from 8 to 15 are 8 second data streams obtained by 1:8 block distribution of the convolutional interleaved data stream 1. Adopting the above Mode 1 can enable the concatenated code to have better ability to resist colored noise.

[0289] For the method 2 in Table 1 above, the implementation of the cyclic shift corresponding to the 16 second data streams can be seen in Figure 8B. Figure 8B satisfies that the number of symbols of the cyclic shift of 8 second data streams from the same first data stream is different. The number of symbols of the cyclic shift of some second data streams from different first data streams is different, and the number of symbols of the cyclic shift of some other second data streams is the same. When 0 ≤ i < 4, the number of symbols of the cyclic shift of the second data stream i and the second data stream i + 8 is the same. When 4 ≤ i < 8, the number of symbols of the cyclic shift of the second data stream i and the second data stream i + 8 is different. The number of symbols of the cyclic shift of the second data stream 0 to the second data stream 7 is different from each other, and the number of symbols of the cyclic shift of the second data stream 8 to the second data stream 15 is different. Among them, CS(a) in Figure 8B represents a right cyclic shift of a RS FEC symbols.

[0290] As an example, when S = 4, for the method 1 in Table 2 above, the implementation of the cyclic shift corresponding to the 8 second data streams can be seen in Figure 8C. Figure 8C satisfies that the number of symbols of the cyclic shift of 2*S second data streams from two data streams are all different. Among them, CS(a) in Figure 8C represents a right cyclic shift of a RS FEC symbols.

[0291] As an example, when S = 4, for the method 3 in Table 2 above, the implementation of the cyclic shift corresponding to the 8 second data streams can be seen in Figure 8D. Figure 8D satisfies that the number of symbols of the cyclic shift of 2*S second data streams from two data streams are all different. Among them, CS(a) in Figure 8D represents a right cyclic shift of a RS FEC symbols.

[0292] Bit pair interleaving processing:

[0293] Perform bit pair interleaving on f = 2*S third data streams to obtain an interleaved data stream. Bit pair interleaving can also be called bit pair multiplexing. Specifically, obtain an inner code word from each third data stream, use to represent the bit pair composed of the 2i-th bit and the 2i + 1-th bit of the inner code word in the third data stream j, and then poll in the order from the third data stream 0 to the third data stream f - 1, and read a bit pair from each inner code word into the fourth data stream, where 0 ≤ j < f, 0 ≤ i < N / 2. Figure 9 shows the implementation scheme of bit pair interleaving. First, read the bit pair from the third data stream 0, then read the bit pair from the third data stream 1, …, then read the bit pair from the third data stream f - 1, and then read the bit pair from the third data stream 0 again, and poll in this way.

[0294] Pad sequence insertion:

[0295] In one possible implementation, the pad sequence may include f blocks. Each of the f blocks comprises N bits, which is an internal codeword. This can be represented by pad_cw_i. <n-1:0>This represents the i-th group of the pad sequence, which can also represent group i. Alternatively, the pad sequence can be understood as consisting of f × N bits. Each group can include a first part and a second part. The first part includes at least one bit pair. The sequence of the first parts of the f groups, arranged in bit pairs according to the group order, includes the frame-aligned sequence, where f = 2 * S. The second part can include a first sub-part and a second sub-part. The second sub-part includes NK bit check information, and the first sub-part includes the scrambled sequence of all zeros. For example, scrambling can use a pseudo-random binary sequence 13 (PRBS13).

[0296] It is understandable that an f×N bit pad sequence can be obtained by encoding and interleaving f×K bit data pads (or information pads) using the aforementioned internal code encoding. f×K bits can also be described as f×K data bits or information bits. Further, each of the f groups can include K information bits and NK parity bits (i.e., NK bit check information). In some implementations, the f groups in the pad sequence can also be described as f pad codewords. Each pad codeword can also be understood as an internal codeword. The K information bits in each internal codeword include the first part and the first sub-part of the second part. The sequence of the first parts of the f groups, arranged in bit pairs according to the group order, includes the frame-aligned sequence.

[0297] Another possible implementation is to group the f×K bit data pads in the pad sequence. For example, Figure 10 shows how the pad sequence is generated, where the f×K bit data pad is divided into f groups, each group consisting of K bits. For instance, using m_i... <k-1:0>Let represent the i-th group of the data pad. The i-th group can also represent group i. The i-th group of the data pad includes the first part. Encode each group of the data pad with its internal code to obtain NK bits of check information, resulting in an N-bit internal codeword called the pad codeword, denoted as pad_cw_i. <n-1:0>pad_cw_i <n-1:0>Bit N-1 in the data is pad_cw_i <n-1>For the bits transmitted first, pad_cw_i <n-1:0>Bit 0 in pad_cw_i <n-1>For the bits to be transmitted later, 0 ≤ i < f. Therefore, a pad sequence includes f inner code codewords, or f pad codewords. Then, the f pad codewords are interleaved by bit pairs as shown in Figure 9 to obtain an f×N-bit pad sequence, denoted as pad<f×N-1:0>. Among them, the pad<f×N-1:f×N-L> of L bits in the pad sequence is the Frame Alignment Sequence. For example, L = 48. It can also be understood that the sequence obtained by arranging the first parts of the f groups of data pads in order by bit pairs includes the frame alignment sequence. Or, the first parts of the f groups of data pads are interleaved by bit pairs as shown in Figure 9 to obtain the frame alignment sequence.

[0298] In some embodiments, when inserting a pad sequence into the fourth data stream, a pad sequence can be inserted every H inner code codewords in the fourth data stream. Or, a pad sequence is inserted after every consecutive H inner code codewords. In some embodiments, a pad sequence is also inserted before the start of the inner code codewords of the fourth data stream. Referring to Figure 11, it is a schematic diagram of a possible pad sequence insertion. H can be an integer multiple of f. Exemplarily, f = 8, H = 8704, L = 48; or f = 16, H = 17408, L = 48.

[0299] As an example, when S = 4, the values of m_i<119:114> of the data pad or pad_cw_i<127:122> of the pad sequence are shown in Table 3.

[0300] Table 3

[0301] Among them, 0 ≤ i < 8, m_i<119:114> represents bits 114 (bit index starting from 0, bit 0 can be represented as the 1st bit, so bit 114 is also represented as the 115th bit) to bit 119 (i.e., the 120th bit) of the i-th group (or the group index i, that is, the (i + 1)-th group) in the f groups included in the data pad. pad_cw_i<127:122> represents bits 122 to bit 127 of the i-th group in the f groups included in the pad sequence. In the above description, group 0 represents the 1st group, group 1 represents the 2nd group, and so on. Bit index 0 represents the 1st bit, bit index 1 represents the 2nd bit, and so on. It should be noted that the value of pad_cw_0<127:122> in Table 3 is "010110", indicating that bits 127 to bit 122 of group 0 of the pad sequence are 0, 1, 0, 1, 1, 0 respectively.

[0302] It should be noted that for each m_i<119:0>, its bit 119 is m_i <119> The first bit transmitted, its bit 0 is m_i <0> This refers to the last transmitted bit. For each pad_cw_i<127:0>, bit 127 is pad_cw_i. <127> The first bit transmitted, its bit 0 is pad_cw_i <0> This represents the last bit transmitted. Where 0 ≤ i <f。

[0303] As another example, when S=8, the m_i of the data pad <k-1:z>Or the pad_cw_i of the pad sequence <n-1:x>The values ​​of are shown in Table 4.

[0304] Table 4

[0305] Where 0 ≤ i < 16, and when 0 ≤ i < 8, z = 116, and when 8 ≤ i < 16, z = 118. Where 0 ≤ i < 16, and when 0 ≤ i < 8, x = 124, and when 8 ≤ i < 16, x = 126.

[0306] Referring to Figures 12A and 12B, which are schematic diagrams of the second data processing method provided in this application embodiment, the sending processing module performs first data processing on every two data streams in the p-length first data streams encoded with external codes. The following example uses two first data streams. The first data processing includes block distribution. In some possible implementation scenarios, the first data processing may also include convolutional interleaving. For ease of explanation, the following description uses RS(544,514) code as the external code encoding example; however, other encoding methods can also be used for external code encoding in practical applications. RS code can also be called RS FEC code.

[0307] S1201, perform first data processing on the two first data streams respectively to obtain 2*S second data streams. All first data streams are encoded using an external code. The first data processing includes block distribution, whereby each first data stream is distributed into S second data streams. For details, please refer to the description of S401, which will not be repeated here.

[0308] In step S1202, the 2*S second data streams are processed to obtain 2*S third data streams. The second data processing includes cyclic shifting and internal code encoding. For details, please refer to the description of step S402, which will not be repeated here.

[0309] S1203 interleaves 2*S third data stream bit pairs into 2 sixth data streams.

[0310] S1204, the two sixth data stream bit pairs are multiplexed into a seventh data stream.

[0311] In some embodiments, the second data processing method executed by the originating processing module may further include pad sequence insertion. Specifically, as shown in Figure 12B, before multiplexing the two sixth data stream bits into a seventh data stream, pad sequence insertion is performed on the sixth data stream.

[0312] In this embodiment, each first data stream is distributed in 1:S blocks to obtain S second data streams. Figure 12B shows two first data streams, first data stream 0 and first data stream 1, as an example. A total of 2×S second data streams are obtained. Then, each second data stream undergoes second data processing, including cyclic shifting and internal code encoding, to obtain an N-bit internal codeword, thus obtaining 2×S third data streams. Next, each of the S third data streams is bit-pair interleaved to obtain a sixth data stream, resulting in a total of 2 sixth data streams. Then, each sixth data stream undergoes pad sequence insertion to obtain two pad-inserted data streams. Finally, the two pad-inserted data streams are bit-pair multiplexed to obtain a seventh data stream.

[0313] In one possible implementation, the first data processing may further include convolutional interleaving. Referring to Figure 12B, convolutional interleaving can be performed in block processing. Convolutional interleaving is performed on each of the two first data streams to obtain two convolutionally interleaved data streams. Then, the two convolutionally interleaved data streams are distributed in a 1:S block ratio to obtain S second data streams, resulting in a total of 2×S second data streams.

[0314] The second data processing method uses the same convolutional interleaving, block distribution, internal code encoding, and bit pair interleaving as the first data processing method, so they will not be repeated here.

[0315] In the second data processing method, pad sequence insertion is performed as follows:

[0316] In one possible implementation, the pad sequence may include f blocks. Each of the f blocks comprises N bits. This can be achieved using pad_cw_i. <n-1:0>This represents the i-th block of the pad sequence. It can also be understood as: the pad sequence comprises f × N bits. Each block includes a first part and a second part. The first part includes at least one bit pair. The sequence of the first parts of the f blocks, arranged in bit pairs according to the block order, includes the frame-aligned sequence, f = S. The second part can include both the first and second sub-parts. The second sub-part includes NK bit check information, and the first sub-part includes the scrambled sequence of all zeros. For example, scrambling can use a pseudo-random binary sequence 13 (PRBS13).

[0317] It is understandable that an f×N bit pad sequence can be obtained by encoding and interleaving f×K bit data pads (or information pads) using the aforementioned internal code encoding. The f×K bit data pads can also be described as f×K data bits or information bits. Further, each of the f groups can include K information bits and NK parity bits (i.e., NK bit check information). In some implementations, the f groups in the pad sequence can also be described as f pad codewords. Each pad codeword can also be understood as an internal codeword. The K information bits in each internal codeword include the first part and the first sub-part of the second part. The sequence of the first parts of the f groups, arranged bit by bit in the group order, includes the frame-aligned sequence.

[0318] Another possible implementation is to group the f×K bit data pads in the pad sequence. The generation method of the pad sequence is shown in Figure 10; the f×K bit data pad is divided into f groups, each group containing K bits. For example, using m_i... <k-1:0>This represents the i-th block of the data pad. The i-th block of the data pad includes the first part. Encoding each block of the data pad with its internal code yields NK bits of check information, resulting in an N-bit internal codeword called the pad codeword, denoted as pad_cw_0. <n-1:0>Then, the f pad codewords are interleaved according to the bit pairs shown in Figure 9 to obtain an f×N bit pad sequence, denoted as pad.<f×N-1:0> The pad sequence contains pads.<f×N-1:f×N-L> The total number of bits is L, which is the frame alignment sequence. For example, L = 48. This can also be understood as the frame alignment sequence being the sequence of the first part of the f packets of the data pad, arranged in bit pairs according to the packet order. Alternatively, the frame alignment sequence is obtained by interleaving the first part of the f packets of the data pad according to the bit pairs shown in Figure 9.

[0319] In some embodiments, when inserting pad sequences into the two sixth data streams respectively, a pad sequence can be inserted every H internal codewords in each sixth data stream. Alternatively, a pad sequence can be inserted after H consecutive internal codewords. In some embodiments, a pad sequence is also inserted before the start of the internal codewords in the fourth data stream. A schematic diagram of pad sequence insertion can be seen in Figure 11. H can be an integer multiple of f; for example, f = 8, H = 8704, L = 48; or f = 4, H = 4352, L = 48.

[0320] As an example, when S=4, the values ​​of m_i<119:108> for data pad or pad_cw_i<127:116> for the pad sequence are shown in Table 5.

[0321] Table 5

[0322] Where 0≤i<4, m_i<119:108> represents bits 108 to 119 of group i in the f groups of data pad. pad_cw_0<127:116> represents bits 116 to 127 of group i in the f groups of pad sequence.

[0323] As another example, when S=8, the values ​​of m_i<119:114> for data pad or pad_cw_i<127:122> for pad sequence are shown in Table 6.

[0324] Table 6

[0325] Where 0≤i<8, m_i<119:114> represents bits 114 to 119 of group i in the f groups of data pad. pad_cw_0<127:122> represents bits 122 to 127 of group i in the f groups of pad sequence.

[0326] Bit-pair multiplexing in the second data processing method:

[0327] After bit pair multiplexing, each consecutive α bit pairs in the two sixth data streams are consecutive in the seventh data stream, where α ≥ 1. Exemplarily, a specific implementation of bit pair multiplexing can be seen in FIG. 13. Polling reads α bit pairs from 2 sixth data streams into the seventh data stream at a time. In FIG. 13, the two sixth data streams are taken as the sixth data stream A and the sixth data stream B respectively. For example, when α = 1, in FIG. 13, A i represents the i-th bit pair of the sixth data stream A, and B i represents the i-th bit pair of the sixth data stream B. For example, when α = β × S, in FIG. 13, A i and B i respectively represent consecutive β × S bit pairs in the sixth data stream A and the sixth data stream B, and the consecutive β × S bit pairs are obtained by taking consecutive β bit pairs from each of the S third data streams and performing bit pair interleaving according to the scheme shown in FIG. 11; where β ≥ 1 and β is divisible by N / 2. Exemplarily, α = 1 or α = 4 or α = 8 or α = 3 or α = 64 or α = 128 or α = 256 or α = 512 can facilitate hardware implementation and simplify the in-code synchronization at the receiving end.

[0328] Cyclic shift in the second data processing method:

[0329] In FIG. 12B, one implementation of cyclic shift and in-code encoding processing is to perform cyclic shift first and then in-code encoding. The specific description can be seen in the description in the first data processing method and will not be elaborated here. Another implementation of cyclic shift and in-code encoding processing in FIG. 12B is to perform in-code encoding first and then cyclic shift. The specific description can be seen in the description in the first data processing method and will not be elaborated here.

[0330] In some embodiments, considering that α = β × S corresponding to bit pair multiplexing, the number of symbols for cyclic shift of the n-th second data stream from different first data streams is the same, 0 ≤ n < S, and the number of symbols for cyclic shift of the S second data streams from the same first data stream is different. Specifically, for example, in FIG. 4B, the first data stream 0 distributes to obtain S second data streams denoted as the second data stream 0 to the second data stream S - 1, and the first data stream 1 distributes to obtain S second data streams denoted as the second data stream S to the second data stream 2 × S - 1. Then, the number of symbols for cyclic shift of any two data streams among the second data stream 0 to the second data stream S - 1 is different; the number of symbols for cyclic shift of any two second data streams among the second data stream S to the second data stream 2 × S - 1 is different; the number of symbols for cyclic shift of the second data stream n and the second data stream S + n is the same. Through cyclic shift and subsequent bit pair interleaving processing, multiple consecutive PAM4 symbol errors introduced in channel transmission can be dispersed to multiple in-code codewords and multiple RS codewords, improving the burst resistance performance of the concatenated code.

[0331] In other embodiments, the number of signs for the 2*S second data streams cyclically shifted from the two data streams are different, for example, S=4.

[0332] In some other embodiments, when the bit pair multiplexing corresponds to α = β × S, the number of symbols cyclically shifted from the S second data streams originating from the same first data stream is different. The β is divisible by N / 2. This ensures that two bit pairs from the same RS codeword in the seventh data stream are spaced at least S symbols apart, improving the burst resistance of the concatenated code.

[0333] As an example, when S=8, α=S, and the cyclic shift of 2*S second data streams can satisfy any of the modes 1 to 17 in Table 1.

[0334] As an example, when S=4, α=S, and the cyclic shift of 2*S second data streams can satisfy any of the methods 1 to 6 in Table 2.

[0335] As another example, when S=8 and α=1, the cyclic shift of the 2*S second data streams can be performed using any of the methods 1 to 16 in Table 7.

[0336] Table 7

[0337] Here, the second data stream *m* represents the *m*th data stream out of 16 second data streams, where *m* = {0, 1, 2, ..., 15}. The data *c* in the *y*th column represents a right circular shift of *c* symbols for every 12 consecutive symbols in the corresponding second data stream *m*, or a left circular shift of *12-c* symbols for every 12 consecutive symbols in the corresponding second data stream *m*, where 1 ≤ *y* ≤ 16. The *y*th column above represents a data column, where the value of *y* satisfies 1 ≤ *y* ≤ 16, excluding the mode name columns corresponding to modes 1 to 16.

[0338] By using the cyclic shifting method exemplified in Table 7 above, the two bit pairs from the same RS codeword in the seventh data stream can be spaced at least 8 symbols apart, thus improving the burst resistance of the concatenated code.

[0339] As another example, when S=4 and α=1, the cyclic shift of the 2*S second data streams can be performed using any of the methods 1 to 6 in Table 8.

[0340] Table 8

[0341] Here, the second data stream *m* represents the m-th data stream out of 8 second data streams, where *m* = {0, 1, 2, ..., 7}. The data *c* in the y-th column represents a right circular shift of *c* symbols for every consecutive 12 symbols in the corresponding second data stream *m*, or a left circular shift of *12-c* symbols for every consecutive 12 symbols in the corresponding second data stream *m*, where 1 ≤ y ≤ 8. The aforementioned y-th column represents a data column, where the value of y satisfies 1 ≤ y ≤ 8, excluding the mode name columns corresponding to modes 1 to 6.

[0342] By using the cyclic shifting method exemplified in Table 8 above, the two bit pairs from the same RS codeword in the seventh data stream can be spaced at least 8 symbols apart, thus improving the burst resistance performance of the concatenated code.

[0343] In some embodiments, a third data processing step can be performed on p fifth data streams encoded with external codes to obtain the p first data streams described above. The third data processing includes alignment marker lock (AM lock). In some embodiments, the third data processing may also include symbol demultiplexing. The two first data streams output after the third data processing have determined the RS-FEC symbol-quarter and the codeword boundaries of the external code encoding. For example, the symbol demultiplexing of the p fifth data streams can be p:q, that is, inputting p fifth data streams, and obtaining q demultiplexed data streams after symbol demultiplexing. Where q = t × p. For example, t = 2 or t = 8.

[0344] In this embodiment, all p fifth data streams are data streams encoded with external codes. For ease of explanation, the following description uses RS encoding as an example of external code encoding. In practical applications, other encoding methods can also be used for external code encoding. The data stream after RS ​​encoding can include multiple RS codewords. In this embodiment, the code length of the RS code is counted in units of symbols. The symbols in the RS code can be called RS symbols or RS FEC symbols. For example, the RS code uses RS(544,514) code, also known as KP4 code. The code length of the RS code is 544 RS FEC symbols, that is, the codeword of the RS code includes 544 RS FEC symbols, and one RS FEC symbol contains 10 bits. In each of the fifth data streams, every a adjacent RS FEC symbols come from a RS codewords, where a is greater than or equal to 4. The RS code can also be called RS FEC code.

[0345] For 400G transmission scenarios, such as under 400GBASE-R internal code encoding, p = 2. In some specific applications, the p = 2 fifth data streams are obtained by processing two AUI data streams from 400G AUI-2 (i.e., two AUI data streams input from one AUI interface) through 400GBASE-R 2:2SM-PMA. SM-PMA represents symbol muxing processing in the Physical Medium Attachment (PMA) sublayer of the transmitting processing module. The two AUI data streams of 400G AUI-2 are obtained by processing 16 Physical Coding Sublayer Lane (PCSL) data streams through 400GBASE-R 16:2SM-PMA. In the 16 PCSL data streams, every two adjacent RS FEC symbols come from two different RS codewords. After 400GBASE-R16:2SM-PMA processing, every four adjacent RS FEC symbols in each fifth data stream come from four RS codewords.

[0346] For 800G transmission scenarios, such as under 800GBASE-R internal code encoding, p = 4. In some specific applications, the p = 4 fifth data streams are obtained by processing 4 AUI data streams of 800G AUI-4 with 800GBASE-R 4:4SM-PMA. The 4 AUI data streams of 800G AUI-4 are obtained by processing 32 PCSL data streams with 800GBASE-R 32:4SM-PMA. In the 32 PCSL data streams, every two adjacent RS FEC symbols come from two different RS codewords. After processing with 800GBASE-R 32:4SM-PMA, every four adjacent RS FEC symbols in each fifth data stream come from four RS codewords.

[0347] For 1.6T transmission scenarios, such as under 1.6TBASE-R internal code encoding, p = 8. In some specific applications, the p = 8 fifth data streams are obtained by processing 8 AUI data streams of 1.6TAUI-8 using 1.6TBASE-R 8:8SM-PMA. The 8 AUI data streams of 1.6TAUI-8 are obtained by processing 16 PCSL data streams using 1.6TBASE-R 16:8SM-PMA. In the 16 PCSL data streams, every 4 adjacent RS FEC symbols come from 4 different RS codewords. After 1.6TBASE-R 16:8SM-PMA processing, every 4 adjacent RS FEC symbols in each fifth data stream come from 4 RS codewords.

[0348] For 3.2T transmission scenarios, such as under 3.2TBASE-R internal code encoding, p = 16. In some specific applications, the p = 16 fifth data streams are obtained by processing 16 AUI data streams of 3.2T AUI-16 with 3.2T BASE-R 16:16SM-PMA or 3.2TBASE-R 32:16PMA. The 16 AUI data streams of 3.2T AUI-16 are obtained by processing w PCSL data streams with 3.2T BASE-R w:16SM-PMA. In the w PCSL data streams, every four adjacent RS FEC symbols come from four different RS codewords. After processing with 3.2T BASE-R w:16SM-PMA, every four adjacent RS FEC symbols in each fifth data stream come from four RS codewords. Where w = 16 or 32.

[0349] It should be noted that, for the above-mentioned 400G BASE-R internal code encoding, 800G BASE-R internal code encoding, 1.6T BASE-R internal code encoding, and 3.2TB BASE-R internal code encoding, the nominal rate of each of the p fifth data streams is 212.5 Gbits per second (b / s).

[0350] It should be noted that in some specific applications, the p fifth data streams are also referred to as p PMA data streams.

[0351] In the above description, the p:q symbol demultiplexing process refers to demultiplexing p fifth data streams and outputting q demultiplexed data streams.

[0352] Referring to Figure 14A, p fifth data streams undergo p:q symbol demultiplexing to obtain q demultiplexed data streams, where q = t × p, and t = 2 or t = 8. Then, alignment identifier locking is performed on the q demultiplexed data streams to obtain p first data streams that implement RS-FEC symbol-quartet delimitation.

[0353] Specifically, the p-length first data stream obtained by performing third data processing on the p-length fifth data stream encoded with external codes can be achieved in the following way:

[0354] A1, demultiplex each of the p fifth data streams encoded with the external code using a 1:t symbol, to obtain t*p demultiplexed data streams.

[0355] A2 performs alignment flag locking on each t demultiplexed data stream in the t*p striped demultiplexed data stream to obtain the first data stream that determines the codeword boundaries of the RS-FEC 4 symbol (RS-FEC symbol-quarter) and the outer code encoding. Each t demultiplexed data stream originates from the same fifth data stream.

[0356] As shown in Figure 14B, the p:q symbol demultiplexing includes p 1:t symbol demultiplexings, each corresponding one-to-one with a p fifth data stream. Alignment marker locking is performed on the t demultiplexed data streams obtained from the symbol demultiplexing of each of the p fifth data streams, resulting in p output first data streams that define the boundaries of RS FEC codewords and RS FEC 4 symbols. This alignment marker locking is also simply referred to as alignment lock. The alignment marker locking operation utilizes the known alignment marker (AM) in the PCSL data stream.

[0357] For 400GBASE-R and 800GBASE-R encoding scenarios, the p:q RS FEC symbol demultiplexing (or simply symbol demultiplexing, or RS symbol demultiplexing, etc., which are not limited in this application embodiment) includes p 1:8 RS FEC symbol demultiplexings, i.e., t=8. Each 1:8 RS symbol demultiplexing uses a round-robin method to distribute 20 bits at a time. This RS symbol demultiplexing can also be called RS symbol pair demultiplexing, distributing two RS FEC symbols each time, i.e., one RS FEC symbol pair. The input fifth data stream is demultiplexed to obtain 8 output demultiplexed data streams. When all 8 output demultiplexed data streams achieve alignment identifier locking. Here, achieving alignment identifier locking means that the alignment identifier is correctly locked. At this time, the boundary of the 20 bits distributed is the boundary of an RS FEC symbol pair. It should be understood that each fifth data stream has its own RS FEC symbol pair boundary. Based on the determined RS FEC symbol pair boundary and the processing of 400GBASE-R16:2SM-PMA or 800GBASE-R 32:4SM-PMA, the four symbols (two consecutive RS FEC symbol pairs) in each fifth data stream come from four RS codewords. These two RS FEC symbol pairs, i.e., four RS FEC symbols, constitute one RS FEC 4 symbol (RS-FEC symbol-quartet), and the boundary of these two RS FEC symbol pairs is the RS FEC 4 symbol boundary. Therefore, by determining the RS FEC symbol pair boundary through alignment flag locking of the eight demultiplexed data streams obtained from symbol demultiplexing of the fifth data stream, the RS FEC 4 symbol boundary of the fifth data stream can be determined. In other words, the data stream with the determined RS FEC 4 symbol boundary can also be referred to as the first data stream.

[0358] It should be noted that within a certain time interval (also called a threshold time interval) or a certain bit interval (e.g., 222,822,400 bits), when the alignment identifier locking is not implemented in the demultiplexed data streams of the 8 outputs, 20-bit boundaries are distributed in the above 1:8RS symbol demultiplexing for shifting (shifting), which is also called slipping. In some specific applications, the above 1:8RS symbol demultiplexing distributes 20-bit boundaries for slipping 1 bit. In other specific applications, the above 1:8RS symbol demultiplexing distributes 20-bit boundaries for slipping a bit greater than 1. In this case, it is necessary to ensure that all possible boundaries are evaluated. A slip of 20×m+1 bits can be made, where m is an integer greater than 0, for example, slipping 21 bits or 41 bits. When the shift interval matches the specific hardware implementation's processing bit width, the implementation is relatively simple and has low complexity. The above shift operation continues until all 8 output demultiplexed data streams achieve alignment flag locking.

[0359] For 1.6TBASE-R encoding or 3.2TBASE-R scenarios, the p:q RS symbol demultiplexing includes p 1:2 RS symbol demultiplexings, i.e., t=2. Each 1:2 symbol demultiplexing uses a round-robin method, distributing 40 bits at a time. This RS symbol demultiplexing can also be called RS FEC 4 symbol demultiplexing (or four-symbol demultiplexing or 4-symbol demultiplexing), distributing 4 RS FEC symbols at a time, i.e., one RS FEC 4 symbol. The input fifth data stream is demultiplexed to obtain two output demultiplexed data streams. When both output demultiplexed data streams achieve alignment flag locking (here, achieving alignment flag locking means correctly locking the alignment flag), the boundary of the 40 bits distributed is the boundary of one RS FEC 4 symbol (RS-FEC symbol-quartet). It should be understood that each fifth data stream has its own RS FEC 4 symbol boundary.

[0360] It should be noted that within a certain time interval (also called a threshold time interval) or a certain bit interval (e.g., 222, 822, 400 bits), when the two output demultiplexed data streams do not achieve alignment identifier locking, the 40-bit boundary distributed in the above 1:2RS symbol demultiplexing is shifted. This shift is also called slipping. In some specific applications, the 40-bit boundary is shifted by 1 bit. In other specific applications, the 40-bit boundary is shifted by a bit greater than 1. In this case, it is necessary to ensure that all possible boundaries are evaluated. A slip of 40×m+1 bits can be made, where m is a positive integer, such as 41 bits or 81 bits. When the shift interval matches the specific hardware implementation's bit width, the implementation is relatively simple and has low complexity. The above shift operation continues until all two output demultiplexed data streams achieve alignment flag locking.

[0361] It should be noted that, for the 400GBASE-R internal code encoding scenario, the p output first data streams correspond one-to-one with the p input fifth data streams. The RS FEC codeword and RS FEC 4 symbol boundary of each fifth data stream are determined by the alignment flag. That is, the output first data stream is the data stream with the RS FEC codeword and RS FEC 4 symbol boundary determined. The first data stream is unchanged relative to the fifth data stream.

[0362] In some possible implementation scenarios, such as 800G and 1.6T transmission scenarios, skew may exist between the PCSL data streams involved in symbol pair multiplexing during SM-PMA processing. This can lead to a situation where, after convolutional interleaving in the subsequent second data processing, it cannot be guaranteed that the K bits of information data of the inner codeword come from K / 10 RS codewords, thus affecting the performance of the concatenated code. Therefore, the third data processing can also include deskew processing and symbol multiplexing. Thus, after A2, A3 and A4 are also executed. A3 performs deskew processing on the t demultiplexed data streams (also known as channel data streams) locked by the alignment identifier; A4 performs symbol multiplexing on the t demultiplexed data streams after deskew processing into a first data stream, thereby obtaining p first data streams.

[0363] For example, during 800GBASE-R 32:4SM-PMA processing, there may be skew between the PCSL data streams participating in 1:8 RS symbol pair multiplexing. This can lead to a situation where, after convolutional interleaving in the subsequent second data processing, it cannot be guaranteed that the K bits of information data of the inner codeword come from K / 10 RS codewords, thus affecting the performance of the concatenated code. Therefore, for the 800GBASE-R inner code encoding scenario, the third data processing can also include deskew processing and symbol multiplexing (here, symbol pair multiplexing can be used). That is, the odd-numbered PCSL data streams indicated by the unique marker (UM) information in the alignment flag are delayed and multiplexed with symbol pairs. It should be noted that for the 800GBASE-R scenario, the physical coding sublayer defines 32 PCSLs, represented as PCSL0 to PCSL31, where PCSL1, PCSL3, PCSL5, PCSL7, ..., PCSL29, PCSL31 are odd-numbered PCSLs. Different sequences were defined for the unique flag UM field of the alignment flag in the 32 PCSLs. Therefore, the PCSL number can be determined based on the specific sequence in the unique flag UM field of the alignment flag in the PCSL. For example, if the unique flag UM field sequence of the alignment flag in a PCSL is the same as the unique flag UM field sequence of the alignment flag in PCSL1, then this PCSL is PCSL1, and it is also an odd PCSL. Specifically, as shown in Figure 14C, each fifth data stream is first demultiplexed by a 1:8 symbol pair to obtain 8 demultiplexed data streams according to the aforementioned scheme. Then, the alignment flag is locked for each of the 8 demultiplexed data streams. After the alignment flag is locked for all 8 demultiplexed data streams, the skew between the 8 PCSL data streams is eliminated according to the alignment flag. That is, the boundary of the desymbol is adjusted according to the result of the alignment flag locking of the 8 demultiplexed data streams, so that there is no skew between the starting positions of the alignment flag (AM) of the output 8 PCSL data streams. Then, the odd PCSL data stream in the 8 PCSL data streams is delayed by 1 RS symbol according to the UM information in the alignment flag. Finally, the 8 PCSLs are multiplexed into a first data stream with defined RS FEC 4-symbol boundaries by polling the RS FEC symbol pairs in a 1:8 RS FEC symbol pair manner.

[0364] For example, during 1.6TBASE-R 16:8SM-PMA processing or 3.2TBASE-R 32:16SM-PMA processing, there may be skew between the PCSL data streams participating in 1:2RS FEC 4-symbol multiplexing. This may result in the inability to guarantee that the K bits of information data of the inner codeword come from K / 10 RS codewords after the convolutional interleaving of the subsequent second data processing, thus affecting the performance of the concatenated code. Therefore, for 1.6TBASE-R inner code encoding scenarios or 3.2TBASE-R inner code encoding scenarios, the first data processing also includes skew removal and RS FEC 4-symbol multiplexing processing. As shown in Figure 14D, according to the aforementioned scheme, each fifth data stream is first demultiplexed with RS FEC 4 symbols at a ratio of 1:2 to obtain two demultiplexed data streams. Then, the alignment flags of the two demultiplexed data streams are locked. After the alignment flags of the two demultiplexed data streams are locked, the skew between the two PCSLs is eliminated according to the alignment flags. That is, the boundary of the demultiplexed symbols is adjusted according to the result of the alignment flag locking in the two demultiplexed data streams, so that there is no skew between the starting positions of the alignment flags (AM) of the two output PCSLs. Finally, the two PCSLs are multiplexed with RS FEC 4 symbols at a ratio of 2:1 according to the RS FEC 4 symbol polling output method to output a first data stream with a determined RS FEC 4 symbol boundary.

[0365] Furthermore, considering the need for better resistance to colored noise in concatenated codes, a specific implementation of the third data processing was described above. This involves deskewing the demultiplexed q data streams to ensure no deviation between the two first data streams undergoing the second data processing. The following describes another specific implementation of the third data processing. This third data processing includes symbol demultiplexing, alignment flag locking, and deskewing. In this alternative implementation, the third data processing is performed on every two fifth data streams; therefore, the following example will focus on the third data processing of two fifth data streams.

[0366] Taking two fifth data streams as an example, the third data processing of the two fifth data streams can be achieved in the following way:

[0367] B1, perform symbolic demultiplexing on each of the two fifth data streams to obtain 2*t demultiplexed data streams. Each fifth data stream is demultiplexed into t demultiplexed data streams.

[0368] B2, perform alignment flag locking processing on the 2*t demultiplexed data streams respectively to obtain 2*t channel data streams with alignment flag locking.

[0369] B3, perform deskewing on 2*t channel data streams;

[0370] B4. Symbol multiplexing is performed on each t channel data stream after the deskewing process to obtain the two first data streams; wherein each t channel data stream comes from the same fifth data stream.

[0371] The following section describes another specific implementation method for third-party data processing, categorized by business scenario.

[0372] In some possible implementations, p = 8 or p = 16, t = 2, and the third data processing includes symbol demultiplexing, alignment identifier locking, and symbol multiplexing. In step B1 above, symbol demultiplexing uses four-symbol demultiplexing, and in step B4, symbol multiplexing uses four-symbol multiplexing.

[0373] For example, in a 1.6TBASE-R or 3.2TBASE-R encoding scenario (i.e., p=8 or p=16, t=2), each pair of fifth data streams undergoes third data processing according to the scheme shown in Figure 14E to obtain two first data streams with determined 4-symbol boundaries. Specifically, each pair of fifth data streams is demultiplexed with RS FEC 4 symbols at a ratio of 1:2 to obtain four demultiplexed data streams. Then, alignment flags are locked on each of the four demultiplexed data streams to obtain four PCSL data streams. After the alignment flags of all four demultiplexed data streams are locked, the skew between the four PCSL data streams is eliminated according to the alignment flags, so that there is no skew between the starting positions of the alignment flags (AM) of the output four PCSL data streams. Finally, the two PCSL data streams obtained from the demultiplexing and processing of one fifth data stream are multiplexed 1:2 according to the RS FEC 4 symbol polling output method to output a first data stream with determined RS FEC 4 symbol boundaries, for a total of two first data streams.

[0374] In other possible implementations, before symbol multiplexing the 2*t channel data streams after deskewing, the odd-numbered channel data streams in the 2*t channel data streams after deskewing are delayed by g symbols. The odd-numbered channel data streams can also be understood as channel data streams whose unique marker (UM) portion in the AM sequence of the PCSL channel data stream is marked with an odd number of symbols. Specifically, the four consecutive symbols in each of the fifth data streams come from four codewords encoded by the outer code; the alignment markers between any two channel data streams in the 2*t channel data streams after deskewing are skewed by D*136 symbols, where D is an integer greater than or equal to 0.

[0375] For example, for a 400GBASE-R encoding scenario, p=2, g=69; for an 800GBASE-R encoding scenario, p=4, g=1, D=0.

[0376] In one possible example, when p=2 or p=4 and t=8, the symbol demultiplexing in step B1 above adopts symbol pair demultiplexing, and the symbol multiplexing in step B4 adopts symbol pair multiplexing.

[0377] For example, in a 400GBASE-R encoding scenario, i.e., p=2, t=8, every two fifth data streams undergo third data processing according to the scheme shown in Figure 14F to obtain two first data streams with determined RS FEC 4 symbol boundaries. Specifically, every two fifth data streams are demultiplexed with a 1:8 symbol pair according to the aforementioned scheme to obtain 16 demultiplexed data streams. Then, alignment flag locking is applied to each of the 16 demultiplexed data streams to obtain 16 PCSL data streams. After all 16 demultiplexed data streams have achieved alignment flag locking, the skew between the 16 PCSL data streams is eliminated according to the alignment flags, so that the starting positions of the alignment flags (AM) of the output 16 PCSL data streams are skewed by D×136 symbols, where D is an integer greater than or equal to 0; then, according to the UM flag information in the alignment flags, the odd-numbered PCSLs are delayed by g RS FEC symbols, in this example g=69; finally, the 8 PCSL data streams obtained from the demultiplexing and other processing of a fifth data stream are multiplexed 1:8 according to the RS FEC symbol pair polling output method to output a first data stream with a determined RS FEC 4-symbol boundary, for a total of 2 first data streams output.

[0378] For example, in an 800GBASE-R encoding scenario (p=4, t=8), every two fifth data streams undergo third data processing according to the scheme shown in Figure 14F to obtain two first data streams with defined RS FEC 4 symbol boundaries. Specifically, every two fifth data streams are demultiplexed with a 1:8 symbol pair according to the aforementioned scheme to obtain 16 demultiplexed data streams. Then, alignment flags are locked on each of the 16 demultiplexed data streams to obtain 16 PCSL data streams. After all 16 demultiplexed data streams have achieved alignment flag locking, the skew between the 16 PCS data streams is eliminated according to the alignment flags, so that there is no skew between the starting positions of the alignment flags (AM) of the output 16 PCSL data streams. Then, according to the UM flag information in the alignment flags, the odd number of PCSL data streams are delayed by one g RS symbols. In this example, g=1. Finally, the 8 PCSL data obtained from the demultiplexing and other processing of a fifth data stream are multiplexed 1:8 according to the RS FEC symbol pair polling output method to output a first data stream with a determined RS FEC 4 symbol boundary. A total of 2 first data streams are output.

[0379] The following describes the solution provided in the embodiments of this application by way of example, in conjunction with specific transmission scenarios.

[0380] Example 1: Consider a 1.6TBASE-R transmission scenario, p = 8 and t = 2, that is, q = 2 × p = 16.

[0381] The transmitting processing module 02 receives eight AUI data streams of 1.6TAUI-8 and performs PAM4 decoding on them to obtain p = eight fifth data streams. Following the scheme shown in Figure 14B, 14D, or 14E, the eight fifth data streams undergo third data processing to obtain eight RS FEC 4-symbol delimited first data streams. Then, every two first data streams are processed according to the first data processing implementation shown in Figure 4A or 4B to obtain one fourth data stream, for a total of four fourth data streams output. It should be noted that if every two fifth data streams undergo third data processing according to the scheme shown in Figure 14E to obtain two aligned first data streams, then inputting these two aligned first data streams into the scheme shown in Figure 4A or 4B for data processing can improve the concatenated code's resistance to colored noise.

[0382] The convolutional interleaver in the first data processing adopts the scheme shown in Figure 5A or Figure 5B, where r = 3 delay lines, the difference in the number of storage units between any two adjacent delay lines is Q ≥ 24, and according to the obtained RS FEC 4 symbol boundaries, each storage unit stores d = 40 bits, and the 40 bits stored in each storage unit correspond to 4 RS FEC symbols, i.e., one RS FEC symbol-quartet. In the convolutional interleaved data stream output by the convolutional interleaving process, 12 consecutive (adjacent) RS FEC symbols come from 12 RS codewords, which allows the 120 information bits of each inner codeword to come from 12 RS codewords, giving the concatenated code better performance, allowing Q = 24, and reducing the system latency, making it suitable for a wider range of transmission scenarios.

[0383] The block distribution uses a 1:8 120-bit distribution, i.e., taking S=8 as an example, a total of 16 second data streams are obtained. Correspondingly, as shown in Figure 7A, the scheme is used to cyclically shift three consecutive RS FEC 4 symbols in every eight second data streams before performing FEC(128, 120) internal code encoding; or as shown in Figure 7B, the scheme is used to first perform FEC(128, 120) internal code encoding on every three consecutive RS FEC 4 symbols in every eight second data streams before cyclically shifting the 120 bits of information data in each internal codeword. For example, in order to make the concatenated code have better resistance to colored noise, the cyclic shifts corresponding to the 16 second data streams can be implemented using the scheme shown in Figure 8A. The cyclic shift values ​​of the second data stream i and the second data stream i+8 are the same, the cyclic shifts of the second data streams 0 to 7 are different, and the cyclic shifts of the second data streams 8 to 15 are different. Here, CS(a) represents a right cyclic shift of a RS symbols, 0≤i<8. The second data streams 0 to 7 are obtained by distributing the convolutional interleaved data stream 0 into 8 blocks in a 1:8 ratio, and the second data streams 8 to 15 are obtained by distributing the convolutional interleaved data stream 1 into 8 blocks in a 1:8 ratio.

[0384] For example, in order to further enhance the concatenation code’s resistance to colored noise, the cyclic shifts corresponding to the 16 second data streams are implemented using any of the implementation methods in Table 1.

[0385] The bit pair interleaving uses a 16:1 bit pair multiplexing method to multiplex the 16 internal code FEC data streams to obtain a fourth data stream, which corresponds to f=16 in Figure 9.

[0386] For each of the 17408 inner codewords in each fourth data stream, a pad sequence of length 2048 bits is inserted, with the first pad sequence inserted before the start of the inner codeword. The data pad is 1920 bits long. The specific sequences corresponding to m_i<119:z> in Figure 10 are shown in Table 4. <z-1:0>The sequence is the result of scrambling an all-zero sequence with PRBS13, where 0 ≤ i < 16, and when 0 ≤ i < 8, z = 116, and when 8 ≤ i < 16, z = 118. The corresponding FAS sequence in the pad sequence is obtained by multiplexing the pad codeword bit-by-bit: 0101100101010010 01100100 10100110 10101101 10011011, where the leftmost bit of the FAS sequence is the first bit transmitted, and the rightmost bit is the last bit transmitted. Correspondingly, for each m_i <119:0>, its bits m_i <119> The first bit transmitted, its bit m_i <0> This refers to the last bit transmitted.

[0387] Example 2: Consider a 1.6TBASE-R transmission scenario, where p = 8 and t = 2, i.e., q = 2 × p = 16.

[0388] Example 2 is based on Example 1, distributing each convolutional interleaved data stream in a 1:4 block ratio. For example, with S=4, this results in 4 second data streams, for a total of 8 second data streams. The method for obtaining the first data stream in Example 2 is described in Example 1, and the convolutional interleaving method in Example 2 is also described in Example 1; it will not be repeated here. Further, the scheme shown in Figure 7A can be used to cyclically shift three consecutive RS FEC 4-symbols in the 8 second data streams before FEC(128, 120) internal code encoding; or the scheme shown in Figure 7B can be used to first encode each three consecutive RS FEC 4-symbols in the 8 second data streams using FEC(128, 120) internal code before cyclically shifting the 120 bits of information data in each internal codeword. To ensure the concatenated code has good resistance to colored noise, the cyclic shifting of the 8 second data streams can be implemented using any of the methods shown in Table 2. Then, the eight internal code FEC data streams are interleaved or multiplexed using an 8:1 bit-pair ratio to obtain a fourth data stream. Correspondingly, as shown in Figure 11, a 1024-bit pad sequence is inserted after every H = 8704 internal codewords in each fourth data stream, with the first pad sequence inserted before the start of the internal codeword, corresponding to f = 8 in Figure 11. For example, where the data pad length is 960 bits, the specific sequence corresponding to m_i<119:114> in Figure 13 can be found in Table 3. m_i<113:0> is the sequence after the all-zero sequence is scrambled with PRBS13, where 0 ≤ i < 8. The corresponding FAS sequence in the pad sequence is obtained by multiplexing the pad codewords bit by bit as follows: 01011001 01010010 01100100 1010011010101101 10011011, where the leftmost bit is the first bit transmitted and the rightmost bit is the last bit transmitted.

[0389] Example 3: Consider a 1.6TBASE-R transmission scenario, where p = 8 and t = 2, i.e., q = 2 × p = 16.

[0390] Example 3 is based on Example 1, processing the first data stream using the second data processing method. Specifically, the processing of the first data stream uses the scheme shown in Figure 12A or Figure 12B. The convolutional interleaving, block distribution (taking S=8 as an example), and internal code encoding schemes in the second data processing method used in Example 3 are consistent with those in Example 1 and will not be repeated. Correspondingly, an 8:1 bit-pair interleaving (or bit-pair multiplexing) method is used to interleave every 8 third data streams to obtain a sixth data stream, corresponding to f=8 in Figure 9. It should be noted that the 8 third data streams input to the 8:1 bit-pair interleaving are obtained by block distribution and internal code encoding of a convolutionally interleaved data stream. Using the scheme shown in Figure 11, a 1024-bit pad sequence is inserted after every H=8704 internal codewords in each of the sixth data streams, with the first pad sequence inserted before the start of the internal codeword. The data pad length is 960 bits. The specific sequence corresponding to m_i<119:114> in Figure 10 can be found in Table 6. m_i<113:0> is the sequence after the all-zero sequence is scrambled with PRBS13, where 0≤i<8. The pad codeword is then multiplexed using an 8:1 bit pair as shown in Figure 9 to obtain the FAS sequence in the pad sequence: 01011001 01010010 01100100 10100110 10101101 10011011, where the leftmost bit is the first bit transmitted and the rightmost bit is the last bit transmitted. Finally, the two fourth data streams after the pad insertion are multiplexed using an α bit pair in a 1:2 ratio to obtain a seventh data stream. Better performance in resisting colored noise can be obtained when α = 1 or α = 8, 16, 32, 64, 128, 256, or 512.

[0391] As an example, when two fourth data streams are multiplexed 1:2 using bit pairs of α to obtain a seventh data stream, corresponding to α = 8, 16, 32, 64, 128, 256, 512, the 16 corresponding second data streams can be cyclically shifted using any of the methods in Table 1, which maximizes the spacing between bit pairs from the same external codeword in the seventh data stream. As another example, when α = 1, to ensure the concatenated code has good resistance to colored noise, the 16 corresponding second data streams can be cyclically shifted using any of the methods in Table 7, which also maximizes the spacing between bit pairs from the same external codeword in the seventh data stream.

[0392] Example 4: Consider a 1.6TBASE-R transmission scenario, where p = 8 and t = 2, i.e., q = 2 × p = 16.

[0393] Example 4 modifies the block distribution of Example 3 to a 1:4 block distribution. Taking S=4 as an example, the corresponding bit pair interleaving is 4:1. The processing of the first data stream in Example 4 uses the second data processing method. That is, the processing of the first data stream uses the scheme shown in Figure 12A or Figure 12B. The convolutional interleaving and internal code encoding schemes in the second data processing method used in Example 4 are consistent with those in Example 3 and will not be repeated. When performing pad sequence insertion, the scheme shown in Figure 11 is used. A 512-bit pad sequence is inserted after every H=4352 internal codewords in each interleaved data stream, and the first pad sequence is inserted before the start of the internal codeword. For example, the data pad length is 480 bits. The specific sequence corresponding to m_i<119:108> in Figure 10 is shown in Table 5. m_i<108:0> is the sequence after the all-zero sequence is scrambled by PRBS13, where 0≤i<4. The corresponding FAS sequence in the pad sequence is obtained by multiplexing the pad codewords using a 4:1 bit pair as shown in Figure 9: 01011001 01010010 01100100 10100110 10101101 10011011, where the leftmost bit is the first bit transmitted and the rightmost bit is the last bit transmitted. Finally, the two data streams after the pad insertion sequence are multiplexed using an α bit pair in a 1:2 ratio to obtain a seventh data stream. Good resistance to colored noise can be obtained when α = 1 or α = 4, 8, 16, 32, 64, 128, or 256.

[0394] For example, when two fourth data streams are multiplexed 1:2 using bit pairs with α=1 to obtain a seventh data stream, in order to ensure that the concatenated code has good resistance to colored noise, the cyclic shift of the corresponding eight second data streams can adopt any of the schemes shown in Table 8, which can maximize the distance between bit pairs from the same external codeword in the seventh data stream. For example, when α=4, 8, 16, 32, 64, 128, 256, the cyclic shift of the corresponding eight second data streams can adopt any of the schemes shown in Table 2, which can maximize the distance between bit pairs from the same external codeword in the seventh data stream.

[0395] Example 5: Consider 800GBASE-R transmission, p=4 and q=4×8=32.

[0396] The transmitting processing module 02 receives four AUI data streams from 800GAUI-4 and performs PAM4 decoding on them to obtain p = four fifth data streams. Following the scheme shown in Figure 14B, Figure 14C, or Figure 14F, the four fifth data streams undergo third data processing to obtain four RS FEC 4-symbol delimited first data streams. Specifically, when the four fifth data streams undergo third data processing according to the scheme shown in Figure 14F to obtain four RS FEC 4-symbol delimited first data streams, g = 1. In one approach, the first data processing method can be applied to every two first data streams according to the processing scheme of either Example 1 or Example 2 to obtain one fourth data stream, resulting in a total of two fourth data streams. In another approach, the second data processing method can be applied to every two first data streams according to the processing scheme of either Example 3 or Example 4 to obtain one seventh data stream, resulting in a total of two seventh data streams.

[0397] For example, the convolutional interleaver described in Example 5 can adopt the scheme shown in Figure 5A or Figure 5B, where r = 3 delay lines, the difference in the number of storage units between any two adjacent delay lines is Q ≥ 46, and according to the obtained four-symbol boundary, each storage unit stores d = 40 bits, and the 40 bits stored in each storage unit correspond to 4 RS FEC symbols, i.e., one RS FEC four-symbol quartet. In the convolutional interleaved data stream output by the convolutional interleaving process, 12 consecutive (adjacent) RS FEC symbols come from 12 RS codewords, which allows the 120 information bits of each inner codeword to come from 12 RS codewords, giving the concatenated code better performance, and allowing Q = 48, while also reducing the system latency and enabling it to be used in a variety of transmission scenarios.

[0398] Example 6: Consider a 400GBASE-R transfer, where p = 2 and q = 2 × 8 = 16.

[0399] The transmitting processing module 02 receives two AUI data streams from 400GAUI-2 and performs PAM4 decoding on them to obtain p = 4 fifth data streams. Following the scheme shown in Figure 14B, 14C, or 14F, the two fifth data streams undergo third data processing to obtain two RS FEC 4-symbol delimited first data streams. Specifically, when the two fifth data streams undergo third data processing according to the scheme shown in Figure 14F to obtain two RS FEC 4-symbol delimited first data streams, g = 69. In one approach, the two first data streams can be processed using the first data processing method according to any one of Examples 1 or 2 to obtain a fourth data stream. In another approach, the two first data streams can be processed using the second data processing method according to any one of Examples 3 or 4 to obtain a seventh data stream.

[0400] For example, the convolutional interleaver in Example 6 adopts the scheme shown in Figure 5A or Figure 5B, where r = 3 delay lines, the difference in the number of storage units between any two adjacent delay lines is Q ≥ 91, and according to the obtained four-symbol boundary, each storage unit stores d = 40 bits, and the 40 bits stored in each storage unit correspond to 4 RS FEC symbols, i.e., one RS FEC four-symbol quartet. In the convolutional interleaved data stream output by the convolutional interleaving process, 12 consecutive (adjacent) RS FEC symbols come from 12 RS codewords, which allows the 120 information bits of each inner codeword to come from 12 RS codewords, giving the concatenated code better performance, and allowing Q = 96, while also reducing the system latency, making it suitable for a wider range of transmission scenarios.

[0401] Example 7: Consider a 3.2TBASE-R transfer, where p = 16 and q = 2 × 16 = 32.

[0402] The transmitting processing module 02 receives 16 AUI data streams of 3.2TAUI-16 and performs PAM4 decoding on them to obtain p = 16 fifth data streams. Following the scheme shown in Figure 14B, 14D, or 14E, the 16 fifth data streams undergo third data processing to obtain 16 RS FEC 4-symbol delimited first data streams. In one approach, every two first data streams can be processed using the first data processing method according to any of the examples in Example 1 or 2 to obtain a fourth data stream, for a total of 8 fourth data streams. In another approach, every two first data streams can be processed using the second data processing method according to any of the examples in Example 3 or 4 to obtain a seventh data stream, for a total of 8 seventh data streams.

[0403] For example, the convolutional interleaver in Example 7 adopts the scheme shown in Figure 5A or Figure 5B, where r = 3 delay lines, the difference in the number of storage units between any two adjacent delay lines is Q ≥ 12, and according to the obtained four-symbol boundary, each storage unit stores d = 40 bits, and the 40 bits stored in each storage unit correspond to 4 RS FEC symbols, i.e., one RS FEC four-symbol quartet. In the convolutional interleaved data stream output by the convolutional interleaving process, 12 consecutive (adjacent) RS FEC symbols come from 12 RS codewords, which allows the 120 information bits of each inner codeword to come from 12 RS codewords, giving the concatenated code better performance, and allowing Q = 12 or 16, while also reducing the system latency and enabling it to be used in a variety of transmission scenarios.

[0404] Referring to Figure 15, which is a schematic flowchart of another data processing method according to an embodiment of this application, Figure 15 is the reverse process of the flow described in Figure 4B. The corresponding description can be found in the relevant description of the embodiment corresponding to Figure 4B. The receiving end processing module performs bit-pair deinterleaving on a fourth data stream to obtain 2*S third data streams; the 2*S third data streams are then subjected to second data inverse processing to obtain 2*S second data streams; the second data inverse processing includes internal code decoding (inverse processing of internal code encoding) and cyclic shifting; the 2*S second data streams are then subjected to first data inverse processing (inverse processing of first data processing) to obtain 2 first data streams, both of which are encoded using external codes. The first data inverse processing includes block merging, wherein every S second data stream blocks in the 2*S second data streams are merged into one first data stream.

[0405] In one possible implementation, the method further includes: deleting the pad sequence from the data stream that has been pad-inserted to obtain the fourth data stream.

[0406] In one possible implementation, the second data inverse processing also includes convolution deinterleaving (the inverse processing of convolution interleaving).

[0407] It should be noted that in the relevant embodiment in Figure 4B, when the cyclic shift uses a left cyclic shift, the reverse processing in Figure 15 uses a right cyclic shift; conversely, if in the relevant embodiment in Figure 4B, the cyclic shift uses a right cyclic shift, the reverse processing in Figure 15 uses a left cyclic shift.

[0408] Referring to Figure 16, which is a schematic flowchart of another data processing method according to an embodiment of this application, Figure 15 is the reverse process of the flow described in Figure 12B. The corresponding description can be found in the relevant description of the embodiment corresponding to Figure 12B. The receiving end processing module performs bit-to-bit demultiplexing on a seventh data stream to obtain two sixth data streams; it then performs bit-to-bit deinterleaving on the two sixth data streams to obtain 2*S third data streams, each sixth data stream being deinterleaved into S third data streams; the 2*S third data streams undergo a second data processing inverse process to obtain 2*S second data streams, the second data inverse process including internal code decoding and cyclic shifting; the 2*S second data streams undergo a first data inverse process to obtain two first data streams; both first data streams are encoded using external codes, the first data inverse process including block merging, where S second data streams from the same sixth data stream are quickly merged into one first data stream.

[0409] In one possible implementation, the method further includes: before performing bit-pair deinterleaving on the two sixth data streams to obtain 2*S third data streams, performing pad sequence deletion (the inverse process of pad sequence insertion) on the two sixth data streams.

[0410] In one possible implementation, the second data inverse processing also includes convolution deinterleaving.

[0411] It should be noted that in the relevant embodiment in Figure 12B, when the cyclic shift uses a left cyclic shift, the reverse processing in Figure 16 uses a right cyclic shift; conversely, if in the relevant embodiment in Figure 12B, the cyclic shift uses a right cyclic shift, the reverse processing in Figure 16 uses a left cyclic shift.

[0412] This application also provides a data processing apparatus, which can be a transmitting device or a component (or module) used in a transmitting device. The apparatus includes multiple units for implementing any of the data processing methods shown in Figures 4A-14F.

[0413] In one possible embodiment, referring to FIG17, the data processing device may include a first processing unit 1701, a second processing unit 1702, and a bit-pair interleaving unit 1703. The first processing unit 1701 is used to perform first data processing on two first data streams to obtain 2*S second data streams. Both first data streams are encoded using an external code, and the first data processing includes block distribution, whereby each first data stream is block-distributed into S second data streams. The second processing unit 1702 is used to perform second data processing on the 2*S second data streams respectively to obtain 2*S third data streams, where the second data processing includes cyclic shifting and internal code encoding. The bit-pair interleaving unit 1703 is used to interleave the 2*S third data streams bit pairs into a fourth data stream. The specific data processing method has been described in detail in the previous embodiments and will not be repeated here.

[0414] In one possible implementation, a pad insertion unit (not shown in the figure) is also included for performing pad sequence insertion on the fourth data stream to obtain a pad-inserted data stream.

[0415] In one possible implementation, the pad insertion unit is specifically used to: insert the pad sequence into the fourth data stream every H internal codewords; where f = 8, H = 8704, or f = 16, H = 17408. The above provides two possible pad insertion methods.

[0416] In one possible implementation, it further includes: a third processing unit (not shown in the figure) for performing third data processing on the two fifth data streams to obtain the two first data streams, wherein the third data processing includes alignment flag locking; wherein the two fifth data streams are both encoded with external codes.

[0417] In one possible implementation, the third processing unit is specifically used for:

[0418] Symbol demultiplexing is performed on each of the two fifth data streams to obtain 2*t demultiplexed data streams. Each fifth data stream is demultiplexed into t demultiplexed data streams.

[0419] Alignment identifier locking is performed on the 2*t demultiplexed data streams respectively to obtain 2*t channel data streams with alignment identifier locking;

[0420] Deskipation processing is performed on 2*t channel data streams;

[0421] Symbol multiplexing is performed on each t channel data stream in the 2*t channel data streams after deskipation to obtain the two first data streams; wherein each t channel data stream comes from the same fifth data stream.

[0422] By employing the above scheme, aligning and locking before de-skewing can further improve the performance of concatenated codes.

[0423] In one possible implementation, the third processing unit is further configured to:

[0424] Before multiplexing the symbol pairs of every 2*t channel data streams after deskipation, the odd-numbered channel data streams indicated by the unique marker (UM) information in the 2*t channel data streams after deskipation are delayed by g symbols.

[0425] In each of the fifth data streams, four consecutive symbols originate from four codewords encoded by the external code; the alignment markers of any two channels in the 2*t channel data streams after de-skewing are skewed by D*136 symbols, where D is an integer greater than or equal to 0. This applies when p=2, g=69, or when p=4, g=1.

[0426] In another possible embodiment, referring to FIG18, the data processing device may include a first processing unit 1801, a second processing unit 1802, a bit-pair interleaving unit 1803, and a bit-pair multiplexing unit 1804. The first processing unit 1801 performs first data processing on two first data streams respectively to obtain 2*S second data streams; the first data streams are all encoded using an external code, and the first data processing includes block distribution, with each first data stream being block-distributed into S second data streams. The second processing unit 1802 performs second data processing on the 2*S second data streams respectively to obtain 2*S third data streams; the second data processing includes cyclic shifting and internal code encoding. The bit-pair interleaving unit 1803 interleaves the bit pairs of the 2*S third data streams into two sixth data streams. The bit-pair multiplexing unit 1804 multiplexes the bit pairs of the two sixth data streams into a seventh data stream.

[0427] In one possible implementation, it further includes a pad insertion unit (not shown in the figure) for inserting a pad sequence into the two sixth data streams before bit multiplexing the two sixth data streams.

[0428] In one possible implementation, the pad insertion unit is specifically used to: insert the pad sequence into the sixth data stream every H internal codewords;

[0429] Where f = 8, H = 8704, or f = 4, H = 4352.

[0430] In one possible implementation, it further includes: a third processing unit (not shown in the figure), used for:

[0431] The two fifth data streams are subjected to third data processing to obtain the two first data streams. The third data processing includes alignment flag locking. Both fifth data streams are encoded with external codes.

[0432] In one possible implementation, the third processing unit is specifically used for:

[0433] Symbol demultiplexing is performed on each of the two fifth data streams to obtain 2*t demultiplexed data streams. Each fifth data stream is demultiplexed into t demultiplexed data streams.

[0434] Alignment identifier locking is performed on the 2*t demultiplexed data streams respectively to obtain 2*t channel data streams with alignment identifier locking;

[0435] Deskipation processing is performed on 2*t channel data streams;

[0436] Symbol multiplexing is performed on each of the 2*t channel data streams after deskipation to obtain the two first data streams; wherein each t channel data stream comes from the same fifth data stream.

[0437] In one possible implementation, the third processing unit is further configured to:

[0438] Before multiplexing symbol pairs of every 2*t channel data stream after deskipation, the odd-numbered channel data streams in the deskipated 2*t channel data streams are delayed by g symbols; when p=2, g=69, or when p=4, g=1.

[0439] The specific data processing methods described above have been described in detail in the previous embodiments and will not be elaborated here.

[0440] This application also provides a data processing apparatus, which can be a receiving device or a receiving processing module. The apparatus includes multiple units for implementing the data processing method described in FIG. 15.

[0441] Referring to Figure 19, the device includes:

[0442] Bit-to-deinterleaving unit 1901 is used to deinterleave one fourth data stream to obtain 2*S third data streams. Second inverse processing unit 1902 is used to perform second data inverse processing on each of the 2*S third data streams to obtain 2*S second data streams; the second data inverse processing includes internal code decoding and cyclic shifting. First inverse processing unit 1903 is used to perform first data inverse processing on the 2*S second data streams to obtain two first data streams, both of which are encoded with external codes. The first data inverse processing includes block merging, wherein every S blocks of the 2*S second data streams are merged into one first data stream.

[0443] In one possible implementation, it further includes a pad sequence deletion unit (not shown in the figure) for deleting the pad sequence in the data stream that has been inserted by pad to obtain the fourth data stream.

[0444] In one possible implementation, the pad sequence deletion unit is specifically used for:

[0445] Delete the pad sequence after every H internal codewords in the data stream inserted by pad;

[0446] Where f = 8, H = 8704, or f = 16, H = 17408.

[0447] In one possible implementation, the bit-pair deinterleaving unit 1901 is specifically used for:

[0448] The bit pairs are deinterleaved for p / 2 fourth data streams, where p is an integer multiple of 2.

[0449] The specific data processing methods described above have been described in detail in the previous embodiments and will not be elaborated here.

[0450] This application also provides a data processing apparatus, which can be a receiving device or a receiving processing module. The apparatus includes multiple units for implementing the data processing method described in FIG20.

[0451] Referring to Figure 20, the device includes:

[0452] Bit-to-demultiplexing unit 2001 is used to demultiplex a seventh data stream to obtain two sixth data streams. Bit-to-deinterlegging unit 2002 is used to deinterleave the two sixth data streams to obtain 2*S third data streams, each sixth data stream being deinterleaved into S third data streams; second inverse processing unit 2003 is used to perform second data processing inverse processing on the 2*S third data streams to obtain 2*S second data streams, the second data inverse processing including internal code decoding and cyclic shifting; first inverse processing unit 2004 is used to perform first data inverse processing on the 2*S second data streams to obtain two first data streams; both first data streams are encoded with external codes, the first data inverse processing includes block merging, where S second data streams from the same sixth data stream are quickly merged into one first data stream.

[0453] In one possible implementation, it further includes a pad sequence deletion unit (not shown in the figure), used to perform pad sequence deletion on the two sixth data streams before performing bit pair deinterleaving on the two sixth data streams to obtain 2*S third data streams.

[0454] In one possible implementation, the pad sequence deletion unit is specifically used for:

[0455] Delete the pad sequence after every H internal codewords in the sixth data stream;

[0456] Where f = 8, H = 8704, or f = 4, H = 4352.

[0457] The specific data processing methods described above have been described in detail in the previous embodiments and will not be elaborated here.

[0458] It should be understood that the data processing apparatus provided in this application can also be implemented in other ways. For example, the unit division in the above apparatus is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system. In addition, the functional units in the various embodiments of this application may be integrated into one processing unit, or they may be independent physical units, or two or more functional units may be integrated into one processing unit. The integrated units described above can be implemented in hardware or as software functional units.

[0459] Figure 21 is a schematic diagram of an optical module in one embodiment of this application. As shown in Figure 21, the optical module includes a processor 2101 and an interface 2102. The processor 2101 is used to execute the operations performed by the data processing device in the above embodiment. The interface 2102 can be a transceiver or an input / output interface. The interface 2102 is used to receive signals from other devices and transmit them to the processor 2101 or to send signals from the processor 2101 to other devices. As an example, after the processor 2101 performs the internal code encoding process to obtain an encoded data stream, it sends the encoded data stream through the interface 2102. In this example, the interface 2102 can specifically refer to an electrical interface. As another example, after the processor 2101 performs the internal code encoding process to obtain an encoded data stream, it performs symbol mapping to obtain a symbol stream to be transmitted. The modulator in the optical module performs signal processing such as electro-optic conversion according to the symbol stream to be transmitted to obtain an optical signal, and then sends the optical signal through the interface 2102. In this example, the interface 2102 can specifically refer to an optical interface. Optionally, the optical module may also include a memory 2103, wherein the memory 2103 is used to store program instructions and / or data.

[0460] Typically, an optical module consists of optoelectronic devices, a processor, and an interface. The optoelectronic devices include transmitting and receiving devices. The transmitting end of the optical module converts electrical signals into optical signals and transmits them through optical fibers. The receiving end of the optical module receives the optical signals and converts them back into electrical signals.

[0461] It should be noted that the types of optical modules in this application embodiment include, but are not limited to, normal optical modules, near package optics (NPO) modules, and co-packaged optics (CPO) modules. Normal optical modules can perform functions including, but not limited to, digital signal processing (DSP) and clock data recovery (CDR). For example, a normal optical module converts analog signals to digital signals, performs DSP on the digital signals, and then converts them back to analog signals before sending them to the host device. Because DSP requires retiming, a normal optical module can also be called a retimed module. Normal optical modules connect to the host device via an attachment unit interface (AUI). NPO and CPO modules do not have pluggable physical packaging and are closer to the host device. NPO and CPO modules can also be called optical engines. NPO or CPO technology is a technology that "packages" the host device (or host chip) and the optical engine. When NPO technology is used to encapsulate the host-side device and the optical engine, the optical engine can be called an NPO module. When CPO technology is used to encapsulate the host-side device and the optical engine, the optical engine can be called a CPO module.

[0462] Figure 22 is a schematic diagram of a communication device according to an embodiment of this application. As shown in Figure 22, the communication device includes a host-side device 2201 and an optical module 2202. The host-side device 2201 is used to send data to the optical module 2202, and the optical module 2202 generates an optical signal based on the data sent by the host-side device 2201 and transmits the optical signal through a channel. For example, the host-side device may specifically be a switch, router, or server. This communication device can be a communication device including the host-side device 2201 and the optical module 2202.

[0463] This application also provides an Optical Transport Network (OTN) device, which includes line-side equipment and client-side equipment. The client-side equipment may also be referred to as a tributary-side equipment in some scenarios. The line-side equipment includes a processor and an interface. The processor is used to execute the data processing methods described in the above embodiments. The interface can be a transceiver or an input / output interface, used to receive signals from other devices outside the line-side equipment and transmit them to the processor, or to send signals from the processor to other devices outside the line-side equipment.

[0464] This application also provides a chip. The chip integrates circuitry for implementing the functions of the aforementioned processor and one or more interfaces. As an example, the chip integrates a memory. As another example, when the chip does not integrate a memory, it can be connected to an external memory via the interface. The chip can perform the method steps of any one or more of the foregoing embodiments. Alternatively, the chip can implement the actions performed by the data processing device in the foregoing embodiments based on program code stored in the memory.

[0465] As an example, the chip in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, any conventional processor, or a processing circuit that implements a specific function.

[0466] This application also provides a computer-readable storage medium, including a program or instructions that, when executed on a computer, cause the data processing method as described in the above embodiments to be implemented.

[0467] It should be understood that the processor mentioned in the embodiments of this application can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc. When implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. The memory can exist independently and be connected to the processor, or the memory can be integrated with the processor.

[0468] As an example, the processor in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, any conventional processor, or a processing circuit that implements a specific function.

[0469] In embodiments of this application, the memory may be random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium may also be a component of the processor. The processor and storage medium may reside in an ASIC. Additionally, the ASIC may reside in a network device or a terminal device. Alternatively, the processor and storage medium may exist as discrete components in the network device or terminal device.

[0470] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof.

[0471] When implemented in hardware, the data processing method provided in this application embodiment may be implemented without reading software code or instructions. For example, it may be implemented by CPU, DSP, ASIC, FPGA, other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0472] When implemented using software, it can be implemented entirely or partially in the form of a computer program product. A computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, all or part of the processes or functions of the embodiments of this application are performed. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a terminal device, or other programmable device. The computer program or instructions can be stored in or transmitted through a computer-readable storage medium. The computer-readable storage medium can be any available medium that a computer can access, or a data storage device such as a server that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a Digital Versatile Disc (DVD); or it can be a semiconductor medium, such as a solid-state disk (SSD).

[0473] Finally, it should be noted that the above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data processing method, characterized in that, include: Perform first data processing on the two first data streams respectively to obtain 2*S second data streams; S is an integer greater than 1. Both first data streams are encoded using an external code. The first data processing includes block distribution, and each first data stream is distributed into S second data streams. The 2*S second data streams are processed to obtain 2*S third data streams. The second data processing includes cyclic shifting and internal code encoding. The 2*S third data stream bit pairs are interleaved into a fourth data stream.

2. The method as described in claim 1, characterized in that, The S = 4 or S = 8.

3. The method as described in claim 1 or 2, characterized in that, The method further includes: performing pad sequence insertion on the fourth data stream to obtain a data stream with pad insertion.

4. The method as described in claim 3, characterized in that, The codeword length of the internal code encoding is N bits, where N = 128, and the information length of the codeword is K bits, where K = 120.

5. The method as described in claim 4, characterized in that, Performing pad sequence insertion on the fourth data stream includes: The pad sequence is inserted into the fourth data stream at intervals of H internal codewords; Where f = 8, H = 8704, or f = 16, H = 17408.

6. The method as described in claim 4 or 5, characterized in that, The pad sequence comprises f groups, where f = 8, and each of the f groups comprises 128 bits. The pad_cw_i<127:122> values ​​for the f groups are: Where 0≤i<8, pad_cw_i<127:122> represents bits 122 to 127 of group i in the f groups.

7. The method as described in claim 4 or 5, characterized in that, The pad sequence comprises f blocks, where f = 16, and each of the f blocks comprises 128 bits. The pad_cw_i of the f blocks... <n-1:x>The value can be: Where 0≤i<16, and when 0≤i<8, x=124; when 8≤i<16, x=126; pad_cw_i<127:x> represents bits x to 127 of group i in f groups.

8. The method according to any one of claims 1-7, characterized in that, The method further includes: The two fifth data streams are subjected to third data processing to obtain the two first data streams. The third data processing includes alignment flag locking. Both fifth data streams are encoded with external codes.

9. The method as described in claim 8, characterized in that, Perform third data processing on the two fifth data streams, including: Symbol demultiplexing is performed on each of the two fifth data streams to obtain 2*t demultiplexed data streams. Each fifth data stream is demultiplexed into t demultiplexed data streams. Alignment identifier locking is performed on the 2*t demultiplexed data streams respectively to obtain 2*t channel data streams with alignment identifier locking; Deskipation processing is performed on 2*t channel data streams; Symbol multiplexing is performed on each t channel data stream in the 2*t channel data streams after deskipation to obtain 2 first data streams; each t channel data stream comes from the same fifth data stream.

10. The method as described in claim 9, characterized in that, The first data streams are processed separately, including: The first data processing is performed on every two first data streams in the obtained p first data streams, where p is an integer multiple of 2.

11. The method as described in claim 10, characterized in that, p = 8 or p = 16, t = 2, the symbol demultiplexing adopts four-symbol demultiplexing, and the symbol multiplexing adopts four-symbol multiplexing.

12. The method as described in claim 10, characterized in that, p=2 or p=4, t=8, the symbol demultiplexing adopts symbol pair demultiplexing, and the symbol multiplexing adopts symbol pair multiplexing.

13. The method as described in claim 10 or 12, characterized in that, The method further includes: Before symbol pair multiplexing of every 2*t channel data streams after de-skewing processing, delay the odd-channel data streams in the 2*t channel data streams after de-skewing processing by g symbols; when p = 2, g = 69, or when p = 4, g = 1.

14. The method according to any one of claims 1-13, characterized in that, The first data processing further includes convolutional interleaving.

15. The method according to any one of claims 1-14, characterized in that, The number of symbols for cyclic shift of the nth second data stream from different first data streams is the same, 0 ≤ n < S, and the number of symbols for cyclic shift of the S second data streams from the same first data stream is different.

16. The method according to any one of claims 1-14, characterized in that, S = 4, and the number of symbols for cyclic shift of any two of the 2*S second data streams is different.

17. The method according to any one of claims 1-14, characterized in that, The cyclic shifting of the S=8, 2*S second data streams is performed in the manner described in any row of the following table: Among them, the second data stream m represents the mth data stream among 16 second data streams, m = {0, 1, 2,..., 15}, and the data c in the yth column represents that every consecutive 12 symbols in the corresponding second data stream m are circularly shifted to the right by c symbols, or the data c in the yth column represents that every consecutive 12 symbols in the corresponding second data stream m are circularly shifted to the left by 12 - c symbols, where 1 ≤ y ≤ 16.

18. The method according to any one of claims 1-14, characterized in that, Where S = 4, the cyclic shifting of the 2*S second data streams is performed in the manner described in any row of the following table: Among them, the second data stream m represents the mth data stream among 8 second data streams, m = {0, 1, 2,..., 7}, and the data c in the yth column represents that every consecutive 12 symbols in the corresponding second data stream m are circularly shifted to the right by c symbols, or the data c in the yth column represents that every consecutive 12 symbols in the corresponding second data stream m are circularly shifted to the left by 12 - c symbols, where 1 ≤ y ≤ 8.

19. The method according to any one of claims 1-18, characterized in that, The nominal rate of the first data stream is 212.5 G bits per second (b / s).

20. A data processing method, characterized in that, The method includes: Obtain a fourth data stream, which is obtained by bit pair interleaving 2*S third data streams. The 2*S third data streams are respectively obtained by performing second data processing on 2*S second data streams. The second data processing includes cyclic shift and inner code encoding. The 2*S second data streams are obtained by performing first data processing on 2 first data streams. Both of the 2 first data streams have undergone outer code encoding. The first data processing includes block distribution. Among them, each of the first data streams is distributed into S second data streams through block distribution, and S is an integer greater than 1.

21. The method as described in claim 20, characterized in that, S = 4 or S = 8.

22. A data processing apparatus, characterized in that, Includes: A first processing unit for respectively performing first data processing on 2 first data streams to obtain 2*S second data streams; S is an integer greater than 1. Both of the 2 first data streams have undergone outer code encoding. The first data processing includes block distribution. Each of the first data streams is distributed into S second data streams through block distribution; A second processing unit for respectively performing second data processing on the 2*S second data streams to obtain 2*S third data streams. The second data processing includes cyclic shift and inner code encoding; A bit pair interleaving unit for bit pair interleaving the 2*S third data streams into a fourth data stream.

23. The apparatus as claimed in claim 22, characterized in that, S = 4 or S = 8.

24. The apparatus as claimed in claim 22 or 23, characterized in that, The device further includes: A pad insertion unit for performing pad sequence insertion on the fourth data stream to obtain a data stream after pad insertion.

25. The apparatus as claimed in claim 24, characterized in that, The codeword length of the inner code encoding is N bits, N = 128, and the information length of the codeword of the inner code encoding is K bits, K = 120.

26. The apparatus as claimed in claim 25, characterized in that, The pad insertion unit is specifically configured to: Insert the pad sequence into every H inner code codewords in the fourth data stream; Where, f = 8, H = 8704, or f = 16, H = 17408.

27. The apparatus as claimed in claim 25 or 26, characterized in that, The pad sequence comprises f groups, where f = 8, and each of the f groups comprises 128 bits. The pad_cw_i<127:122> values ​​for the f groups are: Where, 0 ≤ i < 8, pad_cw_i<127:122> represents bits 122 to 127 of group i in f groups.

28. The apparatus as claimed in claim 25 or 26, characterized in that, The pad sequence comprises f blocks, where f = 16, and each of the f blocks comprises 128 bits. The pad_cw_i of the f blocks... <n-1:x>The value can be: Where 0 ≤ i < 16, and when 0 ≤ i < 8, x = 124; when 8 ≤ i < 16, x = 126; pad_cw_i<127:x> represents bits x to 127 of group i in f groups.

29. The apparatus according to any one of claims 22-27, characterized in that, It further includes: A third processing unit, configured to perform third data processing on 2 fifth data streams to obtain the 2 first data streams, and the third data processing includes alignment flag locking; wherein, the 2 fifth data streams have both undergone outer code encoding.

30. The apparatus as claimed in claim 29, characterized in that, The third processing unit is specifically configured to: Perform symbol demultiplexing on each of the 2 fifth data streams respectively to obtain 2*t demultiplexed data streams, and each fifth data stream is demultiplexed into t demultiplexed data streams through the symbol demultiplexing; Perform alignment identification locking processing on the 2*t demultiplexed data streams respectively to obtain 2*t channel data streams with alignment identification locked; Perform de-skewing processing on the 2*t channel data streams; Perform symbol multiplexing on every t channel data streams among the 2*t channel data streams after de-skewing processing to obtain 2 of the first data streams; the every t channel data streams come from the same fifth data stream.

31. The apparatus as claimed in claim 30, characterized in that, The first processing unit is specifically configured to: Perform the first data processing on every 2 of the p first data streams obtained respectively, and p is an integer multiple of 2.

32. The apparatus as claimed in claim 31, characterized in that, p = 8 or p = 16, t = 2, the symbol demultiplexing adopts four-symbol demultiplexing, and the symbol multiplexing adopts four-symbol multiplexing.

33. The apparatus as claimed in claim 31, characterized in that, p = 2 or p = 4, t = 8, the symbol demultiplexing adopts symbol-pair demultiplexing, and the symbol multiplexing adopts symbol-pair multiplexing.

34. The apparatus as claimed in claim 31 or 33, characterized in that, The third processing unit is further configured to: Before performing symbol-pair multiplexing on every 2*t channel data streams after de-skewing processing, delay the odd-channel data streams among the 2*t channel data streams after de-skewing processing by g symbols; when p = 2, g = 69, or when p = 4, g = 1.

35. The apparatus according to any one of claims 22-34, characterized in that, The first data processing further includes convolutional interleaving.

36. The apparatus according to any one of claims 22-35, characterized in that, The number of symbols for cyclic shift of the nth second data stream from different first data streams is the same, 0 ≤ n < S, and the number of symbols for cyclic shift of the S second data streams from the same first data stream is different.

37. The apparatus according to any one of claims 22-35, characterized in that, The S = 4, and the number of symbols for cyclic shift of any two of the 2*S second data streams is different.

38. The apparatus according to any one of claims 22-35, characterized in that, The cyclic shifting of the S=8, 2*S second data streams is performed in the manner described in any row of the following table: Wherein, the second data stream m represents the m-th data stream among 16 second data streams, m = {0, 1, 2, ..., 15}, and the data c in the y-th column represents the right circular shift of c symbols for every 12 consecutive symbols in the corresponding second data stream m, or the data c in the y-th column represents the left circular shift of 12-c symbols for every 12 consecutive symbols in the corresponding second data stream m, where 1 ≤ y ≤ 16.

39. The apparatus according to any one of claims 22-35, characterized in that, Where S = 4, the cyclic shifting of the 2*S second data streams is performed in the manner described in any row of the following table: Wherein, the second data stream m represents the m-th data stream among the 8 second data streams, m = {0, 1, 2, ..., 7}, and the data c in the y-th column represents the right circular shift of c symbols for every consecutive 12 symbols in the corresponding second data stream m, or the data c in the y-th column represents the left circular shift of 12-c symbols for every consecutive 12 symbols in the corresponding second data stream m, where 1 ≤ y ≤ 8.

40. The apparatus according to any one of claims 22-39, characterized in that, The nominal rate of the first data stream is 212.5 gigabits per second (b / s).

41. A chip, characterized in that, The chip is used to perform the method as described in any one of claims 1 to 19, or to perform the method as described in claim 20 or 21.

42. An optical module, characterized in that, The optical module includes a processor and an interface, the interface being used for transmitting and receiving signals, and the processor being used to perform the method as described in any one of claims 1 to 19, or to perform the method as described in claim 20 or 21.

43. A network device, characterized in that, The network device includes a host-side device and an optical module as described in claim 42; the optical module is used to convert electrical signals from the host-side device into optical signals and transmit the optical signals, or the optical module is used to convert received optical signals into electrical signals and transmit the electrical signals to the host-side device.

44. A communication system, characterized in that, It includes a plurality of network devices as described in claim 43, wherein the plurality of network devices are used to send optical signals to each other.

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