Dual-controller communication system and method, computer product and device, and storage medium

Abstract

The present application relates to a dual-controller communication system and method, a computer product and device, and a storage medium. The dual-controller communication system comprises a first controller and a second controller, wherein the first controller comprises a first processor and a first non-transparent bridge; the second controller comprises a second processor and a signal relay device; an input end of the first non-transparent bridge is connected to an output end of the first processor; an output end of the first non-transparent bridge is connected to an input end of the signal relay device; and an output end of the signal relay device is connected to an input end of the second processor. By using the system, the communication costs of the first controller and the second controller can be reduced, and the reliability of the system can be improved.

Description

Dual-controller communication systems, methods, computer products, devices, and storage media

[0001] Cross-reference to related applications

[0002] This application claims priority to Chinese Patent Application No. 202510181974.2, filed on February 19, 2025, entitled "Dual Controller Communication System, Method, Computer Product, Device and Storage Medium", the entire contents of which are incorporated herein by reference. Technical Field

[0003] This application relates to the field of computer technology, and in particular to a dual-controller communication system, method, computer product, device and storage medium. Background Technology

[0004] In today's world, data growth is exploding at an unprecedented rate, making rapid data transfer within data centers crucial for efficient information utilization. Data reliability is increasingly important, necessitating dual-controller redundant storage to enhance reliability. Current systems utilize dual-NTB (non-transparent bridge) dual-controller communication systems to ensure that if one controller fails, the other provides memory mirror redundancy, preventing service interruption and data loss. However, employing two non-transparent bridges leads to increased communication latency and system performance degradation. Summary of the Invention

[0005] Firstly, a dual-controller communication system is provided, the system comprising:

[0006] First controller and second controller:

[0007] The first controller includes a first processor and a first non-transparent bridge;

[0008] The second controller includes a second processor and a signal relay device;

[0009] The input of the first non-transparent bridge is connected to the output of the first processor, the output of the first non-transparent bridge is connected to the input of the signal relay device, and the output of the signal relay device is connected to the input of the second processor.

[0010] In one embodiment, the first non-transparent bridge includes a first sub-non-transparent bridge and a second sub-non-transparent bridge. The input of the first sub-non-transparent bridge is connected to the output of the first processor, the output of the first sub-non-transparent bridge is connected to the input of the second sub-non-transparent bridge, the output of the second sub-non-transparent bridge is connected to the input of a signal relay device, and the output of the signal relay device is connected to the input of the second processor.

[0011] In one embodiment, the first controller further includes a first memory, and the second controller further includes a second memory. The first memory is communicatively connected to the first processor and the first non-transparent bridge, respectively, and the second memory is communicatively connected to the second processor and the signal relay device, respectively.

[0012] In one embodiment, the first controller further includes a first driving module, and the second controller further includes a second driving module. The first driving module is communicatively connected to the first processor, and the second driving module is communicatively connected to the second processor. The first driving module and the second driving module are used to establish a mapping relationship between the first memory and the second memory.

[0013] In one embodiment, the first controller further includes a first communication module and a first cache module, and the second controller further includes a second communication module and a second cache module. The input terminal of the first communication module is connected to the output terminal of the first cache module, and the output terminal of the first communication module is connected to the input terminal of the first drive module.

[0014] The input terminal of the second communication module is connected to the output terminal of the second buffer module, and the output terminal of the second communication module is connected to the input terminal of the second driver module.

[0015] In one embodiment, the second controller further includes a slot for removably mounting a second opaque bridge to enable the replacement of a signal relay device using the second opaque bridge.

[0016] In one embodiment, in response to a notification from a first non-transparent bridge, the first controller retrieves target transmission data from a memory access queue on the first controller and sends the target transmission data to a signal relay device to transmit the target transmission data to the second controller via the signal relay device.

[0017] In one embodiment, the first sub-opaque bridge and the second sub-opaque bridge are two virtual sub-opaque bridges within a single physical opaque bridge.

[0018] In one embodiment, the first cache module is a cache memory in the first controller, and the second cache module is a cache memory in the second controller.

[0019] In one embodiment, the first communication module is a communication layer configured in the first controller, and the communication layer of the first controller is configured with an NVMe communication protocol stack and a link management program.

[0020] The second communication module is the communication layer configured in the second controller. The communication layer of the second controller is configured with the NVMe communication protocol stack and the link management program.

[0021] Secondly, a dual-controller communication method is provided, applied to the dual-controller communication system of the first aspect, the method comprising:

[0022] In response to the first controller receiving a data transmission instruction, which includes transmitting data, it is determined whether a signal relay device is set on the second controller;

[0023] In response to the setting of a signal relay device on the second controller, the first target transmission path corresponding to the transmitted data is determined based on the first non-transparent bridge and the signal relay device;

[0024] In response to the absence of a signal relay device on the second controller, determine whether a second non-transparent bridge is configured on the second controller;

[0025] In response to setting a second non-transparent bridge on the second controller, a second target transmission path corresponding to the transmitted data is determined based on the first non-transparent bridge and the second non-transparent bridge; and

[0026] A fault warning is issued in response to the absence of a second non-transparent bridge on the second controller.

[0027] The first controller transmits the transmission data to the second controller based on the first target transmission path and / or the second transmission path.

[0028] In one embodiment, determining a first target transmission path corresponding to the transmitted data based on the first non-transparent bridge and the signal relay device, and the first controller transmitting the transmitted data to the second controller based on the first target transmission path includes:

[0029] In response to the first controller receiving a data transmission instruction, the system retrieves the transmission data from the first cache module and sends the transmission data to the first communication module.

[0030] In response to the first communication module receiving the transmitted data, the first communication module converts the transmitted data into a data sequence, performs protocol encapsulation on the data sequence to obtain the encapsulated data, and sends the encapsulated data to the first driver module;

[0031] In response to the first driver module receiving the encapsulated data, the first driver module stores the encapsulated data into the target data pair column; and

[0032] In response to the target data queue meeting preset conditions, the first driving module sends the target transmission data in the target data queue that meets the preset conditions to the memory access queue in the first memory;

[0033] The first driver module sends a notification to the first non-transparent bridge, and at the same time, the target transmission data in the memory access queue is sent to the first non-transparent bridge, and the management data in the first driver module is synchronized to the first non-transparent bridge.

[0034] The first non-transparent bridge sends the target transmission data to the signal relay device, which then transmits the target transmission data to the second memory.

[0035] In one embodiment, determining a second target transmission path corresponding to the transmitted data based on the first non-transparent bridge and the second non-transparent bridge, and the first controller transmitting the transmitted data to the second controller based on the second target transmission path includes:

[0036] In response to the first controller receiving a data transmission instruction, the system retrieves the transmission data from the first cache module and sends the transmission data to the first communication module.

[0037] In response to the first communication module receiving the transmitted data, the first communication module converts the transmitted data into a data sequence, performs protocol encapsulation on the data sequence to obtain the encapsulated data, and sends the encapsulated data to the first driver module;

[0038] In response to the first driver module receiving the encapsulated data, the first driver module stores the encapsulated data into the target data pair column; and

[0039] In response to the target data queue meeting preset conditions, the first driving module sends the target transmission data in the target data queue that meets the preset conditions to the memory access queue in the first memory;

[0040] The first driver module sends a notification to the first non-transparent bridge, and at the same time, the target transmission data in the memory access queue is sent to the first non-transparent bridge, and the management data in the first driver module is synchronized to the first non-transparent bridge.

[0041] The first non-transparent bridge sends the target data to the second non-transparent bridge, and the target data is then transferred to the second memory via the second non-transparent bridge.

[0042] In one embodiment, the method further includes:

[0043] In response to the second memory receiving the target transmission data, the second driver module sends a message to the first controller to inform it to start cache update based on the target transmission data;

[0044] The second controller polls the target transmission data in the second memory and synchronizes the target transmission data to the second communication module. The second communication module then synchronizes the target transmission data to the second cache module.

[0045] In response to the second controller confirming receipt of the target transmission data, a feedback message is sent to the first controller; and

[0046] In response to receiving a feedback message, the first controller synchronously sends feedback information to the first communication module.

[0047] In one embodiment, the first non-transparent bridge sends the target transmission data to the signal relay device, and the signal relay device transmits the target transmission data to the second memory, including:

[0048] In response to the first non-transparent bridge receiving a data read request protocol from the first node corresponding to the first controller, the data read request protocol is obtained and sent to the address translation register;

[0049] In response to the address translation register receiving a data read request protocol, the data read request protocol is parsed to obtain the protocol request address and the first node ID;

[0050] The protocol request address is converted to the target port address using the address translation register, and the first node ID is converted to the agent device ID.

[0051] Based on the proxy device ID, the data read request protocol and the target port address are sent to the proxy device in the second non-transparent sub-bridge. The proxy device converts the proxy device ID to obtain the target ID, and the target port converts the target ID to generate a matching ID, which is then matched with the first node ID.

[0052] The data read request protocol is forwarded to the target port based on the target port address.

[0053] In one embodiment, the first non-transparent bridge sends the target transmission data to the second non-transparent bridge, and the target transmission data is transferred to the second memory via the second non-transparent bridge, including:

[0054] In response to the first non-transparent bridge receiving a data read request protocol from the first node corresponding to the first controller, the data read request protocol is obtained and sent to the address translation register;

[0055] In response to the address translation register receiving a data read request protocol, the data read request protocol is parsed to obtain the protocol request address and the first node ID;

[0056] The protocol request address is converted to the target port address using the address translation register, and the first node ID is converted to the agent device ID.

[0057] Based on the proxy device ID, the data read request protocol and the target port address are sent to the proxy device in the second non-transparent bridge. The proxy device converts the proxy device ID to obtain the target ID, and the target port converts the target ID to generate a matching ID, which is then matched with the first node ID.

[0058] The data read request protocol is forwarded to the target port based on the target port address.

[0059] In one embodiment, after forwarding the data read request protocol to the target port based on the target port address, the method further includes:

[0060] Obtain the matching ID and the completed data protocol ID. The completed data protocol ID is the ID sent to the first node when the target port receives the data request protocol and completes.

[0061] Convert the matching ID and the completed data protocol ID into the first node ID; and

[0062] In response to converting the match ID and completion data protocol ID into the first node ID, the completion data protocol is forwarded to the first node.

[0063] Thirdly, a computer program product is provided, including computer-readable instructions that, when executed by a processor, implement the steps of the method described in the first aspect.

[0064] To address the aforementioned technical problems, a fourth aspect provides a computer device including a memory, a processor, and computer-readable instructions stored in the memory and executable on the processor, wherein the processor, when executing the computer-readable instructions, performs the following steps: the processor executes the steps of the method described in the first aspect.

[0065] Fifthly, this application provides a computer-readable storage medium having computer-readable instructions stored thereon, which, when executed by a processor, implement the steps of the method described in the first aspect. Attached Figure Description

[0066] Figure 1 is a schematic diagram of the structure of a dual-controller communication system in the prior art;

[0067] Figure 2 is a schematic diagram of another dual-controller communication system in the prior art;

[0068] Figure 3 is a schematic diagram of the structure of a dual-controller communication system in one or more embodiments;

[0069] Figure 4 is a schematic diagram of the dual-controller communication system in one or more other embodiments;

[0070] Figure 5 is a schematic diagram of the dual-controller communication system in one or more embodiments;

[0071] Figure 6 is a schematic diagram of the dual-controller communication system in one or more embodiments;

[0072] Figure 7 is a flowchart illustrating the dual-controller communication method in one or more embodiments;

[0073] Figure 8 is a flowchart illustrating the dual-controller communication method in one or more other embodiments;

[0074] Figure 9 is a flowchart illustrating the dual-controller communication method in one or more embodiments;

[0075] Figure 10 is a structural block diagram of a dual-controller communication device in one or more embodiments;

[0076] Figure 11 is an internal structure diagram of a computer device in one or more embodiments. Detailed Implementation

[0077] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0078] Please refer to Figure 1. In related technology one, the dual-controller communication system based on dual NTB (non-transparent bridge) includes a first cache module, a first driver module (NTB driver), a first processor (CPU), and a first non-transparent bridge (NTB) on controller 1, and a second cache module, a second driver module (NTB driver), a second processor (CPU), and a second non-transparent bridge (NTB) on controller 2.

[0079] By mounting a first non-transparent bridge and a second non-transparent bridge on the boards corresponding to the first controller and the second controller respectively, the first non-transparent bridge and the second non-transparent bridge can directly address the remote memory address (second controller memory) through the address translation mechanism. Through one of the methods of CPU and DMA (Direct Memory Access), the local memory data (data in the first controller memory) is copied to the remote memory (second controller memory), thereby realizing data communication.

[0080] Please refer to Figure 2. In related technology 2, the dual-controller communication system based on dual NTB (non-transparent bridge) includes a first cache module, a first cached communication module (communication layer), a first driver module (NTB driver), a first processor (CPU), and a first non-transparent bridge (NTB) on controller 1, and a second cache module, a second cached communication module (communication layer), a second driver module (NTB driver), a second processor (CPU), and a second non-transparent bridge (NTB) on controller 2.

[0081] In related technology two, a first communication module and a second communication module are respectively set on controller 1 and controller 2 to be responsible for the maintenance of communication links, assembly of NVMe protocol, and management of heartbeats. By onboarding a first non-transparent bridge and a second non-transparent bridge on the corresponding boards of the first and second controllers, respectively, the first and second non-transparent bridges can directly address the remote memory address (second controller memory) through an address translation mechanism. Through one of the methods of CPU and DMA (Direct Memory Access), the local memory data (data in the first controller memory) is copied to the remote memory (second controller memory), thereby realizing data communication.

[0082] As can be seen from the above, the relevant technologies mainly use two non-transparent bridges to realize communication between the two controllers. However, each time a non-transparent bridge is added, an address translation will be performed, which will lead to increased communication latency and degraded system performance.

[0083] To address the aforementioned technical problems, in one embodiment, this application provides a dual-controller communication system, which includes a first controller and a second controller.

[0084] The first controller includes a first processor and a first non-transparent bridge; the second controller includes a second processor and a signal relay device; the input terminal of the first non-transparent bridge is connected to the output terminal of the first processor, the output terminal of the first non-transparent bridge is connected to the input terminal of the signal relay device, and the output terminal of the signal relay device is connected to the input terminal of the second processor.

[0085] As shown in Figure 3, the first non-transparent bridge is the NTB card on controller 1, and the signal relay device is the Retimer card on controller 2.

[0086] A controller is a command device that controls the starting, speed regulation, braking, and reversing of a motor by changing the wiring of the main circuit or control circuit and changing the resistance value in the circuit according to a predetermined sequence. It consists of a program counter, instruction register, instruction decoder, timing generator, and operation controller. It is the "decision-making body" that issues commands, that is, it coordinates and directs the operation of the entire computer system.

[0087] Both the first and second processors are Central Processing Units (CPUs), serving as the core of a computer system for computation and control. They are the final execution units for information processing and program execution. Since their inception, CPUs have achieved tremendous development in logical structure, operating efficiency, and functional scope.

[0088] The communication between the two controllers here can be achieved by using a non-transparent PCIe bridge to connect the controllers. Specifically, it can be a non-transparent bridge NTB, which is a type of PCIe bridge chip that connects the independent memory systems of two or more computers to the same PCIe structure. It supports register and memory translation window functions.

[0089] In one embodiment, the first non-transparent bridge includes a first sub-non-transparent bridge and a second sub-non-transparent bridge. The input terminal of the first sub-non-transparent bridge is connected to the output terminal of the first processor, the output terminal of the first sub-non-transparent bridge is connected to the input terminal of the second sub-non-transparent bridge, the output terminal of the second sub-non-transparent bridge is connected to the input terminal of the signal relay device, and the output terminal of the signal relay device is connected to the input terminal of the second processor.

[0090] This application designs to implement two NTBs in the first non-transparent bridge using the Partition method. This is because a single non-transparent bridge cannot achieve a direct connection between the first processor and the second processor. Therefore, the Partition method is used to set up two virtual non-transparent bridges (a first sub-non-transparent bridge and a second sub-non-transparent bridge) in the first non-transparent bridge.

[0091] As shown in Figure 4, the area is divided into two regions using the Pattern method (partition 0 and partition 1). Partition 0 corresponds to the first non-transparent sub-bridge, and partition 1 corresponds to the second non-transparent sub-bridge. Node 0 can be the first processor, and node 1 can be the second processor. US P2P refers to PCI-to-PCI bridge, which is used to connect the PCI main bus and the PCI secondary bus. The PCI bus on which the PCI bridge is located is called the "main bus" (i.e., the parent bus of the secondary bus), and the PCI bus to which the bridge device is connected is called the "secondary bus" (i.e., the child bus of the main bus).

[0092] By setting up two virtual sub-transparent bridges on a physical non-transparent bridge, each sub-transparent bridge corresponds to a partition. Partition 0 corresponds to the first sub-non-transparent bridge, and partition 1 corresponds to the second sub-non-transparent bridge. In this way, a physical non-transparent bridge is used to connect the first processor and the second processor, and a physical non-transparent bridge is used to realize the connection between the two controllers.

[0093] A retimer card is a signal conditioning chip used for signal equalization and enhancement. Similar to a PHY chip, when a signal passes through the retimer card, its internal clock reconstructs the signal, increasing transmission power before continued transmission, thus improving the reliability of the server chassis system.

[0094] In this embodiment, the data transmission link is as follows: Controller 1 CPU data (first processor) -> NTB1 partition1 DMA (link between the first processor and the first sub-transparent bridge) -> NTB1 (NTB1 partition1 -> NTB1 partition2, link between the first sub-transparent bridge and the second sub-transparent bridge) -> NTB1 partition2 DMA (link between the second sub-transparent bridge and the signal relay device, from the signal relay device to the second processor) -> Controller 2 CPU data (second processor).

[0095] In another embodiment, as shown in FIG5, the first non-transparent bridge is the NTB card on controller 1, and the second non-transparent bridge is the NTB card on controller 2.

[0096] The input of the first non-transparent bridge is connected to the output of the first processor (CPU on controller 1), the output of the first non-transparent bridge is connected to the input of the second non-transparent bridge, and the output of the second non-transparent bridge is connected to the input of the second processor (CPU on controller 2).

[0097] In this embodiment, address translation is achieved through a first non-transparent bridge and a second non-transparent bridge, thereby enabling data transmission between the first controller and the second controller. In this embodiment, the data transmission link is as follows: Controller 1 CPU data (first processor) -> NTB1 DMA (link between the first processor and the first non-transparent bridge) -> NTB1 (first non-transparent bridge) -> NTB2 (second non-transparent bridge) -> NTB2 DMA (link between the second processor and the second non-transparent bridge) -> Controller 2 CPU data (second processor).

[0098] In the prior art, the first non-transparent bridge and the signal relay device are both onboard on the controller. In this application, a card slot is provided on the motherboard where the second controller is located. This card slot can be used to install the non-transparent bridge (NTB card) and the signal relay device (Retimer card), as shown in the figure. In this way, different combinations of the first non-transparent bridge and the signal relay device can be flexibly applied to realize the communication between the first controller and the second controller according to different needs.

[0099] This application, by setting up a card slot, enables the replacement of signal relay equipment with a second non-transparent bridge, which can flexibly meet the needs of users.

[0100] In one embodiment, referring to FIG6, the first controller further includes a first memory (memory on controller 1), and the second controller further includes a second memory (memory on controller 2). The first memory is communicatively connected to the first processor and the first non-transparent bridge, respectively, and the second memory is communicatively connected to the second processor and the signal relay device, respectively.

[0101] Memory plays multiple roles in a computer, primarily including storing and quickly accessing data, improving data processing efficiency, supporting multitasking, and accelerating the execution of specific applications. Memory is a crucial component of a computer, used to temporarily store data processed by the CPU, as well as data exchanged with external storage devices such as hard drives. It acts as a bridge between external storage and the CPU; all programs in a computer run within memory.

[0102] The first memory located on the first controller and the second memory located on the second controller in this application are configured to support the operation of the software modules in this application.

[0103] The first controller further includes a first driver module, and the second controller further includes a second driver module. The first driver module is communicatively connected to the first processor, and the second driver module is communicatively connected to the second processor. The first driver module and the second driver module are used to establish a mapping relationship between the first memory and the second memory.

[0104] The first and second driver modules can be NTB drivers. An NTB driver defines an API that encapsulates a set of general functions and allows clients interested in NTB functionality to discover NTB devices supported by the hardware driver. Here, "client" refers to the upper-layer component that calls the NTB API, while "driver" or "hardware driver" refers to the NTB hardware driver program specific to a particular manufacturer and model. The first and second driver modules are configured to support the transmission and reception management of the data link. Specifically, the driver modules are responsible for establishing the NTB channel, establishing memory mappings, and establishing a mapping relationship between the memory of controller 1 and controller 2. They are also responsible for establishing multiple DMA queues (circular queues) in memory, establishing command buffer queues, and managing devices, among other things.

[0105] The first controller further includes a first communication module and a first buffer module, and the second controller further includes a second communication module and a second buffer module. The input terminal of the first communication module is connected to the output terminal of the first buffer module, and the output terminal of the first communication module is connected to the input terminal of the first drive module. The input terminal of the second communication module is connected to the output terminal of the second buffer module, and the output terminal of the second communication module is connected to the input terminal of the second drive module.

[0106] The first cache module is the cache on controller 1, and the second cache module is the cache on controller 2. The cache module (Cache) is a memory hierarchy located between the processor CPU and memory. It is used to store the data and instructions recently accessed by the CPU. It improves system performance and response speed by reducing the number of memory accesses. The cache module is set up to be responsible for maintaining data management in the software. It can be a 4K contiguous page as the data management area.

[0107] The first communication module is the communication layer on controller 1, and the second communication module is the communication layer on controller 2. These modules are responsible for maintaining the communication link, assembling the NVMe protocol, and managing heartbeats. Specifically, this includes establishing login connections, recording login handles, establishing heartbeats for each physical port, sending data, establishing channel priorities, and serializing data objects, among other things.

[0108] Compared to the existing technology that uses two non-transparent bridges on the motherboard corresponding to the controller as a connection device to realize communication between the first controller and the second controller, this application sets a slot on the motherboard corresponding to the second controller to flexibly realize two non-transparent bridges as connection devices, or non-transparent bridges and signal relay devices as connection devices, which can flexibly meet different needs.

[0109] In one embodiment, as shown in FIG7, this application provides a dual-controller communication method applied to the above-mentioned dual-controller communication system. The method specifically includes the following steps:

[0110] Step 101: In response to the first controller receiving a data transmission instruction, the data transmission instruction includes transmitting data, and determining whether a signal relay device is set on the second controller.

[0111] Step 102: If a signal relay device is set on the second controller, then the first target transmission path corresponding to the transmitted data is determined based on the first non-transparent bridge and the signal relay device.

[0112] Step 103: If no signal relay device is set on the second controller, determine whether a second non-transparent bridge is set on the second controller.

[0113] Step 104: If a second non-transparent bridge is set on the second controller, then the second target transmission path corresponding to the transmitted data is determined based on the first non-transparent bridge and the second non-transparent bridge.

[0114] Step 105: If the second non-transparent bridge is not set on the second controller, a fault warning is issued.

[0115] Step 106: The first controller transmits the transmission data to the second controller based on the first target transmission path and / or the second transmission path.

[0116] Specifically, when configuring the dual-controller communication system, this application determines whether a signal relay device is installed on the second controller. If a signal relay device is installed, communication between the first and second controllers is established according to the first target transmission path determined by the signal relay device and the first non-transparent bridge. If no signal relay device is installed on the second controller, it determines whether a second non-transparent bridge is installed on the second controller. If a second non-transparent bridge is installed, communication between the first and second controllers is established according to the second target transmission path determined by the second non-transparent bridge and the first non-transparent bridge. If no second non-transparent bridge is installed on the second controller, it is assumed that communication between the first and second controllers is impossible, and a fault warning is issued to contact operators for timely maintenance. This application allows for flexible implementation of communication between the first and second controllers by determining whether to use a dual non-transparent bridge approach or a combination of a first non-transparent bridge and a signal relay device.

[0117] Referring to Figure 8, in one embodiment, a first target transmission path corresponding to the transmitted data is determined based on the first non-transparent bridge and the signal relay device, and the first controller transmits the transmitted data to the second controller based on the first target transmission path:

[0118] Step 201: In response to the first controller receiving a data transmission instruction, the controller obtains the transmission data from the first cache module and sends the transmission data to the first communication module.

[0119] Step 202: In response to the first communication module receiving the transmitted data, the first communication module converts the transmitted data into a data sequence, performs protocol encapsulation on the data sequence to obtain encapsulated data, and sends the encapsulated data to the first driver module.

[0120] Step 203: In response to the first driver module receiving the encapsulated data, the first driver module stores the encapsulated data into the target data pair column.

[0121] Step 204: In response to the target data queue meeting the preset conditions, the first driving module sends the target transmission data in the target data queue that meets the preset conditions to the memory access queue in the first memory.

[0122] Specifically, the data transmission command here can be a data synchronization command. After the first controller finds the data to be transmitted (modified data) from the first cache module, it calls the communication interface to send it to the second cache module of the second controller. The first communication module (the communication layer on controller 1) converts the data into a data sequence and performs protocol encapsulation on the data sequence to obtain encapsulated data. This encapsulated data is then sent to the first driver module. The first driver module (the NTB driver on controller 1) caches the encapsulated data in the 2000 buf queue and is responsible for aggregating the encapsulated data sequentially in continuous memory to improve transmission efficiency. Finally, it sends the data in the buf space to the first memory (illustrated memory data) DMA queue space (target data queue).

[0123] Here, a circular buffer area is formed by the buf queue on the first driver module to aggregate the received encapsulated data and then send it out in a unified manner. By increasing the block size of the encapsulated data, the data transmission efficiency is improved.

[0124] The specific steps for converting data into a data sequence and encapsulating the data sequence using a protocol to obtain the encapsulated data can be shown in the following code:

[0125] The target data queue here is the DMA queue shown in the diagram, which is configured as a circular queue in this application. A circular queue is a special type of queue that adds constraints to a regular queue, allowing it to be used cyclically within a fixed storage space. A circular queue can be implemented using an array, where elements are arranged in a specific order. When either the head or tail pointer reaches the end of the array, the cycle automatically restarts from the head. One advantage of a circular queue is that when it is full, new elements can be stored by overwriting the head element, thus enabling a degree of cyclical use and saving storage space.

[0126] The process by which the first driver module receives the encapsulated data and stores it in the target data pair column can be illustrated by the following code:

[0127] In one feasible implementation, the target data queue may include a first circular sub-queue and a second circular sub-queue. The first circular sub-queue is used to store data indexes. The second circular sub-queue is used to store the data corresponding to the data indexes. An index value is set for the second circular sub-queue, establishing a correspondence between the index value corresponding to the second circular sub-queue and the stored data indexes in the first circular sub-queue. When retrieving data from the target data queue, the data to be retrieved can be matched with the stored data indexes in the first circular sub-queue. The stored data index that matches the data to be retrieved is taken as the target stored data index, and the data corresponding to the target stored data index is retrieved according to the correspondence. This data is then sent to the other end. This facilitates the rapid retrieval of the required data from the target data queue, improving the reliability of the system.

[0128] Step 205: The first driver module sends a notification to the first non-transparent bridge, and at the same time, the target transmission data in the memory access queue is sent to the first non-transparent bridge, and the management data in the first driver module is synchronized to the first non-transparent bridge.

[0129] Step 206: The first non-transparent bridge sends the target transmission data to the signal relay device, and the signal relay device transmits the target transmission data to the second memory.

[0130] After all the encapsulated data is stored in the target data queue in the first memory, the first driver module will send a notification to the first non-transparent bridge, informing it that the target transmission data in the target data queue will be sent to the first non-transparent bridge. Then, the first non-transparent bridge will perform address translation to send the target transmission data in the target data queue to the second memory on the second controller.

[0131] Specifically, in this embodiment, sending the target transmission data in the target data queue to the second memory on the second controller includes:

[0132] Step 301: In response to the first non-transparent bridge receiving a data read request protocol from the first node corresponding to the first controller, the data read request protocol is obtained and sent to the address translation register.

[0133] Please refer to Figure 9. Step 301 corresponds to process ① in Figure 9. The host corresponding to partition 0, that is, the host where node 0 is located, sends a data read request protocol to the NT EP (NT terminal) of partition 0. After receiving the data read request protocol, the NT EP terminal parses the data read request protocol and compares the address carried in the header of the data read request protocol with the address of the address translation register (address translation register 0, address translation register 2) in the computer configuration. If the address corresponding to the data read request protocol falls on a certain address translation memory, the data read / write request is sent to that address translation register. Here, the address carried in the header of the data read request protocol is set to match the address of the address translation register.

[0134] The address for the data read request protocol here is 0xE000_0000. Click on Address Translation Memory 2. Since Address Translation Memory 2 is a direct translation window for port 3, the address of the data read request protocol is translated to the address of the target port through Address Translation Memory 2. In this case, the address ranges from 0xE000_0000 to 0x1000_0000.

[0135] This operation also hits the part of the rule search table that initiates ID conversion and determines the destination partition number. The converted address and the destination partition number are used to determine the target port. In this embodiment, the target port is determined to be port 3 in downstream partition 1.

[0136] Step 302: In response to the address translation register receiving a data read request protocol, the data read request protocol is parsed to obtain the protocol request address and the first node ID.

[0137] Step 303: Convert the protocol request address to the target port address through the address translation register, and convert the first node ID to the agent device ID.

[0138] Steps 302 and 303 correspond to process ② in Figure 9. After the data read request protocol arrives at the address translation register and address translation memory 2, the data read request protocol will be parsed through the address translation register 2 to obtain the protocol request address and the first node ID (node ​​0). Here, the protocol request address is the address of the data read request protocol. The protocol request address is converted into the target port address. Here, the target port address refers to the address of the target port of the target partition, which is port 3 in the figure. The first node ID is converted into the target ID through the address translation memory. Here, the target ID refers to the ID of the agent device corresponding to the data read request protocol.

[0139] This uses ID routing, where ID = Bus Number + Device Number + Function Number can uniquely identify a specific function of a device.

[0140] In this application, converting the first node ID to the target ID specifically involves converting the BDF of the data read request protocol jumping to the partition into a BDF of the NT proxy function. This proxy function allows the data read request protocol to appear as if it originated from the target partition. It also allows the completion of the data read request protocol return, converting the BDF corresponding to the data read request protocol completion back to the original BDF, and finding the method to return to the original partition, i.e., the original partition from which the data read request protocol was sent.

[0141] When processing TLP (Transaction Layer Protocol) packets, it is often necessary to convert the TLP's BDF (Bus, Device, Function) back to the original BDF value. A function `decode_tlp_bdf` can be defined, which takes an encoded TLP BDF value as an argument, and then extracts the various parts of the BDF through shift and AND operations. Finally, it returns the original BDF value.

[0142] As shown in the diagram, the original TLP displays the requester (first node) ID as 0.1.0. ID translation converts the BDF's device and function numbers to match the device (NT Proxy Fun) and function of the proxy function. The bus number remains unchanged because the ID translation is unaware of the proxy function's bus number at this point. The final target ID value is 0.31.7, where 31 is the proxy device number.

[0143] Step 304: Based on the proxy device ID, the data read request protocol and the target port address are sent to the proxy device in the second sub-transparent bridge. The proxy device converts the proxy device ID to obtain the target ID. The target port converts the target ID to generate a matching ID. The matching ID matches the first node ID.

[0144] Step 305: Forward the data read request protocol to the target port based on the target port address.

[0145] Steps 304 and 305 correspond to process ③ in Figure 9. After the data read request protocol exits from the proxy device's egress port, the proxy device's egress editor performs ID conversion on the proxy device's ID, specifically the bus number of the proxy function. For example, the target ID is changed from 0.31.7 to 1.31.7. This is to match the ID corresponding to the data read request protocol with the proxy device ID. After the target ID conversion, a matching ID is obtained, and the data read request protocol is forwarded to the target port based on the target port address (Figure EP3).

[0146] Step 207: In response to the second memory receiving the target transmission data, the second driver module sends a message to the first controller to inform it to start cache update based on the target transmission data.

[0147] Step 208: The second controller polls the target transmission data in the second memory and synchronizes the target transmission data to the second communication module. The second communication module then synchronizes the target transmission data to the second cache module.

[0148] Step 209: In response to the second controller confirming receipt of the target transmission data, feedback information is sent to the first controller.

[0149] Step 210: In response to the first controller receiving a feedback message, the first controller synchronizes the feedback information to the first communication module.

[0150] Specifically, the second drive module sends a message to the other end to inform it of the cache data update. The second controller polls for the message and, upon receiving the message, synchronizes it to the second communication module, which then synchronizes the message to the second cache module on the second controller.

[0151] In this application, the first controller and the second controller establish a 1M*N space buffer mapping area to handle the transmission of messages from multiple queues and channels of the first and second controllers. Each queue has 1M space and is responsible for sending messages. Messages are mainly divided into two types: read and write. The read type is responsible for reading messages from the peer, and the write type is responsible for writing messages to the peer and synchronizing them to the peer controller.

[0152] After confirming receipt of the message, the second controller sends a feedback message to the first controller. The first controller confirms that the second controller has successfully received the message and synchronizes the message to the second communication module. The second communication module is responsible for deleting this process transaction layer.

[0153] In one embodiment, determining a second target transmission path corresponding to the transmitted data based on the first non-transparent bridge and the second non-transparent bridge, and the first controller transmitting the transmitted data to the second controller based on the second target transmission path includes:

[0154] Step 401: In response to the first controller receiving a data transmission instruction, the controller obtains the transmission data from the first cache module and sends the transmission data to the first communication module.

[0155] Step 402: In response to the first communication module receiving the transmitted data, the first communication module converts the transmitted data into a data sequence, performs protocol encapsulation on the data sequence to obtain encapsulated data, and sends the encapsulated data to the first driver module.

[0156] Step 403: In response to the first driver module receiving the encapsulated data, the first driver module stores the encapsulated data into the target data pair column.

[0157] Step 404: In response to the target data queue meeting the preset conditions, the first driving module sends the target transmission data in the target data queue that meets the preset conditions to the memory access queue in the first memory.

[0158] Step 405: The first driver module sends a notification to the first non-transparent bridge, and at the same time, the target transmission data in the memory access queue is sent to the first non-transparent bridge, and the management data in the first driver module is synchronized to the first non-transparent bridge.

[0159] For specific implementation methods of steps 401-405, please refer to the description of steps 201-205 in the specification, which will not be repeated here.

[0160] Step 406: The first non-transparent bridge sends the target transmission data to the second non-transparent bridge, and the target transmission data is transferred to the second memory through the second non-transparent bridge.

[0161] After all the encapsulated data is stored in the target data queue in the first memory, the first driver module will send a notification to the first non-transparent bridge and the second non-transparent bridge, informing them that the target transmission data in the target data queue will be sent. Then, address translation will be performed through the first non-transparent bridge and the second non-transparent bridge to send the target transmission data in the target data queue to the second memory on the second controller.

[0162] The process involves the first non-transparent bridge sending the target transmission data to the second non-transparent bridge, and the second non-transparent bridge transferring the target transmission data to the second memory, including:

[0163] Step 501: In response to the first non-transparent bridge receiving a data read request protocol from the first node corresponding to the first controller, the data read request protocol is obtained and sent to the address translation register;

[0164] Step 502: In response to the address translation register receiving a data read request protocol, parse the data read request protocol to obtain the protocol request address and the first node ID;

[0165] Step 503: Convert the protocol request address to the target port address using the address translation register, and convert the first node ID to the proxy device ID;

[0166] Step 504: Based on the proxy device ID, send the data read request protocol and the target port address to the proxy device in the second non-transparent bridge. The proxy device converts the proxy device ID to obtain the target ID. The target port converts the target ID to generate a matching ID. The matching ID matches the first node ID.

[0167] Step 505: Forward the data read request protocol to the target port based on the target port address.

[0168] It is understandable that the specific implementation principle of steps 501-505 is the same as that of steps 301-305. The only difference is whether the second controller in steps 301-305 is equipped with a first non-transparent bridge or a signal relay device. Therefore, it will not be elaborated here.

[0169] Step 407: In response to the second memory receiving the target transmission data, the second driver module sends a message to the first controller to inform it to start cache update based on the target transmission data.

[0170] Step 408: The second controller polls the target transmission data in the second memory and synchronizes the target transmission data to the second communication module. The second communication module then synchronizes the target transmission data to the second cache module.

[0171] Step 409: In response to the second controller confirming receipt of the target transmission data, feedback information is sent to the first controller.

[0172] Step 410: In response to the first controller receiving a feedback message, the first controller synchronizes the feedback information to the first communication module.

[0173] For specific implementation methods of steps 407-410, please refer to the description of steps 207-210 in the specification, which will not be repeated here.

[0174] In one embodiment, after forwarding the data read request protocol to the target port based on the target port address, that is, after step 305 or step 505, the method further includes:

[0175] Step 306: Obtain the matching ID and the completed data protocol ID. The completed data protocol ID is the ID sent to the first node when the target port receives the data request protocol and completes it.

[0176] Step 307: Convert the matching ID and the completed data protocol ID into the first node ID.

[0177] Steps 306 and 307 correspond to process ④ in Figure 9. In this application, the target device actively sends data to the first node using a completion message. Unlike the data read request protocol, the completion data protocol corresponding to the completion data uses ID routing for transmission. Using the request ID (matching ID) of the proxy function, the request ID (matching ID) and the completion ID (ID of the completion data protocol) can be converted back to the BDF of the original partition (partition 0).

[0178] The completion ID here refers to the ID corresponding to the request that completes the data read protocol. The matching ID and completion ID are translated to match the node 0 (first node) that initially sent the data read request protocol. The completion ID is translated to match the NT EP initially accessed by the host. The proxy function ID is also used to determine the target port to return the original source partition (partition 0 where the first node is located).

[0179] Step 308: In response to converting the Match ID and the Completion Data Protocol ID into the First Node ID, the Completion Data Protocol is forwarded to the First Node.

[0180] Step 308 corresponds to step ⑤ in Figure 9. Since the requester ID (matching ID) and completion ID have been modified, there is no need to edit the exit of the completion data protocol. The only operation here is to forward the completion data protocol to node 0.

[0181] It should be understood that although the steps in the flowcharts of Figures 7-9 are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in Figures 6-8 may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the sub-steps or stages of other steps.

[0182] In one embodiment, as shown in FIG10, a dual-controller communication device is provided, comprising: a judgment module 20, a determination module 21, and a transmission module 22, wherein:

[0183] The judgment module is used to determine whether a signal relay device is set on the second controller in response to the first controller receiving a data transmission instruction, which includes data transmission.

[0184] The determination module is used to determine the first target transmission path corresponding to the transmitted data based on the first non-transparent bridge and the signal relay device if a signal relay device is set on the second controller; if no signal relay device is set on the second controller, it determines whether a second non-transparent bridge is set on the second controller; if a second non-transparent bridge is set on the second controller, it determines the second target transmission path corresponding to the transmitted data based on the first non-transparent bridge and the second non-transparent bridge; if no second non-transparent bridge is set on the second controller, it issues a fault warning.

[0185] A transmission module is used by the first controller to transmit transmission data to the second controller based on a first target transmission path and / or a second transmission path.

[0186] In one embodiment, the above-described device can implement another implementation of the dual-controller communication method, with the following specific steps:

[0187] Determining the first target transmission path corresponding to the transmitted data based on the first non-transparent bridge and the signal relay device, and transmitting the transmitted data to the second controller based on the first target transmission path, includes:

[0188] In response to the first controller receiving a data transmission instruction, the system retrieves the transmission data from the first cache module and sends the transmission data to the first communication module.

[0189] In response to the first communication module receiving the transmitted data, the first communication module converts the transmitted data into a data sequence, performs protocol encapsulation on the data sequence to obtain the encapsulated data, and sends the encapsulated data to the first driver module;

[0190] In response to the first driver module receiving the encapsulated data, the first driver module stores the encapsulated data into the target data pair column;

[0191] In response to the target data queue meeting preset conditions, the first driving module sends the target transmission data in the target data queue that meets the preset conditions to the memory access queue in the first memory;

[0192] The first driver module sends a notification to the first non-transparent bridge, and at the same time, the target transmission data in the memory access queue is sent to the first non-transparent bridge, and the management data in the first driver module is synchronized to the first non-transparent bridge.

[0193] The first non-transparent bridge sends the target transmission data to the signal relay device, which then transmits the target transmission data to the second memory.

[0194] In one embodiment, the above-described device can implement another implementation of the dual-controller communication method, with the following specific steps:

[0195] Determining the second target transmission path corresponding to the transmitted data based on the first non-transparent bridge and the second non-transparent bridge, and transmitting the transmitted data to the second controller based on the second target transmission path, includes:

[0196] In response to the first controller receiving a data transmission instruction, the system retrieves the transmission data from the first cache module and sends the transmission data to the first communication module.

[0197] In response to the first communication module receiving the transmitted data, the first communication module converts the transmitted data into a data sequence, performs protocol encapsulation on the data sequence to obtain the encapsulated data, and sends the encapsulated data to the first driver module;

[0198] In response to the first driver module receiving the encapsulated data, the first driver module stores the encapsulated data into the target data pair column;

[0199] In response to the target data queue meeting preset conditions, the first driving module sends the target transmission data in the target data queue that meets the preset conditions to the memory access queue in the first memory;

[0200] The first driver module sends a notification to the first non-transparent bridge, and at the same time, the target transmission data in the memory access queue is sent to the first non-transparent bridge, and the management data in the first driver module is synchronized to the first non-transparent bridge.

[0201] The first non-transparent bridge sends the target data to the second non-transparent bridge, and the target data is then transferred to the second memory via the second non-transparent bridge.

[0202] In one embodiment, the above-described device can implement another implementation of the dual-controller communication method, with the following specific steps:

[0203] The method also includes:

[0204] In response to the second memory receiving the target transmission data, the second driver module sends a message to the first controller to inform it to start cache update based on the target transmission data;

[0205] The second controller polls the target transmission data in the second memory and synchronizes the target transmission data to the second communication module. The second communication module then synchronizes the target transmission data to the second cache module.

[0206] After the second controller confirms that the target transmission data has been received, it sends feedback information to the first controller.

[0207] In response to receiving a feedback message, the first controller synchronously sends feedback information to the first communication module.

[0208] In one embodiment, the above-described device can implement another implementation of the dual-controller communication method, with the following specific steps:

[0209] The first non-transparent bridge sends the target transmission data to the signal relay device, and the signal relay device transmits the target transmission data to the second memory, including:

[0210] In response to the first non-transparent bridge receiving a data read request protocol from the first node corresponding to the first controller, the data read request protocol is obtained and sent to the address translation register;

[0211] In response to the address translation register receiving a data read request protocol, the data read request protocol is parsed to obtain the protocol request address and the first node ID;

[0212] The protocol request address is converted to the target port address using the address translation register, and the first node ID is converted to the agent device ID.

[0213] Based on the proxy device ID, the data read request protocol and the target port address are sent to the proxy device in the second sub-transparent bridge. The proxy device converts the proxy device ID to obtain the target ID. The target port converts the target ID to generate a matching ID, which is matched with the first node ID.

[0214] The data read request protocol is forwarded to the target port based on the target port address.

[0215] In one embodiment, the above-described device can implement another implementation of the dual-controller communication method, with the following specific steps:

[0216] The first non-transparent bridge sends the target transmission data to the second non-transparent bridge, and the target transmission data is transferred to the second memory through the second non-transparent bridge, including:

[0217] In response to the first non-transparent bridge receiving a data read request protocol from the first node corresponding to the first controller, the data read request protocol is obtained and sent to the address translation register;

[0218] In response to the address translation register receiving a data read request protocol, the data read request protocol is parsed to obtain the protocol request address and the first node ID;

[0219] The protocol request address is converted to the target port address using the address translation register, and the first node ID is converted to the agent device ID.

[0220] The data read request protocol and the target port address are sent to the proxy device in the second non-transparent bridge based on the proxy device ID. The proxy device converts the proxy device ID to obtain the target ID. The target port converts the target ID to generate a matching ID. The matching ID is matched with the first node ID.

[0221] The data read request protocol is forwarded to the target port based on the target port address.

[0222] In one embodiment, the above-described device can implement another implementation of the dual-controller communication method, with the following specific steps:

[0223] After forwarding the data read request protocol to the target port based on the target port address, the following also includes:

[0224] Obtain the matching ID and the completed data protocol ID. The completed data protocol ID is the ID sent to the first node when the target port receives the data request protocol and completes.

[0225] Convert the matching ID and the completed data protocol ID into the first node ID;

[0226] In response to converting the match ID and completion data protocol ID into the first node ID, the completion data protocol is forwarded to the first node.

[0227] Specific limitations regarding the dual-controller communication device can be found in the limitations of the dual-controller communication method described above, and will not be repeated here. Each module in the aforementioned dual-controller communication device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in hardware or independently of the processor in the computer device, or stored in software in the memory of the computer device, so that the processor can call and execute the operations corresponding to each module.

[0228] In one embodiment, this application also provides a computer program product, which includes computer-readable instructions stored on a non-transitory computer-readable storage medium. The computer-readable instructions include program instructions, and when the program instructions are executed by a computer, the computer is able to execute the dual-controller communication method provided by the above methods.

[0229] In one embodiment, a computer device is provided, which may be a terminal, and its internal structure diagram may be as shown in Figure 11. The computer device includes a processor, memory, network interface, display screen, and input device connected via a system bus. The processor of the computer device provides computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and computer-readable instructions. The internal memory provides an environment for the operation of the operating system and computer-readable instructions in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal via a network connection. When the computer-readable instructions are executed by the processor, a dual-controller communication method is implemented. The display screen of the computer device may be a liquid crystal display (LCD) or an e-ink display. The input device of the computer device may be a touch layer covering the display screen, or buttons, a trackball, or a touchpad mounted on the computer device casing, or an external keyboard, touchpad, or mouse, etc.

[0230] Those skilled in the art will understand that the structure shown in Figure 11 is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device to which the present application is applied. Specific computer devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0231] In one embodiment, a computer device is provided, including a memory, a processor, and computer-readable instructions stored in the memory and executable on the processor, wherein the processor performs the following steps when executing the computer-readable instructions:

[0232] Step 101: In response to the first controller receiving a data transmission instruction, the data transmission instruction includes transmitting data, and determining whether a signal relay device is set on the second controller.

[0233] Step 102: If a signal relay device is set on the second controller, then the first target transmission path corresponding to the transmitted data is determined based on the first non-transparent bridge and the signal relay device.

[0234] Step 103: If no signal relay device is set on the second controller, determine whether a second non-transparent bridge is set on the second controller.

[0235] Step 104: If a second non-transparent bridge is set on the second controller, then the second target transmission path corresponding to the transmitted data is determined based on the first non-transparent bridge and the second non-transparent bridge.

[0236] Step 105: If the second non-transparent bridge is not set on the second controller, a fault warning is issued.

[0237] Step 106: The first controller transmits the transmission data to the second controller based on the first target transmission path and / or the second transmission path.

[0238] In one embodiment, the processor further performs the following steps when executing computer-readable instructions:

[0239] Determining the first target transmission path corresponding to the transmitted data based on the first non-transparent bridge and the signal relay device, and transmitting the transmitted data to the second controller based on the first target transmission path, includes:

[0240] In response to the first controller receiving a data transmission instruction, the system retrieves the transmission data from the first cache module and sends the transmission data to the first communication module.

[0241] In response to the first communication module receiving the transmitted data, the first communication module converts the transmitted data into a data sequence, performs protocol encapsulation on the data sequence to obtain the encapsulated data, and sends the encapsulated data to the first driver module;

[0242] In response to the first driver module receiving the encapsulated data, the first driver module stores the encapsulated data into the target data pair column;

[0243] In response to the target data queue meeting preset conditions, the first driving module sends the target transmission data in the target data queue that meets the preset conditions to the memory access queue in the first memory;

[0244] The first driver module sends a notification to the first non-transparent bridge, and at the same time, the target transmission data in the memory access queue is sent to the first non-transparent bridge, and the management data in the first driver module is synchronized to the first non-transparent bridge.

[0245] The first non-transparent bridge sends the target transmission data to the signal relay device, which then transmits the target transmission data to the second memory.

[0246] In one embodiment, the processor further performs the following steps when executing computer-readable instructions:

[0247] Determining the second target transmission path corresponding to the transmitted data based on the first non-transparent bridge and the second non-transparent bridge, and transmitting the transmitted data to the second controller based on the second target transmission path, includes:

[0248] In response to the first controller receiving a data transmission instruction, the system retrieves the transmission data from the first cache module and sends the transmission data to the first communication module.

[0249] In response to the first communication module receiving the transmitted data, the first communication module converts the transmitted data into a data sequence, performs protocol encapsulation on the data sequence to obtain the encapsulated data, and sends the encapsulated data to the first driver module;

[0250] In response to the first driver module receiving the encapsulated data, the first driver module stores the encapsulated data into the target data pair column;

[0251] In response to the target data queue meeting preset conditions, the first driving module sends the target transmission data in the target data queue that meets the preset conditions to the memory access queue in the first memory;

[0252] The first driver module sends a notification to the first non-transparent bridge, and at the same time, the target transmission data in the memory access queue is sent to the first non-transparent bridge, and the management data in the first driver module is synchronized to the first non-transparent bridge.

[0253] The first non-transparent bridge sends the target data to the second non-transparent bridge, and the target data is then transferred to the second memory via the second non-transparent bridge.

[0254] In one embodiment, the processor further performs the following steps when executing computer-readable instructions:

[0255] The method also includes:

[0256] In response to the second memory receiving the target transmission data, the second driver module sends a message to the first controller to inform it to start cache update based on the target transmission data;

[0257] The second controller polls the target transmission data in the second memory and synchronizes the target transmission data to the second communication module. The second communication module then synchronizes the target transmission data to the second cache module.

[0258] After the second controller confirms that the target transmission data has been received, it sends feedback information to the first controller.

[0259] In response to receiving a feedback message, the first controller synchronously sends feedback information to the first communication module.

[0260] In one embodiment, the processor further performs the following steps when executing computer-readable instructions:

[0261] The first non-transparent bridge sends the target transmission data to the signal relay device, and the signal relay device transmits the target transmission data to the second memory, including:

[0262] In response to the first non-transparent bridge receiving a data read request protocol from the first node corresponding to the first controller, the data read request protocol is obtained and sent to the address translation register;

[0263] In response to the address translation register receiving a data read request protocol, the data read request protocol is parsed to obtain the protocol request address and the first node ID;

[0264] The protocol request address is converted to the target port address using the address translation register, and the first node ID is converted to the agent device ID.

[0265] Based on the proxy device ID, the data read request protocol and the target port address are sent to the proxy device in the second sub-transparent bridge. The proxy device converts the proxy device ID to obtain the target ID. The target port converts the target ID to generate a matching ID, which is matched with the first node ID.

[0266] The data read request protocol is forwarded to the target port based on the target port address.

[0267] In one embodiment, the processor further performs the following steps when executing computer-readable instructions:

[0268] The first non-transparent bridge sends the target transmission data to the second non-transparent bridge, and the target transmission data is transferred to the second memory through the second non-transparent bridge, including:

[0269] In response to the first non-transparent bridge receiving a data read request protocol from the first node corresponding to the first controller, the data read request protocol is obtained and sent to the address translation register;

[0270] In response to the address translation register receiving a data read request protocol, the data read request protocol is parsed to obtain the protocol request address and the first node ID;

[0271] The protocol request address is converted to the target port address using the address translation register, and the first node ID is converted to the agent device ID.

[0272] The data read request protocol and the target port address are sent to the proxy device in the second non-transparent bridge based on the proxy device ID. The proxy device converts the proxy device ID to obtain the target ID. The target port converts the target ID to generate a matching ID. The matching ID is matched with the first node ID.

[0273] The data read request protocol is forwarded to the target port based on the target port address.

[0274] In one embodiment, the processor further performs the following steps when executing computer-readable instructions:

[0275] After forwarding the data read request protocol to the target port based on the target port address, the following also includes:

[0276] Obtain the matching ID and the completed data protocol ID. The completed data protocol ID is the ID sent to the first node when the target port receives the data request protocol and completes.

[0277] Convert the matching ID and the completed data protocol ID into the first node ID;

[0278] In response to converting the match ID and completion data protocol ID into the first node ID, the completion data protocol is forwarded to the first node.

[0279] In one embodiment, a non-volatile computer-readable storage medium is provided, on which computer-readable instructions are stored, which, when executed by a processor, perform the following steps:

[0280] Step 101: In response to the first controller receiving a data transmission instruction, the data transmission instruction includes transmitting data, and determining whether a signal relay device is set on the second controller.

[0281] Step 102: If a signal relay device is set on the second controller, then the first target transmission path corresponding to the transmitted data is determined based on the first non-transparent bridge and the signal relay device.

[0282] Step 103: If no signal relay device is set on the second controller, determine whether a second non-transparent bridge is set on the second controller.

[0283] Step 104: If a second non-transparent bridge is set on the second controller, then the second target transmission path corresponding to the transmitted data is determined based on the first non-transparent bridge and the second non-transparent bridge.

[0284] Step 105: If the second non-transparent bridge is not set on the second controller, a fault warning is issued.

[0285] Step 106: The first controller transmits the transmission data to the second controller based on the first target transmission path and / or the second transmission path.

[0286] In one embodiment, when the computer-readable instructions are executed by the processor, the following steps are also performed:

[0287] Determining the first target transmission path corresponding to the transmitted data based on the first non-transparent bridge and the signal relay device, and transmitting the transmitted data to the second controller based on the first target transmission path, includes:

[0288] In response to the first controller receiving a data transmission instruction, the system retrieves the transmission data from the first cache module and sends the transmission data to the first communication module.

[0289] In response to the first communication module receiving the transmitted data, the first communication module converts the transmitted data into a data sequence, performs protocol encapsulation on the data sequence to obtain the encapsulated data, and sends the encapsulated data to the first driver module;

[0290] In response to the first driver module receiving the encapsulated data, the first driver module stores the encapsulated data into the target data pair column;

[0291] In response to the target data queue meeting preset conditions, the first driving module sends the target transmission data in the target data queue that meets the preset conditions to the memory access queue in the first memory;

[0292] The first driver module sends a notification to the first non-transparent bridge, and at the same time, the target transmission data in the memory access queue is sent to the first non-transparent bridge, and the management data in the first driver module is synchronized to the first non-transparent bridge.

[0293] The first non-transparent bridge sends the target transmission data to the signal relay device, which then transmits the target transmission data to the second memory.

[0294] In one embodiment, when the computer-readable instructions are executed by the processor, the following steps are also performed:

[0295] Determining the second target transmission path corresponding to the transmitted data based on the first non-transparent bridge and the second non-transparent bridge, and transmitting the transmitted data to the second controller based on the second target transmission path, includes:

[0296] In response to the first controller receiving a data transmission instruction, the system retrieves the transmission data from the first cache module and sends the transmission data to the first communication module.

[0297] In response to the first communication module receiving the transmitted data, the first communication module converts the transmitted data into a data sequence, performs protocol encapsulation on the data sequence to obtain the encapsulated data, and sends the encapsulated data to the first driver module;

[0298] In response to the first driver module receiving the encapsulated data, the first driver module stores the encapsulated data into the target data pair column;

[0299] In response to the target data queue meeting preset conditions, the first driving module sends the target transmission data in the target data queue that meets the preset conditions to the memory access queue in the first memory;

[0300] The first driver module sends a notification to the first non-transparent bridge, and at the same time, the target transmission data in the memory access queue is sent to the first non-transparent bridge, and the management data in the first driver module is synchronized to the first non-transparent bridge.

[0301] The first non-transparent bridge sends the target data to the second non-transparent bridge, and the target data is then transferred to the second memory via the second non-transparent bridge.

[0302] In one embodiment, when the computer-readable instructions are executed by the processor, the following steps are also performed:

[0303] The method also includes:

[0304] In response to the second memory receiving the target transmission data, the second driver module sends a message to the first controller to inform it to start cache update based on the target transmission data;

[0305] The second controller polls the target transmission data in the second memory and synchronizes the target transmission data to the second communication module. The second communication module then synchronizes the target transmission data to the second cache module.

[0306] After the second controller confirms that the target transmission data has been received, it sends feedback information to the first controller.

[0307] In response to receiving a feedback message, the first controller synchronously sends feedback information to the first communication module.

[0308] In one embodiment, when the computer-readable instructions are executed by the processor, the following steps are also performed:

[0309] The first non-transparent bridge sends the target transmission data to the signal relay device, and the signal relay device transmits the target transmission data to the second memory, including:

[0310] In response to the first non-transparent bridge receiving a data read request protocol from the first node corresponding to the first controller, the data read request protocol is obtained and sent to the address translation register;

[0311] In response to the address translation register receiving a data read request protocol, the data read request protocol is parsed to obtain the protocol request address and the first node ID;

[0312] The protocol request address is converted to the target port address using the address translation register, and the first node ID is converted to the agent device ID.

[0313] Based on the proxy device ID, the data read request protocol and the target port address are sent to the proxy device in the second sub-transparent bridge. The proxy device converts the proxy device ID to obtain the target ID. The target port converts the target ID to generate a matching ID, which is matched with the first node ID.

[0314] The data read request protocol is forwarded to the target port based on the target port address.

[0315] In one embodiment, when the computer-readable instructions are executed by the processor, the following steps are also performed:

[0316] The first non-transparent bridge sends the target transmission data to the second non-transparent bridge, and the target transmission data is transferred to the second memory through the second non-transparent bridge, including:

[0317] In response to the first non-transparent bridge receiving a data read request protocol from the first node corresponding to the first controller, the data read request protocol is obtained and sent to the address translation register;

[0318] In response to the address translation register receiving a data read request protocol, the data read request protocol is parsed to obtain the protocol request address and the first node ID;

[0319] The protocol request address is converted to the target port address using the address translation register, and the first node ID is converted to the agent device ID.

[0320] The data read request protocol and the target port address are sent to the proxy device in the second non-transparent bridge based on the proxy device ID. The proxy device converts the proxy device ID to obtain the target ID. The target port converts the target ID to generate a matching ID. The matching ID is matched with the first node ID.

[0321] The data read request protocol is forwarded to the target port based on the target port address.

[0322] In one embodiment, when the computer-readable instructions are executed by the processor, the following steps are also performed:

[0323] After forwarding the data read request protocol to the target port based on the target port address, the following also includes:

[0324] Obtain the matching ID and the completed data protocol ID. The completed data protocol ID is the ID sent to the first node when the target port receives the data request protocol and completes.

[0325] Convert the matching ID and the completed data protocol ID into the first node ID;

[0326] In response to converting the match ID and completion data protocol ID into the first node ID, the completion data protocol is forwarded to the first node.

[0327] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by instructing related hardware with computer-readable instructions. These computer-readable instructions can be stored in a non-volatile computer-readable storage medium. When executed, these computer-readable instructions can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0328] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0329] The above embodiments are merely illustrative of several implementation methods of this application, and their descriptions are relatively specific and detailed. However, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application.

Claims

1. A dual controller communication system, characterized by, The system includes a first controller and a second controller: The first controller includes a first processor and a first non-transparent bridge; The second controller includes a second processor and a signal relay device; The input terminal of the first non-transparent bridge is connected to the output terminal of the first processor, the output terminal of the first non-transparent bridge is connected to the input terminal of the signal relay device, and the output terminal of the signal relay device is connected to the input terminal of the second processor.

2. The system of claim 1, wherein, The first non-transparent bridge includes a first sub-non-transparent bridge and a second sub-non-transparent bridge. The input terminal of the first sub-non-transparent bridge is connected to the output terminal of the first processor. The output terminal of the first sub-non-transparent bridge is connected to the input terminal of the second sub-non-transparent bridge. The output terminal of the second sub-non-transparent bridge is connected to the input terminal of the signal relay device. The output terminal of the signal relay device is connected to the input terminal of the second processor.

3. The system of claim 1, wherein, The first controller further includes a first memory, and the second controller further includes a second memory. The first memory is communicatively connected to the first processor and the first non-transparent bridge, and the second memory is communicatively connected to the second processor and the signal relay device.

4. The system of claim 1, wherein, The first controller further includes a first driver module, and the second controller further includes a second driver module. The first driver module is communicatively connected to the first processor, and the second driver module is communicatively connected to the second processor. The first driver module and the second driver module are used to establish a mapping relationship between the first memory and the second memory.

5. The system of claim 1, wherein, The first controller further includes a first communication module and a first buffer module, and the second controller further includes a second communication module and a second buffer module. The input terminal of the first communication module is connected to the output terminal of the first buffer module, and the output terminal of the first communication module is connected to the input terminal of the first drive module. The input terminal of the second communication module is connected to the output terminal of the second buffer module, and the output terminal of the second communication module is connected to the input terminal of the second driver module.

6. The system of claim 1, wherein, The second controller also includes a slot for detachably mounting a second non-transparent bridge to enable the replacement of signal relay equipment using the second non-transparent bridge.

7. The system of claim 1, wherein, In response to a notification from the first non-transparent bridge, the first controller retrieves the target transmission data from the memory access queue on the first controller and sends the target transmission data to the signal relay device to transmit the target transmission data to the second controller via the signal relay device.

8. The system of claim 2, wherein, The first sub-opaque bridge and the second sub-opaque bridge are two virtual sub-opaque bridges within a single physical opaque bridge.

9. The system of claim 5, wherein, The first cache module is a high-speed cache memory in the first controller, and the second cache module is a high-speed cache memory in the second controller.

10. The system of claim 5, wherein, The first communication module is the communication layer configured in the first controller, and the communication layer of the first controller is configured with an NVMe communication protocol stack and a link management program. The second communication module is the communication layer configured in the second controller, and the communication layer of the second controller is configured with an NVMe communication protocol stack and a link management program.

11. A dual controller communication method, comprising: The dual-controller communication method is applied in the dual-controller communication system as described in any one of claims 1-10, and the method includes: In response to the first controller receiving a data transmission instruction, the data transmission instruction including data transmission, it is determined whether a signal relay device is set on the second controller; In response to the setting of a signal relay device on the second controller, a first target transmission path corresponding to the transmitted data is determined based on the first non-transparent bridge and the signal relay device; In response to the absence of a signal relay device on the second controller, determine whether a second non-transparent bridge is configured on the second controller; In response to setting a second non-transparent bridge on the second controller, a second target transmission path corresponding to the transmitted data is determined based on the first non-transparent bridge and the second non-transparent bridge; and A fault warning is issued in response to the absence of a second non-transparent bridge on the second controller. The first controller transmits the transmission data to the second controller based on the first target transmission path and / or the second transmission path.

12. The method of claim 11, wherein, Determining a first target transmission path corresponding to the transmitted data based on the first non-transparent bridge and the signal relay device, and then transmitting the transmitted data to the second controller based on the first target transmission path, includes: In response to the first controller receiving a data transmission instruction, the system retrieves the transmission data from the first cache module and sends the transmission data to the first communication module. In response to the first communication module receiving the transmitted data, the first communication module converts the transmitted data into a data sequence, performs protocol encapsulation on the data sequence to obtain encapsulated data, and sends the encapsulated data to the first driver module; In response to the first driver module receiving the encapsulated data, the first driver module stores the encapsulated data into the target data pair column; and In response to the target data queue meeting preset conditions, the first driving module sends the target transmission data in the target data queue that meets the preset conditions to the memory access queue in the first memory; The first driver module sends a notification to the first non-transparent bridge, and at the same time, the target transmission data in the memory access queue is sent to the first non-transparent bridge, and the management data in the first driver module is synchronized to the first non-transparent bridge. The first non-transparent bridge sends the target transmission data to the signal relay device, which then transmits the target transmission data to the second memory.

13. The method of claim 11, wherein, Determining a second target transmission path corresponding to the transmitted data based on the first non-transparent bridge and the second non-transparent bridge, and the first controller transmitting the transmitted data to the second controller based on the second target transmission path, includes: In response to the first controller receiving a data transmission instruction, the system retrieves the transmission data from the first cache module and sends the transmission data to the first communication module. In response to the first communication module receiving the transmitted data, the first communication module converts the transmitted data into a data sequence, performs protocol encapsulation on the data sequence to obtain encapsulated data, and sends the encapsulated data to the first driver module; In response to the first driver module receiving the encapsulated data, the first driver module stores the encapsulated data into the target data pair column; and In response to the target data queue meeting preset conditions, the first driving module sends the target transmission data in the target data queue that meets the preset conditions to the memory access queue in the first memory; The first driver module sends a notification to the first non-transparent bridge, and at the same time, the target transmission data in the memory access queue is sent to the first non-transparent bridge, and the management data in the first driver module is synchronized to the first non-transparent bridge. The first non-transparent bridge sends the target transmission data to the second non-transparent bridge, and the target transmission data is then transferred to the second memory via the second non-transparent bridge.

14. The method according to claim 12 or 13, characterized in that, The method further includes: In response to the second memory receiving the target transmission data, the second driver module sends a message to the first controller to inform it to start cache update based on the target transmission data; The second controller polls the target transmission data in the second memory and synchronizes the target transmission data to the second communication module, and the second communication module synchronizes the target transmission data to the second cache module; In response to the second controller confirming receipt of the target transmission data, a feedback message is sent to the first controller; and In response to receiving a feedback message, the first controller synchronously sends feedback information to the first communication module.

15. The method of claim 12, wherein, The first non-transparent bridge sends the target transmission data to the signal relay device, and the signal relay device transmits the target transmission data to the second memory, including: In response to the first non-transparent bridge receiving a data read request protocol from the first node corresponding to the first controller, the data read request protocol is obtained and sent to the address translation register; In response to the address translation register receiving a data read request protocol, the data read request protocol is parsed to obtain the protocol request address and the first node ID; The protocol request address is converted to the target port address using the address translation register, and the first node ID is converted to the agent device ID. Based on the proxy device ID, the data read request protocol and the target port address are sent to the proxy device in the second sub-transparent bridge. The proxy device converts the proxy device ID to obtain the target ID. The target port converts the target ID to generate a matching ID, which is matched with the first node ID. The data read request protocol is forwarded to the target port based on the target port address.

16. The method of claim 13, wherein, The first non-transparent bridge sends the target transmission data to the second non-transparent bridge, and the second non-transparent bridge transmits the target transmission data to the second memory, including: In response to the first non-transparent bridge receiving a data read request protocol from the first node corresponding to the first controller, the data read request protocol is obtained and sent to the address translation register; In response to the address translation register receiving a data read request protocol, the data read request protocol is parsed to obtain the protocol request address and the first node ID; The protocol request address is converted to the target port address using the address translation register, and the first node ID is converted to the agent device ID. Based on the proxy device ID, the data read request protocol and the target port address are sent to the proxy device in the second non-transparent bridge. The proxy device converts the proxy device ID to obtain the target ID. The target port converts the target ID to generate a matching ID, which is matched with the first node ID. The data read request protocol is forwarded to the target port based on the target port address.

17. The method according to claim 15 or 16, characterized in that, After forwarding the data read request protocol to the target port based on the target port address, the process also includes: Obtain the matching ID and the completed data protocol ID, wherein the completed data protocol ID is the ID sent to the first node when the target port receives the data request protocol completion; Convert the matching ID and the completed data protocol ID into a first node ID; and In response to converting the matching ID and the completion data protocol ID into a first node ID, the completion data protocol is forwarded to the first node.

18. A computer program product comprising computer readable instructions, characterized in that, When executed by a processor, the computer-readable instructions implement the steps of the method according to any one of claims 11 to 17.

19. A computer device comprising a memory, a processor, and computer readable instructions stored on the memory and executable on the processor, the computer readable instructions comprising: When the processor executes the computer-readable instructions, it implements the steps of the method according to any one of claims 11 to 17.

20. A non-transitory computer readable storage medium having stored thereon computer readable instructions, the computer readable instructions comprising: When the computer-readable instructions are executed by a processor, they implement the steps of the method according to any one of claims 11 to 17.

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