An improved GAN switching technique applied to current source inverter apparatus

Abstract

There is provided a current source inverter (CSI) comprising at least one Gallium Nitride (GaN) transistor including a gate, wherein a predetermined voltage value is applied to the gate of the GaN transistor for at least a portion of time, in order to provide an extended reverse voltage blocking capability for the GaN transistor.

Description

[0001] AN IMPROVED GaN SWITCHING TECHNIQUE APPLIED TO CURRENT SOURCE INVERTER APPARATUS

[0002] FIELD OF THE INVENTION

[0003] The present invention relates to an improved GaN current source inverter and method for driving the same.

[0004] BACKGROUND OF THE INVENTION

[0005] Existing power converters are starting to reach the limits of their capabilities, or at least their efficiencies. Accordingly, there is a desire to develop better switching arrangements that are more efficient.

[0006] SUMMARY

[0007] It is an object of the present disclosure to provide improved Gallium Nitride (GaN) switching device arrangements and current source inverters derived therefrom.

[0008] BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Examples of the invention are further described hereinafter with reference to the accompanying drawings, in which:

[0010] Figure 1 shows an example of a depletion mode GaN device according to an example of the disclosure; Figure 2 shows an example of an enhancement mode GaN device according to an example of the disclosure;

[0011] Figure 3 shows an example of a Common Source, back-to-back monolithic, enhancement mode device according to an example of the disclosure;

[0012] Figure 4 shows a voltage source inverter (VSI);

[0013] Figure 5 shows an idealised example (i.e. H6) of an Current Source Inverter according to an example of the disclosure;

[0014] Figure 6A to 6D shows how an H6 CDI of Figure 5 operates in terms of current paths during switching; Figure 7 A shows a destructive interphase short issue, according to an example of the disclosure;

[0015] Figure 7B shows how diode behaviour scan be beneficial to overlap switching according to an example of the disclosure;

[0016] Figure 8 shows three examples of reverse blocking capable switching devices, according to an example of the disclosure;

[0017] Figure 9 shows an example of the Current Source Inverter of Figure 5, using back-to-back monolithic devices according to Figure 3 or 8, according to an example of the disclosure;

[0018] Figure 10 shows the device of Figure 2, in a gated On state, according to an example of the disclosure; Figure 11 shows the device of Figure 2, in a gated Off state, according to an example of the disclosure; Figure 12 shows different reverse voltage blocking capabilities of enhancement mode GaN due to different negative Gate biases, according to an example of the disclosure;

[0019] Figure 13 shows an example of an H7 Current Source Inverter, according to an example of the disclosure;

[0020] Figure 14 shows an example of an H8 Current Source Inverter, according to an example of the disclosure.

[0021] DETAILED DESCRIPTION HGF Ref: P390373WO;The technical operation and advantages of the present disclosure shall now be provided by way of a plurality of examples that are merely illustrative of the novel and inventive features, and the disclosed examples are intended to be fully combinable in any reasonable combination.

[0022] Figures 1 to 3 show different generic GaN device structures that will now be described in more detail, but only at a level relevant to the present disclosure (i.e. there may be other layers that are not described here, as they are not relevant to the disclosure).

[0023] Figure 1 shows an example of a standard depletion mode GaN device 100 according to an example of the disclosure, which is where GaN devices began. These depletion mode GaN devices may also be referred to as D-GaNs, normally-on GaNs, or simply depletion GaN devices. These may be High Electron Mobility Transistor (HEMT) devices.

[0024] The depletion mode GaN device shown in Figure 1 comprises (from the bottom of the figure, up towards to top) a layered structure comprising: a first silicon substrate layer 110, a second gallium nitride buffer layer(s) 120, a third gallium nitride 2DEG channel layer 130, and an aluminium gallium nitride barrier layer 140. The 2DEG channel layer is the name for the conducting channel in such devices, and is referred to as a two-dimensional electron gas (2DEG) at the AIGaN / GaN interface. The combination of spontaneous and piezoelectric polarization at the AIGaN / GaN interface creates a strong electric field. This electric field attracts electrons from the GaN layer towards the interface, forming a 2DEG).

[0025] The device comprises a source 150 and drain 160 that are formed within the top two layers. The device also comprises a gate 170 that is located at a position between the source and drain, where the definition of the source and drain is dependent on horizontal distance from the gate. This is to say, the source is defined as the entity located nearest the gate, and the drain is the entity located furthest from the gate. This type of device is a form of depletion mode device, which means the device is normally on unless a voltage is applied to the gate. The voltage threshold for conduction is 0V - i.e. the device is on when gated at 0V. Whereas, the device is switched off when the gate-source voltage, Vgs, is less than the threshold voltage, Vth - i.e. when Vgs < Vth, where Vth < 0. These devices are less common, but examples of the present disclosure may be applied to them, by suitable adjustment to the voltages involved. In more detail, when the device is gated OFF (i.e. VGS< Vth), an electric field is created that depletes the 2DEG channel, effectively stopping the current flow when the GaN device is forward biased (i.e. Vds > 0V). Whereas, under reverse bias (i.e. for Vds < 0V), the drain potential is lower than the source, which modifies the potential barrier at the 2DEG channel 130. If the magnitude of Vds, IVdsl, becomes large enough, i.e. |Vds| > |Vgs|, it partially reopens the 2DEG channel 130, allowing current to flow in the reverse direction even though Vgs< Vth. For example, for a depletion mode GaN with Vth = -3V, and Vds = -4V this would lead to a reverse conduction of 1V, since a typical Vgs_TH for the depletion mode GaN is -3V.Note, the specific level of the D-GaN threshold is dependent on manufacturing specifications of the respective device, so can vary. What is always true is that Vth in D-GaN is always negative. Typically Vth sits around -3V but examples can even extend to below -5V.

[0026] Figure 2 shows an example of an enhancement mode GaN device 200 according to an example of the disclosure. These enhancement mode GaNs may also be referred to as E-GaNs, normally-off GaNs, or simply enhancement (or enhanced) GaNs. These may also be High Electron Mobility Transistor (HEMT) devices.

[0027] As can be seen from Figure 2, this enhancement mode GaN device structure is largely the same as that shown in Figure 1 for the depletion mode GaN device, except that it has an additional P-GaN layer 175 formed underneath the gate 170. It is this additional P-GaN layer 175 that turns the device into an enhancement mode GaN device, which then makes the device normally off at 0V gate voltage. This is to say adding the P-GaN layer HGF Ref: P390373WO;175 to the gate 170 means a positive voltage is required at the gate (compared to the source), that is, it requires a Vgs> Vth, where Vth > OV. This is currently an industry standard formation for a discrete GaN device, and standard Gate drivers typically apply about a +5V signal to turn the device on, and OV to turn the device off. However, due to the relatively low threshold voltage of these enhancement-mode GaN devices (e.g. typically 1.5-2V), it has become common to apply a small negative gate voltage (e.g. up to only -1 V) to ensure the respective device is truly off. This mitigates instances of false turn-on events from parasitic capacitance discharge, for example, but is limited to only very low negative gate voltages (i.e. no more than -1 ) and for the very specific purpose of preventing inadvertent turn on. This is to say, negative turn off voltage exists but are very limited in magnitude of Vgs, and for a very specific and different purpose to that of the present disclosure (i.e. reverse voltage blocking capability extension).

[0028] Figure 3 shows an example of an enhancement mode GaN monolithic back-to-back device 300 according to an example of the disclosure, in a Common Source arrangement. This type of device is called a back-to-back monolithic device because it connects two enhancement mode GaN devices in series, with their polarities reversed forming a back-to-back device on a single substrate, and they may be in either common source, or common drain, arrangements. The monolithic device 300 of Figure 3 comprises two enhancement mode GaN devices 200 of Figure 2, formed back-to-back so that they have a common source arrangement. These monolithic devices are driven with the same threshold characteristics as the standard enhancement mode GaN of Figure 2, but have two distinct gates. Commercial versions of these devices tend to sit at higher voltage classes than the simple standard / single enhancement mode GaN devices of Figure 2, and they tend to be used for four-quadrant operation (i.e. bi-directional blocking and bi-directional current flow).

[0029] By way of introduction to the benefits of the present disclosure, the current state of play in the power electronics converters area will now be described, in examples involving an inverter, which is a circuit that converts a DC input signal to an AC output signal. These are commonly used in situations where some DC voltage source (e.g. a battery) is used to provide the power source for an AC equipment such as a motor (e.g. in a Electric Vehicle), or the like.

[0030] There are two main types of inverter - the voltage source inverter (VSI) and the current source inverter (CSI). The following description will describe these in terms of a three-phase topology, but they may comprise any number of phases.

[0031] Figure 4 shows a voltage source inverter (VSI) 400 in the example three phase topology, where the voltage source inverter utilises a constant DC voltage source 410 that feeds into a switching arrangement 430, comprising 3 separate half bridges sub-arrangements 432, each comprising two switches (e.g. MOSFETS) 435, that switches the DC voltage 410 to different paths of the three phase arrangements in order to provide the requisite output AC voltages (e.g. approximated sine wave voltages) 440, in this case a set of 3 phase AC signals that are 120 degree out of phase with one another. A suitably sized DC link capacitor Cbus 420 is also usually provided to maintain voltage levels of the DC input voltage 410 - i.e. reduce ripple. Key points to note about this arrangement are: a VSI uses modulated half bridge switching of the DC input voltage 410 to create a sine wave output(s) 440; the bus capacitor (Cbus) 420 is sized to provide a desired amount of ripple (which may result in large sizes for high power).

[0032] Whilst GaNs type devices have been looked into for use in this VSI topology (as drop in replacement for all the switches 435 - i.e. S1 to S6), there are issues meaning that market introduction of practical GaN VSI inverters will take a while. The following issues must be overcome: the switching methodology required causes high dV / dt in the phase legs (i.e. large voltage changes / swings in each of the legs 432 and across each of the HGF Ref: P390373WO;GaN devices 435), which can damage devices, cause voltage stress, e.g. at motor terminals, which can lead to motor burn out, cause electromagnetic interference (EMI), which can easily cause the VSI inverter itself, or neighbouring technical circuitries to fail EMI regulations. As such, GaN VSI inverters require output filters or cable shielding to confirm with EMI regulations, and including those mitigating techniques all impact cost / power density / efficiency of the overall implementations.

[0033] Whilst VSIs have been common to date, there has been an increased interest in finding alternative arrangements, especially for inductive loads.

[0034] Current source inverter’s (CSIs) are a type of power inverter that regulates the current supplied to a load, but the input of a CSI is a DC current. The key difference between a VSI and CSI lies with their energy storage components: CSIs use bus inductors to store energy and ensure a steady input current, whereas VSIs rely on a capacitor for steady input voltage. Both topologies utilize half-bridge transistor layouts to achieve power conversion and can apply multiple phase legs to expand the operational range of the output.

[0035] The development of the concepts of this disclosure started off from beginning to identify the operational needs of CSIs in terms of both passive components and modulation techniques. Together these work to provide the generation of smooth output current waveforms and constant current paths, preventing the interruption of the current flow, which is key consideration for successful operation of a CSI. This is to say, CSIs always provide a defined current path throughout its operation, as will become apparent in the later explanation of their operation, after a quick description of their construction.

[0036] Figure 5 shows an idealised example of a Current Source Inverter 500 according to an example of the disclosure. In a CSI 500, a constant DC voltage source, Vdc, 510 supplies a voltage across a bus inductor Lbus, 520, to supply a constant current to the input of a switching arrangement 530. In this case the switching arrangement 530 comprises a three phase arrangement, where each phase has a half bridge switch subarrangement 532, each comprising two reverse blocking switches 535. These three sub-arrangements 532 operate to provide a respective one of the output currents 540, each having a respective filter capacitor, Ctii, 550 in place, in order to provide current paths for switching inductive loads. Key points to note about this arrangement compared to the VSI of Figure 4 are: a CSI 500 modulates by sinusoidal voltage and current, so there is negligible dV / dt, so there is a naturally low EMI, meaning better EMI regulation support and reduced stress, so longer component life, e.g. electronic motor life, and less EMI mitigation is also needed. Additional passive components can be small, contributing to less losses, however, more importantly, the circuit (especially if in ideal H6 form) requires Reverse Blocking capable switches, in order to preserve correct current paths and protect the passive components (e.g. Lbus, Ctii, etc).

[0037] In more detail, the passive components in a CSI serve very specific roles in ensuring the successful operation of the power conversion. Compared to a VSI, there are two main changes in the passive components: the use of a DC bus inductor 520 in place of a capacitor bus (420 in Figure 4), and a filter capacitor 550 (per output phase).

[0038] The DC bus inductor 520 is the defining feature of a CSI 500 that is integral in realizing sinusoidal output currents, by providing the constant current at the inverter input, switching modulation can be used to produce the desired output waveforms 540. The magnitude and ripple of the current input in a CSI is determined by the sizing of the DC bus inductor 520 and therefore proper design of the bus is required for optimising a CSI.

[0039] On the output side of the CSI inverter 500, the filter capacitor(s) 550 ensures smooth sinusoidal outputs waveforms in the phases. These provide the overall CSI invertor system with the above mentioned benefits of HGF Ref: P390373WO;filtering such as reduced harmonics; reducing voltage spikes and stress on components; reducing EMI; but most importantly providing the desirable smoothing of the output waveforms.

[0040] The sizing of all these passive components (DC bus inductor 520, Cms. 550), directly links to the conduction losses contributed to the overall system efficiency. For example, it is seen that in many CSI applications, the DC bus inductor 520 can be large, causing a significant drop in efficiency. It is because of this, that finding ways to reduce the size of these components is of significant importance when designing a CSI. Below are the equations that may be used to determine the required sizing of passive components:

[0041]

[0042] Where VPh is the phase Voltage, Fswis the switching frequency, idc-PPis the required DC current ripple through the inductor, and LPus is the desired bus inductance. Cf is the required filter capacitance, Idc-rated is the rated current through the output phases, AVCf is the required voltage ripple at the phases.

[0043] From the above equations, it can be seen that for both the bus inductor and the filter capacitor, increasing the switching frequency of the inverter decreases their required size (i.e. higher switching frequency results in lower inductor and capacitor values). As the other variables are fixed by the operational requirements of the CSI and its application, the inverse proportionality of the switching frequency makes it possible to reduce the conduction losses of a CSI and increase its power density at the cost of higher switching frequency and switching losses. Thus, it can be seen that by using GaNs, which have improved switching capability, an improved CSI may be provided, because this may improve the overall efficiency and power density (e.g. of a motor drive).

[0044] Turning now to the general operation of a CSI, Figure 6A to 6D show how the paths are switched using switches 1 to 6, of Figure 5. Note these Figures are shown using non-reverse voltage blocking (RVB) capable switches (i.e. FET1-FET6) in a specific example before the invention was conceived, and so there are some details of the components and / or paths that are only relevant to this way to show the overall circuit. This is to say, only the paths through the switches are really relevant to this discussion). Also, these Figures (and Figures 7A / 7B) also show a true nature of the filter capacitor - 610 and Inductor loads 620 being driven.

[0045] In a CSI according to an example, at no point can all high side (HS) switches (S1 , S3, S5) or low side (LS) switches S2, S4, S6, be off simultaneously, since a constant current path should always be provided for the DC bus inductor. Therefore, in some examples, instead of introducing a switching deadtime, the respective HS and LS switches should undergo a switching overlap. For example, in one example as shown in Figures 6A to 6D (which shows a transition between state 1 and state 2, whilst maintaining constant current flow, as noted is desirable above, from using Switch S1 to S3 via S5), before device S1 can turn off, device S5 should turn on. Once device S5 is on, device S1 can turn off and device S3 can turn on. Then device S5 can turn off, etc.

[0046] However, during this switching overlap, an interphase short can occur dependent on the polarity state of the filter capacitors. This can be destructive to the system, especially the filter capacitors. Therefore, it is necessary to provide an intermediary reverse voltage blocking capability for this overlap. This breaks the current short around the loop, avoiding the instances of shorting between the phases and protecting the filtering circuitry. This is shown in Figures 7A and 7B, where 7B shows that by having reverse voltage blocking (RVB) capable switches, the short is avoided. Also, reverse voltage may also occur as a result of a differential between HGF Ref: P390373WO;Vin and Vout when switches are in their OFF state, so when choosing suitable switching devices for the CSI (esp. a H6 variety), they should be able to provide RVB in both their ON and OFF states.

[0047] However, to date, there were limited ways to provide the required RVB capability for the GaN switches, each having their own disadvantages.

[0048] Accordingly, there is a desire to find practical real-life high performance reverse blocking capable switches to use in a CSI arrangement.

[0049] Figure 8 shows three examples of previously used or suggested reverse blocking capable switching according to an example of the disclosure. These include: a first RVB capable switch 300 which is a monolithic enhancement mode GaN switch (common source arrangement) as shown in Figure 3; a second RVB capable switch 820, this time a common drain monolithic arrangement; and a third RVB capable switch 830, which is a normal enhancement mode GaN switch 834 in series with an independent series diode 834. However, each of these has one or more disadvantages - the monolithic devices double up on device, and hence real estate cost , but they also have complex gate driving requirements for timing purposes. Meanwhile, the switches with a series diode also have increased real estate cost, and contribute to additional losses when conducting.

[0050] GaN devices are still desirable to use, since they have a very fast switching capability, due to them having no reverse recovery charge requirements. Whilst this means that when used in a VSI, the higher switching speed (Fsw) requires quicker turn on and turn off transitions causing high dV / dt, in a CSI, the size of dV / dt is mitigated substantially because current is switched instead. Lower dV / dt reduces EMI and Voltage stress on the system. Also, in a CSI, higher switching speed (Fsw) reduces the size (and losses) of passive components, i.e. Bus Inductor 520, Filter Capacitors 550. Thus, using GaN devices in CSIs enable size and weight reductions, increase power density, and reduce losses. This is to say, as a result of using higher switching speed GaNs, signal integrity may be maintained, Motor lifetime may be preserved, and standards may be easier to adhere to.

[0051] However, there is still a need to provide reverse blocking capability, and the previous examples of known RVB switches, as per Figure 8 have their disadvantages. For example, Figure 9 shows an example of the Current Source Inverter of Figure 5, using back-to-back monolithic devices 300 according to Figure 3 or 6, according to an example of the disclosure. This uses two of the monolithic devices in each half bridge circuit 530, and has the following disadvantages: is requires the use of twice as many devices (four per half bridge circuit, rather than two of the ideal version), it exhibits reduced Power density, at least five isolated grounds are required, and has a significant increase in modulation complexity (i.e. the switching signals for each of the four switches in each half bridge circuit are complex, if overshoot + etc name issues are to be avoided - timing is important), there is higher resistance (Ron) when the switches are on , which leads to higher conduction loss. Thus, this circuit using monolithic devices does not realize the full potential of CSI topologies.

[0052] Accordingly, the present disclosure provides an alternative way to provide reverse blocking capability This alternative is to apply a specific level of reverse bias voltage to the gate 170, so that the natural reverse blocking capability of the GaN device can be extended. The natural reverse bias capability of an enhancement mode GaN device is shown in Figures 10 and 11 , where Figure 10 shows the device of Figure 2, in a gated On state, and Figure 11 shows the device of Figure 2, in a gated Off state.

[0053] In more detail: in Figure 10, the device is being gated On, by applying an example 5V 1010 to the gate 170. Therefore the 2DEG channel 130 produces a sufficiently high electric field, and can carry current 1020 (i.e. the device is switched ON). Whereas, in Figure 11, the gate 170 of the enhancement mode GaN device has 0V applied (i.e. less than the threshold voltage of the device, Vth, which is typically ~1 ,7V), so the 2DEG channel is HGF Ref: P390373WO;‘shut’, i.e. the electric field is not sufficient to form a conductive 2DEG layer, and the enhancement mode GaN exhibits “diode-like” behaviour 1120, thus is in an unidirectional OFF state. In Figure 11, the “diode-like” behaviour 1120 has an effective diode threshold voltage at Vgs= OV that is equal to Vth. This is to say, at OV gate input voltage, the RVB capability of the diode, and hence the overall enhancement mode GaN device, is up to -1.7V.

[0054] The above description of Figure 11 is the simplest operation, but it has been discovered that it is easy to control the effective diode RVB capability, by controlling the voltage applied to the gate - in simplest terms, the larger the negative voltage applied to the gate, then the larger the RVB capability of the diode in the GaN.

[0055] Reverse conduction in a GaN primarily occurs due to the diode-like behaviour of the structure between the drain and source. This parasitic diode is formed between these two terminals. When a negative voltage is applied to the drain relative to the source (reverse bias), this parasitic diode can conduct. When the device is properly turned off (negative Vgs for enhancement-mode or sufficiently negative Vgs for depletion-mode), the electric field in the 2DEG is too weak and the device blocks current flow. However, the parasitic diode remains. Thus a large enough reverse voltage cause the diode to break-down and conduct. In this mode of operation the gate modulates the reverse current of the parasitic diode. This reverse conduction is lossy and unwanted in many circuit topologies. In these occurrences, both the drain potential and the gate potential are contributing to the conductivity of the device. As a result, the GaN exhibits a reverse conduction despite not having a built in body diode. This phenomenon is frequently referred to as GaN’s ”Diode-like Behaviour”. Without a true body diode, when reverse conduction occurs, there is also no reverse recovery charge (Qrr).

[0056] Figure 12 shows the conductive modes 1200 of an Enhancement-mode GaN and the link between reverse voltage, gate bias and conduction through the 2DEG channel, and thereby shows how different reverse voltage blocking capabilities of an enhancement mode GaN HEMTs can be provided by applying different negative Gate biases, according to an example of the disclosure. This figures shows examples at -1 ,7V 1210, -3.7V 1220, -5.7V 1230 and -7.7V 1240, which are provided by applying 0V, -2V, -4V and -6V to the gate respectively. A new term for this RVB capability has been used in the figure - VTHCDR (standing for Controlled Dynamic Reverse Threshold) which tries to encapsulate that this provides a new diode like behaviour based on the threshold voltage. This is all to say, by driving the GaN device with negative voltage in the magnitude ofn(i.e. the input voltage of the whole circuit = Vdc 510 in Figure 5), a true off state for the GaN device can be realized and reverse blocking can be achieved.

[0057] These reverse voltage blocking capabilities at different values of negative gate voltage being applied are also being compared to the normal forward biased conducting status, that is shown as a straight line 1250 in Figure 12. It is of interest to understand that quadrant 3 is the sector within the graph of most interest as it outlines the devices behaviour while a negative voltage is realized across its drain and source (i.e. Vds < 0).

[0058] The different states can be broken down into three distinct types / cases:

[0059] • Case 1 : Device receives a positive gate voltage exceeding its threshold (Vgs> Vth) with Vds < 0.

[0060] • Case 2: The device receives Vgs= 0 with Vds < -Vth.

[0061] • Case 3: The device is subject to negative voltage Vds < 0 and Vgs< Vds.

[0062] Thus, reverse conduction is dependent on the relation between the magnitude of the reverse voltage across the drain source, Vds, and the magnitude and bias of the gate signal, Vgs, so by specific control of the gate voltage, a GaN device can block reverse voltage when it is in its OFF state, and in some examples, the scope of RVB is determined by the maximum rated capabilities of the gate.

[0063] HGF Ref: P390373WO;It will be appreciated that once a working RVB capable GaN device is realised, they may be applied to the different types of CSI’s currently in use - the H6 of Figure 5, as well as the H7 and H8 variants described below, which use seven and eight devices respectively, as opposed to the six devices in the simplest H6 version).

[0064] To recap with reference to the description of Figures 5 to 7B above, in a H6 variant, the CSI deadtime is replaced by a switching overlap between devices on the high side and the low side. Thus, before a device on the high side can turn off, the next current path must be provided. Meanwhile, a complementary null path is provided to maintain the current path, where, with the null path active, the respective switching GaN device can turn off, and the desired next switching GaN device can turn on. Then, the complementary null GaN switching device can now be turned off. The GaN switch used to achieve the complementary null is always the HS or LS switch of the leg that is staying on after the commutation, This is then dependant on the modulation scheme used. The examples shown use a space vector pulse width modulation (SVPWM) scheme but this is just one of many different types of modulation that may be used to drive the switches of an inverter according to the present disclosure.

[0065] A first variant of the CSI topology is the H7 Current Source Inverter (H7-CSI) variant. Figure 13 shows an example of an H7 Current Source Inverter, according to an example of the disclosure. This H7-CSI topology introduces a 7th switching package, S7, 1310, between the Vin and the Ground of the system, without an output phase connected to it. The aim of this extra switch is to replace the need for the overlapping switching occurrence’s at the output phases by providing the constant current path for the DC Link inductor through this additional leg and S7.

[0066] As a result, the phase legs of the CSI do not need the complex modulation technique that causes the shorting of the output phases, and can use simpler methods utilized by VSIs. By doing this, the HS (S1 , S3, S5) and LS (S2, S4, S6) switches on the phase legs no longer need to block reverse voltage during their ON state. The ON state RVB requirement as outlined for H6-CSIs is then placed on S7 only. However, the OFF State RVB requirement still exists for all switching devices in the system.

[0067] To recap with reference to the description of Figures 5 to 7B above, and as described for the H6 variant, a complementary null state switch is required in a H7 topology, this null switch, S7 is always assigned as the 7th shorting leg. Before a device on the high side (e.g. S1 , S3, S5) or low side (S2, S4, S6) can turn off, the next current path must be provided. Thus, switch S7 is turned on to provide a null state current path during those transitions, i.e. before the respective HS switch is turned off. Then the desired next switch can be turned on, and S7 is then turned off.

[0068] A second variant of the CSI topology is the H8 Current Source Inverter (H8-CSI) variant. Figure 14 shows an example of an H8 Current Source Inverter, according to an example of the disclosure. The H8 topology adds a phase short protector 1410 comprising a series diode 1420 and parallel switching device 1430 in series with the DC link Bus inductor 520, on top of the 7thswitch (S7) 1310 of the H7 topology, which removes the requirement of S1-S6 overlap events completely (i.e. no need to have an overlap at all).

[0069] Examples provide a method of driving a GaN in such a way that the device is gated to a negative voltage (~-Vin), i.e. it is not only in its off state, but in a functionally extended state of reverse voltage blocking capability, by using a much higher than normal negative voltage, in order to extend the intrinsic reverse blocking capabilities of the GaN device, thereby enabling their use in Current Source Inverters. The specific level of the negative voltage to use on the gate, in any given implementation, may be determined by matching the

[0070] HGF Ref: P390373WO;magnitude of the negative voltage to the magnitude of the input voltage of the overall CSI circuit (i.e. Vgs= -Vin = (Vdc 510)).

[0071] The foregoing examples may be particularly useful to drive inductive loads Examples of inductive loads are electric motors (e.g. in EVs), transformers, and inductive heating. However, examples may also be used for resistive and other load types.

[0072] The disclosure may provide a new CSI arrangement that uses GaN transistors with a gate voltage purposefully driven to apply a definable blocking voltage to each GaN transistor, in order to induce / define a reverse blocking capability for the respective GaN transistor. In GaN examples, the blocking voltage is a negative gate voltage. Typically, the blocking voltage may be dependent on the CSI input voltage, more typically it is a negative version thereof. This may be so that the negative voltage applied to the gate is such that the reverse blocking capability matches the maximum voltage that could be needed to be blocked.

[0073] The value of the negative voltage applied to the gate of the respective GaN transistor may also be a linear function of the desired reverse blocking voltage, plus the intrinsic threshold voltage of the respective GaN device. For example, where the intrinsic threshold voltage of the respective GaN device, Vth, is 1 ,7V, then the reverse voltage relationship is Vth+(-Vin). In a non-limiting specific example, if the reverse blocking capability required for a particular voltage output is -9.7V, then the value of the negative voltage to be applied to the gate voltage is -8V.

[0074] According to examples, the gate voltage is purposefully controlled to be (a relatively larger) negative voltage in order to maintain a reverse blocking function, rather than (and distinct from) only being a (relatively smaller - e.g. 1V) negative voltage merely used to ensure a respective transistor is fully off, which is a prior measure to only prevent so called false turn-on event, for example caused by parasitic capacitance discharges. This is to say, the previous use of a negative gate voltage was not being applied in order to extend the reverse blocking capability of the device, as per the present disclosure, which is done in order to provide a GaN device that can be used in a current source inverter, but only to prevent inadvertent turn on. Accordingly, the newly proposed GaN device (or method to control the same) enables a CSI to be made out of these newly proposed devices, such that the CSI may actually operate and provide all the theoretical benefits, without any of the known compromises.

[0075] Examples may use existing base discrete GaN devices, since these have been shown to be able to accept up to -30V negative gate voltages, even though the datasheets would suggest they are only good for up to -10V negative gate voltages. This is a surprising result. However, on review, it is believed the high frequency switching nature of operation of these negative gated GaN transistors in CSI’s according to the present disclosure prevents destruction since at no point is the larger value of the negative gate voltage applied for any significant length of time. For example, the high frequency switching may mean the application of only microseconds (or less) of the larger negative voltage.

[0076] Examples may be applied to a high-electron-mobility transistor (HEMT or HEM FET), which is a fieldeffect transistor incorporating a junction between two materials with different band gaps (i.e. a heterojunction) as the channel, instead of a doped region (as per the general case for a MOSFET). HEMTs may also be known as a heterostructure FET (HFET) or a modulation-doped FET (MODFET).

[0077] Examples may provide a method of controlling the switches in a CSI, comprising applying a negative voltage to the gate of each GaN transistor of the CSI at an appropriate time in the control modulation, in order to provide an extended reverse voltage blocking capability for each GaN transistor.

[0078] HGF Ref: P390373WO;Examples may provide a current source inverter (CSI) comprising at least one Gallium Nitride (GaN) transistor including a gate, wherein a predetermined voltage value is applied to the gate of the GaN transistor for at least a portion of time, in order to provide an extended reverse voltage blocking capability for the GaN transistor.

[0079] In some examples, a reverse voltage blocking capability comprises a diode like behaviour, with extendable blocking capability.

[0080] In some examples, the predetermined voltage is a negative voltage.

[0081] In some examples, the predetermined negative voltage applied to the gate extends the intrinsic reverse blocking capabilities of the GaN transistor to a predetermined voltage level.

[0082] In some examples, the predetermined voltage level comprises upto and including a negated version of the input voltage.

[0083] In some examples, the extended reverse voltage blocking capability is defined as to extend beyond simply applying a small negative voltage to only ensure turn off of the GaN transistor.

[0084] In some examples, the negative voltage comprises a negative version of Vin of the CSI.

[0085] In some examples, the negative voltage is scaled according to the input voltage supply of the CSI, in particular to match the input voltage.

[0086] In some examples, the intrinsic reverse voltage blocking capability is derived from a threshold voltage (VT ) of the transistor and wherein the extended reverse voltage blocking capability comprises VT + extended reverse voltage, V1.

[0087] In some examples, VT +V1 = Vth -Vgs. Vth may be dependent on device type (for example, it may be either be positive or negative), In some examples, VTHCDR may be defined as Negative in the Vds direction but positive in the Vsd direction.

[0088] In some examples, the GaN transistor is an enhancement mode GaN or a depletion mode GaN, wherein Enhancement mode GaN = E-GaN, normally-off GaN, and Depletion mode GaN = D-GaN, normally-on Ga.

[0089] In some examples, the enhancement or depletion mode transistors are HEMT transistors.

[0090] In some examples, an enhancement mode GaN transistor comprises a depletion mode transistor with an additional P-GaN material layer between the gate and channel

[0091] In some examples, the at least one GaN transistor comprises one of two switches in a half bridge rectifier arrangement.

[0092] In some examples, the CSI comprises at least three half bridge rectifier arrangements, to provide a three phase power inverter.

[0093] In some examples, the three phase CSI is in an H6 CSI topology.

[0094] In some examples, the CSI is in an H7 topology, comprising three half bridges and a series diode bypass transistor, S7, coupled to the bus inductor (Lbus), wherein two transistors of each half bridge, and the bypass transistor, are GaN transistors with a controlled gate voltage.

[0095] In some examples, a modulation scheme applied to the gate control voltage provides an operation mode of the GaN device comprising: an ON state, a diode mode state and a RVB OFF state.

[0096] In some examples, a switching speed of each of the at least one GaNs is such that a discharge time of filter capacitors at an output of the CSI are slower than a switching overlap transition time between inverter legs of the CSI, wherein an inverter leg consists of two power electronic switches (GaNs) connected in series.

[0097] HGF Ref: P390373WO;In some examples, the upper switch is connected with the positive DC-rail and the lower switch with the negative DC-rail. Both positive and negative rails form the input of a CSI inverter. The mid-point of the two switches is connected with output.

[0098] In some examples, the CSI is an H8 topology, further comprising a phase-short protector, wherein the phase-short protector comprises: a bypass switch transistor, S8, placed in parallel to a diode; and wherein the bypass switch transistor is operable to switch complementarily with the series diode transistor, S7.

[0099] In some examples, the phase-short protector is made from Silicon.

[0100] Examples further comprise a bus inductor and at least one capacitor filter at an output of the CSI.

[0101] In some examples, the CSI is used fordriving inductive loads.

[0102] In some examples, the bypass transistor is coupled between the bus inductor (Lbus) and the series diode (rectifier).

[0103] Examples provide a GaN transistor module for use in a CSI, comprising, a GaN transistor; and a gate driver circuit, configured to selectively apply a predefined negative voltage to the gate of the GaN transistor, in order to provide a reverse voltage blocking capability, especially for use in a CSI arrangement. In some examples, the negative voltage is a negative voltage having the same magnitude as the input voltage of the CSI (i.e. it’s negative version of the input voltage).

[0104] Examples also provide electronic circuitry configured to selectively apply a negative gate voltage to one or more GaN transistors of a CSI, in order to prevent reverse conduction of the one or more GaN transistors.

[0105] Examples also provide a CSI comprising at least one (e.g. E-mode) GaN transistor, wherein a gate voltage of the at least one GaN transistor is controlled to provide a user definable reverse blocking capability of the at least one GaN. Examples also provide a current source inverter (CSI) comprising at least one Gallium Nitride (GaN) transistor including a gate, wherein the gate is configured to receive a predetermined negative voltage value for at least a predetermined portion of time, wherein the application of a predetermined negative voltage value to the gate enhances a reverse blocking voltage capability of the GaN transistor.

[0106] While preferred embodiments of the present invention have been shown and described herein, it will be obvious to those skilled in the art that such embodiments are provided by way of example only. Numerous variations, changes, and substitutions will now occur to those skilled in the art without departing from the scope of the disclosure. For example, all of the dependent claims, or examples, may be intermixed to produce one or more embodiments having various foreseeable attributes (esp. beneficial attributes) derived from such mixtures, and the dependencies are certainly not to be limiting. It should be understood that various alternatives to the embodiments of the invention described herein may be employed in any combination in practicing the disclosure. It is intended that the following claims define the scope of the invention and that methods and structures within the scope of these claims and their equivalents be covered thereby.

[0107] HGF Ref: P390373WO;

Claims

Claims:

1. A current source inverter (CSI) comprising at least one Gallium Nitride (GaN) transistor including a gate, wherein a predetermined voltage value is applied to the gate of the GaN transistor for at least a portion of time, in order to provide an extended reverse voltage blocking capability for the GaN transistor.

2. The CSI of claim 1 , wherein a reverse voltage blocking capability comprises a diode like behaviour, with extendable blocking capability.

3. The CSI of claim 1 or 2, wherein the predetermined voltage is a negative voltage.

4. The CSI of claim 3, wherein the predetermined negative voltage applied to the gate extends the intrinsic reverse blocking capabilities of the GaN transistor to a predetermined voltage level.

5. The CSI of claim 4, wherein the predetermined voltage level comprises up to and including a negated version of the input voltage.

6. The CSI of claim 4 or 5, wherein the negative voltage comprises a negative version of Vin of the CSI.

7. The CSI of any of claims 4 to 6, wherein the intrinsic reverse voltage blocking capability is derived from a threshold voltage (VT ) of the transistor; andwherein the extended reverse voltage blocking capability comprises VT + extended reverse voltage, V1.

8. The CSI of claim 7, wherein VT +V1 = Vth -Vgs.

9. The CSI of any preceding claim, wherein the GaN transistor is an enhancement mode GaN or a depletion mode GaN10. The CSI of claim 9, wherein an enhancement mode GaN transistor comprises a depletion mode transistor with an additional P-GaN material layer between the gate and channel11. The CSI of any preceding claim, wherein the at least one GaN transistor comprises one of two switches in a half bridge rectifier arrangement.

12. The CSI of claim 11 , wherein the CSI comprises at least three half bridge rectifier arrangements, to provide a three phase power inverter.

13. The CSI of claim 12, wherein the CSI is in an H7 topology, comprising:three half bridges and a series diode bypass transistor, S7, coupled to the bus inductor (Lbus), wherein two transistors of each half bridge, and the bypass transistor, are GaN transistors with a controlled gate voltage.HGF Ref: P390373WO;14. The CSI of claim 13, wherein a modulation scheme applied to the gate control voltage provides an operation mode of the GaN device comprising: an ON state, a diode mode state and a RVB OFF state.

15. The CSI of any preceding claim, wherein a switching speed of each of the at least one GaNs is such that a discharge time of filter capacitors at an output of the CSI are slower than a switching overlap transition time between inverter legs of the CSI, wherein an inverter leg consists of two power electronic switches (GaNs) connected in series.

16. The CSI of any of claims 13 to 15, wherein the CSI is an H8 topology, further comprising a phase-short protector, wherein the phase-short protector comprises:a bypass switch transistor, S8, placed in parallel to a diode; andwherein the bypass switch transistor is operable to switch complementarily with the series diode transistor, S7.

17. The CSI of claim 16, wherein phase-short protector is made from Silicon.

18. The CSI of any preceding claim, further comprising a bus inductor and at least one capacitor filter at an output of the CSI.

19. The CSI of any preceding claim, wherein the CSI is used for driving inductive loads.

20. A method of controlling the switches in a CSI, comprising:applying a negative voltage to the gate of each GaN transistor of the CSI at an appropriate time in the control modulation, in order to provide an extended reverse voltage blocking capability for each GaN transistor.

21. The method of claim 20, wherein the negative voltage comprises a negative version of Vin.HGF Ref: P390373WO;

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