Display device

Abstract

Provided is a display device having high reliability and a narrow bezel. The display device includes pixels and a drive circuit having a function of controlling driving of the pixels. The drive circuit includes a plurality of first transistors provided in a first layer, and a plurality of second transistors provided in a second layer overlapping the first layer. The electrical characteristics of the first transistors are different from the electrical characteristics of the second transistors. The second transistors each have a region overlapping at least one of the first transistors.

Description

display device

[0001] One aspect of the present invention relates to a display device. One aspect of the present invention relates to a transistor. One aspect of the present invention relates to a display device having a transistor.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), methods for driving them, or methods for manufacturing them.

[0003] In this specification, a semiconductor device refers to a device that utilizes semiconductor properties, including circuits containing semiconductor elements (transistors, diodes, photodiodes, etc.), and devices having such circuits. It also refers to any device that can function by utilizing semiconductor properties. For example, integrated circuits, chips equipped with integrated circuits, and electronic components with chips housed in packages are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, and electronic devices are themselves semiconductor devices, and may each have semiconductor devices.

[0004] In recent years, there has been a growing demand for high-definition display devices. Devices requiring high-definition display capabilities include those for virtual reality (VR), augmented reality (AR), substitute reality (SR), and mixed reality (MR), all of which are being actively developed.

[0005] Examples of display devices include display devices having liquid crystal elements and display devices having light-emitting elements (also called light-emitting devices). Examples of light-emitting elements include organic EL (Electroluminescence) elements and light-emitting diodes (LEDs). Patent document 1 discloses a high-definition display device using organic EL elements.

[0006] Technology related to transistors using semiconductor thin films is attracting attention. These transistors are widely applied in electronic devices such as integrated circuits (ICs) and display devices. While silicon-based semiconductor materials are widely known as semiconductor materials applicable to transistors, oxide semiconductors are also attracting attention as other materials.

[0007] Examples of oxide semiconductors applicable to transistors include indium oxide and indium gallium zinc oxide. Non-patent documents 1 and 2 disclose thin-film transistors using indium oxide.

[0008] International Publication No. 2016 / 038508

[0009] Dhananjay and C. W. Chu, “Realization of In▲2▼O▲3▼ thin film transistors through reactive evaporation process” Appl. Phys. Lett. 91, 132111 (2007). Y. Magari et al. Takashi Koida, “High-mobility hydrogenerated polycrystalline In2O3 (In2O3:H) thin-film transistors”, Nature Communications, 13, 1078 (2022) Takashi Koida, “High-mobility transparent conductive film”, National Institute of Advanced Industrial Science and Technology, AIST Photovoltaic Power Generation Research Results Presentation Meeting 2019, Internet <URL: https: / / unit.aist.go.jp / rpd-envene / PV / ja / results / 2019 / oral / T13.pdf>

[0010] One aspect of the present invention aims to provide a display device with a narrow bezel. Alternatively, it aims to provide a semiconductor device or display device with a small footprint. Alternatively, it aims to provide a highly reliable transistor, semiconductor device, or display device. Alternatively, it aims to provide a semiconductor device or display device that operates at high speed. Alternatively, it aims to provide a semiconductor device or display device with low power consumption. Alternatively, it aims to provide a semiconductor device or display device with low wiring resistance. Alternatively, it aims to provide a display device with high display quality. Alternatively, it aims to provide a high-definition display device.

[0011] Alternatively, one of the objectives is to provide a semiconductor device or display device having a transistor with high field-effect mobility. Alternatively, one of the objectives is to provide a semiconductor device or display device having a transistor with a large on-current. Alternatively, one of the objectives is to provide a semiconductor device or display device having a transistor of a very small size. Alternatively, one of the objectives is to provide a semiconductor device or display device having a transistor with a short channel length. Alternatively, one of the objectives is to provide a semiconductor device or display device having a transistor with good electrical characteristics.

[0012] Alternatively, one of the objectives is to provide a method for manufacturing the aforementioned transistor, semiconductor device, or display device. Alternatively, one of the objectives is to provide a highly productive method for manufacturing a transistor, semiconductor device, or display device. Alternatively, one of the objectives is to provide a novel transistor, semiconductor device, display device, or a method for manufacturing the same.

[0013] Furthermore, the description of these problems does not preclude the existence of other problems. One aspect of the present invention does not necessarily have to solve all of these problems. It is possible to extract other problems from the description in the specification, drawings, and claims.

[0014] One aspect of the present invention is a display device comprising a drive circuit and a pixel, wherein the drive circuit comprises a plurality of first transistors provided in a first layer and a plurality of second transistors provided in a second layer overlapping the first layer, the source or drain of at least one of the plurality of first transistors is electrically connected to the pixel, and the channel width of the first transistor is greater than the channel width of the second transistor.

[0015] Alternatively, in the above embodiment, the drive circuit may have a buffer circuit, and the plurality of first transistors may be included in the buffer circuit.

[0016] Alternatively, in the above embodiment, the pixel has a third transistor provided in the first layer and a fourth transistor provided in the second layer, and the source or drain of at least one of the plurality of first transistors may be electrically connected to the source, drain, or gate of the third transistor.

[0017] Alternatively, in the above embodiment, the pixel may have an element-emitting element, and the source or drain of the fourth transistor may be connected to one electrode of the element-emitting element.

[0018] Alternatively, one aspect of the present invention is a display device comprising a drive circuit and a pixel, wherein the drive circuit is electrically connected to the pixel, and the drive circuit is composed of a plurality of first transistors provided on a first layer, a plurality of second transistors provided on a second layer on the first layer, and a plurality of first capacitive elements provided on the second layer, wherein the source or drain of each of the plurality of second transistors is electrically connected to an electrode of one of the plurality of first capacitive elements.

[0019] Alternatively, in the above embodiment, the semiconductor layers of each of the multiple first transistors and the multiple second transistors may be made of the same material.

[0020] Alternatively, in the above embodiment, the off-current of the second transistor may be lower than the off-current of the first transistor.

[0021] Alternatively, in the above embodiment, the pixel may include a light-emitting element, a third transistor provided in the first layer, a fourth transistor provided in the second layer, and a second capacitive element provided in the second layer, wherein one electrode of the light-emitting element is electrically connected to the source or drain of the third transistor, one of the source and drain of the fourth transistor is electrically connected to a drive circuit, and the other of the source and drain of the fourth transistor is electrically connected to one electrode of the second capacitive element.

[0022] Alternatively, in the above embodiment, the semiconductor layers of each of the multiple first transistors, multiple second transistors, third transistors, and fourth transistors may be made of the same material.

[0023] Alternatively, in the above embodiment, the off-currents of the second transistor and the fourth transistor may be lower than the off-currents of the first transistor and the third transistor.

[0024] Alternatively, in the above embodiment, the semiconductor layer may have indium and oxygen.

[0025] According to one aspect of the present invention, a narrow-bezel display device can be provided. Alternatively, a semiconductor device or display device with a small footprint can be provided. Alternatively, a highly reliable transistor, semiconductor device, or display device can be provided. Alternatively, a high-speed operating semiconductor device or display device can be provided. Alternatively, a semiconductor device or display device with low power consumption can be provided. Alternatively, a semiconductor device or display device with low wiring resistance can be provided. Alternatively, a display device with high display quality can be provided. Alternatively, a high-definition display device can be provided.

[0026] Alternatively, a semiconductor device or display device can be provided that has a transistor with high field-effect mobility. Alternatively, a semiconductor device or display device can be provided that has a transistor with a large on-current. Alternatively, a semiconductor device or display device can be provided that has a transistor of a very small size. Alternatively, a semiconductor device or display device can be provided that has a transistor with a short channel length. Alternatively, a semiconductor device or display device can be provided that has a transistor with good electrical characteristics.

[0027] Alternatively, we can provide a method for manufacturing the aforementioned transistors, semiconductor devices, or display devices. Alternatively, we can provide a highly productive method for manufacturing transistors, semiconductor devices, or display devices. Alternatively, we can provide novel transistors, semiconductor devices, display devices, or methods for manufacturing them.

[0028] Furthermore, the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description, drawings, and claims.

[0029] Figure 1A is a block diagram showing an example of the configuration of a display device. Figure 1B is a cross-sectional view showing an example of the configuration of a display device. Figure 2 is a block diagram showing an example of the configuration of a display device. Figure 3 is a block diagram showing an example of the configuration of a display device. Figures 4A and 4B are block diagrams showing an example of the configuration of a drive circuit. Figures 5A and 5B are plan views showing an example of the configuration of a display device. Figure 6 is a cross-sectional view showing an example of the configuration of a display device. Figures 7A and 7B are cross-sectional views showing an example of the configuration of a display device. Figure 8 is a cross-sectional view showing an example of the configuration of a display device. Figure 9 is a cross-sectional view showing an example of the configuration of a display device. Figures 10A and 10B are cross-sectional views showing an example of the configuration of a display device. Figure 11 is a cross-sectional view showing an example of the configuration of a display device. Figure 12A is a cross-sectional view showing an example of the configuration of a display device. Figure 12B is a circuit diagram showing an example of the configuration of a display device. Figure 13 is a cross-sectional view showing an example of the configuration of a display device. Figures 14A and 14B are plan views showing an example of the configuration of a display device. Figure 15 is a cross-sectional view showing an example of the configuration of a display device. Figure 16 is a cross-sectional view showing an example of the configuration of a display device. Figures 17A and 17B are plan views showing an example of the configuration of a display device. Figure 18 is a cross-sectional view showing an example of the configuration of a display device. Figures 19A and 19B are cross-sectional views showing an example of the configuration of a display device. Figures 20A, 20B, 20C, and 20D are cross-sectional views showing an example of the configuration of a transistor. Figure 21 is a block diagram showing an example of the configuration of a drive circuit. Figures 22A and 22B are circuit diagrams showing an example of the configuration of a drive circuit. Figures 23A and 23B are circuit diagrams showing an example of the configuration of a drive circuit. Figures 24A and 24B are circuit diagrams showing an example of the configuration of a drive circuit. Figures 25A and 25B are circuit diagrams showing an example of the configuration of a drive circuit. Figure 26 is a circuit diagram showing an example of the configuration of a drive circuit. Figures 27A and 27B are cross-sectional views showing an example of the configuration of a display device. Figure 28 is a cross-sectional view showing an example of the configuration of a display device. Figures 29A and 29B are cross-sectional views showing an example of the configuration of a display device. Figures 30A, 30B, 30C, and 30D are circuit diagrams showing an example of the configuration of a pixel. Figures 31A and 31B are circuit diagrams showing an example of the configuration of a pixel. Figures 32A and 32B are circuit diagrams showing examples of pixel configurations. Figures 33A and 33B are circuit diagrams showing examples of memory cell configurations.Figures 34A and 34B illustrate the carrier concentration dependence of hole mobility. Figure 34C is a cross-sectional view illustrating an indium oxide film. Figures 35A, 35B, 35C, and 35D show examples of electronic equipment. Figures 36A, 36B, 36C, 36D, 36E, and 36F show examples of electronic equipment. Figures 37A, 37B, 37C, 37D, 37E, 37F, and 37G show examples of electronic equipment. Figures 38A and 38B show examples of vehicles.

[0030] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Accordingly, the present invention shall not be construed as being limited to the descriptions of the embodiments shown below.

[0031] In the configuration of the invention described below, the same reference numerals are used in common across different drawings for identical parts or parts having similar functions, and repeated explanations are omitted. Furthermore, when referring to similar functions, the hatching patterns are the same, and reference numerals may not be assigned.

[0032] The position, size, and scope of each component shown in the drawings may not represent the actual position, size, and scope for the sake of ease of understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, and scope disclosed in the drawings.

[0033] In this specification, ordinal numbers such as "first," "second," etc., are added to avoid confusion of components and do not limit the number of components or the order of components (e.g., process order or stacking order). Furthermore, even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion of components. Even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Even if a term has an ordinal number in this specification, an ordinal number may be omitted in the claims.

[0034] In this specification and drawings, when the same reference numeral is used for multiple elements, and especially when it is necessary to distinguish them, the reference numeral may be accompanied by an identifying numeral such as "_1", "[n]", or "[m,n]". Furthermore, when describing a common matter for multiple elements with identifying numerals, or when it is not necessary to distinguish them, the identifying numeral may be omitted.

[0035] The words "film" and "layer" can be interchanged depending on the context or situation. For example, the term "conductive layer" can be changed to "conductive film." Or, for example, the term "insulating film" can be changed to "insulating layer."

[0036] A transistor is a type of semiconductor device that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conductivity. Transistors as used herein include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0037] The functions of "source" and "drain" may be reversed when transistors of different polarities are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably. Furthermore, the names of the source and drain of a transistor can be appropriately rephrased as source region and drain region, or source electrode and drain electrode, etc., depending on the situation.

[0038] The terms "gate" and "back gate" are interchangeable. Therefore, in this specification, the terms "gate" and "back gate" may be used interchangeably. Furthermore, the names of the gate and back gate of a transistor can be appropriately rephrased as gate electrode and back gate electrode, etc., depending on the context.

[0039] In this specification, "connection" includes, for example, "electrical connection." The term "electrical connection" is sometimes used to define the connection relationship of circuit elements as a physical object. Furthermore, "electrical connection" includes both "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the use of circuit elements (e.g., transistors, switches, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected through one or more circuit elements. A, B, and C (described later) refer to objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0040] For example, assuming a circuit containing A and B is in operation, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected" as physical objects. Furthermore, even if there is a timing during the circuit's operation when no electrical signals are exchanged or potential interactions occur between A and B, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected."

[0041] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where "A and B are not indirectly connected" is when an insulator is interposed in the path from A to B. Specifically, this includes cases where a capacitive element is connected between A and B, or where the gate insulating layer of a transistor is interposed between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of a transistor are indirectly connected."

[0042] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via source and drain in the path from A to B, and a constant potential V is supplied from a power supply, GND, etc., to the nodes between the transistors.

[0043] In this specification, unless otherwise specified, on-current refers to the drain current (also called the conduction state) when the transistor is in the on state. Unless otherwise specified, the on state refers to the state in an n-channel transistor where the voltage between the gate and source (gate voltage, also called Vg or Vgs) is equal to or greater than the threshold voltage (also called Vth), and in a p-channel transistor where it is less than or equal to the threshold voltage.

[0044] In this specification, unless otherwise specified, off-current refers to the source-drain leakage current when the transistor is in the off state (also called the non-conductive state or cutoff state). Unless otherwise specified, the off state refers to the state in an n-channel transistor where the voltage between the gate and source is lower than the threshold voltage, and in a p-channel transistor where it is higher than the threshold voltage.

[0045] In this specification, "parallel" means a state in which two lines are positioned at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Furthermore, "approximately parallel" means a state in which two lines are positioned at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" means a state in which two lines are positioned at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Furthermore, "approximately perpendicular" means a state in which two lines are positioned at an angle of 60 degrees or more and 120 degrees or less.

[0046] In this specification, the top surface shape of a component refers to the contour shape of the component when viewed from above (also called a plan view). Furthermore, a top view refers to viewing from the direction normal to the surface on which the component is formed, or to the surface of the support (e.g., substrate) on which the component is formed.

[0047] In this specification, "matching or roughly matching top shapes" means that at least a portion of the contours overlaps between stacked layers. For example, this includes cases where the upper and lower layers are processed with the same mask pattern, or partially with the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer, and in this case too, it may be said that "matching or roughly matching top shapes." Furthermore, when the top shapes match or roughly match, it may also be said that "the edges match or roughly match," or "the edges are aligned or roughly aligned."

[0048] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. The angle formed between the inclined side surface and the substrate surface or the surface to be formed may be called the taper angle.

[0049] In this specification, "step breakage" refers to the phenomenon in which a layer, film, or electrode is divided due to the shape of the surface on which it is formed (e.g., a step or other difference).

[0050] In this specification, "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated. For example, an island-like metal oxide layer refers to a state in which the metal oxide layer and adjacent metal oxide layers are physically separated.

[0051] In this specification, space groups are denoted using the international notation (or Hermann-Mauguin notation) Short notation. In addition, space group numbers from the International Tables for Crystallography Volume A (hereinafter also referred to as ITA) may be included. Furthermore, Miller indices are used to indicate crystal planes and crystal directions. In crystallography, space groups, crystal planes, and crystal directions are indicated by a bar above the number, but in this specification, due to formatting constraints, a minus sign (-) may be placed before the number instead of a bar above it. In addition, individual orientations indicating directions within a crystal are indicated by [ ], collective orientations indicating all equivalent directions are indicated by < >, individual crystal planes are indicated by ( ), and collective planes with equivalent symmetry are indicated by {}. Note that even with the same space group number, the notation for the space group may differ depending on how the crystal axes are defined.

[0052] In this specification, devices fabricated using a metal mask or FMM (Fine Metal Mask, a high-resolution metal mask) may be referred to as MM (metal mask) structured devices. In addition, in this specification, devices fabricated without using a metal mask or FMM may be referred to as MML (metal maskless) structured devices.

[0053] In this specification, holes or electrons may be referred to as "carriers." For example, in a light-emitting element, a hole injection layer or electron injection layer may be called a "carrier injection layer," a hole transport layer or electron transport layer may be called a "carrier transport layer," and a hole blocking layer or electron blocking layer may be called a "carrier blocking layer." Note that the above-mentioned carrier injection layer, carrier transport layer, and carrier blocking layer may not always be clearly distinguishable. Furthermore, a single layer may combine the functions of two or three of the carrier injection layer, carrier transport layer, and carrier blocking layer.

[0054] In this specification, a light-emitting element has an EL layer between a pair of electrodes (a first electrode and a second electrode). The light-emitting element includes a first electrode, an EL layer on the first electrode, and a second electrode on the EL layer. The EL layer has at least a light-emitting layer. Here, examples of layers (also called functional layers) that the EL layer has include a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier block layer (hole block layer and electron block layer). In this specification, a photodetector (also called a photodetector device) has at least an active layer that functions as a photoelectric conversion layer between a pair of electrodes. In this specification, one of the first electrode and the second electrode may be referred to as a pixel electrode, and the other as a common electrode.

[0055] In this specification, flexibility refers to the property of an object being flexible and able to bend. It is the property of an object being able to deform in response to an external force applied to it, regardless of whether it is elastic or able to return to its original shape.

[0056] For example, flexible electronic devices, flexible display devices (also called flexible displays, etc.), flexible batteries (also called flexible batteries, etc.), and flexible substrates (also called flexible substrates, etc.) can each be deformed in response to external forces. Flexible electronic devices, flexible display devices, flexible batteries, and flexible substrates can each be used fixed in a deformed state, repeatedly deformed and used, or used in an undeformed state. The phrase "deforms in response to external forces" above means that it can be deformed by an average adult's hand without requiring excessive force. Furthermore, flexibility can be quantified as the deformation of an object in response to an external force using a testing machine capable of measuring stress-strain (tensile testing machine, compression testing machine, etc.).

[0057] In this specification, when an object is described as having flexibility, it means that at least a part of the object is flexible. In other words, a flexible object may also have parts that are not flexible (which can be called rigid parts).

[0058] In this specification, when two objects are deformed by the same external force, the object that deforms more is said to be the object with higher flexibility. Also, when a first part and a second part of an object are deformed by the same external force, the part that deforms more is said to be the part with higher flexibility.

[0059] (Embodiment 1) In this embodiment, a display device and a semiconductor device according to one aspect of the present invention will be described with reference to the drawings. The semiconductor device according to one aspect of the present invention can be suitably used, for example, in one or both of the pixel circuit and the drive circuit of a display device.

[0060] <Example of Display Device Configuration 1> Figure 1A is a block diagram showing an example of the configuration of a display device 70. The display device 70 has a display unit 62 and a circuit unit 64.

[0061] The display unit 62 is an area for displaying an image and has a plurality of periodically arranged pixels 17. Each of the plurality of pixels 17 has, for example, a display element and a transistor. Alternatively, each of the plurality of pixels 17 has, for example, a sensor element and a transistor. Alternatively, each of the plurality of pixels 17 has, for example, a display element, a sensor element and a transistor. However, one aspect of the present invention is not limited to these. For example, the display unit 62 may have elements other than pixels 17. Alternatively, for example, the display unit 62 may have a plurality of pixels 17 with different configurations.

[0062] In this specification, a pixel refers to the smallest unit constituting a display unit. A pixel has a pixel circuit. A pixel circuit has at least one transistor. A pixel also has an element connected to the pixel circuit. The pixel circuit has a function to control the driving of the element. Examples of such elements include display elements and sensor elements. A pixel circuit can be described as a semiconductor device.

[0063] The pixel arrangement in a display device according to one aspect of the present invention is not particularly limited, and various methods can be applied. Examples of pixel arrangements include stripe arrangements, S-stripe arrangements, matrix arrangements, delta arrangements, Bayer arrangements, and pentile arrangements.

[0064] Various elements can be used as display elements. Examples of display elements include organic EL elements, liquid crystal elements, light-emitting diodes, and electrophoretic elements. In addition, various elements can be used as sensor elements. Examples of sensor elements include photodiodes, image sensors, illuminance sensors, ultrasonic detection elements, and touch sensor elements.

[0065] The display unit 62 may have at least one display area and one sensor area. In this case, one pixel 17 may have at least one of a display element, a sensor element, and a transistor. Alternatively, one pixel 17 may have a display element and a transistor, and another pixel 17 may have a sensor element and a transistor. Therefore, a pixel 17 having a sensor element and a pixel 17 having a display element may be arranged adjacent to each other. For example, in the display unit 62, the display area and the sensor area may be arranged to overlap. However, one aspect of the present invention is not limited to these. In the display unit 62, for example, the display area and the sensor area may be arranged separately. Or, for example, the display unit 62 may have multiple display areas. Or, for example, the display unit 62 may have multiple sensor areas. Or, for example, the display unit 62 may have only a display area and no sensor area. Alternatively, for example, the display unit 62 may have display elements but not sensor elements. Alternatively, for example, the display unit 62 may have only a sensor area but not a display area. Alternatively, for example, the display unit 62 may have sensor elements but not display elements. If the display unit 62 does not have a display area or display elements but has a sensor area or sensor elements, it may be referred to by a different device name (e.g., imaging device, sensor device, reading device, etc.) instead of a display device. Similarly, if it has sensor elements, it may be referred to as an imaging unit, sensor unit, or reading unit instead of a display unit.

[0066] The circuit section 64 is provided with a drive circuit. The drive circuit has the function of controlling the operation of the pixel 17, specifically the operation of the pixel circuit of the pixel 17. In the example shown in Figure 1A, the drive circuit is shown as a scan line drive circuit 33, a scan line drive circuit 34, a signal line drive circuit 35, and a signal line drive circuit 36. Note that the circuit section 64 does not necessarily have to be provided with a scan line drive circuit 33 or a scan line drive circuit 34. Also, the circuit section 64 does not necessarily have to be provided with a signal line drive circuit 35 or a signal line drive circuit 36. Furthermore, the circuit section 64 may be provided with circuits other than the scan line drive circuit and the signal line drive circuit. Here, the scan line drive circuit is also called a gate driver circuit. The signal line drive circuit is also called a source driver circuit. Note that the drive circuit can be described as a semiconductor device.

[0067] The circuit section 64 can be equipped with various circuits such as a shift register circuit, a level shifter circuit, an inverter circuit, a latch circuit, an analog switch circuit, a demultiplexer circuit, and a logic circuit. The circuit section 64 can also be provided with transistors, capacitive elements, and the like.

[0068] Scan line drive circuits 33 and 34 are connected to pixels 17 via wiring 23. Wiring 23 is connected, for example, to the gate of a transistor in a pixel 17. This transistor functions, for example, as a switch. Here, pixels 17 in the same row can be connected to the same wiring 23. Wiring 23 is also called a scan line.

[0069] The signal line drive circuit 35 and the signal line drive circuit 36 ​​are connected to the pixels 17 via wiring 25. The wiring 25 is connected, for example, to the source or drain of a transistor in the pixel 17. Here, pixels 17 in the same row can be connected to the same wiring 25. The wiring 25 is also called a signal line.

[0070] In this specification, etc., if an element A not included in the pixel is connected to at least one of the pixel's components, such as the source, drain, and gate of a transistor in the pixel, then element A is said to be connected to the pixel. For example, if at least one of the source, drain, and gate of a transistor included in circuit A is connected to at least one of the source, drain, and gate of a transistor included in the pixel, then circuit A is said to be connected to the pixel.

[0071] The scan line drive circuits 33 and 34 have a function to select, for example, the pixels 17 on which to write image data, row by row. Specifically, the scan line drive circuits 33 and 34 can select the pixels 17 on which to write image data by supplying a selection signal to the wiring 23.

[0072] In the example shown in Figure 1A, the scan line drive circuit 33 and the scan line drive circuit 34 can supply the same selection signal to the same wiring 23 from both the left and right sides. This allows the display device 70 to operate at a higher speed than when it does not have the scan line drive circuit 33 or the scan line drive circuit 34. Furthermore, even if the size of the display unit 62 is large or the length of the wiring 23 is long, it is possible to suppress a decrease in the operation of the display device 70.

[0073] The signal line drive circuits 35 and 36 have the function of generating image data. The image data can be represented as a signal (image signal). The image signal is supplied to the pixels 17 via the wiring 25. For example, image data can be written to all pixels 17 included in the row selected by the scan line drive circuits 33 and 34.

[0074] One or both of the signal line drive circuit 35 and the signal line drive circuit 36 ​​can have the function of a reading circuit. One or both of the signal line drive circuit 35 and the signal line drive circuit 36 ​​can have the function of reading current from wiring arranged in the display unit 62, for example, from output lines. Alternatively, one or both of the signal line drive circuit 35 and the signal line drive circuit 36 ​​can have the function of reading signals from wiring connected to the pixel 17, for example. For example, current can be supplied from the transistor in the pixel 17, and the current from the pixel 17 can be supplied to the signal line drive circuit 35 or the signal line drive circuit 36 ​​via the output line. As a result, for example, the characteristic variation of the transistor in the pixel 17 can be read by the signal line drive circuit 35 or the signal line drive circuit 36. As a result, for example, it becomes possible to correct the characteristic variation of the transistor in the pixel 17.

[0075] Furthermore, one or both of the signal line drive circuit 35 and the signal line drive circuit 36 ​​have the function of reading signals from wiring arranged in the display unit 62, for example, from sensor lines. As a result, the signals read from the sensor elements of the display unit 62 can be extracted to the outside with as little attenuation as possible.

[0076] In the example shown in Figure 1A, the signal line drive circuit 35 and the signal line drive circuit 36 ​​can supply the same signal, for example, the same image signal, to the same wiring 25 from both the upper and lower sides. This allows the display device 70 to operate at a higher speed than when it does not have the signal line drive circuit 35 or the signal line drive circuit 36. Furthermore, even if the size of the display unit 62 is large or the length of the wiring 25 is long, it is possible to suppress a slowdown in the operation of the display device 70.

[0077] Figure 1B is a cross-sectional view showing an example of the configuration of the display device 70. Figure 1B shows the circuit section 64 and the display section 62 of the display device 70.

[0078] Figure 1B shows an example where the circuit section 64 does not overlap with the display section 62. However, at least a portion of the circuit section 64 may overlap with the display section 62.

[0079] As shown in Figure 1B, the display device 70 includes a substrate 51, a layer 11 on the substrate 51, and a layer 21 on the layer 11. In the circuit section 64, a transistor 10A is provided on layer 11. A transistor 20A is also provided on layer 21. Here, the circuit section 64 can be provided with multiple transistors 10A. Similarly, the circuit section 64 can be provided with multiple transistors 20A.

[0080] It is preferable that transistor 20A has a region that overlaps with transistor 10A. This allows the occupied area of ​​the circuit section 64 to be reduced compared to the case where transistor 20A does not overlap with transistor 10A. Thus, a narrow-bezel display device can be realized.

[0081] The display unit 62 includes a display element 13 and a pixel circuit 15. In the display unit 62, a transistor 10B is provided in layer 11. A transistor 20B is provided in layer 21. The transistor 20B shown in Figure 1B is connected to the display element 13. Alternatively, the transistor 10B may be connected to the display element 13.

[0082] Multiple transistors 10B can be provided on layer 11 of the display unit 62. Furthermore, multiple transistors 20B can be provided on layer 21 of the display unit 62. In the case where multiple transistors 20B are provided on layer 21, for example, one of the multiple transistors 20B is connected to the display element 13. Alternatively, one of the multiple transistors 10B may be connected to the display element 13.

[0083] It is preferable that transistor 20B has a region that overlaps with transistor 10B. This allows the area occupied per pixel 17 to be reduced compared to the case where transistor 20B does not overlap with transistor 10B. Thus, a high-definition display device can be realized.

[0084] Figure 2 shows an example in which the scan line drive circuit 33 and scan line drive circuit 34 shown in Figure 1A are connected to different wirings 23. In Figure 2, the wiring 23 connected to the scan line drive circuit 33 is denoted as wiring 23a, and the wiring 23 connected to the scan line drive circuit 34 is denoted as wiring 23b.

[0085] Figure 2 shows an example where the signal line drive circuit 35 and signal line drive circuit 36 ​​shown in Figure 1A are connected to different wirings 25. In Figure 2, the wiring 25 connected to the signal line drive circuit 35 is denoted as wiring 25a, and the wiring 25 connected to the signal line drive circuit 36 ​​is denoted as wiring 25b.

[0086] In the example shown in Figure 2, the scan line drive circuit 33 and the scan line drive circuit 34 can supply selection signals to separate wirings 23. In this case, the layout area of ​​the scan line drive circuit 33 and the scan line drive circuit 34 can be reduced compared to the case where the scan line drive circuit 33 and the scan line drive circuit 34 supply selection signals to the same wiring 23, as shown in Figure 1A. On the other hand, in the example shown in Figure 1A, the display device 70 can be operated at a higher speed than in the example shown in Figure 2.

[0087] Furthermore, in the example shown in Figure 2, the signal line drive circuit 35 and the signal line drive circuit 36 ​​can supply signals to separate wirings 25, for example. In this case, the layout area of ​​the signal line drive circuit 35 and the signal line drive circuit 36 ​​can be reduced compared to the case where the signal line drive circuit 35 and the signal line drive circuit 36 ​​supply signals to the same wiring 25, as shown in Figure 1A. On the other hand, the example shown in Figure 1A allows the display device 70 to operate at a higher speed than the example shown in Figure 2. Note that the scan line drive circuit 33 and the scan line drive circuit 34 may supply the same selection signal to the same wiring 23 from both the left and right sides, for example, while the signal line drive circuit 35 and the signal line drive circuit 36 ​​supply signals to separate wirings 25. Alternatively, the scan line drive circuit 33 and the scan line drive circuit 34 may supply selection signals to separate wirings 23, while the signal line drive circuit 35 and the signal line drive circuit 36 ​​supply signals to the same wiring 25.

[0088] When the signal line drive circuit 35 and the signal line drive circuit 36 ​​supply a signal to another wiring 25, for example, the signal line drive circuit 35 may drive pixels that display a certain color and pixels that display another color, and the signal line drive circuit 36 ​​may drive pixels that display the remaining colors. For example, the signal line drive circuit 35 may drive pixels that display a first color and pixels that display a second color, and the signal line drive circuit 36 ​​may drive pixels that display a third color. In this way, by separating the signal line drive circuit 35 and the signal line drive circuit 36 ​​for each color, the layout area of ​​the circuit section 64 can be reduced. For example, when the pixel arrangement is a pentile arrangement or a diamond arrangement, the number of pixels provided in the pixel 17 differs depending on the color. For example, the number of pixels that display a third color may be greater than the number of pixels that display a first color and the number of pixels that display a second color. Specifically, the number of pixels displaying the third color may be equal to the sum of the number of pixels displaying the first color and the number of pixels displaying the second color. In this case, the signal line drive circuit 35 drives the pixels displaying the first color and the pixels displaying the second color, and the signal line drive circuit 36 ​​drives the pixels displaying the third color, thereby making the number of pixels driven by the signal line drive circuit 35 equal to the number of pixels driven by the signal line drive circuit 36. This makes the layout area of ​​the signal line drive circuit 35 equal to the layout area of ​​the signal line drive circuit 36.

[0089] Alternatively, the signal line drive circuit 35 and the signal line drive circuit 36 ​​may read current from, for example, another output line. In that case, the circuit that reads current from another output line can be arranged separately above and below, thus reducing the layout area of ​​the circuit section 64.

[0090] Alternatively, the signal line drive circuit 35 and the signal line drive circuit 36 ​​may read signals from, for example, another sensor line. In that case, the circuits that read signals from the sensor line can be arranged separately, one above the other, thus reducing the layout area of ​​the circuit section 64.

[0091] Alternatively, for example, the signal line drive circuit 35 may be connected to the wiring 25 and supply a signal to the wiring 25, while the signal line drive circuit 36 ​​may be connected to the output line and read current from the output line. In this case, the signal line drive circuit 35 will drive pixels of all colors, and the signal line drive circuit 36 ​​will read current from pixels of all colors.

[0092] Alternatively, for example, the signal line drive circuit 35 may be connected to the wiring 25 and supply a signal to the wiring 25, while the signal line drive circuit 36 ​​may be connected to the sensor line and read a signal from the sensor line. In this case, the signal line drive circuit 35 will drive pixels of all colors.

[0093] Alternatively, for example, the signal line drive circuit 35 may be connected to the wiring 25 and supply a signal to the wiring 25, the signal line drive circuit 36 ​​may be connected to the output line and read current from the output line, and the signal line drive circuit 36 ​​may also be connected to the sensor line and read a signal from the sensor line. In this case, the signal line drive circuit 35 will drive pixels of all colors, and the signal line drive circuit 36 ​​will read current from pixels of all colors.

[0094] Figure 3 shows an example in which the pixel 17 shown in Figure 1A is connected to multiple scan lines. In Figure 3, an example is shown in which the pixel 17 is connected to wiring 23_1 and wiring 23_2. Here, the pixel 17 may be connected to three or more scan lines. If the pixel 17 has multiple transistors that function as switches, the pixel 17 can be configured to be connected to multiple scan lines as shown in Figure 3. Note that in Figure 3, similar to the example shown in Figure 1A, the scan line driving circuit 33 and the scan line driving circuit 34 are shown supplying the same selection signal to the same wiring 23 from both the left and right sides, for example. However, similar to the example shown in Figure 2, they may supply the same selection signal to separate wirings 23 from both the left and right sides, for example.

[0095] Figure 4A is a block diagram showing examples of the configurations of scan line drive circuits 33 and 34. Scan line drive circuits 33 and 34 each include, for example, a shift register circuit 43 and a buffer circuit 45. However, one aspect of the present invention is not limited to these. Scan line drive circuits 33 and 34 may also include circuits not shown in Figure 4A, such as a level shifter circuit and an output switching circuit (DEMUX: Demultiplexer).

[0096] The shift register circuit 43 has the function of outputting a signal to select one row at a time. A clock signal line CLKLa is connected to the shift register circuit 43. Multiple clock signal lines CLKLa can be connected to the shift register circuit 43. Figure 4A shows an example in which m clock signal lines CLKLa (clock signal line CLKLa_1 to clock signal line CLKLa_m) (where m is an integer of 2 or more) are connected to the shift register circuit 43.

[0097] A clock signal is supplied to the clock signal line CLKLa. The shift register circuit 43 can output signals sequentially, one row at a time, based on the clock signal supplied to the clock signal line CLKLa.

[0098] The buffer circuit 45 has the function of increasing the current of the signal output by the shift register circuit 43, for example. The output terminal of the buffer circuit 45 is connected to the pixel 17 via the wiring 23. Therefore, the buffer circuit 45 can output a signal to the pixel 17 via the wiring 23. The signal that the buffer circuit 45 outputs to the wiring 23 can be called a selection signal. The signal output by the shift register circuit 43 can also be called a selection signal.

[0099] Figure 4B is a block diagram showing an example configuration of signal line drive circuits 35 and 36. Signal line drive circuits 35 and 36 each include, for example, a shift register circuit 53, a latch circuit 54, and a buffer circuit 55. However, one aspect of the present invention is not limited to these. Signal line drive circuits 35 and 36 may further include other circuits. For example, signal line drive circuits 35 and 36 may include an output switching circuit (DEMUX).

[0100] The shift register circuit 53 has the function of outputting a signal to select one column at a time. A clock signal line CLKLb is connected to the shift register circuit 53. Multiple clock signal lines CLKLb can be connected to the shift register circuit 53. Figure 4B shows an example in which n clock signal lines CLKLb (clock signal line CLKLb_1 to clock signal line CLKLb_n) (where n is an integer of 2 or more) are connected to the shift register circuit 53.

[0101] A clock signal is supplied to the clock signal line CLKLb. The shift register circuit 53 can output signals one column at a time sequentially based on the clock signal supplied to the clock signal line CLKLb.

[0102] The latch circuit 54 has a function, for example, to hold image data. The latch circuit 54 also has a function to output the held image data as an image signal. The operation of the latch circuit 54 is controlled by the shift register circuit 53. Specifically, the latch circuit 54 can hold and output image data based on the signal output by the shift register circuit 53.

[0103] The buffer circuit 55 has the function of increasing the current of the signal output by the latch circuit 54, for example. The output terminal of the buffer circuit 55 is connected to the pixel 17 via the wiring 25. Therefore, the buffer circuit 55 can output a signal, specifically an image signal, to the pixel 17 via the wiring 25.

[0104] <Example of Display Device Configuration 2> Below, a planar configuration example and a cross-sectional configuration example of a display device according to one embodiment of the present invention will be described. Specifically, an example of the configuration of the circuit section 64 and the display section 62 shown in Figure 1B, etc., will be described.

[0105] Figures 5A and 5B are plan views showing examples of the configuration of the display device 70A. Figure 5A shows an example of the configuration of layer 11 shown in Figure 1B. Figure 5B shows an example of the configuration of layer 21 shown in Figure 1B. Note that some components of the display device 70A, such as the insulating layer, are omitted in Figures 5A and 5B. Some components are also omitted in the plan views shown hereafter.

[0106] Figure 6 is a cross-sectional view showing configuration examples between dashed lines A1-A2 and A2-A3 as shown in Figures 5A and 5B. Figure 7A is a cross-sectional view showing configuration examples between dashed lines B1-B2 as shown in Figures 5A and 5B. Figure 7B is a cross-sectional view showing configuration examples between dashed lines B3-B4 as shown in Figures 5A and 5B. Here, the sections between dashed lines A1-A2 and B1-B2 correspond to the circuit section 64. The sections between dashed lines A2-A3 and B3-B4 correspond to the display section 62.

[0107] The configuration of the display device 70 described above can also be applied to the display device 70A. Furthermore, the configuration of the display device 70 described above can also be applied to the display devices described later.

[0108] The display device 70A includes a substrate 51 and transistors 10a, 10b, 20a, and 20b on the substrate 51. The substrate 51 has an insulating surface, and the above-mentioned transistors can be provided on this insulating surface. Alternatively, an insulating layer can be provided on the substrate 51, and the above-mentioned transistors can be provided on this insulating layer.

[0109] Transistor 10a corresponds to transistor 10A shown in Figure 1B. Transistor 10b corresponds to transistor 10B shown in Figure 1B. Transistor 20a corresponds to transistor 20A shown in Figure 1B. Transistor 20b corresponds to transistor 20B shown in Figure 1B. In Figures 5 to 7B, one transistor each of transistors corresponding to transistor 10A, transistor 10B, transistor 20A, and transistor 20B is shown, but the display device 70A can be provided with multiple of each of these transistors. In the display devices described below, multiple transistors each of transistors corresponding to transistor 10A, transistor 10B, transistor 20A, and transistor 20B can also be provided.

[0110] In the following description, transistors provided on layer 11 shown in Figure 1B, such as transistor 10a and transistor 10b, may be simply referred to as transistor 10. Similarly, transistors provided on layer 21 shown in Figure 1B, such as transistor 20a and transistor 20b, may be simply referred to as transistor 20. Transistors 10 and 20 can be, for example, n-channel transistors.

[0111] Figure 5A shows an example configuration of transistors 10a and 10b in a top view. Figure 5B shows an example configuration of transistors 20a and 20b in a top view.

[0112] An insulating layer 191 is provided on the transistor 10. An insulating layer 231 is provided on the insulating layer 191. An insulating layer 232 is provided on the insulating layer 231. A transistor 20 is provided on the insulating layer 232. An insulating layer 291 is provided on the transistor 20.

[0113] Transistor 10a has a conductive layer 103a on the substrate 51, an insulating layer 105 on the conductive layer 103a and on the substrate 51, a semiconductor layer 108a on the insulating layer 105, an insulating layer 106 on the semiconductor layer 108a and on the insulating layer 105, and a conductive layer 104a on the insulating layer 106. Transistor 10b has a conductive layer 103b on the substrate 51, an insulating layer 105 on the conductive layer 103b and on the substrate 51, a semiconductor layer 108b on the insulating layer 105, an insulating layer 106 on the semiconductor layer 108b and on the insulating layer 105, and a conductive layer 104b on the insulating layer 106. Transistor 20a has a conductive layer 203a on an insulating layer 232, an insulating layer 205 on the conductive layer 203a and on the insulating layer 232, a semiconductor layer 208a on the insulating layer 205, an insulating layer 206 on the semiconductor layer 208a and on the insulating layer 205, and a conductive layer 204a on the insulating layer 206. Transistor 20b has a conductive layer 203b on an insulating layer 232, an insulating layer 205 on the conductive layer 203b and on the insulating layer 232, a semiconductor layer 208b on the insulating layer 205, an insulating layer 206 on the semiconductor layer 208b and on the insulating layer 205, and a conductive layer 204b on the insulating layer 206.

[0114] In the following, conductive layer 103a, conductive layer 103b, etc., may be simply referred to as conductive layer 103. The same applies to other components whose symbols are denoted by letters.

[0115] The conductive layer 104 has a region that overlaps with the semiconductor layer 108 via the insulating layer 106. The conductive layer 204 has a region that overlaps with the semiconductor layer 208 via the insulating layer 206. In transistor 10, the conductive layer 104 functions as a first gate electrode, and the insulating layer 106 functions as a first gate insulating layer. In transistor 20, the conductive layer 204 functions as a first gate electrode, and the insulating layer 206 functions as a first gate insulating layer.

[0116] The conductive layer 103 has a region that overlaps with the conductive layer 104 via the insulating layer 105, the semiconductor layer 108, and the insulating layer 106. The conductive layer 203 has a region that overlaps with the conductive layer 204 via the insulating layer 205, the semiconductor layer 208, and the insulating layer 206. In transistor 10, the conductive layer 103 functions as a second gate electrode, and the insulating layer 105 functions as a second gate insulating layer. In transistor 20, the conductive layer 203 functions as a second gate electrode, and the insulating layer 205 functions as a second gate insulating layer.

[0117] It is preferable that the conductive layer 103 has a region that protrudes from the edge of the conductive layer 104. This enhances the effect (also called the electric field shielding effect) of the conductive layer 103 shielding from electric fields generated outside the transistor 10 and making it difficult for the externally generated electric field to act on the channel formation region. Similarly, by having a region that protrudes from the edge of the conductive layer 204, the electric field shielding effect on the transistor 20 can be enhanced.

[0118] Semiconductor layer 108a has regions 109A and 109B that do not overlap with conductive layer 104a. Semiconductor layer 108b has regions 109C and 109D that do not overlap with conductive layer 104b. Semiconductor layer 208a has regions 209A and 209B that do not overlap with conductive layer 204a. Semiconductor layer 208b has regions 209C and 209D that do not overlap with conductive layer 204b.

[0119] Regions 109 and 209 each contain impurities. By supplying impurities to semiconductor layer 108, the electrical resistance of region 109 can be lowered. Similarly, by supplying impurities to semiconductor layer 208, the electrical resistance of region 209 can be lowered. The concentration of impurities in region 109 is higher than the concentration of impurities in the channel formation region of semiconductor layer 108. Similarly, the concentration of impurities in region 209 is higher than the concentration of impurities in the channel formation region of semiconductor layer 208.

[0120] In transistor 10a, region 109A functions as either the source region or the drain region, and region 109B functions as the other source region or drain region. In transistor 10b, region 109C functions as either the source region or the drain region, and region 109D functions as the other source region or drain region. In transistor 20a, region 209A functions as either the source region or the drain region, and region 209B functions as the other source region or drain region. In transistor 20b, region 209C functions as either the source region or the drain region, and region 209D functions as the other source region or drain region.

[0121] In semiconductor layer 108, the region located between the source region and the drain region and overlapping with the conductive layer 104 via the insulating layer 106 functions as the channel formation region of transistor 10. In semiconductor layer 208, the region located between the source region and the drain region and overlapping with the conductive layer 204 via the insulating layer 206 functions as the channel formation region of transistor 20. In transistor 10, a region that overlaps with the conductive layer 103 but does not overlap with the conductive layer 104 can also function as the channel formation region. Similarly, in transistor 20, a region that overlaps with the conductive layer 203 but does not overlap with the conductive layer 204 can also function as the channel formation region.

[0122] Transistors 10 and 20 have gate electrodes (a first gate electrode and a second gate electrode) on both sides of a channel formation region. Therefore, transistors 10 and 10B can be described as dual-gate transistors. In some cases, one of the first gate electrode and the second gate electrode is referred to as the front gate electrode (or simply as the gate electrode), and the other as the back gate electrode.

[0123] By providing a back gate electrode on transistor 10, the potential on the back gate electrode side (also called the back channel side) of semiconductor layer 108 is fixed, which increases the saturation in the Id-Vd characteristics. Furthermore, by fixing the potential on the back channel side of semiconductor layer 108, the threshold voltage shift can be suppressed. Therefore, a transistor with a small drain current (hereinafter also referred to as cutoff current) when the gate voltage (Vg) is 0V can be made, resulting in a display device with low power consumption. Similarly, by providing a back gate electrode on transistor 20, the saturation in the Id-Vd characteristics of transistor 20 can be increased, and a display device with low power consumption can also be made.

[0124] In this specification and other documents, the term "high saturation" may be used to describe a transistor whose Id-Vd characteristics exhibit a small change in current in the saturation region.

[0125] In this embodiment, an example is shown in which all transistors 10 and 20 have back gate electrodes, but the present invention is not limited thereto. For example, at least some of the transistors 10 may not have back gate electrodes. Similarly, at least some of the transistors 20 may not have back gate electrodes. Furthermore, transistors other than transistors 10 and 20 may not have back gate electrodes.

[0126] In the following, matters common to the first gate insulating layer and the second gate insulating layer may be described simply as "gate insulating layer." Similarly, matters common to the first gate electrode and the second gate electrode may be described simply as "gate electrode."

[0127] An insulating layer 191 is provided on the conductive layer 104 and on the insulating layer 106. In the example shown in Figures 6 to 7B, an insulating layer 191 is provided on the conductive layer 104a, on the conductive layer 104b, and on the insulating layer 106. Similarly, an insulating layer 291 is provided on the conductive layer 204 and on the insulating layer 206. In the example shown in Figures 6 to 7B, an insulating layer 291 is provided on the conductive layer 204a, on the conductive layer 204b, and on the insulating layer 206.

[0128] Insulating layer 191 and insulating layer 106 have openings 147 that reach region 109. Similarly, insulating layer 291 and insulating layer 206 have openings 247 that reach region 209. In the example shown in Figure 6, insulating layer 191 and insulating layer 106 have openings 147a that reach region 109A, openings 147b that reach region 109B, openings 147c that reach region 109C, and openings 147d that reach region 109D. In addition, insulating layer 291 and insulating layer 206 have openings 247a that reach region 209A, openings 247b that reach region 209B, openings 247c that reach region 209C, and openings 247d that reach region 209D.

[0129] A conductive layer 112 is provided to cover opening 147, and a conductive layer 212 is provided to cover opening 247. In the example shown in Figure 6, a conductive layer 112a is provided to cover opening 147a, a conductive layer 112b is provided to cover openings 147b and 147c, and a conductive layer 112c is provided to cover opening 147d. Furthermore, a conductive layer 212a is provided to cover opening 247a, a conductive layer 212b is provided to cover opening 247b, a conductive layer 212c is provided to cover opening 247c, and a conductive layer 212d is provided to cover opening 247d.

[0130] In the example shown in Figure 6, conductive layer 112a is in contact with region 109A at opening 147a. Conductive layer 112b is in contact with region 109B at opening 147b and with region 109C at opening 147c. Regions 109B and 109C are connected via conductive layer 112b. Conductive layer 112c is in contact with region 109D at opening 147d. Conductive layer 212a is in contact with region 209A at opening 247a. Conductive layer 212b is in contact with region 209B at opening 247b. Conductive layer 212c is in contact with region 209C at opening 247c. Conductive layer 212d is in contact with region 209D at opening 247d.

[0131] Conductive layer 112a functions as one of the source and drain electrodes of transistor 10a. Conductive layer 112b functions as the other of the source and drain electrodes of transistor 10a, and as one of the source and drain electrodes of transistor 10b. Conductive layer 112c functions as the other of the source and drain electrodes of transistor 10b. Conductive layer 212a functions as one of the source and drain electrodes of transistor 20a. Conductive layer 212b functions as the other of the source and drain electrodes of transistor 20a. Conductive layer 212c functions as one of the source and drain electrodes of transistor 20b. Conductive layer 212d functions as the other of the source and drain electrodes of transistor 20b.

[0132] Figure 5A shows conductive layers 112a, 112b, and 112c. Figure 5B shows conductive layers 212a, 212b, 212c, and 212d, as well as conductive layer 112c. Note that the hatching pattern of conductive layer 112c is omitted in Figure 5B.

[0133] In the examples shown in Figures 5A and 6, as described above, the region 109B of transistor 10a provided in the circuit section 64 is connected to the region 109C of transistor 10b provided in the display section 62. Therefore, the source or drain of transistor 10a is connected to the pixel 17 shown in Figures 1A to 3. Transistor 10a can be provided in the buffer circuit 55 shown in Figure 4B. Also, at least a part of the conductive layer 112b functions as wiring 25. Transistor 20a can be provided in circuits other than the buffer circuit 55. Transistor 20a can be provided, for example, in the shift register circuit 53 or the latch circuit 54.

[0134] Figures 5A, 5B, 7A, and 7B show the channel widths W1 of transistor 10a, W2 of transistor 10b, W3 of transistor 20a, and W4 of transistor 20b. As shown in Figures 5A, 5B, 7A, and 7B, channel width W1 is greater than channel widths W2, W3, and W4.

[0135] A buffer circuit has the function of increasing the current of the input signal. Therefore, if the on-current of the transistor in the buffer circuit is large, it becomes easier to increase the current of the input signal, and the reliability of the display device can be improved. As mentioned above, transistor 10a is provided in the buffer circuit. Therefore, it is preferable that the channel width W1 of transistor 10a is large. On the other hand, if the channel width of transistors provided in circuits other than the buffer circuit, such as the shift register circuit 53 and the latch circuit 54, is small, it is preferable that the occupied area of ​​the circuit section 64 can be reduced. Therefore, it is preferable that the channel width W1 is larger than the channel width W3 of transistor 20a. In other words, it is preferable that the channel width W3 is smaller than the channel width W1. Also, if the channel width of the transistors provided in the display section 62 is small, the occupied area per pixel 17 can be reduced, and a high-definition display device can be realized. Therefore, it is more preferable that the channel width W1 is larger than the channel width W2 of transistor 10b and the channel width W4 of transistor 20b. In other words, it is more preferable that channel widths W2 and W4 are smaller than channel width W1.

[0136] Therefore, in the display device 70A, the buffer circuit is provided in layer 11 as shown in Figure 1B, and the circuits other than the buffer circuit are provided in layer 21. The channel width of the transistors provided in layer 11 is made larger than the channel width of the transistors provided in layer 21. That is, the channel width of transistor 10A is made larger than the channel width of transistor 20A. As mentioned above, transistor 20A is provided so as to have a region that overlaps with transistor 10A. As a result, the occupied area of ​​the circuit unit 64 can be reduced while securing the occupied area of ​​the buffer circuit, compared to, for example, the case in which all the transistors of the circuit unit 64 are provided in one layer. Thus, the display device 70A can be a highly reliable and narrow-bezel display device. Alternatively, the buffer circuit may be provided in layer 21 and the circuits other than the buffer circuit may be provided in layer 11. In this case, the channel width of transistor 20A is made larger than the channel width of transistor 10A.

[0137] In the example shown in Figures 5A to 7B, both the transistor provided in the drive circuit of the circuit unit 64 and connected to the pixel 17, and the transistor provided in the pixel 17 and connected to the drive circuit, are provided in layer 11 as shown in Figure 1B. This allows for a shorter wiring distance between these two transistors compared to the case where one of the two transistors is provided in layer 11 and the other in layer 21. Therefore, the wiring resistance between these two transistors can be reduced. Consequently, a high-speed display device can be realized. Note that these two transistors may also be provided in layer 21.

[0138] An insulating layer 231 is provided on the conductive layer 112 and on the insulating layer 191. As mentioned above, an insulating layer 232 is provided on the insulating layer 231. The insulating layers 231 and 232 are provided between the insulating layer 191 on the transistor 10 and the transistor 20.

[0139] As shown in Figures 5B and 7B, the insulating layers 206, 205, 232, and 231 have openings 248a that reach the conductive layer 112c. The conductive layer 204b is provided so as to cover the opening 248a. The conductive layer 204b is in contact with the conductive layer 112c at the opening 248a. As a result, the gate electrode of transistor 20b can be connected to the source electrode and the other drain electrode of transistor 10b. Although not shown in Figures 5A to 7B, the conductive layer 212c or conductive layer 212d can be connected to, for example, the display element 13 shown in Figure 1B, specifically to one electrode of the display element 13.

[0140] The connection configurations of transistors 10b and 20b shown in Figures 5A to 7B are merely examples, and the present invention is not limited thereto. For example, transistor 10b does not have to be connected to transistor 20b. Also, for example, the conductive layer 112c may be connected to a transistor 10B (transistor 10 provided in the display unit 62) not shown in Figures 5A to 7B.

[0141] Figure 8 shows an example in the display device 70A shown in Figure 6, where the conductive layer 112b is connected to the conductive layer 104b instead of region 109C. In the example shown in Figure 8, the insulating layer 191 has an opening 148 that reaches the conductive layer 104b. The conductive layer 112b is provided so as to cover the opening 148. The conductive layer 112b is in contact with the conductive layer 104b at the opening 148. Thus, in the example shown in Figure 8, region 109B and the conductive layer 104b are connected via the conductive layer 112b. Note that in Figure 8, one of the source electrode and drain electrode of the transistor 10b is not shown.

[0142] The transistor 10a shown in Figure 8 can be provided in the buffer circuit 45 shown in Figure 4A. Furthermore, at least a portion of the conductive layer 112b functions as wiring 23. Note that the transistor 20a can be provided in circuits other than the buffer circuit 45. For example, the transistor 20a can be provided in the shift register circuit 43.

[0143] The transistors 10 and 20 shown in Figures 5A to 8 are planar transistors, each with semiconductor layers arranged in a planar configuration. They are also so-called top-gate transistors, having a gate electrode above the semiconductor layer. Furthermore, by supplying the aforementioned impurities to the semiconductor layer using the gate electrode as a mask, the source and drain regions can be formed in a self-aligned manner. Therefore, transistors 10 and 20 can each be described as TGSA (Top Gate Self-Aligned) type transistors.

[0144] TGSA-type transistors allow for a larger physical distance between the source and drain electrodes and the gate electrode, thereby reducing parasitic capacitance between them.

[0145] It is preferable to use a metal oxide (also called an oxide semiconductor) that exhibits semiconductor properties for semiconductor layer 108 and semiconductor layer 208. The band gap of the metal oxide in the semiconductor layer is preferably 2.0 eV or more, and more preferably 2.5 eV or more. Transistors using oxide semiconductors (hereinafter also referred to as OS transistors) have extremely high field-effect mobility compared to transistors using amorphous silicon. Furthermore, OS transistors have a remarkably low off-current and can retain the charge accumulated in a capacitive element connected in series with the transistor for a long period of time. In addition, the power consumption of the display device can be reduced by applying an OS transistor. When a metal oxide is used for the semiconductor layer, the semiconductor layer can be called a metal oxide layer.

[0146] When metal oxides are used as semiconductor layers 108 and 208, it is preferable that semiconductor layers 108 and 208 each contain indium and oxygen, respectively, and it is particularly preferable to use indium oxide. Indium oxide will be described in detail in Embodiment 2.

[0147] The semiconductor layers 108 and 208 may use semiconductors made of single elements, such as silicon or germanium. Examples of silicon include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low-temperature polysilicon (LTPS). Transistors using amorphous silicon in the channel formation region can be formed on large glass substrates and can be manufactured at low cost. Transistors using polycrystalline silicon in the channel formation region have high field-effect mobility and can operate at high speeds. Transistors using microcrystalline silicon in the channel formation region have higher field-effect mobility than transistors using amorphous silicon and can operate at high speeds. Note that transistors using silicon in the channel formation region are sometimes referred to as Si transistors, and transistors using LTPS in the channel formation region are sometimes referred to as LTPS transistors.

[0148] Compound semiconductors may be used for semiconductor layer 108 and semiconductor layer 208. Examples of compound semiconductors include gallium arsenide and silicon germanium. Other examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors (OS). These semiconductor materials may contain impurities as dopants.

[0149] The crystallinity of the semiconductor material is not particularly limited, and any amorphous semiconductor, single-crystal semiconductor, or semiconductor having crystalline properties other than single crystal (microcrystalline semiconductor, polycrystalline semiconductor, or semiconductor having a crystalline region in part) can be used. Using a single-crystal semiconductor or a semiconductor having crystalline properties is preferable because it can suppress the degradation of transistor characteristics.

[0150] It is preferable to use the same material for semiconductor layer 108 and semiconductor layer 208. For example, if indium oxide is used for semiconductor layer 108, it is preferable to also use indium oxide for semiconductor layer 208. This allows the apparatus used for forming semiconductor layer 108 and the apparatus used for forming semiconductor layer 208 to be the same. Therefore, the display device can be manufactured at a lower cost than when the apparatus used for forming semiconductor layer 108 and the apparatus used for forming semiconductor layer 208 are different.

[0151] When a metal oxide is used for the semiconductor layer 108, the elements contained in the impurities in region 109 may include one or more of the following: hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, silicon, and noble gases. Representative examples of noble gases include helium, neon, argon, krypton, and xenon. Of the above elements, it is particularly preferable to use one or more of the following: hydrogen, boron, phosphorus, aluminum, magnesium, and silicon. The elements contained in the impurities in region 209 may also include the above elements.

[0152] The insulating layer 191 and the insulating layer 291 can each be a single-layer structure or a laminated structure of two or more layers. The insulating layer 191 and the insulating layer 291 can each be an inorganic insulating layer or an organic insulating layer, or both. Examples of materials that can be used for the inorganic insulating layer (inorganic insulating materials) include oxides, nitrides, oxidized nitrides, and nitride oxides. Examples of oxides include silicon oxide, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, cerium oxide, zinc gallium oxide, and hafnium aluminate. Examples of nitrides include silicon nitride and aluminum nitride. Examples of oxidized nitrides include silicon oxidized nitride, aluminum oxidized nitride, gallium oxidized nitride, yttrium oxidized nitride, and hafnium oxidized nitride. Examples of nitride oxides include silicon nitride and aluminum nitride. Examples of materials that can be used for the organic insulating layer (organic insulating material) include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimidoamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins. It is preferable that the insulating layer 191 and the insulating layer 291 each have one or more inorganic insulating layers.

[0153] In this specification, "oxide-nitride" refers to a material whose composition contains more oxygen than nitrogen. "Nitride oxide" refers to a material whose composition contains more nitrogen than oxygen.

[0154] A barrier insulating layer can also be used on one or both of the insulating layer 191 and the insulating layer 291. By providing a barrier insulating layer, the diffusion of impurities (e.g., water and hydrogen) into the transistor from the outside can be effectively suppressed. Therefore, the reliability of the display device can be improved.

[0155] In this specification, the term "barrier insulating layer" refers to a film having barrier properties. Barrier properties refer to one or both of the following functions: a function that makes it difficult for the target substance to diffuse, thereby suppressing the permeation of the substance through the film (also known as low permeability); and a function that captures or fixes the substance (also known as gettering).

[0156] The barrier insulating layer can be made from, for example, one or more oxides having aluminum and / or hafnium, an oxide having magnesium, an oxide having gallium, a nitride having silicon, an oxidized nitride having silicon, and an oxide nitride having silicon. Typically, the barrier insulating layer can be made from one or more of aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, zinc gallium oxide, silicon nitride, silicon oxidized nitride, and silicon nitride oxide.

[0157] The insulating layer 231 preferably functions as a planarizing layer, and an organic insulating layer is preferred. By providing a planarizing layer on the transistor 10, irregularities caused by the transistor 10 can be reduced. This makes the surface of the layer formed on the insulating layer 231 flatter, and prevents defects such as step breaks or porosity from occurring in the layer. For materials that can be used for the organic insulating layer, please refer to the above description.

[0158] The insulating layer 232 preferably functions as an etching protection layer, and an inorganic insulating layer is preferred. By providing the insulating layer 232, it is possible to suppress the formation of recesses in the insulating layer 231 when the transistor 20 is formed on the insulating layer 232. This makes the surface of the layer formed on the insulating layer 231 flatter, and it is possible to suppress defects such as step breaks or porosity in the layer. For materials that can be used for the inorganic insulating layer, please refer to the above description.

[0159] The insulating layer 232 preferably functions as a barrier insulating layer. By providing a barrier insulating layer between the planarization layer and the transistor 20, it is possible to suppress the diffusion of impurities contained in the layer below the insulating layer 232 (for example, the insulating layer 231) into the transistor 10.

[0160] <Example of Display Device Configuration 3> Below, we will describe a display device that differs in some configurations from the display device 70A described above. Note that we will mainly describe the configurations that differ from the display device 70A, and will omit explanations of similar configurations as appropriate.

[0161] [Configuration Example 3-1] Figures 9, 10A, and 10B are cross-sectional views showing configuration examples of the display device 70B. Figure 9 is a cross-sectional view showing configuration examples of the circuit section 64 and the display section 62 shown in Figure 1B, etc., and includes a cross-sectional configuration example in the channel length direction of the transistor. Figure 10A is a cross-sectional view showing configuration examples of the circuit section 64, and includes a cross-sectional configuration example in the channel width direction of the transistor. Figure 10B is a cross-sectional view showing configuration examples of the display section 62, and includes a cross-sectional configuration example in the channel width direction of the transistor.

[0162] The display device 70B includes a substrate 51 and transistors 10c, 10d, 20c, 20d, capacitive element 27a, and 27b on the substrate 51. Transistor 10c corresponds to transistor 10A shown in Figure 1B. Transistor 10d corresponds to transistor 10B shown in Figure 1B. Transistor 20c corresponds to transistor 20A shown in Figure 1B. Transistor 20d corresponds to transistor 20B shown in Figure 1B.

[0163] Transistor 10c has a conductive layer 103c on the substrate 51, an insulating layer 105 on the conductive layer 103c and on the substrate 51, a semiconductor layer 108c on the insulating layer 105, an insulating layer 106 on the semiconductor layer 108c and on the insulating layer 105, and a conductive layer 104c on the insulating layer 106. Transistor 10d has a conductive layer 103d on the substrate 51, an insulating layer 105 on the conductive layer 103d and on the substrate 51, a semiconductor layer 108d on the insulating layer 105, an insulating layer 106 on the semiconductor layer 108d and on the insulating layer 105, and a conductive layer 104d on the insulating layer 106. Transistor 20c has a conductive layer 203c on the insulating layer 232, an insulating layer 205 on the conductive layer 203c and on the insulating layer 232, a semiconductor layer 208c on the insulating layer 205, an insulating layer 206 on the semiconductor layer 208c and on the insulating layer 205, and a conductive layer 204c on the insulating layer 206. Transistor 20d has a conductive layer 203d on the insulating layer 232, an insulating layer 205 on the conductive layer 203d and on the insulating layer 232, a semiconductor layer 208d on the insulating layer 205, an insulating layer 206 on the semiconductor layer 208d and on the insulating layer 205, and a conductive layer 204d on the insulating layer 206.

[0164] Capacitive element 27a has a conductive layer 214a on the insulating layer 206, an insulating layer 291 on the conductive layer 214a, and a conductive layer 212f on the insulating layer 291. Capacitive element 27b has a conductive layer 214b on the insulating layer 206, an insulating layer 291 on the conductive layer 214b, and a conductive layer 212h on the insulating layer 291.

[0165] The semiconductor layer 108c has regions 109E and 109F that do not overlap with the conductive layer 104c. The semiconductor layer 108d has regions 109G and 109H that do not overlap with the conductive layer 104d. The semiconductor layer 208c has regions 209E and 209F that do not overlap with the conductive layer 204c. The semiconductor layer 208d has regions 209G and 209H that do not overlap with the conductive layer 204d.

[0166] In transistor 10c, region 109E functions as either the source region or the drain region, and region 109F functions as the other source region or drain region. In transistor 10d, region 109G functions as either the source region or the drain region, and region 109H functions as the other source region or drain region. In transistor 20c, region 209E functions as either the source region or the drain region, and region 209F functions as the other source region or drain region. In transistor 20d, region 209G functions as either the source region or the drain region, and region 209H functions as the other source region or drain region.

[0167] An insulating layer 191 is provided on the conductive layer 104c, the conductive layer 104d, and the insulating layer 106. An insulating layer 291 is provided on the conductive layer 204c, the conductive layer 204d, and the insulating layer 206.

[0168] The insulating layer 191 and the insulating layer 106 have openings 147e reaching region 109E, 147f reaching region 109F, 147g reaching region 109G, and 147h reaching region 109H. The insulating layer 291 and the insulating layer 206 have openings 247e reaching region 209E, 247f reaching region 209F, 247g reaching region 209G, and 247h reaching region 209H.

[0169] A conductive layer 112d is provided so as to cover the opening 147e. A conductive layer 112e is provided so as to cover the opening 147f. A conductive layer 112f is provided so as to cover the opening 147g. A conductive layer 112g is provided so as to cover the opening 147h. A conductive layer 212e is provided so as to cover the opening 247e. A conductive layer 212f is provided so as to cover the opening 247f. A conductive layer 212g is provided so as to cover the opening 247g. A conductive layer 212h is provided so as to cover the opening 247h.

[0170] Conductive layer 112d is in contact with region 109E at opening 147e. Conductive layer 112e is in contact with region 109F at opening 147f. Conductive layer 112f is in contact with region 109G at opening 147g. Conductive layer 112g is in contact with region 109H at opening 147h. Conductive layer 212e is in contact with region 209E at opening 247e. Conductive layer 212f is in contact with region 209F at opening 247f. Conductive layer 212g is in contact with region 209G at opening 247g. Conductive layer 212h is in contact with region 209H at opening 247h.

[0171] Conductive layer 112d functions as one of the source and drain electrodes of transistor 10c. Conductive layer 112e functions as the other of the source and drain electrodes of transistor 10c. Conductive layer 112f functions as one of the source and drain electrodes of transistor 10d. Conductive layer 112g functions as the other of the source and drain electrodes of transistor 10d. Conductive layer 212e functions as one of the source and drain electrodes of transistor 20c. Conductive layer 212f functions as the other of the source and drain electrodes of transistor 20c. Conductive layer 212g functions as one of the source and drain electrodes of transistor 20d. Conductive layer 212h functions as the other of the source and drain electrodes of transistor 20d.

[0172] The conductive layer 214a functions as one electrode of the capacitive element 27a. The conductive layer 212f functions as the other electrode of the capacitive element 27a. The conductive layer 214b functions as one electrode of the capacitive element 27b. The conductive layer 212h functions as the other electrode of the capacitive element 27b. The insulating layer 291 functions as a dielectric for the capacitive elements 27a and 27b.

[0173] From the above, the conductive layer 212f has the function of both the other source electrode and drain electrode of transistor 20c and the other electrode of capacitive element 27a. Therefore, the source or drain of transistor 20c is connected to the other electrode of capacitive element 27a. Also, the conductive layer 212h has the function of both the other source electrode and drain electrode of transistor 20d and the other electrode of capacitive element 27b. Therefore, the source or drain of transistor 20d is connected to the other electrode of capacitive element 27b. Here, Figure 9 shows only one capacitive element provided in the circuit section 64, but multiple capacitive elements can be provided in the circuit section 64. Similarly, multiple capacitive elements can be provided in the display section 62. The fact that multiple capacitive elements can be provided in the circuit section 64 and the display section 62 is also true for the display devices described later. Note that the configurations of capacitive elements 27a and 27b shown in Figure 9 are merely examples and are not particularly limited. For example, the insulating layer 205 or the insulating layer 206 may be configured to function as a dielectric for the capacitive elements 27a and 27b.

[0174] When manufacturing the display device 70 shown in Figure 1B, the transistor 10 included in layer 11 is formed first, and then the transistor 20 included in layer 21 is formed. Therefore, the thermal history (thermal budget) of transistor 10 is greater than that of transistor 20. Consequently, for example, the threshold voltage of transistor 10 may be smaller than the threshold voltage of transistor 20. As a result, transistor 10 may become, for example, a normally-on type transistor (a transistor with a threshold voltage of less than 0V). Therefore, even when the same material is used for semiconductor layer 108 and semiconductor layer 208, the off-current of transistor 10 may be larger than that of transistor 20.

[0175] Therefore, in the display device 70B, a transistor is provided in layer 21 shown in Figure 1B, in which one or both of the source and drain are connected to the electrodes of a capacitive element. This can suppress the leakage of charge held in the capacitive element compared to when the transistor is provided in layer 11. In this case, the charge can be held in the capacitive element for a long time. Thus, a highly reliable display device can be realized.

[0176] Furthermore, by providing the capacitive element in layer 21, the wiring distance between the transistor and the capacitive element can be shortened compared to when the capacitive element is provided in layer 11. Therefore, the wiring resistance between the transistor and the capacitive element can be reduced, enabling the realization of a high-speed operating display device.

[0177] Transistors whose source and drain are not connected to the electrodes of a capacitive element are provided in layer 11 as shown in Figure 1B. This reduces the occupied area of ​​the circuit section 64 compared to, for example, the case where all the transistors of the display device are provided in a single layer. It also reduces the occupied area per pixel 17. As a result, a narrow-bezel, high-definition display device can be realized. Note that some of the transistors connected to the electrodes of a capacitive element may be provided in layer 11. For example, transistors whose source or drain is connected to an electrode of the capacitive element that does not become electrically floating (also called a floating state) during the operation of the display device, and not connected to an electrode that becomes electrically floating, can be provided in layer 11. Also, transistors for which increasing the on-current is more important than decreasing the off-current can be provided in layer 11.

[0178] For example, a transistor in layer 11 may have one or both of its source and drain connected to the electrodes of a capacitive element, while a transistor in layer 21 may have its source and drain not connected to the capacitive element. That is, in the display device 70B, the transistor that would be provided in layer 11 may be provided in layer 21, and the transistor that would be provided in layer 21 may be provided in layer 11. For example, depending on the manufacturing conditions of the display device, the threshold voltage of the transistor provided in layer 21 may be lower than the threshold voltage of the transistor provided in layer 11. In this case, by providing a transistor in layer 11 with one or both of its source and drain connected to the electrodes of a capacitive element, the leakage of charge held in the capacitive element can be suppressed more effectively than when the transistor is provided in layer 21. Therefore, a highly reliable display device can be realized that holds charge in the capacitive element for a long time. In a display device with this configuration, it is preferable to provide the capacitive element in layer 11.

[0179] [Configuration Example 3-2] Figures 11 and 12A are cross-sectional views showing configuration examples of the display device 70C. Figure 11 is a cross-sectional view showing configuration examples of the circuit section 64 shown in Figure 1B, etc., and includes a cross-sectional configuration example in the channel length direction of the transistor. Figure 12A is a cross-sectional view showing configuration examples of the circuit section 64, and includes a cross-sectional configuration example in the channel width direction of the transistor.

[0180] The display device 70C includes a substrate 51, a transistor 60 on the substrate 51, and a transistor 10c. For a description of the configuration of transistor 10c, please refer to the description of the display device 70B. Below, we will mainly describe the configurations that differ from those of the display device 70B, and will omit descriptions of similar configurations as appropriate.

[0181] The transistor 60 has a conductive layer 103e on the substrate 51, an insulating layer 105 on the conductive layer 103e and on the substrate 51, a semiconductor layer 108e on the insulating layer 105, an insulating layer 106 on the semiconductor layer 108e and on the insulating layer 105, a conductive layer 104e on the insulating layer 106, a conductive layer 203e on the insulating layer 232, an insulating layer 205 on the conductive layer 203e and on the insulating layer 232, a semiconductor layer 208e on the insulating layer 205, an insulating layer 206 on the semiconductor layer 208e and on the insulating layer 205, and a conductive layer 204e on the insulating layer 206. The capacitive element 27c has a conductive layer 214c on the insulating layer 206, an insulating layer 291 on the conductive layer 214c, and a conductive layer 212m on the insulating layer 291.

[0182] The semiconductor layer 108e has regions 109K and 109M that do not overlap with the conductive layer 104e. The semiconductor layer 208e has regions 209K and 209M that do not overlap with the conductive layer 204e.

[0183] Insulating layer 191 and insulating layer 106 have an opening 147k that reaches region 109K and an opening 147m that reaches region 109M. Insulating layer 291 and insulating layer 206 have an opening 247k that reaches region 209K and an opening 247m that reaches region 209M. Insulating layer 291, insulating layer 206, insulating layer 205, insulating layer 232, and insulating layer 231 have an opening 248b that reaches conductive layer 112h. Insulating layer 232, insulating layer 231, insulating layer 191, insulating layer 106, and insulating layer 105 have an opening 248c that reaches conductive layer 103e. Insulating layer 206, insulating layer 205, insulating layer 232, insulating layer 231, and insulating layer 191 have an opening 248d that reaches conductive layer 104e.

[0184] A conductive layer 112h is provided so as to cover the opening 147k. A conductive layer 112k is provided so as to cover the opening 147m. A conductive layer 212k is provided so as to cover the openings 247k and 248b. A conductive layer 212m is provided so as to cover the opening 247m. A conductive layer 203e is provided so as to cover the opening 248c. A conductive layer 204e is provided so as to cover the opening 248d.

[0185] Conductive layer 112h is in contact with region 109K at opening 147k. Conductive layer 112k is in contact with region 109M at opening 147m. Conductive layer 212k is in contact with region 209K at opening 247k and is also in contact with conductive layer 112h at opening 248b. Conductive layer 212m is in contact with region 209M at opening 247m. Conductive layer 203e is in contact with conductive layer 103e at opening 248c. Conductive layer 204e is in contact with conductive layer 104e at opening 248d.

[0186] As described above, region 109K and region 209K are connected via conductive layer 112h and conductive layer 212k. Furthermore, conductive layer 103e and conductive layer 203e are connected to each other. In addition, conductive layer 104e and conductive layer 204e are connected to each other.

[0187] Figure 12B is a circuit diagram showing an example configuration of transistor 60. Transistor 60 can be considered as a transistor in which transistors 60a and 60b are connected in series. Here, the gates of transistor 60a and 60b are connected to each other. Similarly, the back gates of transistor 60a and 60b are connected to each other. In addition, one of the source and drain of transistor 60a is connected to one of the source and drain of transistor 60b.

[0188] Transistor 60a can be considered, for example, as a transistor having conductive layers 103e, 104e, insulating layer 105, 106, semiconductor layer 108e, conductive layer 112h, and conductive layer 112k, as shown in Figures 11 and 12A. Therefore, transistor 60a can be considered as a transistor provided on layer 11, as shown in Figure 1B. Transistor 60b can also be considered, for example, as a transistor having conductive layers 203e, 204e, insulating layer 205, 206, semiconductor layer 208e, conductive layer 212k, and conductive layer 212m, as shown in Figures 11 and 12A. Therefore, transistor 60b can be considered as a transistor provided on layer 21, as shown in Figure 1B.

[0189] Conductive layers 104e and 204e function as gate electrodes of transistor 60. Conductive layers 103e and 203e function as back gate electrodes of transistor 60. Insulating layers 106 and 206 function as first gate insulating layers of transistor 60. Insulating layers 105 and 205 function as second gate insulating layers of transistor 60. Region 109M functions as one of the source and drain regions of transistor 60. Region 209M functions as the other of the source and drain regions of transistor 60. Conductive layer 112k functions as one of the source and drain electrodes of transistor 60. Conductive layer 212m functions as the other of the source and drain electrodes of transistor 60. Conductive layers 112h and 212k function as wiring for connecting region 109K and region 209K.

[0190] The conductive layer 214c functions as one electrode of the capacitive element 27c. The conductive layer 212m functions as the other electrode of the capacitive element 27c. The insulating layer 291 functions as the dielectric of the capacitive element 27c.

[0191] As described above, the conductive layer 212m has the function of both the other source electrode and drain electrode of the transistor 60 and the other electrode of the capacitive element 27c. Therefore, the source or drain of the transistor 60 is connected to the other electrode of the capacitive element 27c. Note that the configuration of the capacitive element 27c shown in Figure 11 is merely an example and is not particularly limited. For example, the insulating layer 205 or insulating layer 206 may function as the dielectric of the capacitive element 27c.

[0192] As mentioned above, the transistors provided in layer 11 and layer 21, as shown in Figure 1B, have different thermal histories, for example. Therefore, even if the same material is used for the semiconductor layers, the transistors provided in layer 11 and layer 21 may have different electrical characteristics. For example, one of the transistors provided in layer 11 and layer 21 may be normally-on type transistors. By using transistor 60 as the transistor connected to the capacitive element, even if one of the transistors 60a and 60b shown in Figure 12B is a normally-on type transistor, the leakage of charge held in the capacitive element can be suppressed. As a result, the display device 70C can be made into a highly reliable display device.

[0193] Figures 11 and 12A show an example in which the capacitive element 27c is provided on layer 21 as shown in Figure 1B, but the capacitive element 27c may also be provided on layer 11. Furthermore, when multiple capacitive elements are provided in the circuit section 64, some of the capacitive elements may be provided on layer 11 and the remaining capacitive elements on layer 21.

[0194] [Configuration Example 3-3] Figure 13 is a cross-sectional view showing an example configuration of the display device 70D. Figure 13 is a cross-sectional view showing an example configuration of the scan line drive circuit 33, scan line drive circuit 34, and display unit 62 shown in Figure 1A, and includes an example of a cross-sectional configuration in the channel length direction of the transistor.

[0195] The display device 70D includes a substrate 51 and transistors 10e, 40a, 40b, and 20e on the substrate 51. Transistor 10e is provided in the scan line driving circuit 33. Transistor 20e is provided in the scan line driving circuit 34. Transistors 40a and 40b are provided in the pixels 17 shown in Figure 1A, specifically in different pixels 17.

[0196] Transistor 10e has a conductive layer 103f on the substrate 51, an insulating layer 105 on the conductive layer 103f and on the substrate 51, a semiconductor layer 108f on the insulating layer 105, an insulating layer 106 on the semiconductor layer 108f and on the insulating layer 105, and a conductive layer 104f on the insulating layer 106. Transistors 40a and 40b are transistors with the same configuration as transistor 10e and can be formed in the same process. Transistor 20e has a conductive layer 203f on the insulating layer 232, an insulating layer 205 on the conductive layer 203f and on the insulating layer 232, a semiconductor layer 208f on the insulating layer 205, an insulating layer 206 on the semiconductor layer 208f and on the insulating layer 205, and a conductive layer 204f on the insulating layer 206.

[0197] The semiconductor layer 108f has regions 109N and 109P that do not overlap with the conductive layer 104f. The semiconductor layer 208f has regions 209N and 209P that do not overlap with the conductive layer 204f.

[0198] In transistor 10e, region 109N functions as either the source region or the drain region, and region 109P functions as the other source region or drain region. In transistor 20e, region 209N functions as either the source region or the drain region, and region 209P functions as the other source region or drain region.

[0199] The insulating layer 191 and the insulating layer 106 have an opening 147n that reaches region 109N and an opening 147p that reaches region 109P. The insulating layer 291 and the insulating layer 206 have an opening 247n that reaches region 209N and an opening 247p that reaches region 209P.

[0200] A conductive layer 112m is provided so as to cover the opening 147n. A conductive layer 112n is provided so as to cover the opening 147p. A conductive layer 212n is provided so as to cover the opening 247n. A conductive layer 212p is provided so as to cover the opening 247p.

[0201] The conductive layer 112m is in contact with region 109N at opening 147n. The conductive layer 112n is in contact with region 109P at opening 147p and is in contact with the gate electrode of transistor 40a at an opening in the insulating layer 191. The conductive layer 212n is in contact with region 209N at opening 247n and is in contact with the gate electrode of transistor 40b at an opening in the insulating layer 191. The conductive layer 212p is in contact with region 209P at opening 247p.

[0202] The conductive layer 112m functions as one of the source and drain electrodes of transistor 10e. The conductive layer 112n functions as the other of the source and drain electrodes of transistor 10e. The conductive layer 212p functions as one of the source and drain electrodes of transistor 20e. The conductive layer 212n functions as the other of the source and drain electrodes of transistor 20e.

[0203] At least a portion of the conductive layer 112n and at least a portion of the conductive layer 212n function as wiring 23. The conductive layer 112n and the conductive layer 212n are connected to each other.

[0204] In the display device 70D, the transistors of the scan line drive circuit 33 are located on layer 11 as shown in Figure 1B. The transistors of the scan line drive circuit 34 are located on layer 21. As mentioned above, the transistors located on layer 11 and the transistors located on layer 21 have different thermal histories, for example. Therefore, even if the same material is used for the semiconductor layers, the transistors located on layer 11 and the transistors located on layer 21 may have different electrical characteristics. Consequently, a characteristic defect may occur in either the transistor located on layer 11 or the transistor located on layer 21. Here, as shown in Figure 1A, if the scan line drive circuit 33 and the scan line drive circuit 34 supply the same selection signal to the same wiring 23, for example, the display device can be operated even if one of the scan line drive circuit 33 or the scan line drive circuit 34 is not operating. Thus, by providing the transistors of the scan line drive circuit 33 on layer 11 and the transistors of the scan line drive circuit 34 on layer 21, a highly reliable display device can be realized. Alternatively, the transistors of the scan line driving circuit 33 may be provided on layer 21, and the transistors of the scan line driving circuit 34 may be provided on layer 11.

[0205] As shown in Figure 3, when two or more scan lines are connected to a single pixel 17, the transistors included in the circuits that supply selection signals to different scan lines in either the scan line driving circuit 33 or the scan line driving circuit 34 can be placed on different layers. In the example shown in Figure 3, the scan line driving circuit 33 has a first circuit for supplying a selection signal to wiring 23_1 and a second circuit for supplying a selection signal to wiring 23_2. The scan line driving circuit 34 has a third circuit for supplying a selection signal to wiring 23_1 and a fourth circuit for supplying a selection signal to wiring 23_2. In this case, for example, the transistors included in the first circuit and the transistors included in the fourth circuit can be placed on layer 11, and the transistors included in the second circuit and the transistors included in the third circuit can be placed on layer 21. Even in this case, if a characteristic defect occurs in either the transistor on layer 11 or the transistor on layer 21, the display device 70D can still supply selection signals to both wiring 23_1 and wiring 23_2. Furthermore, since both the scan line drive circuit 33 and the scan line drive circuit 34 can have transistors provided in layer 11 and transistors provided in layer 21, the area occupied by the scan line drive circuit 33 and the scan line drive circuit 34 can be reduced. As a result, a highly reliable and narrow-bezel display device can be realized.

[0206] Figures 1A and 3 show an example in which signal line drive circuits 35 and 36 supply signals to the same wiring 25, as described above. In this case, a highly reliable display device can be realized by providing the transistor of one of the signal line drive circuits 35 and 36 on layer 11 shown in Figure 1B, and the transistor of the other signal line drive circuit 35 and 36 on layer 21.

[0207] [Configuration Example 3-4] Figures 14A and 14B are plan views showing configuration examples of the display device 70E. Figure 14A shows a configuration example of the layer 11 shown in Figure 1B. Figure 14B shows a configuration example of the layer 21 shown in Figure 1B.

[0208] Figure 15 is a cross-sectional view showing an example configuration between the dashed lines C1 and C2 shown in Figures 14A and 14B. Figure 16 is a cross-sectional view showing an example configuration between the dashed lines D1 and D2 shown in Figures 14A and 14B. The sections between the dashed lines C1 and C2, and between the dashed lines D1 and D2, correspond to the circuit section 64. Figure 15 includes an example of a cross-sectional configuration in the channel length direction of the transistor.

[0209] The display device 70E includes a substrate 51 and transistors 10f, 10g, 20f, 20g, conductive layers 151a, 151b, 251a, and 251b on the substrate 51. Figure 14A shows an example of the configuration of transistors 10f and 10g in a top view. Figure 14B shows an example of the configuration of transistors 20f and 20g in a top view.

[0210] Transistor 10f has a conductive layer 103g on the substrate 51, an insulating layer 105 on the conductive layer 103g and on the substrate 51, a semiconductor layer 108g on the insulating layer 105, an insulating layer 106 on the semiconductor layer 108g and on the insulating layer 105, and a conductive layer 104g on the insulating layer 106. Transistor 10g has a conductive layer 103h on the substrate 51, an insulating layer 105 on the conductive layer 103h and on the substrate 51, a semiconductor layer 108h on the insulating layer 105, an insulating layer 106 on the semiconductor layer 108h and on the insulating layer 105, and a conductive layer 104h on the insulating layer 106. Transistor 20f has a conductive layer 203g on an insulating layer 232, an insulating layer 205 on the conductive layer 203g and on the insulating layer 232, a semiconductor layer 208g on the insulating layer 205, an insulating layer 206 on the semiconductor layer 208g and on the insulating layer 205, and a conductive layer 204g on the insulating layer 206. Transistor 20g has a conductive layer 203h on an insulating layer 232, an insulating layer 205 on the conductive layer 203h and on the insulating layer 232, a semiconductor layer 208h on the insulating layer 205, an insulating layer 206 on the semiconductor layer 208h and on the insulating layer 205, and a conductive layer 204h on the insulating layer 206.

[0211] Semiconductor layer 108g has regions 109Q and 109R that do not overlap with conductive layer 104g. Semiconductor layer 108h has regions 109S and 109T that do not overlap with conductive layer 104h. Semiconductor layer 208g has regions 209Q and 209R that do not overlap with conductive layer 204g. Semiconductor layer 208h has regions 209S and 209T that do not overlap with conductive layer 204h.

[0212] In transistor 10f, region 109Q functions as either the source region or the drain region, and region 109R functions as the other source region or drain region. In transistor 10g, region 109S functions as either the source region or the drain region, and region 109T functions as the other source region or drain region. In transistor 20f, region 209Q functions as either the source region or the drain region, and region 209R functions as the other source region or drain region. In transistor 20g, region 209S functions as either the source region or the drain region, and region 209T functions as the other source region or drain region.

[0213] In the display device 70E, conductive layers 151a and 151b are provided on the substrate 51. The insulating layer 105 is provided on conductive layer 103g, conductive layer 103h, conductive layer 151a, and conductive layer 151b. Conductive layers 251a and 251b are provided on the insulating layer 232. The insulating layer 205 is provided on conductive layer 203g, conductive layer 203h, conductive layer 251a, and conductive layer 251b. Therefore, conductive layers 151a and 151b are provided on layer 11 shown in Figure 1B. Conductive layers 251a and 251b are provided on layer 12 shown in Figure 1B.

[0214] Conductive layers 151a, 151b, 251a, and 251b are shown in both Figure 14A and Figure 14B. In Figure 14A, conductive layers 251a and 251b are shown with dashed lines. In Figure 14B, conductive layers 151a and 151b are shown with dashed lines.

[0215] As shown in Figures 14A to 15, the conductive layers 151a, 151b, 251a, and 251b are arranged to extend in a predetermined direction and not overlap each other. Figures 14A to 16 show an example in which the conductive layers 151a, 151b, 251a, and 251b extend in a direction parallel to the channel width direction of transistors 10f, 10g, 20f, and 20g. Figures 14A and 14B also show an example in which the conductive layer 251a is provided between the conductive layer 151a and the conductive layer 151b, and the conductive layer 151b is provided between the conductive layer 251a and the conductive layer 251b.

[0216] Insulating layer 191 and insulating layer 106 have openings 147q reaching region 109Q, 147r reaching region 109R, 147s reaching region 109S, and 147t reaching region 109T. Insulating layer 106 and insulating layer 105 have openings 149a reaching the conductive layer 151a. Insulating layer 191, insulating layer 106, and insulating layer 105 have openings 149b reaching the conductive layer 151b. Insulating layer 291 and insulating layer 206 have openings 247q reaching region 209Q, 247r reaching region 209R, 247s reaching region 209S, and 247t reaching region 209T. Insulating layer 291, insulating layer 206, and insulating layer 205 have openings 249a reaching the conductive layer 251a. The insulating layer 206 and the insulating layer 205 have openings 249b that reach the conductive layer 251b.

[0217] A conductive layer 112p is provided so as to cover the opening 147q. A conductive layer 112q is provided so as to cover the opening 147r. A conductive layer 112r is provided so as to cover the openings 147s and 149b. A conductive layer 112s is provided so as to cover the opening 147t. A conductive layer 104g is provided so as to cover the opening 149a. A conductive layer 212p is provided so as to cover the openings 247q and 249a. A conductive layer 212q is provided so as to cover the opening 247r. A conductive layer 212r is provided so as to cover the opening 247s. A conductive layer 212s is provided so as to cover the opening 247t. A conductive layer 204h is provided so as to cover the opening 249b.

[0218] Conductive layer 112p is in contact with region 109Q at opening 147q. Conductive layer 112q is in contact with region 109R at opening 147r. Conductive layer 112r is in contact with region 109S at opening 147s and is in contact with conductive layer 151b at opening 149b. Conductive layer 112s is in contact with region 109T at opening 147t. Conductive layer 104g is in contact with conductive layer 151a at opening 149a. Conductive layer 212p is in contact with region 209Q at opening 247q and is in contact with conductive layer 251a at opening 249a. Conductive layer 212q is in contact with region 209R at opening 247r. Conductive layer 212r is in contact with region 209S at opening 247s. The conductive layer 212s is in contact with region 209T at the opening 247t. The conductive layer 204h is in contact with conductive layer 251b at the opening 249b.

[0219] As described above, conductive layer 151a is connected to conductive layer 104g. Conductive layer 151b is connected to conductive layer 112r. Conductive layer 251a is connected to conductive layer 212p. Conductive layer 251b is connected to conductive layer 204h.

[0220] Conductive layer 112p functions as one of the source and drain electrodes of transistor 10f. Conductive layer 112q functions as the other of the source and drain electrodes of transistor 10f. Conductive layer 112r functions as one of the source and drain electrodes of transistor 10g. Conductive layer 112s functions as the other of the source and drain electrodes of transistor 10g. Conductive layer 212p functions as one of the source and drain electrodes of transistor 20f. Conductive layer 212q functions as the other of the source and drain electrodes of transistor 20f. Conductive layer 212r functions as one of the source and drain electrodes of transistor 20g. Conductive layer 212s functions as the other of the source and drain electrodes of transistor 20g.

[0221] Figure 14A shows conductive layers 112p, 112q, 112r, and 112s. Figure 14B shows conductive layers 212p, 212q, 212r, and 112s.

[0222] Conductive layers 151a, 151b, 251a, and 251b each function as clock signal lines (CLKL) in at least a portion thereof. Figures 14A to 16 show an example in which at least a portion of conductive layer 151a functions as clock signal line CLKL_1, at least a portion of conductive layer 251a functions as clock signal line CLKL_2, at least a portion of conductive layer 151b functions as clock signal line CLKL_3, and at least a portion of conductive layer 251b functions as clock signal line CLKL_4.

[0223] For example, when transistors 10f, 10g, 20f, and 20g are provided in the scan line drive circuit 33 or scan line drive circuit 34 shown in Figure 1A, at least a portion of conductive layers 151a, 151b, 251a, and 251b functions as the clock signal line CLKLa shown in Figure 4A. Also, when transistors 10f, 10g, 20f, and 20g are provided in the signal line drive circuit 35 or signal line drive circuit 36 ​​shown in Figure 1A, at least a portion of conductive layers 151a, 151b, 251a, and 251b functions as the clock signal line CLKLb shown in Figure 4B.

[0224] In the display device 70E, at least one of the multiple clock signal lines CLKL is provided on layer 11 as shown in Figure 1B, and the remaining ones are provided on layer 21. For example, if the display device 70E has 2k clock signal lines CLKL (where k is an integer of 1 or more), k lines are provided on layer 11 and the remaining k lines are provided on layer 21. Also, if the display device 70E has 2k+1 clock signal lines CLKL (where k is an integer of 1 or more), k lines or k+1 lines are provided on layer 11 and the remaining ones are provided on layer 21. As a result, the distance between clock signal lines CLKL in a top view can be shortened while preventing contact between clock signal lines CLKL compared to the case where all clock signal lines CLKL are provided on the same layer. Therefore, the occupied area of ​​the circuit section 64 can be reduced. Consequently, a narrow-bezel display device can be realized.

[0225] Furthermore, the display device 70E shows an example where multiple clock signal lines CLKL do not overlap with each other. This prevents the formation of parasitic capacitance between the clock signal line CLKL provided on layer 11 and the clock signal line CLKL provided on layer 21, as shown in Figure 1B. Thus, a high-speed display device can be realized.

[0226] At least a portion of the clock signal line CLKL provided in layer 11 may overlap with at least a portion of the clock signal line CLKL provided in layer 21. In the examples shown in Figures 14A to 16, at least a portion of conductive layer 151a may overlap with at least a portion of conductive layer 251a. Also, at least a portion of conductive layer 251a may overlap with at least a portion of conductive layer 151b. Furthermore, at least a portion of conductive layer 151b may overlap with at least a portion of conductive layer 251b. By overlapping at least a portion of the clock signal line CLKL provided in layer 11 with at least a portion of the clock signal line CLKL provided in layer 21, the occupied area of ​​the circuit section 64 can be reduced.

[0227] Furthermore, in the display device 70E, the transistor connected to the clock signal line CLKL provided on layer 11 as shown in Figure 1B is provided on layer 11. Also, the transistor connected to the clock signal line CLKL provided on layer 21 is provided on layer 21. In the examples shown in Figures 14A to 16, the transistor connected to conductive layer 151a and the transistor connected to conductive layer 151b are provided on layer 11 as transistor 10f and transistor 10g, respectively. Also, the transistor connected to conductive layer 251a and the transistor connected to conductive layer 251b are provided on layer 21 as transistor 20f and transistor 20g, respectively. As a result, the wiring distance between the clock signal line CLKL and the transistor can be shortened compared to the case where the transistor connected to the clock signal line CLKL provided on layer 11 is provided on layer 21, and the case where the transistor connected to the clock signal line CLKL provided on layer 21 is provided on layer 11. Therefore, the wiring resistance between the clock signal line CLKL and the transistor can be reduced. Consequently, a high-speed display device can be realized.

[0228] The connection configurations of the clock signal line CLKL and the transistors shown in Figures 14A to 16 are merely examples, and the present invention is not limited to these. For example, the conductive layer 151a may be connected to the source electrode or drain electrode of transistor 10f. Alternatively, the conductive layer 151b may be connected to the gate electrode of transistor 10g. Furthermore, the conductive layer 251a may be connected to the gate electrode of transistor 20f. In addition, the conductive layer 251b may be connected to the source electrode or drain electrode of transistor 20g. Also, while Figures 14A to 16 show an example where the clock signal line CLKL is directly connected to the gate electrode, source electrode, or drain electrode of a transistor, other conductive layers may be interposed between them.

[0229] [Configuration Example 3-5] Figures 17A and 17B are plan views showing configuration examples of the display device 70F. Figure 17A shows a configuration example of the layer 11 shown in Figure 1B. Figure 17B shows a configuration example of the layer 21 shown in Figure 1B.

[0230] Figure 18 is a cross-sectional view showing an example configuration between dashed lines A1 and A2, and between dashed lines A2 and A3, as shown in Figures 17A and 17B. Figure 19A is a cross-sectional view showing an example configuration between dashed lines B1 and B2, as shown in Figures 17A and 17B. Figure 19B is a cross-sectional view showing an example configuration between dashed lines B3 and B4, as shown in Figures 17A and 17B.

[0231] The display device 70F includes a substrate 51 and transistors 10h, 10k, 20h, and 20k on the substrate 51. Transistor 10h corresponds to transistor 10A shown in Figure 1B. Transistor 10k corresponds to transistor 10B shown in Figure 1B. Transistor 20h corresponds to transistor 20A shown in Figure 1B. Transistor 20k corresponds to transistor 20B shown in Figure 1B.

[0232] Figure 17A shows an example configuration of transistors 10h and 10k in a top view. Figure 17B shows an example configuration of transistors 20h and 20k in a top view.

[0233] An insulating layer 198 is provided on transistor 10h and transistor 10k. An insulating layer 231 is provided on insulating layer 198. An insulating layer 232 is provided on insulating layer 231. Transistors 20h and 20k are provided on insulating layer 232. An insulating layer 298 is provided on transistor 20h and transistor 20k.

[0234] It is preferable to use barrier insulating layers for insulating layers 198 and 298. This effectively suppresses the diffusion of impurities (e.g., water and hydrogen) into the transistor from the outside. Therefore, the reliability of the display device can be improved.

[0235] Transistor 10h has a conductive layer 104k, an insulating layer 106, a semiconductor layer 108k, a semiconductor layer 108m, a conductive layer 122, and a conductive layer 123a. Transistor 10k has a conductive layer 104m, an insulating layer 106, a semiconductor layer 108n, a conductive layer 122, and a conductive layer 123b. Transistor 20h has a conductive layer 204k, an insulating layer 206, a semiconductor layer 208k, a conductive layer 222a, and a conductive layer 223a. Transistor 20k has a conductive layer 204m, an insulating layer 206, a semiconductor layer 208m, a conductive layer 222b, and a conductive layer 223b.

[0236] The conductive layer 104k functions as the gate electrode of transistor 10h. The conductive layer 104m functions as the gate electrode of transistor 10k. The insulating layer 106 functions as the gate insulating layer of transistor 10h and the gate insulating layer of transistor 10k. The conductive layer 122 functions as one of the source electrode and drain electrode of transistor 10h, and as one of the source electrode and drain electrode of transistor 10k. The conductive layer 123a functions as the other of the source electrode and drain electrode of transistor 10h. The conductive layer 123b functions as the other of the source electrode and drain electrode of transistor 10k.

[0237] The conductive layer 123b is shown in both Figure 17A and Figure 17B. Note that the hatching pattern of the conductive layer 123b is omitted in Figure 17B.

[0238] The conductive layer 204k functions as the gate electrode of transistor 20h. The conductive layer 204m functions as the gate electrode of transistor 20k. The insulating layer 206 functions as the gate insulating layer of transistor 20h and the gate insulating layer of transistor 20k. The conductive layer 222a functions as one of the source electrode and drain electrode of transistor 20h. The conductive layer 222b functions as one of the source electrode and drain electrode of transistor 20k. The conductive layer 223a functions as the other of the source electrode and drain electrode of transistor 10h. The conductive layer 223b functions as the other of the source electrode and drain electrode of transistor 10k.

[0239] In transistors 10h, 10k, 20h, and 20k, the region of the semiconductor layer between the source electrode and the drain electrode, sandwiched between the gate insulating layers and facing the gate electrode, functions as a channel formation region. Furthermore, the region of the semiconductor layer in contact with the source electrode functions as the source region, and the region in contact with the drain electrode functions as the drain region. In the semiconductor layer, the channel formation region is located between the source region and the drain region.

[0240] In the display device 70F, a conductive layer 122 is provided on the substrate 51, an insulating layer 110 is provided on the conductive layer 122 and on the substrate 51, and a conductive layer 123a and a conductive layer 123b are provided on the insulating layer 110. The conductive layer 122 has a region that overlaps with the conductive layer 123a via the insulating layer 110, and a region that overlaps with the conductive layer 123b via the insulating layer 110. The conductive layer 123a and the insulating layer 110 have openings 141a and 141b that reach the conductive layer 122. The conductive layer 123b and the insulating layer 110 have an opening 141c that reaches the conductive layer 122. The openings 141a and 141b have an opening in the insulating layer 110 and an opening in the conductive layer 123a. The opening 141c has an opening in the insulating layer 110 and an opening in the conductive layer 123b. The openings in the insulating layer 110 are located in positions that overlap with the openings in the conductive layer 123.

[0241] Based on the above, in the examples shown in Figures 17A to 19B, transistor 10h is provided across two openings 141. On the other hand, transistor 10k is provided in one opening 141.

[0242] The shape of the top surface of the opening 141 is not limited and can be, for example, a circle, an ellipse, a triangle, a quadrilateral (including rectangles, rhombuses, and squares), a pentagon, or a polygon with rounded corners. The polygon may be either a concave polygon (a polygon in which at least one interior angle exceeds 180 degrees) or a convex polygon (a polygon in which all interior angles are 180 degrees or less). As shown in Figure 17A, the shape of the top surface of the opening 141 is preferably circular. By making the shape of the top surface of the opening circular, the processing accuracy when forming the opening can be improved, and a fine-sized opening can be formed. In this specification, the term "circular" is not limited to a perfect circle.

[0243] In this specification, the upper surface shape of an opening refers to the shape of the upper edge of the insulating layer on the side of the opening in which the opening is formed. For example, the upper surface shape of opening 141 refers to the shape of the upper edge of the insulating layer 110 on the side of opening 141.

[0244] The semiconductor layer 108k is provided so as to cover the opening 141a. The semiconductor layer 108k has a region in contact with the upper surface of the conductive layer 122, a region in contact with the side surface of the insulating layer 110, and a region in contact with the side surface of the conductive layer 123a at the opening 141a. Preferably, the semiconductor layer 108k has a region in contact with the upper surface of the conductive layer 123a. The semiconductor layer 108k has a shape that follows the upper surface and side surface of the conductive layer 123a at the opening 141a, the side surface of the insulating layer 110 at the opening 141a, and the upper surface of the conductive layer 122. The above description of the semiconductor layer 108k can also be applied to the semiconductor layer 108m by reading the opening 141a as opening 141b. Similarly, the above description of the semiconductor layer 108k can also be applied to the semiconductor layer 108n by reading the opening 141a as opening 141c and the conductive layer 123a as conductive layer 123b. Furthermore, semiconductor layer 108k and semiconductor layer 108m may be treated as a single semiconductor layer. That is, the semiconductor layer provided at opening 141a and the semiconductor layer provided at opening 141b may be the same semiconductor layer.

[0245] The insulating layer 106 is provided so as to cover the semiconductor layer 108k, semiconductor layer 108m, semiconductor layer 108n, conductive layer 123a, and conductive layer 123b. The insulating layer 106 has a shape that conforms to the top and side surfaces of the semiconductor layer 108k, the top and side surfaces of the semiconductor layer 108m, the top and side surfaces of the semiconductor layer 108n, the top and side surfaces of the conductive layer 123a, and the top and side surfaces of the conductive layer 123b.

[0246] The conductive layer 104k and the conductive layer 104m are provided on the insulating layer 106. The conductive layer 104k has a region at the opening 141a that faces the semiconductor layer 108k with the insulating layer 106 in between. The conductive layer 104k also has a region at the opening 141b that faces the semiconductor layer 108m with the insulating layer 106 in between. The conductive layer 104m has a region at the opening 141c that faces the semiconductor layer 108n with the insulating layer 106 in between.

[0247] An insulating layer 198 is provided on the conductive layer 104k, on the conductive layer 104m, and on the insulating layer 106. An insulating layer 231 is provided on the insulating layer 198, and an insulating layer 232 is provided on the insulating layer 231. Furthermore, a conductive layer 222a and a conductive layer 222b are provided on the insulating layer 232. An insulating layer 210 is provided on the conductive layer 222a, on the conductive layer 222b, and on the insulating layer 232. A conductive layer 223a and a conductive layer 223b are provided on the insulating layer 210. The conductive layer 222a has a region that overlaps with the conductive layer 223a via the insulating layer 210. Similarly, the conductive layer 222b has a region that overlaps with the conductive layer 223b via the insulating layer 210. The conductive layer 223a and the insulating layer 210 have an opening 241a that reaches the conductive layer 222a. Similarly, the conductive layer 223b and the insulating layer 210 have openings 241b that reach the conductive layer 222b. The opening 241a has an opening in the insulating layer 210 and an opening in the conductive layer 223a. Similarly, the opening 241b has an opening in the insulating layer 210 and an opening in the conductive layer 223b. The opening in the insulating layer 210 is located in a position that overlaps with the opening in the conductive layer 223.

[0248] Based on the above, in the examples shown in Figures 17A to 19B, transistors 20h and 20k are each provided in one opening 241. The upper surface shape of opening 241 can be the same as the upper surface shape of opening 141 described above.

[0249] The explanation for semiconductor layer 208k can be found by substituting conductive layer 122 for conductive layer 222a, insulating layer 110 for insulating layer 210, conductive layer 123a for conductive layer 223a, and opening 141a for opening 241a, and referring to the above explanation for semiconductor layer 108k. Similarly, the explanation for semiconductor layer 208m can be found by substituting conductive layer 122 for conductive layer 222b, insulating layer 110 for insulating layer 210, conductive layer 123a for conductive layer 223b, and opening 141a for opening 241b, and referring to the above explanation for semiconductor layer 108k.

[0250] The insulating layer 206 is provided so as to cover the semiconductor layer 208k, the semiconductor layer 208m, the conductive layer 223a, and the conductive layer 223b. The insulating layer 206 has a shape that conforms to the top and side surfaces of the semiconductor layer 208k, the top and side surfaces of the semiconductor layer 208m, the top and side surfaces of the conductive layer 223a, and the top and side surfaces of the conductive layer 223b.

[0251] The conductive layer 204k and the conductive layer 204m are provided on the insulating layer 206. The conductive layer 204k has a region at the opening 241a that faces the semiconductor layer 208k with the insulating layer 206 in between. Similarly, the conductive layer 204m has a region at the opening 241b that faces the semiconductor layer 208m with the insulating layer 206 in between. An insulating layer 298 is provided on the conductive layer 204k, the conductive layer 204m, and the insulating layer 206.

[0252] As shown in Figures 17B and 19B, insulating layers 206, 210, 232, 231, 198, and 106 have openings 248e that reach the conductive layer 123b. The conductive layer 204m is in contact with the conductive layer 123b at the opening 248e. As a result, the gate electrode of transistor 20k can be connected to the source electrode and the other drain electrode of transistor 10k. Although not shown in Figures 17A to 19B, conductive layer 222b or conductive layer 223b can be connected to, for example, the display element 13 shown in Figure 1B, specifically to one electrode of the display element 13.

[0253] In transistors 10h, 10k, 20h, and 20k, the source electrode and drain electrode are located at different heights relative to the surface to be formed (here, the upper surface of the substrate 51 or the upper surface of the insulating layer 232), and the drain current flows perpendicular to the surface to be formed, or approximately perpendicular. In other words, transistors 10h, 10k, 20h, and 20k are transistors in which the drain current flows in the vertical direction. Therefore, transistors 10h, 10k, 20h, and 20k can also be called VFETs (Vertical Field Effect Transistors), vertical transistors, vertical channel transistors, or vertical channel type transistors. In VFETs, the source electrode, semiconductor layer, and drain electrode can be stacked. Therefore, VFETs can significantly reduce the occupied area compared to so-called planar transistors in which the semiconductor layers are arranged in a planar manner. On the other hand, planar transistors can be manufactured with fewer steps compared to VFETs.

[0254] The display device 70F shown in Figures 17A to 19B can be described as a display device in which the transistors 10a, 10b, 20a, and 20b of the display device 70A shown in Figures 5A to 7B are replaced with VFETs. Here, the transistor 10h shown in Figures 17A, 18, and 19A can be provided in the buffer circuit 55 shown in Figure 4B.

[0255] Conductive layer 122 can be considered the lower electrode of transistor 10h and the lower electrode of transistor 10k. Conductive layer 222a can be considered the lower electrode of transistor 20h. Conductive layer 222b can be considered the lower electrode of transistor 20k. Conductive layer 123a can be considered the upper electrode of transistor 10h. Conductive layer 123b can be considered the upper electrode of transistor 10k. Conductive layer 223a can be considered the upper electrode of transistor 20h. Conductive layer 223b can be considered the upper electrode of transistor 20k.

[0256] The channel length of transistor 10h and transistor 10k can be controlled by the thickness of the insulating layer 110 provided between conductive layer 122 and conductive layer 123a, and between conductive layer 122 and conductive layer 123b. The channel length of transistor 20h and transistor 20k can be controlled by the thickness of the insulating layer 210 provided between conductive layer 222a and conductive layer 223a, and between conductive layer 222b and conductive layer 223b. Therefore, transistors with channel lengths shorter than the minimum exposure dimension of the exposure apparatus used to manufacture the transistors can be manufactured with high precision. In addition, variations in electrical characteristics between transistors 10h and 10k, and between transistors 20h and 20k are also reduced. Thus, a highly reliable display device can be realized. Furthermore, when variations in transistor characteristics are reduced, the degree of freedom in circuit design increases, and the operating voltage of the display device can be lowered. Thus, a display device with low power consumption can be realized.

[0257] The channel width of transistor 10h can be a length corresponding to the sum of the periphery length of the aperture 141a in a top view and the periphery length of the aperture 141b in a top view. The channel width of transistor 10k can be a length corresponding to the periphery length of the aperture 141c in a top view. Similarly, the channel width of transistor 20h can be a length corresponding to the periphery length of the aperture 241a in a top view. Furthermore, the channel width of transistor 20k can be a length corresponding to the periphery length of the aperture 241b in a top view.

[0258] The channel width of transistor 10h can be calculated, for example, when the openings 141a and 141b are circular in a top view, by multiplying the sum of the value obtained by subtracting twice the thickness of the insulating layer 106 from the width (diameter) of opening 141a and the value obtained by subtracting twice the thickness of the insulating layer 106 from the width (diameter) of opening 141b by multiplying the sum by pi (π). The channel width of transistor 10k can be calculated, for example, when the opening 141c is circular in a top view, by multiplying the value obtained by subtracting twice the thickness of the insulating layer 106 from the width (diameter) of opening 141c by multiplying the sum by pi (π). The channel width of transistor 20h can be calculated, for example, when the opening 241a is circular in a top view, by multiplying the value obtained by subtracting twice the thickness of the insulating layer 206 from the width (diameter) of opening 241a by multiplying the sum by pi (π). The channel width of transistor 20k can be calculated, for example, by multiplying the value obtained by subtracting twice the thickness of the insulating layer 206 from the width (diameter) of the opening 241b when viewed from above, by pi (π).

[0259] As described above, when the perimeter lengths of the top views of the openings 141a, 141b, 141c, 241a, and 241b are equal, the channel width of transistor 10h becomes larger than the channel widths of transistor 10k, transistor 20h, and transistor 20k. As mentioned above, transistor 10h is provided in a buffer circuit. Therefore, by increasing the channel width of transistor 10h, it becomes easier to increase the current of the signal input to the buffer circuit. Thus, a highly reliable display device can be realized, similar to the display device 70A. Alternatively, the channel width of transistor 10h may be made larger than the channel widths of transistor 10k, transistor 20h, and transistor 20k by making the size of the top view of the opening in which transistor 10h is provided larger than the size of the top view of the opening in which transistor 10k is provided, the size of the top view of the opening in which transistor 20h is provided, and the size of the top view of the opening in which transistor 20k is provided. In this case, transistor 10h may be provided in, for example, one opening, similar to transistors 10k, 20h, and 20k.

[0260] The insulating layer 110 has a region in contact with the semiconductor layer 108, and the insulating layer 210 has a region in contact with the semiconductor layer 208. To improve the interface characteristics between the semiconductor layer 108 and the insulating layer 110, it is preferable that at least a portion of the region of the insulating layer 110 in contact with the semiconductor layer 108 contains oxygen. Similarly, to improve the interface characteristics between the semiconductor layer 208 and the insulating layer 210, it is preferable that at least a portion of the region of the insulating layer 210 in contact with the semiconductor layer 208 contains oxygen. Specifically, it is preferable that the region of the insulating layer 110 in contact with the channel-forming region of the semiconductor layer 108, and the region of the insulating layer 210 in contact with the channel-forming region of the semiconductor layer 208 contain oxygen. One or more oxides and oxiditrides can be suitably used in the region of the insulating layer 110 in contact with the channel-forming region of the semiconductor layer 108, and in the region of the insulating layer 210 in contact with the channel-forming region of the semiconductor layer 208.

[0261] When a metal oxide is used for the semiconductor layer 108, it is preferable that at least a portion of the region of the insulating layer 110 that is in contact with the semiconductor layer 108 releases oxygen when heat is applied. This supplies oxygen from the insulating layer 110 to the semiconductor layer 108, reducing oxygen deficiencies (V) in the semiconductor layer 108. Ｏ ) and V Ｏ A defect containing hydrogen (V Ｏ H) can be reduced. Similarly, when a metal oxide is used for the semiconductor layer 208, it is preferable that at least a portion of the region of the insulating layer 210 that is in contact with the semiconductor layer 208 releases oxygen when heat is applied. As a result, oxygen is supplied from the insulating layer 210 to the semiconductor layer 208, and V in the semiconductor layer 208 can be reduced. Ｏ and V Ｏ H can be reduced.

[0262] It is preferable that the insulating layer 110 and the insulating layer 210 each have a laminated structure. Figure 18 and others show an example in which the insulating layer 110 has insulating layer 110_1, insulating layer 110_2 on insulating layer 110_1, and insulating layer 110_3 on insulating layer 110_2. Also, an example is shown in which the insulating layer 210 has insulating layer 210_1, insulating layer 210_2 on insulating layer 210_1, and insulating layer 210_3 on insulating layer 210_2.

[0263] The region of semiconductor layer 108 in contact with insulating layer 110_2, and the region of semiconductor layer 208 in contact with insulating layer 210_2, function as channel-forming regions. Insulating layers 110_2 and 210_2 preferably contain oxygen, and it is preferable to use one or more of the aforementioned oxides and oxiditrides. Specifically, it is preferable to use one or both silicon oxide and silicon oxiditride for insulating layers 110_2 and 210_2, respectively.

[0264] It is more preferable to use materials that release oxygen when heat is applied for insulating layer 110_2 and insulating layer 210_2. During the manufacturing process of the display device 70F, the heat applied causes insulating layer 110_2 to release oxygen, thereby supplying oxygen to semiconductor layer 108. Similarly, the release of oxygen by insulating layer 210_2 allows oxygen to be supplied to semiconductor layer 208. By supplying oxygen from insulating layer 110_2 to semiconductor layer 108, particularly to the channel formation region, oxygen vacancies (V) in semiconductor layer 108 can be reduced. Ｏ ) was repaired, V Ｏ This can reduce the V in the channel formation region. Ｏ H can be reduced. Therefore, transistor 10 can be made into a transistor that exhibits good electrical characteristics and is highly reliable. Similarly, by supplying oxygen from the insulating layer 210_2 to the semiconductor layer 208, transistor 20 can be made into a transistor that exhibits good electrical characteristics and is highly reliable.

[0265] For example, oxygen can be supplied to insulating layer 110_2 and insulating layer 210_2 by performing a heat treatment in an oxygen-containing atmosphere or a plasma treatment in an oxygen-containing atmosphere. Alternatively, oxygen can be supplied to the upper surface of insulating layer 110_2 by forming a film in an oxygen-containing atmosphere using a sputtering method. This film can then be removed. Similarly, oxygen can be supplied to the upper surface of insulating layer 210_2 by forming a film in an oxygen-containing atmosphere using a sputtering method.

[0266] The deposition of insulating layer 110_2 and insulating layer 210_2 is preferably carried out using sputtering or plasma enhanced chemical vapor deposition (PECVD). In particular, by depositing the film using a method that does not use gases containing hydrogen (e.g., hydrogen gas and ammonia gas) as the deposition gas, it is possible to obtain a film with an extremely low hydrogen content. The deposition of insulating layer 110_2 and insulating layer 210_2 can be particularly preferably carried out using sputtering. This suppresses the supply of hydrogen to the channel formation region, thereby stabilizing the electrical characteristics of transistors 10 and 20.

[0267] The insulating layer 110_1 is provided between the insulating layer 110_2 and the conductive layer 122. The insulating layer 110_3 is provided between the insulating layer 110_2 and the conductive layers 123a and 123b. The insulating layer 210_1 is provided between the insulating layer 210_2 and the conductive layers 222a and 222b. The insulating layer 210_3 is provided between the insulating layer 210_2 and the conductive layers 223a and 223b. Each of the insulating layer 110_1, the insulating layer 110_3, the insulating layer 210_1, and the insulating layer 210_3 preferably has a small amount of impurities (e.g., water and hydrogen) released therefrom. Further, each of the insulating layer 110_1, the insulating layer 110_3, the insulating layer 210_1, and the insulating layer 210_3 preferably functions as a barrier insulating layer. Thereby, the diffusion of oxygen contained in the insulating layer 110_2 to the conductive layer 122 side through the insulating layer 110_1 and the diffusion to the conductive layer 123 side through the insulating layer 110_3 can be suppressed. Similarly, the diffusion of oxygen contained in the insulating layer 210_2 to the conductive layer 222 side through the insulating layer 210_1 and the diffusion to the conductive layer 223 side through the insulating layer 210_3 can be suppressed. As described above, the amount of oxygen supplied from the insulating layer 110_2 to the channel formation region of the semiconductor layer 108 and the amount of oxygen supplied from the insulating layer Ｏ Ｏ 210_2 to the channel formation region of the semiconductor layer 208 increase, and the oxygen deficiency (V Ｏ H) and V

[0268] H can be reduced. Therefore, the transistors 10 and 20 can be made into transistors having good electrical characteristics and high reliability. Also, the oxidation of the conductive layers 122 and 123 by the oxygen contained in the insulating layer 110_2 and the increase in the electrical resistance of the conductive layers 122 and 123 can be suppressed. Similarly, the oxidation of the conductive layers 222 and 223 by the oxygen contained in the insulating layer 210_2 and the increase in the electrical resistance of the conductive layers 222 and 223 can be suppressed. As described above, the transistors 10 and 20 can be made into transistors having a large on-current.

[0268] For insulating layer 110_1, insulating layer 110_3, insulating layer 210_1, and insulating layer 210_3, one or more of the following can be suitably used, for example: aluminum oxide, hafnium oxide, hafnium aluminate, magnesium oxide, gallium oxide, zinc gallium oxide, silicon nitride, and silicon nitride oxide.

[0269] By using an oxide or oxiditride for the insulating layer 110_3, oxygen can be supplied to the insulating layer 110_2 (or the insulating film that becomes the insulating layer 110_2) when the insulating layer 110_3 (or the insulating film that becomes the insulating layer 110_3) is formed. Similarly, by using an oxide or oxiditride for the insulating layer 210_3, oxygen can be supplied to the insulating layer 210_2 (or the insulating film that becomes the insulating layer 210_2) when the insulating layer 210_3 (or the insulating film that becomes the insulating layer 210_3) is formed.

[0270] <Examples of Semiconductor Layer Configurations> Below, we will describe examples of semiconductor layer configurations in a transistor. Specifically, we will describe examples of stacked configurations of semiconductor layer 108 and semiconductor layer 208.

[0271] The semiconductor layer 108 and the semiconductor layer 208 can each have a single-layer structure or a multilayer structure of two or more layers. When a metal oxide is used for the semiconductor layer, it is preferable that the semiconductor layer has a multilayer structure. Figure 20A shows a configuration in which the semiconductor layer 108 has a multilayer structure, and Figure 20B shows a configuration in which the semiconductor layer 208 has a multilayer structure. Figure 20A shows a configuration in which the semiconductor layer 108 has a three-layer structure consisting of semiconductor layer 108_1, semiconductor layer 108_2 on semiconductor layer 108_1, and semiconductor layer 108_3 on semiconductor layer 108_2. Figure 20B shows a configuration in which the semiconductor layer 208 has a three-layer structure consisting of semiconductor layer 208_1, semiconductor layer 208_2 on semiconductor layer 208_1, and semiconductor layer 208_3 on semiconductor layer 208_2. Furthermore, an enlarged view of the semiconductor layer 108 and its vicinity is shown in Figure 20C, and an enlarged view of the semiconductor layer 208 and its vicinity is shown in Figure 20D.

[0272] The band gaps of the metal oxides in semiconductor layers 108_1, 108_2, 108_3, 208_1, 208_2, and 208_3 are preferably 2.0 eV or greater, and more preferably 2.5 eV or greater.

[0273] The following describes semiconductor layers 108_1, 108_2, and 108_3. However, by making the necessary substitutions as appropriate, these descriptions can also be applied to semiconductor layers 208_1, 208_2, and 208_3, respectively. For example, by substituting conductive layer 103 for conductive layer 203, conductive layer 104 for conductive layer 204, insulating layer 105 for insulating layer 205, and insulating layer 106 for insulating layer 206, the description of semiconductor layer 108_1 can be applied to semiconductor layer 208_1, the description of semiconductor layer 108_2 for semiconductor layer 208_2, and the description of semiconductor layer 108_3 for semiconductor layer 208_3.

[0274] The semiconductor layers 108_1, 108_2, and 108_3 can use the same material for each other. This allows the equipment used for depositing the semiconductor layers 108_1, 108_2, and 108_3 to be common, thereby reducing the manufacturing cost of the display device. Alternatively, different materials can be used for at least one of the semiconductor layers 108_1, 108_2, and 108_3. This broadens the range of materials that can be selected for the semiconductor layers 108_1, 108_2, and 108_3.

[0275] In this specification, "different materials" means materials in which some or all of the constituent elements are different, or materials in which the constituent elements are the same but the composition is different.

[0276] In some cases, the boundaries between semiconductor layer 108_1 and semiconductor layer 108_2, and between semiconductor layer 108_2 and semiconductor layer 108_3, cannot be clearly identified. Therefore, in Figures 20A to 20D, these boundaries are shown with dashed lines.

[0277] Preferably, the conductivity of semiconductor layer 108_2 is higher than that of either semiconductor layer 108_1 or semiconductor layer 108_3. This ensures that the main current path in transistor 10 is semiconductor layer 108_2. On the other hand, in semiconductor layer 108, it is preferable that semiconductor layer 108_1, which is provided in contact with insulating layer 105 which functions as a second gate insulating layer, and semiconductor layer 108_3, which is provided in contact with insulating layer 106 which functions as a first gate insulating layer, are both denser and have fewer defects than semiconductor layer 108_2.

[0278] Trap levels caused by impurities or defects may form at the interface between the insulating layer 106 and the semiconductor layer 108, and at the interface between the insulating layer 105 and the semiconductor layer 108, and at the interface at the interface at the interface. Furthermore, when the insulating layer 106 is deposited, damage may be inflicted at the interface between the insulating layer 106 and the semiconductor layer 108, causing trap levels to form at the interface at the interface at the interface. By sandwiching the semiconductor layer 108_2, which is the main current path, between semiconductor layers 108_1 and 108_3, the semiconductor layer 108_2 can be moved away from the interface between the semiconductor layer 108 and the insulating layer, thereby reducing the trap levels at and near the interface of semiconductor layer 108_2. This makes it possible to create a transistor with high field-effect mobility.

[0279] Here, when a high potential is applied to the conductive layer 104, which functions as the first gate electrode, trap levels may be formed at and near the interface between the insulating layer 106 and the semiconductor layer 108. Similarly, when a high potential is applied to the conductive layer 103, which functions as the second gate electrode, trap levels may be formed at and near the interface between the insulating layer 105 and the semiconductor layer 108. If electrons are trapped in these trap levels, the threshold voltage of the transistor may shift to the positive side, potentially reducing reliability. By providing a semiconductor layer 108_3 with few defects in contact with the insulating layer 106, the formation of trap levels at and near the interface between the insulating layer 106 and the semiconductor layer 108 can be suppressed. Similarly, by providing a semiconductor layer 108_1 with few defects in contact with the insulating layer 105, the formation of trap levels at and near the interface between the insulating layer 105 and the semiconductor layer 108 can be suppressed. This makes it possible to create a highly reliable transistor.

[0280] In this way, by sandwiching the highly conductive semiconductor layer 108_2 between the defect-free semiconductor layers 108_1 and 108_3, a transistor can be made that achieves both high field-effect mobility and high reliability. Therefore, a display device can be made that achieves both high-speed operation and high reliability.

[0281] In the channel formation region, it is preferable that the carrier mobility of semiconductor layer 108_2 is higher than that of semiconductor layer 108_1 and semiconductor layer 108_3. Here, when a non-single-crystal (e.g., polycrystalline) metal oxide is used for the semiconductor layer, the carrier mobility can be increased by increasing the carrier concentration. It is preferable that the carrier concentration of semiconductor layer 108_2 is higher than that of semiconductor layer 108_1 and semiconductor layer 108_3. As a result, the conductivity of semiconductor layer 108_2, which is the main current path, is increased, and a transistor with high field-effect mobility can be made.

[0282] It is preferable that semiconductor layer 108_1, semiconductor layer 108_2, and semiconductor layer 108_3 each contain an element that increases the carrier concentration (hereinafter also referred to as the first element). When a metal oxide is used for semiconductor layer 108_1, semiconductor layer 108_2, and semiconductor layer 108_3, one or more of hydrogen, carbon, and nitrogen can be used as the first element. Hydrogen can be suitably used as the first element. Hydrogen reacts with oxygen bonded to the metal atoms of the metal oxide to form water, thereby creating oxygen vacancies (V) in the metal oxide. Ｏ ) is formed. Furthermore, V Ｏ H acts as a donor, generating electrons, which are carriers, thereby increasing the carrier concentration in the metal oxide. Note that in the following explanation, hydrogen may be used as the first element.

[0283] In the channel formation region, it is preferable that semiconductor layer 108_2 has a region with a higher concentration of the first element compared to semiconductor layer 108_1 and semiconductor layer 108_3. Typically, it is preferable that semiconductor layer 108_2 has a region with a higher hydrogen concentration compared to semiconductor layer 108_1 and semiconductor layer 108_3. In the channel formation region, semiconductor layer 108_2 has a concentration of the first element (for example, hydrogen) of 1 × 10⁻¹⁰. １９ atoms / cm ３ The above 1 x 10 ２２ atoms / cm ３ Preferably, it has the following region, and more preferably 1 × 10 ２０ atoms / cm ３ The above 1 x 10 ２２ atoms / cm ３ Preferably, it has the following region, and more preferably 5 × 10 ２０ atoms / cm ３ The above 1 x 10 ２２ atoms / cm ３ Preferably, it has the following region, and more preferably 5 × 10 ２０ atoms / cm ３ The above 5 x 10 ２１ atoms / cm ３It is preferable that the semiconductor layer 108_2 has the following region. If the concentration of the first element in the semiconductor layer 108_2 is too low, the carrier concentration will be low, and there is a risk that the carrier mobility will be low. On the other hand, if the concentration of the first element in the semiconductor layer 108_2 is too high, the amount of VoH in the channel formation region will increase, which may cause the threshold voltage to shift and the cutoff current to increase. By setting the concentration of the first element in the semiconductor layer 108_2 within the above range, it is possible to create a transistor that achieves both high field-effect mobility and a small cutoff current. Note that the concentration of the first element in the semiconductor layer 108 may have a gradient in the thickness direction of the semiconductor layer 108. It is preferable that the maximum value of the concentration of the first element in the semiconductor layer 108_2 is within the above range. Note that the concentration of the first element in the semiconductor layer 108_2 is not limited to the above range.

[0284] In the channel formation region, it is preferable that semiconductor layer 108_1 and semiconductor layer 108_3 each have regions where the concentration of the first element is lower than that of semiconductor layer 108_2. In the channel formation region, it is preferable that semiconductor layer 108_1 and semiconductor layer 108_3 each have regions where the concentration of the first element (e.g., hydrogen) is 1 / 100 to 1 / 2 of the concentration of the first element in semiconductor layer 108_2, more preferably 1 / 100 to 1 / 4, more preferably 1 / 100 to 1 / 6, more preferably 1 / 100 to 1 / 8, and more preferably 1 / 100 to 1 / 10. If the concentration of the first element in semiconductor layer 108_1 and semiconductor layer 108_3 is too high, the film density will be low, and there is a risk of many defects. On the other hand, if the concentration of the first element in semiconductor layer 108_1 and semiconductor layer 108_3 is too low, the carrier concentration will be low, resulting in low carrier mobility, which may lead to low field-effect mobility. By setting the concentration of the first element in semiconductor layer 108_1 and semiconductor layer 108_3 within the aforementioned range, a transistor can be made that achieves both high field-effect mobility and high reliability. As mentioned above, the concentration of the first element in semiconductor layer 108 may have a gradient in the thickness direction of semiconductor layer 108. It is preferable that the minimum value of the concentration of the first element in semiconductor layer 108_1 and the minimum value of the concentration of the first element in semiconductor layer 108_3 are within the aforementioned range. However, the concentration of the first element in semiconductor layer 108_1 and semiconductor layer 108_3 is not limited to the aforementioned range.

[0285] For analyzing the concentration of the first element in the semiconductor layer 108, for example, secondary ion mass spectrometry (SIMS), or X-ray photoelectron spectroscopy (XPS, or ESCA) can be used. For example, SIMS can be suitably used for analyzing hydrogen concentration. However, the reliability of the measured values ​​may be low at the interface between the semiconductor layer 108 and the semiconductor layer 108, and in its vicinity, due to the matrix effect. For example, when measuring in the direction from the insulating layer 106 toward the semiconductor layer 108, the reliability of the measured values ​​may be low at the interface between the insulating layer 106 and the semiconductor layer 108, and in its vicinity. Measurement values ​​in the unreliable region will not be treated as the concentration of the first element in the semiconductor layer 108. Furthermore, by combining measurements taken from the insulating layer 106 towards the semiconductor layer 108 and measurements taken from the insulating layer 105 towards the semiconductor layer 108, the accuracy of the analysis of the concentration of the first element in the semiconductor layer 108 may be improved.

[0286] In concentration analysis, the intensity of the constituent elements of the metal oxide can sometimes be used to infer the location of the interface between the insulating layer 106 and the semiconductor layer 108, and the location of the interface between the insulating layer 105 and the semiconductor layer 108. For example, the range in which the intensity of the constituent elements of the metal oxide present in the semiconductor layer 108 is 1 / 2 or more of its maximum value can be called the semiconductor layer 108. When indium oxide is used for the semiconductor layer 108 and SIMS is used for the concentration analysis of the first element, the range in which the secondary ion intensity of indium is 1 / 2 or more of its maximum value can be called the semiconductor layer 108, and the range in which it is less than 1 / 2 of its maximum value can be called layers other than the semiconductor layer 108 (e.g., insulating layer 105 and insulating layer 106). Alternatively, the range in which the secondary ion intensity of an indium-containing cluster (e.g., an indium-oxygen cluster) is 1 / 2 or more of its maximum value can be called the semiconductor layer 108, and the range in which it is less than 1 / 2 of its maximum value can be called layers other than the semiconductor layer 108 (e.g., insulating layer 105 and insulating layer 106).

[0287] Preferably, the film density of semiconductor layer 108_1 and semiconductor layer 108_3 is higher than that of semiconductor layer 108_2. This reduces defects in semiconductor layer 108_1 and semiconductor layer 108_3. Furthermore, by providing semiconductor layer 108_3 with a high film density on semiconductor layer 108_2, damage to semiconductor layer 108_2 during the deposition of insulating layer 106 can be suppressed. For example, film density can be evaluated using Rutherford backscattering spectrum (RBS) or X-ray reflectivity (XRR).

[0288] Differences in film density can sometimes be evaluated using a cross-sectional transmission electron microscope (TEM) image. In TEM observation, a high film density results in a darker (darker) transmission electron (TE) image, while a low film density results in a fainter (brighter) transmission electron (TE) image. Therefore, even when the same material, such as indium oxide, is used for semiconductor layers 108_1, 108_2, and 108_3, differences in film density among these layers can sometimes be observed as differences in contrast in cross-sectional TEM observations. Specifically, in the TE image, semiconductor layers 108_1 and 108_3 may have darker (darker) regions compared to semiconductor layer 108_2. Also, semiconductor layer 108_2 may have lighter (brighter) regions compared to semiconductor layers 108_1 and 108_3.

[0289] Furthermore, the film densities of semiconductor layer 108_1 and semiconductor layer 108_3 can be configured to be the same as, or lower than, the film densities of semiconductor layer 108_2, respectively.

[0290] Even when using the same material, the etching rate may be slower if the film is denser and has a higher film density. It is preferable that the etching rate in one etchant of semiconductor layer 108_1 and semiconductor layer 108_3 is slower than the etching rate of semiconductor layer 108_2. It is also preferable to provide semiconductor layer 108_3, which has a slow etching rate, on top of semiconductor layer 108_2. This makes it possible to suppress the disappearance of semiconductor layer 108_3 in the etching process after the formation of semiconductor layer 108, and to suppress the thinning of the thickness of semiconductor layer 108.

[0291] The semiconductor layer 108 can be formed by depositing a metal oxide film and processing the metal oxide film into island shapes. It is preferable to perform a heat treatment to crystallize the metal oxide film after depositing it or after processing the metal oxide film into island shapes. By performing the heat treatment, the particle size of the crystal grains contained in the semiconductor layer 108 can be increased and the crystallinity of the semiconductor layer 108 can be improved. In addition, the heat treatment can reduce defects in the semiconductor layer 108. Furthermore, the heat treatment can remove impurities contained in the semiconductor layer 108 or adsorbed on its surface.

[0292] When the semiconductor layer 108 has a three-layer structure consisting of semiconductor layer 108_1, semiconductor layer 108_2, and semiconductor layer 108_3, the metal oxide films are formed in the following order: a first metal oxide film to become semiconductor layer 108_1, a second metal oxide film to become semiconductor layer 108_2, and a third metal oxide film to become semiconductor layer 108_3.

[0293] The first, second, and third metal oxide films are preferably deposited by sputtering using a metal target or a metal oxide target. Alternatively, the first, second, and third metal oxide films are preferably deposited by atomic layer deposition (ALD). The ALD method allows for easy control of the deposition rate, enabling the deposition of thin films with good yield. Therefore, the ALD method is particularly suitable when the metal oxide film is thin. CVD can also be used instead of sputtering and ALD.

[0294] Examples of power supplies used in sputtering apparatuses include DC (Direct Current) power supplies, RF (Radio Frequency) power supplies, and AC (Alternating Current) power supplies. A pulsed DC power supply that applies a pulsed voltage to the target can also be used. Furthermore, the magnetron sputtering method, which utilizes the magnetic field of a magnet, offers a high deposition rate, thus increasing productivity. The deposition of the first, second, and third metal oxide films can be suitably performed using sputtering methods, particularly magnetron sputtering. In the following, the magnetron sputtering method may be used as an example to describe the deposition methods for the first, second, and third metal oxide films.

[0295] When forming the first metal oxide film, the second metal oxide film, and the third metal oxide film, an inert gas (for example, helium gas, argon gas, xenon gas, etc.) can be used.

[0296] It is preferable to deposit a second metal oxide film in a vacuum after depositing a first metal oxide film, without exposing the surface of the first metal oxide film to the atmosphere. Similarly, it is preferable to deposit a third metal oxide film in a vacuum after depositing a second metal oxide film, without exposing the surface of the second metal oxide film to the atmosphere. By depositing the first, second, and third metal oxide films in succession, it is possible to suppress the adhesion of airborne impurities to the surfaces of the first and second metal oxide films. Examples of such impurities include water and organic matter.

[0297] When using the same material for two or more of the first, second, and third metal oxide films, the films can be deposited using the same sputtering target and in the same processing chamber.

[0298] It is particularly preferable that semiconductor layers 108_1, 108_2, and 108_3 use the same material. The first metal oxide film, the second metal oxide film, and the third metal oxide film can be deposited continuously in the same processing chamber using the same sputtering target. This increases the productivity of the display device and reduces manufacturing costs. Furthermore, it is possible to suppress the adhesion of airborne impurities to the surfaces of the first metal oxide film and the second metal oxide film.

[0299] When using one or more different materials for semiconductor layer 108_1, semiconductor layer 108_2, and semiconductor layer 108_3, that is, when using two or more sputtering targets, it is preferable to continuously deposit the metal oxide film in a vacuum within the same apparatus without exposing the surface of the metal oxide film to the atmosphere. For example, it is preferable to continuously deposit each metal oxide film in different processing chambers within the same apparatus in a vacuum.

[0300] As mentioned above, there are cases where the boundary between semiconductor layer 108_1 and semiconductor layer 108_2, and the boundary between semiconductor layer 108_2 and semiconductor layer 108_3, cannot be clearly identified. In particular, in configurations where the same material is used for semiconductor layer 108_1, semiconductor layer 108_2, and semiconductor layer 108_3, these boundaries may not be clearly identified. Furthermore, by continuously depositing the first metal oxide film, the second metal oxide film, and the third metal oxide film in a vacuum, no interface may be formed between each metal oxide film, and these boundaries may not be identified. In such cases, semiconductor layer 108_1, semiconductor layer 108_2, and semiconductor layer 108_3 can be read as the first region, the second region, and the third region, respectively. The semiconductor layer 108 has a first region (corresponding to semiconductor layer 108_1) on the insulating layer 105 side, a third region (corresponding to semiconductor layer 108_3) on the insulating layer 106 side, and a second region (corresponding to semiconductor layer 108_2) between the first region and the third region.

[0301] Preferably, the concentration of the first element in the second region is higher than the concentration of the first element in the first region and higher than the concentration of the first element in the third region. The concentration of the first element in the second region can be described by referring to the explanation of the concentration of the first element in semiconductor layer 108_2 above. The concentrations of the first element in the first region and the third region can be described by referring to the explanations of the concentrations of the first element in semiconductor layer 108_1 and semiconductor layer 108_3 above, respectively. Note that the concentrations of the first element in the first region, the second region, and the third region are not limited to the ranges described above.

[0302] Preferably, the film density of the first region and the third region is higher than the film density of the second region. When observing the cross-section of the semiconductor layer 108 using TEM, the TE image may show that the first region and the third region are denser (darker) compared to the second region. Also, the second region may be thinner (brighter) compared to the first region and the third region.

[0303] Here, by varying the deposition conditions for the metal oxide film, the film quality of the metal oxide film (later the semiconductor layer) can be varied. Examples of film quality include conductivity, band gap, defect amount, impurity concentration, and crystallinity. Examples of deposition conditions include power density, pressure, gas type, gas flow rate, substrate temperature, and the distance between the sputtering target and the substrate (also called T-S distance or TS distance). When varying the deposition conditions, one or more of the power density, pressure, gas type, gas flow rate, substrate temperature, and T-S distance can be varied. Note that changing the substrate temperature and T-S distance may take time. Therefore, when depositing two or more metal oxide films in the same processing chamber, it is preferable to keep the substrate temperature and T-S distance the same. Note that even when using the same material, the band gap may differ by varying the deposition conditions.

[0304] It is preferable that the deposition conditions for the first metal oxide film are different from those for the second metal oxide film. It is preferable that the deposition conditions for the third metal oxide film are different from those for the second metal oxide film. For example, it is preferable that one or both of the power density and pressure in the deposition of the first metal oxide film are different from those in the deposition of the second metal oxide film. Similarly, it is preferable that one or both of the power density and pressure in the deposition of the second metal oxide film are different from those in the deposition of the second metal oxide film. It is particularly preferable that the power density and pressure in the deposition of the first metal oxide film are different from those in the deposition of the second metal oxide film, and that the power density and pressure in the deposition of the third metal oxide film are different from those in the deposition of the second metal oxide film.

[0305] Preferably, the power density during the deposition of the first and third metal oxide films is higher than the power density during the deposition of the second metal oxide film. By increasing the power density, dense and defect-free semiconductor layers 108_1 and 108_3 can be formed. The power density during the deposition of the first and third metal oxide films is 0.3 W / cm². ２ More than 2W / cm ２ The following is preferable, and more preferably 0.4 W / cm². ２ More than 2W / cm ２ The following is preferable, and more preferably 0.5 W / cm². ２ More than 2W / cm ２ The following is preferable, and more preferably 0.6 W / cm². ２ More than 2W / cm ２ The following is preferable, and more preferably 0.6 W / cm². ２ 1W / cm or more ２The following is preferable. If the power density is too low, there is a risk of an increase in defects in semiconductor layer 108_1 and semiconductor layer 108_3, while if the power density is too high, there is a risk of an increased load on the device. By setting the power density during the deposition of the first metal oxide film and the third metal oxide film within the aforementioned range, it is possible to obtain dense semiconductor layer 108_1 and semiconductor layer 108_3 with few defects, and to reduce the load on the device. Note that the power density during the deposition of the first metal oxide film and the third metal oxide film is not limited to the aforementioned range.

[0306] Power density is calculated by dividing the power applied to the substrate by the magnet area. The magnet area is the area of ​​the surface of the magnet that overlaps with the sputtering target.

[0307] The power density during the deposition of the second metal oxide film was 0.1 W / cm². ２ 1W / cm or more ２ The following is preferable, and more preferably 0.2 W / cm². ２ 1W / cm or more ２ The following is preferable, and more preferably 0.2 W / cm². ２ 0.8W / cm or more ２ The following is preferable, and more preferably 0.2 W / cm². ２ 0.6W / cm or more ２ The following is preferable, and more preferably 0.3 W / cm². ２ 0.6W / cm or more ２ The following is preferable. Furthermore, it is preferable that the power density during the deposition of the second metal oxide film is lower than the power density during the deposition of the first and third metal oxide films. If the power density is too high, the conductivity of the semiconductor layer 108_2 may be reduced, while if the power density is too low, the deposition rate will be slow, which may reduce productivity. Also, if the power density is too low, the discharge may become unstable. By setting the power density during the deposition of the second metal oxide film within the above range, it is possible to obtain a semiconductor layer 108_2 with high conductivity and to increase productivity. Note that the power density during the deposition of the second metal oxide film is not limited to the above range.

[0308] The pressure used in the deposition of the first and third metal oxide films is preferably lower than the pressure used in the deposition of the second metal oxide film. Lowering the pressure allows for the formation of dense semiconductor layers 108_1 and 108_3 with fewer defects. The pressure used in the deposition of the first and third metal oxide films is preferably 0.1 Pa or more and 0.8 Pa or less, more preferably 0.1 Pa or more and 0.6 Pa or less, more preferably 0.1 Pa or more and 0.4 Pa or less, and more preferably 0.1 Pa or more and 0.3 Pa or less. If the pressure is too high, there is a risk of an increase in defects in semiconductor layers 108_1 and 108_3, while if the pressure is too low, it may take a long time to adjust the pressure in the processing chamber, potentially reducing productivity. Also, if the pressure is too low, arcing may occur, making discharge difficult. By setting the pressure during the deposition of the first and third metal oxide films within the aforementioned ranges, it is possible to produce dense semiconductor layers 108_1 and 108_3 with few defects, while also increasing productivity. However, the pressure during the deposition of the first and third metal oxide films is not limited to the aforementioned ranges.

[0309] The pressure used in the deposition of the second metal oxide film is preferably 0.2 Pa or more and 1 Pa or less, more preferably 0.3 Pa or more and 1 Pa or less, more preferably 0.4 Pa or more and 1 Pa or less, and more preferably 0.4 Pa or more and 0.8 Pa or less. Furthermore, the pressure used in the deposition of the second metal oxide film is preferably higher than the pressure used in the deposition of the first and third metal oxide films. If the pressure is too low, the conductivity of the semiconductor layer 108_2 may be reduced. On the other hand, if the pressure is too high, the deposition rate will be slow, which may reduce productivity. Also, if the pressure is too high, discharge may become difficult. By setting the pressure used in the deposition of the second metal oxide film within the above range, it is possible to obtain a semiconductor layer 108_2 with high conductivity and to increase productivity. Note that the pressure used in the deposition of the second metal oxide film is not limited to the above range.

[0310] <Example of drive circuit configuration> Below, an example of the configuration of a drive circuit in a display device according to one aspect of the present invention will be described.

[0311] Figure 21 is a block diagram showing an example configuration of a scan line drive circuit, and provides a more detailed configuration example than Figure 4A. As shown in Figure 21, the shift register circuit 43 has multiple circuits 46. The buffer circuit 45 has multiple circuits 47.

[0312] Multiple circuits 46 are connected in series via wiring 24. Each of the multiple circuits 46 is connected to at least one of multiple clock signal lines CLKLa. For example, at least one clock signal line CLKLa connected to a predetermined circuit 46 is different from at least one clock signal line CLKLa connected to the preceding circuit 46. Similarly, at least one clock signal line CLKLa connected to the predetermined circuit 46 is different from at least one clock signal line CLKLa connected to the subsequent circuit 46. For example, if a shift register circuit 43 is connected to a first clock signal line, a second clock signal line, and a third clock signal line, and a predetermined circuit 46 is connected to the first clock signal line and the second clock signal line, then the preceding circuit 46 can be connected to the third clock signal line and the first clock signal line. Also, the subsequent circuit 46 can be connected to the second clock signal line and the third clock signal line.

[0313] Multiple circuits 47 are each connected to different circuits 46 and different wiring 23. When a start pulse signal is supplied to the shift register circuit 43, the multiple circuits 46 sequentially output signals to circuit 47. The signals input to circuit 47 are amplified and output to wiring 23. Note that circuit 46 may be called a shift register circuit or simply a register circuit. Also, circuit 47 may be called a buffer circuit.

[0314] As shown in Figure 21, circuits 46 and 47 are combined to form circuit 48. Specifically, one circuit 48 has one of circuits 46 and one of circuits 47. Circuit 48 is also called a drive circuit.

[0315] The configuration of the shift register circuit 43 shown in Figure 21 can also be applied to the shift register circuit 53 shown in Figure 4B. Furthermore, the configuration of the buffer circuit 45 shown in Figure 21 can also be applied to the buffer circuit 55 shown in Figure 4B.

[0316] Figures 22A to 26 are circuit diagrams showing example configurations of circuit 48. Figures 22A to 26 show example configurations of circuit 46 and circuit 47. In Figures 22A to 26, the wiring 24 connected to the preceding circuit 46 is denoted as wiring 24I. The wiring 24 connected to the subsequent circuit 46 is denoted as wiring 24O. The signal supplied to wiring 24I is supplied to wiring 24O and circuit 47.

[0317] The circuit 46 shown in Figure 22A includes transistors Tr101, Tr102, Tr103, Tr104, Tr105, Tr106, Tr107, Tr108, ​​Tr109, capacitive element C101, and capacitive element C102. The circuit 47 shown in Figure 22A includes transistors Tr110, Tr111, Tr112, and capacitive element C103. Note that circuit 46 does not necessarily have to include transistors Tr103 and Tr106.

[0318] The circuit 46 shown in Figure 22A has two clock signal lines CLKLa connected to it. Specifically, clock signal line CLKLa_1 is connected to either the source or drain of transistor Tr108. Clock signal line CLKLa_2 is connected to the gate of transistor Tr104.

[0319] Wiring 24I is connected to the gates of transistors Tr101, Tr105, and Tr106. One electrode of capacitive element C101 is connected to the gate of transistor Tr102, the gate of transistor Tr103, one source and one drain of transistor Tr104, one source and one drain of transistor Tr105, the gate of transistor Tr109, and the gate of transistor Tr112. One electrode of capacitive element C102 is connected to one source and one drain of transistor Tr107, and the gate of transistor Tr108. The other electrode of capacitive element C102, the other source and drain of transistor Tr108, ​​and one source and one drain of transistor Tr109 are connected to wiring 24O. One electrode of capacitive element C103 is connected to one source and one drain of transistor Tr110, and the gate of transistor Tr111. The other electrode of the capacitive element C103, one of the source and drain of the transistor Tr111, and one of the source and drain of the transistor Tr112 are connected to the wiring 23.

[0320] The potential VDD is supplied to one source and drain of transistor Tr101, the other source and drain of transistor Tr104, the gate of transistor Tr107, and the gate of transistor Tr110. The potential VSS is supplied to one source and drain of transistor Tr103, one source and drain of transistor Tr106, the other source and drain of transistor Tr109, the other source and drain of transistor Tr112, and the other electrode of capacitive element C101. If circuit 46 does not have transistors Tr103 and Tr106, the potential VSS is supplied to one source and drain of transistor Tr102 and the other source and drain of transistor Tr105.

[0321] In this specification, the potential VDD refers to a power supply potential that is higher than the potential VSS. The potential VSS refers to a power supply potential that is lower than the potential VDD. The potential VDD is also called the high potential, and the potential VSS is also called the low potential. Here, the ground potential GND can also be used as the potential VDD or the potential VSS. For example, if the potential VDD is the ground potential GND, then the potential VSS is lower than the ground potential GND. Also, if the potential VSS is the ground potential GND, then the potential VDD is higher than the ground potential GND.

[0322] In the display device 70A shown in Figures 7A and 8, it is preferable to use transistor 10a as transistors Tr110, Tr111, and Tr112. It is also preferable to use transistor 10a as transistors Tr107, Tr108, ​​and Tr109, which are included in the buffer circuit for increasing the current of the signal output to the wiring 24O. On the other hand, it is preferable to use transistor 20a as transistors Tr101 to Tr106.

[0323] Here, as shown in Figure 7A, the channel width W2 of transistor 20a is smaller than the channel width W1 of transistor 10a. Therefore, the off-current of transistor 20a can be made smaller than the off-current of transistor 10a. Accordingly, transistor 20a may be applied to transistors Tr107 and Tr110, where one of the source and drain is connected to one electrode of a capacitive element. This allows the capacitive elements C102 and C103 to retain charge for a longer period than when transistor 10a is applied to transistors Tr107 and Tr110. In addition, the occupied area of ​​circuits 46 and 47 can be reduced. On the other hand, when transistor 10a is applied to transistors Tr107 and Tr110, the current of the signal output by circuit 47 to wiring 23 can be increased compared to when transistor 20a is applied.

[0324] In the display device 70B shown in Figures 9 to 10B, it is preferable to use transistor 10c as transistors Tr101 to Tr103, Tr108, ​​Tr109, Tr111, and Tr112. On the other hand, it is preferable to use transistor 20c as transistors Tr104 to Tr107 and Tr110. Transistor 10c may also be used for transistor Tr106.

[0325] Figure 22B shows an example where transistors Tr104, Tr107, and Tr110, shown in Figure 22A, are transistors in which two transistors are connected in series. Transistors Tr104, Tr107, and Tr110 in Figure 22B are the same as transistors 60 shown in Figures 11 to 12B. In the example shown in Figure 22B, transistors Tr105 and Tr106 may be used to form a transistor with the same configuration as transistor 60. In this case, one of transistors Tr105 and Tr106 corresponds to transistor 60a shown in Figure 12B. The other of transistors Tr105 and Tr106 corresponds to transistor 60b shown in Figure 12B.

[0326] The circuit 46 shown in Figure 23A includes transistors Tr121, Tr122, Tr123, Tr124, Tr125, Tr126, Tr127, Tr128, Tr129, and Tr130. The circuit 47 shown in Figure 23A includes transistors Tr131, Tr132, and a capacitive element C121.

[0327] A clock signal line CLKLa is connected to one of the source and drain terminals of transistor Tr131. Wiring 24I is connected to the gate of transistor Tr123 and the gate of transistor Tr128. One electrode of capacitive element C121 is connected to one of the source and drain terminals of transistor Tr123, one of the source and drain terminals of transistor Tr124, one of the source and drain terminals of transistor Tr125, the gate of transistor Tr129, and the gate of transistor Tr131. The other electrode of capacitive element C121, one of the source and drain terminals of transistor Tr121, one of the source and drain terminals of transistor Tr122, the other source and drain terminal of transistor Tr131, and one of the source and drain terminals of transistor Tr132 are connected to wiring 24O.

[0328] The potential VDD is supplied to the other source and drain of transistor Tr123, one source and drain of transistor Tr127, and the gate of transistor Tr127. The potential VSS is supplied to the other source and drain of transistor Tr121, the other source and drain of transistor Tr122, the other source and drain of transistor Tr124, the other source and drain of transistor Tr125, one source and drain of transistor Tr126, one source and drain of transistor Tr128, one source and drain of transistor Tr129, one source and drain of transistor Tr130, and the other source and drain of transistor Tr132.

[0329] In the display device 70A shown in Figures 7A and 8, it is preferable to use transistor 10a as transistor Tr131 and transistor Tr132. On the other hand, it is preferable to use transistor 20a as transistors Tr121 to Tr130.

[0330] In the display device 70B shown in Figures 9 to 10B, it is preferable to use transistor 10c as transistors Tr121, Tr122, and Tr126 to Tr132. On the other hand, it is preferable to use transistor 20c as transistors Tr123 to Tr125.

[0331] Figure 23B shows an example where transistors Tr123, Tr124, and Tr125, shown in Figure 23A, are transistors in which two transistors are connected in series. Transistors Tr123, Tr124, and Tr125 in Figure 23B are the same transistors 60 shown in Figures 11 to 12B.

[0332] The circuit 46 shown in Figure 24A includes transistors Tr141, Tr142, Tr143, Tr144, Tr145, Tr146, and a capacitive element C141. The circuit 47 shown in Figure 24A includes transistors Tr147, Tr148, and a capacitive element C142.

[0333] Two clock signal lines CLKLa are connected to circuit 46 shown in Figure 24A. Specifically, clock signal line CLKLa_1 is connected to the gate of transistor Tr144 and to one of the source and drain of transistor Tr147. Clock signal line CLKLa_2 is connected to the gate of transistor Tr141, the gate of transistor Tr142, and one of the source and drain of transistor Tr143.

[0334] Wiring 24I is connected to one of the source and drain of transistor Tr141. One electrode of capacitive element C141 is connected to one of the source and drain of transistor Tr142, the other of the source and drain of transistor Tr143, the gate of transistor Tr145, and the gate of transistor Tr148. One electrode of capacitive element C142 is connected to one of the source and drain of transistor Tr146, and the gate of transistor Tr147. The other electrode of capacitive element C142, the other of the source and drain of transistor Tr147, and one of the source and drain of transistor Tr148 are connected to wiring 23 and wiring 24O, respectively. In the circuit shown in Figure 24A, wiring 23 and wiring 24O can be considered as the same wiring.

[0335] The potential VDD is supplied to the source and the other drain of transistor Tr142, and to the gate of transistor Tr146. The potential VSS is supplied to one of the source and drain of transistor Tr145, the other source and drain of transistor Tr148, and the other electrode of capacitive element C141.

[0336] In the display device 70A shown in Figures 7A and 8, it is preferable to use transistor 10a as transistor Tr147 and transistor Tr148. On the other hand, it is preferable to use transistor 20a as transistors Tr141 to Tr146.

[0337] In the display device 70B shown in Figures 9 to 10B, and the display device 70C shown in Figures 11 and 12A, it is preferable to use transistor 10c as transistors Tr141, Tr144, Tr145, Tr147, and Tr148. On the other hand, it is preferable to use transistor 20c or transistor 60 as transistors Tr142, Tr143, and Tr146.

[0338] The circuit 46 shown in Figure 24B includes transistors Tr151, Tr152, Tr153, Tr154, Tr155, Tr156, Tr157, Tr158, Tr159, Tr160, Tr161, and Tr162. The circuit 47 shown in Figure 24B includes transistors Tr163 and Tr164, and capacitive elements C151 and C152.

[0339] The circuit 46 shown in Figure 24B has four clock signal lines CLKLa connected to it. Specifically, clock signal line CLKLa_1 is connected to the gate of transistor Tr162. Clock signal line CLKLa_2 is connected to either the source or drain of transistor Tr163. Clock signal line CLKLa_3 is connected to the gate of transistor Tr161. Furthermore, clock signal line CLKLa_4 is connected to the gate of transistor Tr153.

[0340] Wiring 24I is connected to the gate of transistor Tr152 and the gate of transistor Tr156. One electrode of capacitive element C151 is connected to one source and one drain of transistor Tr154, one source and one drain of transistor Tr155, one source and one drain of transistor Tr158, one source and one drain of transistor Tr160, and the gate of transistor Tr163. One electrode of capacitive element C152 is connected to one source and one drain of transistor Tr151, one source and one drain of transistor Tr156, the gate of transistor Tr157, one source and one drain of transistor Tr161, one source and one drain of transistor Tr162, and the gate of transistor Tr164. The other electrode of the capacitive element C151, the other source and drain of transistor Tr163, and one source and drain of transistor Tr164 are connected to wiring 23 and wiring 24O, respectively. In the circuit shown in Figure 24B, wiring 23 and wiring 24O can be considered as the same wiring.

[0341] The potential VDD is supplied to one of the source and drain of transistor Tr152, the gate of transistor Tr154, the gate of transistor Tr155, the gate of transistor Tr158, the gate of transistor Tr160, the other of the source and drain of transistor Tr161, and the other of the source and drain of transistor Tr162. The potential VSS is supplied to the other of the source and drain of transistor Tr151, the other of the source and drain of transistor Tr156, one of the source and drain of transistor Tr157, one of the source and drain of transistor Tr159, the other of the source and drain of transistor Tr164, and the other electrode of capacitive element C152.

[0342] In the display device 70A shown in Figures 7A and 8, it is preferable to use transistor 10a as transistor Tr163 and transistor Tr164. On the other hand, it is preferable to use transistor 20a as transistors Tr151 to Tr162.

[0343] In the display device 70B shown in Figures 9 to 10B, and the display device 70C shown in Figures 11 and 12A, it is preferable to use transistor 10c as transistors Tr152, Tr153, Tr157, Tr159, Tr163, and Tr164. On the other hand, it is preferable to use transistor 20c or transistor 60 as transistors Tr151, Tr154 to Tr156, Tr158, and Tr160 to Tr162.

[0344] The circuit 46 shown in Figure 25A includes transistors Tr171, Tr172, Tr173, Tr174, Tr175, Tr176, Tr177, capacitive element C171, and capacitive element C172. The circuit 47 shown in Figure 25A includes transistors Tr178, Tr179, and capacitive element C173.

[0345] The circuit 46 shown in Figure 25A has two clock signal lines CLKLa connected to it. Specifically, clock signal line CLKLa_1 is connected to either the source or drain of transistor Tr179. Clock signal line CLKLa_2 is connected to the gate of transistor Tr177.

[0346] Wiring 24I is connected to the gate of transistor Tr172 and the gate of transistor Tr174. One electrode of capacitive element C171 and one electrode of capacitive element C172 are connected to one source and one drain of transistor Tr171, one source and one drain of transistor Tr174, the gate of transistor Tr175, one source and one drain of transistor Tr176, one source and one drain of transistor Tr177, and the gate of transistor Tr178. One electrode of capacitive element C173 is connected to one source and one drain of transistor Tr173, and the gate of transistor Tr179. The other electrode of capacitive element C173, the gate of transistor Tr176, one source and one drain of transistor Tr178, and the other source and one drain of transistor Tr179 are connected to wiring 23 and wiring 24O, respectively. In the circuit shown in Figure 25A, wiring 23 and wiring 24O can be considered as the same wiring.

[0347] The potential VDD is supplied to the source and drain of transistor Tr171, one source and drain of transistor Tr172, the gate of transistor Tr173, the source and drain of transistor Tr177, and the other electrode of capacitive element C172. The potential VSS is supplied to the source and drain of transistor Tr174, one source and drain of transistor Tr175, the other source and drain of transistor Tr176, the other source and drain of transistor Tr178, and the other electrode of capacitive element C171.

[0348] In the display device 70A shown in Figures 7A and 8, it is preferable to use transistor 10a as transistor Tr178 and transistor Tr179. On the other hand, it is preferable to use transistor 20a as transistors Tr171 to Tr177.

[0349] In the display device 70B shown in Figures 9 to 10B, and the display device 70C shown in Figures 11 and 12A, it is preferable to use transistor 10c as transistors Tr172, Tr175, Tr178, and Tr179. On the other hand, it is preferable to use transistor 20c or transistor 60 as transistors Tr171, Tr173, Tr174, Tr176, and Tr177.

[0350] The circuit 46 shown in Figure 25B includes transistors Tr181, Tr182, Tr183, Tr184, Tr185, Tr186, and a capacitive element C181. The circuit 47 shown in Figure 25B includes transistors Tr187, Tr188, and a capacitive element C182.

[0351] The circuit 46 shown in Figure 25B has two clock signal lines CLKLa connected to it. Specifically, clock signal line CLKLa_1 is connected to the gate of transistor Tr184 and to one of the source and drain of transistor Tr187. Clock signal line CLKLa_2 is connected to the gate of transistor Tr181 and the gate of transistor Tr182.

[0352] Wiring 24I is connected to one of the source and drain of transistor Tr181, and to one of the source and drain of transistor Tr183. One electrode of capacitive element C181 is connected to one of the source and drain of transistor Tr182, the other of the source and drain of transistor Tr183, the gate of transistor Tr185, and the gate of transistor Tr188. One electrode of capacitive element C182 is connected to one of the source and drain of transistor Tr186, and to the gate of transistor Tr187. The other electrode of capacitive element C182, the other of the source and drain of transistor Tr187, and one of the source and drain of transistor Tr188 are connected to wiring 23 and wiring 24O, respectively. In the circuit shown in Figure 25B, wiring 23 and wiring 24O can be considered as the same wiring.

[0353] The potential VDD is supplied to the source and the other drain of transistor Tr182, and to the gate of transistor Tr186. The potential VSS is supplied to one of the source and drain of transistor Tr185, the other source and drain of transistor Tr188, and the other electrode of capacitive element C181.

[0354] In the display device 70A shown in Figures 7A and 8, it is preferable to use transistor 10a as transistor Tr187 and transistor Tr188. On the other hand, it is preferable to use transistor 20a as transistors Tr181 to Tr186.

[0355] In the display device 70B shown in Figures 9 to 10B, and the display device 70C shown in Figures 11 and 12A, it is preferable to use transistor 10c as transistors Tr181, Tr184, Tr185, Tr187, and Tr188. On the other hand, it is preferable to use transistor 20c or transistor 60 as transistors Tr182, Tr183, and Tr186.

[0356] The circuit 46 shown in Figure 26 includes transistors Tr191, Tr192, Tr193, Tr194, Tr195, Tr196, Tr197, capacitive element C191, and capacitive element C192. The circuit 47 shown in Figure 26 includes transistors Tr198, Tr199, and capacitive element C193.

[0357] The circuit 46 shown in Figure 26 has two clock signal lines CLKLa connected to it. Specifically, clock signal line CLKLa_1 is connected to the gate of transistor Tr196. Clock signal line CLKLa_2 is connected to one of the source and drain electrodes of transistor Tr195, one of the source and drain electrodes of transistor Tr198, and one electrode of capacitive element C192.

[0358] In the circuit 46 shown in Figure 26, wires 24I_1 and 24I_2 are connected as wires 24I. In addition, wire 24O_1 is connected to circuit 47, and wire 24O_2 is connected to circuit 46 as wires 24O. Signals supplied to circuit 46 from wire 24I_1 are output to wire 24O_1. Signals supplied to circuit 46 from wire 24I_2 are output to wire 24O_2.

[0359] Wiring 24I_1 is connected to the gate of transistor Tr193. Wiring 24I_2 is connected to the gate of transistor Tr197. One electrode of capacitive element C191 is connected to one source and one drain of transistor Tr192, the gate of transistor Tr194, the other source and drain of transistor Tr195, and the gate of transistor Tr199. The other electrode of capacitive element C192 is connected to the gate of transistor Tr195, one source and one drain of transistor Tr196, and one source and one drain of transistor Tr197. One electrode of capacitive element C193 is connected to one source and one drain of transistor Tr191, and the gate of transistor Tr198.

[0360] The other electrode of the capacitive element C193, the other source and drain of transistor Tr198, and one source and drain of transistor Tr199 are connected to wiring 23 and wiring 24O_1, respectively. In the circuit shown in Figure 26, wiring 23 and wiring 24O_1 can be considered as the same wiring. In addition, the other source and drain of transistor Tr191, the gate of transistor Tr192, one source and drain of transistor Tr193, and one source and drain of transistor Tr194 are connected to wiring 24O_2.

[0361] The gate of transistor Tr191, and the other source and drain of transistor Tr193, are supplied with a potential VDD. The other source and drain of transistor Tr192, the other source and drain of transistor Tr194, the other source and drain of transistor Tr196, the other source and drain of transistor Tr197, and the other source and drain of transistor Tr199 are supplied with a potential VSS.

[0362] In the display device 70A shown in Figures 7A and 8, it is preferable to use transistor 10a as transistor Tr198 and transistor Tr199. On the other hand, it is preferable to use transistor 20a as transistors Tr191 to Tr197.

[0363] In the display device 70B shown in Figures 9 to 10B, and the display device 70C shown in Figures 11 and 12A, it is preferable to use transistor 10c as transistors Tr193, Tr194, Tr198, and Tr199. On the other hand, it is preferable to use transistor 20c or transistor 60 as transistors Tr191, Tr192, Tr195 to Tr197.

[0364] <Example of Display Device Configuration 4> Below, an example of the configuration of a display device according to one embodiment of the present invention will be described. For example, a cross-sectional configuration example including a display element will be described with reference to the drawings.

[0365] A display device according to one aspect of the present invention can be a high-resolution display device or a large-screen display device. Therefore, a display device according to one aspect of the present invention can be used in electronic devices equipped with relatively large screens, such as television equipment, desktop or notebook computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as in the display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal information terminals, and audio playback devices.

[0366] A display device according to one aspect of the present invention can be a high-definition display device. Therefore, a display device according to one aspect of the present invention can be used, for example, as a display unit for information terminals (wearable devices) such as wristwatches and bracelets, and as a display unit for wearable devices that can be worn on the head, such as VR devices such as head-mounted displays (HMDs) and AR devices such as glasses.

[0367] A display device according to one aspect of the present invention may also function as a touch panel. For example, various detection elements (also called sensor elements) capable of detecting the proximity or contact of an object to be detected, such as a finger, can be applied to the display device.

[0368] Examples of sensor types include capacitive, resistive, surface acoustic wave, infrared, optical, and pressure-sensitive sensors.

[0369] Examples of capacitance methods include surface capacitance and projected capacitance. Furthermore, projected capacitance methods include self-capacitance and mutual capacitance. Mutual capacitance is preferable because it enables simultaneous multi-point detection.

[0370] Examples of touch panels include out-cell, on-cell, and in-cell types. An in-cell type touch panel refers to a configuration in which electrodes constituting the sensing element are provided on one or both of the substrate supporting the display element and the opposing substrate.

[0371] If the display device has a touch panel function, it can perform computational processing using a neural network based on touch information. Specifically, a GPU (Graphics Processing Unit) is provided in the circuit unit 64, and this GPU can perform computational processing using a neural network. In addition, an NPU (Neural Processing Unit) is provided in the circuit unit 64, and this NPU can perform computational processing using a neural network.

[0372] Various elements can be used as display elements, such as liquid crystal elements and light-emitting elements. In addition, display elements using shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems), microcapsule-type, electrophoretic-type, electrowetting-type, or electronic powder fluid (registered trademark)-type methods can also be used. Furthermore, QLEDs (Quantum-dot LEDs) using a light source and color conversion technology using quantum dot materials can be used.

[0373] Examples of display devices using liquid crystal elements include transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices.

[0374] Modes that can be used in display devices using liquid crystal elements include, for example, Vertical Alignment (VA) mode, FFS (Fringe Field Switching) mode, IPS (In-Plane-Switching) mode, TN (Twisted Nematic) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optically Compensated Birefringence) mode, FLC (Ferroelectric Liquid Crystal) mode, AFLC (AntiFerroelectric Liquid Crystal) mode, and ECB (Electrically Examples of VA modes include Controlled Birefringence mode and Guest Host mode. Examples of VA modes include MVA (Multi-Domain Vertical Alignment) mode, PVA (Patterned Vertical Alignment) mode, and ASV (Advanced Super View) mode.

[0375] Examples of liquid crystal materials that can be used in liquid crystal elements include thermotropic liquid crystals, low molecular weight liquid crystals, polymer liquid crystals, polymer dispersed liquid crystals (PDLC), polymer network liquid crystals (PNLC), ferroelectric liquid crystals, and antiferroelectric liquid crystals. Depending on the conditions, these liquid crystal materials exhibit cholesteric phases, smectic phases, cubic phases, chiral nematic phases, isotropic phases, blue phases, etc. Furthermore, either positive-type or negative-type liquid crystals can be used as the liquid crystal material, and can be selected according to the applied mode or design.

[0376] Examples of light-emitting elements include self-emissive light-emitting elements such as LEDs (Light Emitting Diodes), OLEDs (Organic LEDs), and semiconductor lasers. For example, mini-LEDs and micro-LEDs can be used as LEDs.

[0377] The light-emitting element can emit infrared, red, green, blue, cyan, magenta, yellow, or white, among others. Furthermore, the color purity can be improved by adding a microcavity structure to the light-emitting element.

[0378] Of the pair of electrodes in a light-emitting element, one electrode functions as the anode and the other electrode functions as the cathode.

[0379] Furthermore, a display device according to one aspect of the present invention can be a top-emission type that emits light in the direction opposite to the substrate on which the light-emitting element is formed, a bottom-emission type that emits light toward the substrate on which the light-emitting element is formed, or a dual-emission type that emits light on both sides.

[0380] [Configuration Example 4-1] Figure 27A is a cross-sectional view showing an example configuration of the display device 70. Figure 27A shows an example configuration of the display unit 62 and the circuit unit 64. The configurations of the display devices 70A to 70F can be applied as the display unit 62 and the circuit unit 64. In the display devices 70 described below, the configurations of the display devices 70A to 70F can also be applied as the display unit 62 and the circuit unit 64.

[0381] The display device 70 shown in Figure 27A has transistors 107D and 207D of the circuit unit 64 and transistors 107R, 107G, 107B, 207R, 207G, 207B, light-emitting elements 61R, 61G, and 61B of the display unit 62, all located between substrates 51 and 52. Transistors 107D, 107R, 107G, and 107B are located on layer 11. Transistors 207D, 207R, 207G, and 207B are located on layer 21.

[0382] The description of transistor 10 described above can be applied to transistors 107D, 107R, 107G, and 107B. The description of transistor 20 described above can be applied to transistors 207D, 207R, 207G, and 207B. In the example shown in Figure 27A, transistors 107D, 107R, 107G, and 107B are planar transistors, but these transistors may also be VFETs. The same applies to the display device 70 described below.

[0383] In the following explanation, transistors 107D, 107R, 107G, and 107B may be simply referred to as transistor 107. Similarly, transistors 207D, 207R, 207G, and 207B may be simply referred to as transistor 207.

[0384] The light-emitting element 61R emits, for example, red light. The light-emitting element 61G emits, for example, green light. The light-emitting element 61B emits, for example, blue light. Full-color display can be achieved using the light-emitting elements 61R, 61G, and 61B. The light-emitting elements 61R, 61G, and 61B correspond to the display element 13 shown in Figure 1B.

[0385] The display device 70 shown in Figure 27A employs a structure that creates separate light-emitting layers using light-emitting elements with different emission wavelengths (also known as the SBS (Side By Side) structure). The SBS structure allows for optimization of materials and configurations for each light-emitting element, thus increasing the freedom in selecting materials and configurations and making it easier to improve brightness and reliability.

[0386] The display device 70 is a top-emission type. In the top-emission type, transistors and the like can be arranged overlapping with the light-emitting region of the light-emitting element, which allows for a higher aperture ratio of pixels compared to the bottom-emission type.

[0387] An insulating layer 235 is provided on the conductive layer 212 and on the insulating layer 291. On the insulating layer 235, a light-emitting element 61R, a light-emitting element 61G, and a light-emitting element 61B are provided.

[0388] The insulating layer 235 preferably functions as a planarization layer. For the insulating layer 235, a material that can be used for the insulating layer 231 can be used.

[0389] The light-emitting element 61R includes a pixel electrode 111R on the insulating layer 235, an EL layer 113R on the pixel electrode 111R, and a common electrode 115 on the EL layer 113R. The light-emitting element 61R shown in FIG. 27A emits red light (R). The EL layer 113R has a light-emitting layer that emits red light.

[0390] The light-emitting element 61G includes a pixel electrode 111G on the insulating layer 235, an EL layer 113G on the pixel electrode 111G, and a common electrode 115 on the EL layer 113G. The light-emitting element 61G shown in FIG. 27A emits green light (G). The EL layer 113G has a light-emitting layer that emits green light.

[0391] The light-emitting element 61B includes a pixel electrode 111B on the insulating layer 235, an EL layer 113B on the pixel electrode 111B, and a common electrode 115 on the EL layer 113B. The light-emitting element 61B shown in FIG. 27A emits blue light (B). The EL layer 113B has a light-emitting layer that emits blue light.

[0392] In FIG. 27A, the EL layer 113R, the EL layer 113G, and the EL layer 113B are all shown with the same thickness, but it is not limited thereto. The respective thicknesses of the EL layer 113R, the EL layer 113G, and the EL layer 113B may be different. For example, it is preferable to set the thicknesses of the EL layer 113R, the EL layer 113G, and the EL layer 113B so that the optical path lengths of the light emitted by each are increased. Thereby, a microcavity structure can be realized, and the color purity of the light emitted from each light-emitting element can be enhanced.

[0393] The pixel electrode 111R is connected to the conductive layer 212 of the transistor 207R through an opening provided in the insulating layer 235. Similarly, the pixel electrode 111G is connected to the conductive layer 212 of the transistor 207G, and the pixel electrode 111B is connected to the conductive layer 212 of the transistor 207B.

[0394] The respective end portions of the pixel electrode 111R, the pixel electrode 111G, and the pixel electrode 111B are covered by the insulating layer 237. The insulating layer 237 functions as a partition wall. The insulating layer 237 can be provided in a single-layer structure or a laminated structure using one or both of an inorganic insulating material and an organic insulating material. For example, the above-described organic insulating material or inorganic insulating material can be used for the insulating layer 237. The insulating layer 237 can electrically insulate the pixel electrode and the common electrode. Further, the insulating layer 237 can electrically insulate adjacent light-emitting elements from each other.

[0395] The insulating layer 237 is provided at least in the display portion 62. The insulating layer 237 may be provided not only in the display portion 62 but also in the circuit portion 64.

[0396] The common electrode 115 is a continuous film provided in common to the light-emitting elements 61R, the light-emitting element 61G, and the light-emitting element 61B.

[0397] In the display device according to one aspect of the present invention, among the pixel electrode and the common electrode, a conductive film that transmits visible light (wavelength: 380 nm or more and 780 nm or less) is used for the electrode on the light extraction side. Further, it is preferable to use a conductive film that reflects visible light for the electrode on the side where light is not extracted.

[0398] A conductive film that transmits visible light may also be used for the electrode on the side where light is not extracted. In this case, it is preferable to dispose the electrode between the reflective layer and the EL layer. That is, the light emitted from the EL layer may be reflected by the reflective layer and extracted from the display device.

[0399] As the material for forming the pair of electrodes of the light-emitting element, metals, alloys, electrically conductive compounds, and mixtures thereof can be used as appropriate. Specifically, such materials include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, and alloys containing these in appropriate combinations. Other examples of such materials include indium tin oxide (In-Sn oxide, also called ITO), In-Si-Sn oxide (also called ITSO), indium zinc oxide (In-Zn oxide), and In-W-Zn oxide. Furthermore, other examples of such materials include aluminum alloys such as aluminum, nickel, and lanthanum alloys (Al-Ni-La), as well as silver alloys of silver and magnesium, and silver alloys of silver, palladium, and copper (Ag-Pd-Cu, also written as APC). Other materials include elements belonging to Group 1 or Group 2 of the periodic table not exemplified above (e.g., lithium, cesium, calcium, strontium), rare earth metals such as europium and ytterbium, alloys containing these in appropriate combinations, graphene, and the like.

[0400] It is preferable that the light-emitting element has a microcavity structure. Therefore, it is preferable that one of the pair of electrodes in the light-emitting element is a semitransmitting / semi-reflective electrode that transmits and reflects visible light, and the other is a reflective electrode that reflects visible light. By having a microcavity structure in the light-emitting element, the light emitted from the light-emitting layer can be resonated between the two electrodes, thereby strengthening the light emitted from the light-emitting element.

[0401] The light transmittance of the transparent electrode shall be 40% or more. For example, it is preferable to use an electrode with a transmittance of 40% or more for visible light (light with a wavelength of 400 nm or more and less than 750 nm) for the transparent electrode of the light-emitting element. The visible light reflectance of the semi-transparent and semi-reflective electrodes shall be 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode shall be 40% or more and 100% or less, preferably 70% or more and 100% or less. Furthermore, the electrical resistivity of these electrodes shall be 1 × 10⁻⁶ −２ A value of Ωcm or less is preferable.

[0402] The EL layers 113R, 113G, and 113B are each provided in an island-like manner. In Figure 27A, the edges of adjacent EL layers 113R and 113G overlap, the edges of adjacent EL layers 113G and 113B overlap, and the edges of adjacent EL layers 113R and 113B overlap. When forming island-like EL layers using a fine metal mask, the edges of adjacent EL layers may overlap as shown in Figure 27A, but this is not limited to this. In other words, adjacent EL layers may not overlap and may be separated from each other. Furthermore, in a display device, there may be both areas where adjacent EL layers overlap and areas where adjacent EL layers do not overlap and are separated.

[0403] Each of the EL layers 113R, 113G, and 113B has at least one light-emitting layer. The light-emitting layer has one or more types of light-emitting materials. As the light-emitting material, a material that exhibits a light-emitting color such as blue, purple, blue-violet, green, yellow-green, yellow, orange, or red can be used as appropriate. In addition, a material that emits near-infrared light can also be used as the light-emitting material.

[0404] Examples of luminescent materials include fluorescent materials, phosphorescent materials, thermally activated delayed fluorescence (TADF) materials, and inorganic compounds (such as quantum dot materials).

[0405] In Figure 27A, when a tandem light-emitting element is used, it is preferable that the EL layer 113R has a structure having multiple light-emitting units that emit red light, the EL layer 113G has a structure having multiple light-emitting units that emit green light, and the EL layer 113B has a structure having multiple light-emitting units that emit blue light.

[0406] A protective layer 131 is provided on the light-emitting elements 61R, 61G, and 61B. The protective layer 131 and the substrate 52 are bonded via an adhesive layer 142. A light-shielding layer 117 is provided on the substrate 52. For sealing the light-emitting elements, for example, a solid sealing structure or a hollow sealing structure can be applied. In Figure 27A, the space between the substrate 52 and the substrate 51 is filled with the adhesive layer 142, and a solid sealing structure is applied. Alternatively, the space may be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure may be applied. In this case, the adhesive layer 142 may be provided in a frame shape so as not to overlap with the light-emitting elements. Furthermore, the space may be filled with a resin different from the adhesive layer 142 provided in a frame shape.

[0407] [Configuration Example 4-2] Figure 27B is a cross-sectional view showing a configuration example of the display unit 62 that differs from that shown in Figure 27A. The display unit 62 shown in Figure 27B differs from the display unit 62 shown in Figure 27A in that each color pixel uses a light-emitting element having a common EL layer 113 and a coloring layer (color filter, etc.). The configuration shown in Figure 27B can be combined with the laminated structure from the substrate 51 to the insulating layer 235 of the circuit unit 64 and the display unit 62 shown in Figure 27A. In the following description of the display device, parts that are the same as those described earlier may be omitted.

[0408] The display unit 62 shown in Figure 27B is provided with, in addition to the light-emitting elements 61R, 61G, and 61B, a colored layer 132R that transmits red light, a colored layer 132G that transmits green light, and a colored layer 132B that transmits blue light.

[0409] The light-emitting element 61R shown in Figure 27B has a pixel electrode 111R, an EL layer 113 on the pixel electrode 111R, and a common electrode 115 on the EL layer 113. The light emitted from the light-emitting element 61R shown in Figure 27B is extracted as red light to the outside of the display device 70 via the colored layer 132R.

[0410] The light-emitting element 61G shown in Figure 27B has a pixel electrode 111G, an EL layer 113 on the pixel electrode 111G, and a common electrode 115 on the EL layer 113. The light emitted from the light-emitting element 61G shown in Figure 27B is extracted as green light to the outside of the display device 70 via the colored layer 132G.

[0411] The light-emitting element 61B shown in Figure 27B has a pixel electrode 111B, an EL layer 113 on the pixel electrode 111B, and a common electrode 115 on the EL layer 113. The light emitted from the light-emitting element 61B shown in Figure 27B is extracted as blue light to the outside of the display device 70 via the colored layer 132B.

[0412] The light-emitting elements 61R, 61G, and 61B shown in Figure 27B each share an EL layer 113 and a common electrode 115. Providing a common EL layer 113 for each color pixel reduces the number of manufacturing steps compared to providing a different EL layer for each color pixel.

[0413] For example, the light-emitting elements 61R, 61G, and 61B shown in Figure 27B emit white light. The white light emitted by the light-emitting element 61R passes through the colored layer 132R, the white light emitted by the light-emitting element 61G passes through the colored layer 132G, and the white light emitted by the light-emitting element 61B passes through the colored layer 132B, thereby obtaining light of the desired color.

[0414] A light-emitting element that emits white light preferably includes two or more light-emitting layers. When obtaining white light emission using two light-emitting layers, the light-emitting layers can be selected such that their emission colors are complementary. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary, a configuration can be obtained in which the entire light-emitting element emits white light. Furthermore, when obtaining white light emission using three or more light-emitting layers, the emission colors of the three or more light-emitting layers combine to create a configuration in which the entire light-emitting element emits white light.

[0415] The EL layer 113 preferably has, for example, an emissive layer having a light-emitting material that emits blue light, and an emissive layer having a light-emitting material that emits visible light with a longer wavelength than blue. The EL layer 113 preferably has, for example, an emissive layer that emits yellow light and an emissive layer that emits blue light. Alternatively, the EL layer 113 preferably has, for example, an emissive layer that emits red light, an emissive layer that emits green light, and an emissive layer that emits blue light.

[0416] For light-emitting elements that emit white light, a tandem structure is preferable. Specifically, a two-stage tandem structure having a light-emitting unit that emits yellow light and a light-emitting unit that emits blue light, a two-stage tandem structure having a light-emitting unit that emits red and green light and a light-emitting unit that emits blue light, a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light and a light-emitting unit that emits blue light in that order, or a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light and red light and a light-emitting unit that emits blue light in that order, etc. can be applied. For example, the number of layers and color order of the light-emitting unit can be, from the anode side, a two-layer structure of blue (B) and yellow (Y), a two-layer structure of B and light-emitting unit X, a three-layer structure of B, Y, B, or a three-layer structure of B, X, B. The number of layers and color order of the light-emitting layers in light-emitting unit X can be, from the anode side, a two-layer structure of red (R) and Y, a two-layer structure of R and green (G), a two-layer structure of G, R, G, a three-layer structure of G, R, G, or a three-layer structure of R, G, R. In addition, other layers may be provided between the two light-emitting layers.

[0417] Furthermore, by applying a microcavity structure, a light-emitting element that normally emits white light may also emit light of specific wavelengths such as red, green, or blue, with the intensity of these wavelengths being amplified.

[0418] Alternatively, for example, the light-emitting elements 61R, 61G, and 61B shown in Figure 27B emit blue light. In this case, the EL layer 113 has one or more light-emitting layers that emit blue light. In the pixel 17 that emits blue light, the blue light emitted by the light-emitting element 61B can be extracted. In addition, in the pixel 17 that emits red light and the pixel 17 that emits green light, by providing a color conversion layer between the light-emitting element 61R or light-emitting element 61G and the substrate 52, the blue light emitted by the light-emitting element 61R or light-emitting element 61G can be converted into longer wavelength light, and red or green light can be extracted. The color conversion layer can be described above. Specifically, the various quantum dot materials described above can be used for the color conversion layer. Furthermore, it is preferable to provide a coloring layer 132R between the color conversion layer and the substrate 52 on the light-emitting element 61R, and a coloring layer 132G between the color conversion layer and the substrate 52 on the light-emitting element 61G. Some of the light emitted by a light-emitting element may pass through without being converted by the color conversion layer. By extracting the light that has passed through the color conversion layer via a colored layer, the color of light other than the desired color can be absorbed by the colored layer, thereby increasing the color purity of the light exhibited by the pixel.

[0419] [Configuration Example 4-3] Figure 28 shows an example in which a layer 31 is provided between the substrate 51 and layer 11 shown in Figure 27A. The layer 31 is provided with transistors 307D, 307R, 307G, 307B, etc. Transistor 307D is provided in the circuit section 64. Transistors 307R, 307G, and 307B are provided in the display section 62. In the following description, transistors 307D, 307R, 307G, and 307B may be simply referred to as transistor 307.

[0420] The transistor 307 includes a conductive layer 303 on the substrate 51, an insulating layer 305 on the conductive layer 303 and on the substrate 51, a semiconductor layer 308 on the insulating layer 305, an insulating layer 306 on the semiconductor layer 308 and on the insulating layer 305, and a conductive layer 304 on the insulating layer 306. The semiconductor layer 308 has a region 309p that does not overlap with the conductive layer 304. The region 309p contains impurities.

[0421] The conductive layer 304 functions as the first gate electrode of the transistor 307. The conductive layer 303 functions as the second gate electrode of the transistor 307. The insulating layer 306 functions as the first gate insulating layer of the transistor 307. The insulating layer 305 functions as the second gate insulating layer of the transistor 307. Region 309p functions as the source region and drain region of the transistor 307.

[0422] Transistor 307 can be a transistor with a different polarity from transistors 107 and 207. For example, if transistors 107 and 207 are n-channel transistors, transistor 307 can be a p-channel transistor. By making the polarity of transistor 307 different from that of transistors 107 and 207, the design freedom of the display unit 62 and the circuit unit 64 can be increased compared to the case where the polarity of all transistors in the display device 70 is the same. Even if the display device 70 has a layer 31, the display device 70 does not have to have at least one of transistors 307D, 307R, 307G, and 307B. For example, the display device 70 may have transistors 307R, 307G, and 307B, but not transistor 307D.

[0423] For the semiconductor layer 308, for example, silicon can be used. Therefore, the transistor 307 can be a Si transistor. Specific examples of silicon include single-crystalline silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon as described above. When the transistor 307 is a p-channel transistor and silicon is used as the semiconductor layer 308, as elements included in the impurities in the region 309p, for example, one or more of boron, aluminum, and gallium can be used.

[0424] An insulating layer 391 is provided on the conductive layer 304 and on the insulating layer 306. For the insulating layer 391, materials that can be used for the insulating layer 191 and the insulating layer 291 can be used.

[0425] The insulating layer 391 and the insulating layer 306 have an opening 347 that reaches the region 309p. A conductive layer 312 is provided so as to cover the opening 347. The conductive layer 312 is in contact with the region 309p at the opening 347. The conductive layer 312 functions as the source electrode and the drain electrode of the transistor 307.

[0426] An insulating layer 331 is provided on the conductive layer 312 and on the insulating layer 391. An insulating layer 332 is provided on the insulating layer 331. A transistor 107 is provided on the insulating layer 332.

[0427] The insulating layer 331 preferably functions as a planarization layer in the same manner as the insulating layer 231. For the insulating layer 331, materials that can be used for the insulating layer 231 can be used. The insulating layer 332 preferably functions as an etching protection layer and a barrier insulating layer in the same manner as the insulating layer 232. For the insulating layer 332, materials that can be used for the insulating layer 232 can be used.

[0428] [Configuration Example 4-4] FIG. 29A is a cross-sectional view showing a configuration example of the display device 70, and is an example of a display device to which an MML (Metal Maskless) structure is applied. That is, the display device 70 shown in FIG. 29A has a light-emitting element manufactured without using a fine metal mask.

[0429] In a display device using an MML structure, the island-shaped light-emitting layers in the light-emitting elements are formed by depositing a light-emitting layer onto one surface and then processing it using lithography. Therefore, it is possible to realize high-definition display devices or display devices with high aperture ratios, which have been difficult to achieve until now. Furthermore, since the light-emitting layers can be made separately for each color, it is possible to realize a display device that is extremely vivid, has high contrast, and displays high quality. For example, if the display device is composed of three types of light-emitting elements, such as a blue light-emitting element, a green light-emitting element, and a red light-emitting element, three types of island-shaped light-emitting layers can be formed by repeating the deposition of the light-emitting layer and processing by lithography three times.

[0430] Since MML (Multilayer Molded) devices can be fabricated without using a metal mask, they can exceed the resolution limits imposed by the precision required for metal mask alignment. Furthermore, when fabricating devices without a metal mask, the equipment and cleaning processes associated with metal mask fabrication are eliminated. In addition, the lithography process can use equipment common to or similar to that used for transistor fabrication, eliminating the need to introduce special equipment for fabricating MML devices. Thus, MML structures can be manufactured at a low cost, making them suitable for mass production of devices.

[0431] In a display device to which an MML structure is applied, there is no need to artificially increase the resolution by applying a special pixel arrangement such as a pentile arrangement. Therefore, a display device with high resolution (for example, 500 ppi or more, 1000 ppi or more, 2000 ppi or more, 3000 ppi or more, or 5000 ppi or more) can be realized using a so-called stripe arrangement in which R, G, and B pixels are each arranged in one direction.

[0432] By providing a sacrificial layer on the light-emitting layer, damage to the light-emitting layer during the manufacturing process of the display device can be reduced, thereby improving the reliability of the light-emitting element.

[0433] By employing a film deposition process using an area mask and a processing process using a resist mask, light-emitting elements can be fabricated using a relatively simple process.

[0434] Note that the laminated structure from substrate 51 to insulating layer 235, and the laminated structure from protective layer 131 to substrate 52 are the same as those of the display device 70 shown in Figure 27A, so their explanation will be omitted.

[0435] In Figure 29A, light-emitting elements 61R, 61G, and 61B are provided on the insulating layer 235. For details on the laminated structure from the substrate 51 to the insulating layer 235, please refer to the explanation for Figure 27A.

[0436] The light-emitting element 61R includes a conductive layer 124R on an insulating layer 235, a conductive layer 126R on the conductive layer 124R, a layer 133R on the conductive layer 126R, a common layer 114 on the layer 133R, and a common electrode 115 on the common layer 114. The light-emitting element 61R shown in Figure 29A emits red light (R). Layer 133R has a light-emitting layer that emits red light. In the light-emitting element 61R, layer 133R and the common layer 114 can be collectively called the EL layer. In addition, one or both of the conductive layer 124R and the conductive layer 126R can be called the pixel electrode.

[0437] The light-emitting element 61G includes a conductive layer 124G on an insulating layer 235, a conductive layer 126G on the conductive layer 124G, a layer 133G on the conductive layer 126G, a common layer 114 on the layer 133G, and a common electrode 115 on the common layer 114. The light-emitting element 61G shown in Figure 29A emits green light (G). Layer 133G has a light-emitting layer that emits green light. In the light-emitting element 61G, layer 133G and the common layer 114 can be collectively called the EL layer. In addition, one or both of the conductive layer 124G and the conductive layer 126G can be called the pixel electrode.

[0438] The light-emitting element 61B includes a conductive layer 124B on an insulating layer 235, a conductive layer 126B on the conductive layer 124B, a layer 133B on the conductive layer 126B, a common layer 114 on the layer 133B, and a common electrode 115 on the common layer 114. The light-emitting element 61B shown in Figure 29A emits blue light (B). Layer 133B has a light-emitting layer that emits blue light. In the light-emitting element 61B, layer 133B and the common layer 114 can be collectively called the EL layer. In addition, one or both of the conductive layer 124B and the conductive layer 126B can be called the pixel electrode.

[0439] In this specification, among the EL layers of a light-emitting element, layers provided in an island-like manner for each light-emitting element are referred to as layer 133B, layer 133G, or layer 133R, and a layer shared by multiple light-emitting elements is referred to as the common layer 114. In this specification, the common layer 114 may be omitted, and layers 133R, 133G, and 133B may be referred to as island-like EL layers, island-shaped EL layers, etc. Furthermore, light-emitting elements manufactured without using a metal mask may not have a common layer, and all layers constituting the EL layer may be formed in an island-like manner.

[0440] Layers 133R, 133G, and 133B are separated from each other. By providing the EL layer in an island-like configuration for each light-emitting element, leakage current between adjacent light-emitting elements can be suppressed. This prevents unintended light emission caused by crosstalk, enabling the realization of a display device with extremely high contrast.

[0441] Note that in Figure 29A, layers 133R, 133G, and 133B are all shown to be the same thickness, but this is not the only option. The thicknesses of layers 133R, 133G, and 133B may be different.

[0442] The conductive layer 124R is connected to the conductive layer 212 of transistor 207R through an opening provided in the insulating layer 235. Similarly, the conductive layer 124G is connected to the conductive layer 212 of transistor 207G, and the conductive layer 124B is connected to the conductive layer 212 of transistor 207B.

[0443] The conductive layer 124R, conductive layer 124G, and conductive layer 124B are formed to cover the openings provided in the insulating layer 235. Layer 128 is embedded in the recesses of conductive layer 124R, conductive layer 124G, and conductive layer 124B, respectively.

[0444] Layer 128 has the function of flattening the recesses of conductive layers 124R, 124G, and 124B. Conductive layer 126R is provided on conductive layer 124R and on layer 128, connected to conductive layer 124R. Similarly, conductive layer 126G is provided on conductive layer 124G and on layer 128, connected to conductive layer 124G. Furthermore, conductive layer 126B is provided on conductive layer 124B and on layer 128, connected to conductive layer 124B. As a result, regions overlapping with the recesses of conductive layers 124R, 124G, and 124B can also be used as light-emitting regions, thereby increasing the aperture ratio of the pixels. It is preferable to use conductive layers that function as reflective electrodes for conductive layer 124R and conductive layer 126R.

[0445] Layer 128 may be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be used for layer 128 as appropriate. In particular, it is preferable that layer 128 be formed using an insulating material, and especially preferable that it be formed using an organic insulating material. For example, an organic insulating material that can be used for the insulating layer 237 described above can be applied to layer 128.

[0446] Figure 29A shows an example where the upper surface of layer 128 has a flat portion, but the shape of layer 128 is not particularly limited. The upper surface of layer 128 can have at least one of a convex curved surface, a concave curved surface, and a flat surface.

[0447] The height of the top surface of layer 128 and the height of the top surface of conductive layer 124R may be the same, approximately the same, or different from each other. For example, the height of the top surface of layer 128 may be lower or higher than the height of the top surface of conductive layer 124R.

[0448] The end of the conductive layer 126R may be aligned with the end of the conductive layer 124R, or it may cover the side surface of the end of the conductive layer 124R. Preferably, the ends of the conductive layer 124R and the conductive layer 126R have a tapered shape. Specifically, it is preferable that the ends of the conductive layer 124R and the conductive layer 126R have a tapered shape with a taper angle greater than 0 degrees and less than 90 degrees. When the end of the pixel electrode has a tapered shape, the layer 133R provided along the side surface of the pixel electrode has an inclined portion. By making the side surface of the pixel electrode tapered, the coverage of the EL layer provided along the side surface of the pixel electrode can be improved.

[0449] Since conductive layers 124G and 126G, and conductive layers 124B and 126B are the same as conductive layers 124R and 126R, a detailed explanation is omitted.

[0450] The top and sides of the conductive layer 126R are covered by layer 133R. Similarly, the top and sides of the conductive layer 126G are covered by layer 133G, and the top and sides of the conductive layer 126B are covered by layer 133B. Therefore, the entire region where the conductive layer 126R is provided can be used as the light-emitting region of the light-emitting element 61R. Similarly, the entire region where the conductive layer 126G is provided can be used as the light-emitting region of the light-emitting element 61G. Furthermore, the entire region where the conductive layer 126B is provided can be used as the light-emitting region of the light-emitting element 61B. As a result, the aperture ratio of the pixels can be increased.

[0451] The upper surfaces and sides of layers 133R, 133G, and 133B are covered by insulating layers 125 and 127, respectively. A common layer 114 is provided on layer 133R, layer 133G, layer 133B, insulating layer 125, and insulating layer 127, and a common electrode 115 is provided on the common layer 114. The common layer 114 and the common electrode 115 are each a continuous film provided in common to multiple light-emitting elements.

[0452] In Figure 29A, the insulating layer 237 shown in Figure 27A, etc., is not provided between the conductive layer 126R and layer 133R. Similarly, the insulating layer 237 is not provided between the conductive layer 126G and layer 133G, and between the conductive layer 126B and layer 133B. In other words, the display device 70 shown in Figure 29A does not have an insulating layer (also called a partition, bank, spacer, etc.) that is in contact with the pixel electrodes and covers the upper edge of the pixel electrodes. Therefore, the spacing between adjacent light-emitting elements can be made extremely narrow. Consequently, a high-definition or high-resolution display device can be made. In addition, a mask for forming the insulating layer is not required, and the manufacturing cost of the display device can be reduced.

[0453] As described above, layers 133R, 133G, and 133B each have an emissive layer. Preferably, layers 133R, 133G, and 133B each have one or both of a carrier transport layer (electron transport layer or hole transport layer) and a carrier block layer (hole block layer or electron block layer) on the emissive layer. Since the surfaces of layers 133R, 133G, and 133B are exposed during the manufacturing process of the display device, providing one or both of the carrier transport layer and the carrier block layer on the emissive layer suppresses exposure of the emissive layer to the outermost surface and reduces damage to the emissive layer. This improves the reliability of the light-emitting element.

[0454] The common layer 114 may have, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 114 may have an electron transport layer and an electron injection layer stacked together, or a hole transport layer and a hole injection layer stacked together. The common layer 114 is shared by the light-emitting element 61R, the light-emitting element 61G, and the light-emitting element 61B.

[0455] Each side of layer 133R, layer 133G, and layer 133B is covered by the insulating layer 125. The insulating layer 127 covers each side of layer 133R, layer 133G, and layer 133B via the insulating layer 125.

[0456] The sides (and even a portion of the top surface) of layers 133R, 133G, and 133B are covered by at least one of the insulating layers 125 and 127, thereby suppressing contact between the common layer 114 (or common electrode 115) and the pixel electrode, layers 133R, 133G, and 133B, and preventing short circuits in the light-emitting element. This improves the reliability of the light-emitting element.

[0457] Preferably, the insulating layer 125 has regions that are in contact with the respective sides of layers 133R, 133G, and 133B. By configuring the insulating layer 125 to be in contact with layers 133R, 133G, and 133B, peeling of the layers 133R, 133G, and 133B can be prevented, and the reliability of the light-emitting element can be improved.

[0458] The insulating layer 127 is provided on the insulating layer 125 so as to fill any recesses in the insulating layer 125. Preferably, the insulating layer 127 covers at least a portion of the side surface of the insulating layer 125.

[0459] By providing insulating layers 125 and 127, the gaps between adjacent island-shaped layers can be filled, thereby reducing the large height differences and irregularities on the surface of layers formed on the island-shaped layers (e.g., carrier injection layers and common electrodes), making it flatter. Consequently, the coverage of the carrier injection layers and common electrodes can be improved.

[0460] As described above, the common layer 114 and the common electrode 115 are provided on layer 133R, layer 133G, layer 133B, insulating layer 125, and insulating layer 127. Before the insulating layers 125 and 127 are provided, a step difference occurs due to the region where the pixel electrode and island-shaped EL layer are provided and the region where the pixel electrode and island-shaped EL layer are not provided (the region between light-emitting elements). In one embodiment of the present invention, the presence of the insulating layers 125 and 127 can flatten this step difference and improve the coverage of the common layer 114 and the common electrode 115. Therefore, connection failures due to step breaks can be suppressed. In addition, it is possible to suppress the local thinning of the common electrode 115 due to the step difference, which would increase its electrical resistance.

[0461] The upper surface of the insulating layer 127 is preferably flatter. The upper surface of the insulating layer 127 may have at least one of a flat surface, a convex surface, and a concave surface. For example, the upper surface of the insulating layer 127 is preferably a convex surface with a large radius of curvature.

[0462] [Configuration Example 4-5] Figure 29B is a cross-sectional view showing a configuration example of the display unit 62 different from that shown in Figure 29A. The display unit 62 shown in Figure 29B differs from the display unit 62 shown in Figure 29A mainly in that each pixel of each color is provided with a coloring layer (color filter, etc.). The configuration shown in Figure 29B can be combined with the laminated structure from the substrate 51 to the insulating layer 235 of the circuit unit 64 and the display unit 62 shown in Figure 29A. Note that the explanation will mainly focus on configurations different from the display device 70 shown in Figure 27B, and explanations of similar configurations will be omitted as appropriate.

[0463] Each of the light-emitting elements 61R, 61G, and 61B has a layer 133. These three layers 133 are formed using the same material and the same process. Furthermore, these three layers 133 are spaced apart from each other. By providing the EL layer in an island-like configuration for each light-emitting element, leakage current between adjacent light-emitting elements can be suppressed. This prevents unintended light emission caused by crosstalk, enabling the realization of a display device with extremely high contrast.

[0464] For example, the light-emitting elements 61R, 61G, and 61B shown in Figure 29B emit white light. Alternatively, for example, the light-emitting elements 61R, 61G, and 61B shown in Figure 29B emit blue light. When the light-emitting elements 61R, 61G, and 61B emit blue light, layer 133 has one or more light-emitting layers that emit blue light.

[0465] <Example of Pixel Configuration> Below, an example of the configuration of pixel 17 will be explained using the circuit diagrams shown in Figures 30A to 32B. Here, the polarity of the transistors shown in Figures 30A to 32B is just an example and may be different from those shown in Figures 30A to 32B. For example, the transistor that is a p-channel type transistor in Figures 30A to 32B may be an n-channel type transistor. Also, the transistor that is an n-channel type transistor in Figures 30A to 32B may be a p-channel type transistor.

[0466] The pixel 17 shown in Figure 30A comprises a pixel circuit 15A and a light-emitting element 61. The pixel circuit 15A comprises a transistor Tr200, a transistor Tr201, a capacitive element C200, and a capacitive element C201. The pixel circuit 15A is a 2Tr2C type pixel circuit having two transistors and two capacitive elements. Note that the pixel circuit 15A does not necessarily have to have the capacitive element C201. In this case, the pixel circuit 15A can be a 2Tr1C type pixel circuit.

[0467] One electrode of the light-emitting element 61 is connected to one of the source and drain of transistor Tr200, one electrode of capacitive element C200, and one electrode of capacitive element C201. The gate of transistor Tr200 is connected to one of the source and drain of transistor Tr201, and the other electrode of capacitive element C200.

[0468] The other electrode of the light-emitting element 61 and the other electrode of the capacitive element C201 are connected to the wiring 28. The source and the other drain of transistor Tr200 are connected to the wiring 27. The source and the other drain of transistor Tr201 are connected to the wiring 25. The gate of transistor Tr201 is connected to the wiring 23.

[0469] Wires 27 and 28 are wires that provide a potential for supplying current to the light-emitting element 61. For example, a potential VDD is supplied to wire 27 and a potential VSS is supplied to wire 28. Wires 27 and 28 are also called power lines.

[0470] In the pixel 17 shown in Figure 30A, one electrode of the light-emitting element 61 is the anode and the other electrode of the light-emitting element 61 is the cathode, but the anode and cathode of the light-emitting element 61 may be swapped. Also, the potential VSS may be supplied to the wiring 27 and the potential VDD may be supplied to the wiring 28. The same applies to the pixels 17 shown later.

[0471] Transistor Tr200 functions as a drive transistor that controls the amount of current flowing to the light-emitting element 61. Capacitive element C200 has the function of maintaining the gate potential of transistor Tr200. The intensity of the light emitted by the light-emitting element 61 is controlled according to the gate potential of transistor Tr200.

[0472] Transistor Tr201 has the function of controlling the conduction or non-conduction state between the wiring 25 and the gate of transistor Tr200 based on the potential of the wiring 23. Transistor Tr201 also functions as a selection transistor for controlling the selected state of pixel 17.

[0473] In the pixel 17 shown below, the transistor that functions as a drive transistor is designated as transistor Tr200. Furthermore, the transistor that functions as a selector transistor, with its source or drain connected to the wiring 25, is designated as transistor Tr201. Additionally, the capacitive element that has the function of maintaining the gate potential of transistor Tr200 is designated as capacitive element C200.

[0474] In the display device 70A shown in Figures 5A to 8, transistor 10b corresponds to transistor Tr201. In the display device 70B shown in Figures 9 to 10B, it is preferable to use transistor 10d as transistor Tr200 and transistor 20d as transistor Tr201. When transistor 20d is used as transistor Tr201, the capacitive element 27b shown in Figure 9 corresponds to the capacitive element C200.

[0475] The pixel 17 shown in Figure 30B comprises a pixel circuit 15B and a light-emitting element 61. The pixel circuit 15B comprises a transistor Tr200, a transistor Tr201, a transistor Tr202, and a capacitive element C200. In other words, the pixel circuit 15B is a configuration in which the transistor Tr202 is added to the pixel circuit 15A and the capacitive element C201 is omitted from the pixel circuit 15A. The pixel circuit 15B is a 3Tr1C type pixel circuit having three transistors and one capacitive element.

[0476] In the pixel 17 having the pixel circuit 15B, the gate of transistor Tr201 is connected to wiring 23_1. One of the source and drain of transistor Tr202 is connected to one electrode of the light-emitting element 61, one of the source and drain of transistor Tr200, and one electrode of the capacitive element C200. The other of the source and drain of transistor Tr202 is connected to wiring 29. The gate of transistor Tr202 is connected to wiring 23_2.

[0477] The wiring 29 is supplied with an initialization potential for initializing the potential of one electrode of the light-emitting element 61. The wiring 29 is also called the initialization line.

[0478] Transistor Tr201 has the function of controlling the conduction or non-conduction state between wiring 25 and the gate of transistor Tr200 based on the potential of wiring 23_1. Transistor Tr202 has the function of controlling the conduction or non-conduction state between wiring 29 and one electrode of the light-emitting element 61 based on the potential of wiring 23_2. In the pixel 17 shown below, the transistor that has the function of controlling the conduction or non-conduction state between wiring 29 and one electrode of the light-emitting element 61 is also referred to as transistor Tr202.

[0479] In the display device 70B shown in Figures 9 to 10B, it is preferable to use transistor 10d as transistor Tr202.

[0480] The following describes an example of a different configuration of pixel 17 from that shown in Figure 30B. Note that we will mainly describe the configuration that differs from that of pixel 17 shown in Figure 30B, and will omit explanations of similar configurations as appropriate.

[0481] The pixel 17 shown in Figure 30C has a pixel circuit 15C and a light-emitting element 61. The pixel circuit 15C has transistors Tr200, Tr201, Tr202, and Tr211, as well as capacitive elements C200 and C211. The pixel circuit 15C is a 4Tr2C type pixel circuit having four transistors and two capacitive elements. Note that the pixel circuit 15C does not have to have the capacitive element C211. In this case, the pixel circuit 15A can be a 4Tr1C type pixel circuit.

[0482] In a pixel 17 having a pixel circuit 15C, one electrode of the light-emitting element 61 is connected to one of the source and drain of transistor Tr200, one of the source and drain of transistor Tr202, one electrode of capacitive element C200, and one electrode of capacitive element C211. The other of the source and drain of transistor Tr200 is connected to one of the source and drain of transistor Tr211.

[0483] The source and drain of transistor Tr211, as well as the other electrode of capacitive element C211, are connected to wiring 27. The gate of transistor Tr211 is connected to wiring 23_3.

[0484] In the display device 70B shown in Figures 9 to 10B, it is preferable to use transistor 10d as transistor Tr211.

[0485] The pixel 17 shown in Figure 30D comprises a pixel circuit 15D and a light-emitting element 61. The pixel circuit 15D comprises transistors Tr200, Tr201, Tr202, Tr221, and a capacitive element C200. The pixel circuit 15D is a 4Tr1C type pixel circuit having four transistors and one capacitive element.

[0486] In a pixel 17 having a pixel circuit 15D, the gate electrode of transistor Tr200 is connected to one of the source and drain electrodes of transistor Tr201, one of the source and drain electrodes of transistor Tr221, and the other electrode of capacitive element C200. The other of the source and drain electrodes of transistor Tr221 is connected to wiring 37. The gate of transistor Tr221 is connected to wiring 23_4.

[0487] A reference potential is supplied to wiring 37. Wiring 37 is also called a reference potential line.

[0488] The transistor Tr221 in the pixel circuit 15D has the function of controlling the conduction or non-conduction state between the wiring 37 and the gate of transistor Tr200 based on the potential of the wiring 23_4.

[0489] In the display device 70B shown in Figures 9 to 10B, it is preferable to use transistor 20d as transistor Tr221.

[0490] The pixel 17 shown in Figure 31A has a pixel circuit 15E and a light-emitting element 61. The pixel circuit 15E has transistors Tr200, Tr201, Tr202, Tr231, Tr232, Tr233 and a capacitive element C200. The pixel circuit 15E is a 6Tr1C type pixel circuit having six transistors and one capacitive element.

[0491] In a pixel 17 having a pixel circuit 15E, one electrode of the light-emitting element 61 is connected to one of the source and drain of transistor Tr202, one of the source and drain of transistor Tr233, and one electrode of the capacitive element C200. The other source and drain of transistor Tr233 is connected to one of the source and drain of transistor Tr200, and one of the source and drain of transistor Tr201. The other source and drain of transistor Tr200 is connected to one of the source and drain of transistor Tr231, and one of the source and drain of transistor Tr232. The gate of transistor Tr200 is connected to the other source and drain of transistor Tr232, and the other electrode of the capacitive element C200.

[0492] The source and drain of transistor Tr231 are connected to wire 27. The gates of transistor Tr202 and Tr232 are connected to wire 23_2. The gate of transistor Tr231 is connected to wire 23_5. The gate of transistor Tr233 is connected to wire 23_6.

[0493] In the display device 70B shown in Figures 9 to 10B, it is preferable to use transistor 10d as transistors Tr200 to Tr202, Tr231, and Tr233, and transistor 20d as transistor Tr232. When transistor 20d is used as transistor Tr232, the capacitive element 27b shown in Figure 9 corresponds to the capacitive element C200.

[0494] The pixel 17 shown in Figure 31B has a pixel circuit 15F and a light-emitting element 61. The pixel circuit 15F has transistors Tr200, Tr201, Tr203, Tr241, Tr242, Tr243 and a capacitive element C200. The pixel circuit 15F is a 6Tr1C type pixel circuit having six transistors and one capacitive element.

[0495] In a pixel 17 having a pixel circuit 15F, one electrode of the light-emitting element 61 is connected to one of the source and drain of transistor Tr241, and to one of the source and drain of transistor Tr243. The other source and drain of transistor Tr241 is connected to one of the source and drain of transistor Tr200, and to one of the source and drain of transistor Tr242. The gate of transistor Tr200 is connected to the other source and drain of transistor Tr242, and to one electrode of capacitive element C200. The other electrode of capacitive element C200 is connected to one of the source and drain of transistor Tr201, and to one of the source and drain of transistor Tr203.

[0496] The source and drain of transistor Tr203, and the other source and drain of transistor Tr243, are connected to wiring 26. The gates of transistor Tr203 and transistor Tr241 are connected to wiring 23_7. The gate of transistor Tr242 is connected to wiring 23_8. The gate of transistor Tr243 is connected to wiring 23_9.

[0497] Wiring 26 functions as a power line. For example, if the potential VDD is supplied to wiring 27 and the potential VSS is supplied to wiring 28, then the potential VSS can be supplied to wiring 26.

[0498] Transistor Tr203 has the function of controlling the conduction or non-conduction state between wiring 26 and the other electrode of capacitive element C200 based on the potential of wiring 23_7. Transistor Tr241 has the function of controlling the conduction or non-conduction state between one of the source and drain of transistor Tr200 and one electrode of the light-emitting element 61 based on the potential of wiring 23_7. Transistor Tr242 has the function of controlling the conduction or non-conduction state between the gate of transistor Tr200 and one of the source and drain of transistor Tr200 based on the potential of wiring 23_8. Transistor Tr243 has the function of controlling the conduction or non-conduction state between wiring 26 and one electrode of the light-emitting element 61 based on the potential of wiring 23_9. In the pixel 17 described below, the transistor that has the function of controlling the conduction or non-conduction state between wiring 26 and the other electrode of capacitive element C200 is referred to as transistor Tr203.

[0499] During the operation of the pixel circuit 15F, when one of transistors Tr201 and Tr203 is conducting, the other transistor is not conducting. Therefore, the other electrode of the capacitive element C200 does not become floating. Consequently, the off-currents of transistors Tr201 and Tr203 do not need to be small. Based on the above, in the display device 70B shown in Figures 9 to 10B, it is preferable to use transistor 10d as transistors Tr200, Tr201, Tr203, Tr241, and Tr243, and transistor 20d as transistor Tr242. When transistor 20d is used as transistor Tr242, the capacitive element 27b shown in Figure 9 corresponds to the capacitive element C200.

[0500] The pixel 17 shown in Figure 32A has a pixel circuit 15G and a light-emitting element 61. The pixel circuit 15G has transistors Tr200, Tr201, Tr202, Tr251, Tr252, Tr253, Tr254, and capacitive elements C200, C251, and C252. The pixel circuit 15G is a 7Tr3C type pixel circuit having seven transistors and three capacitive elements. Note that the pixel circuit 15G does not have to have capacitive elements C251 and C252. If the pixel circuit 15G does not have both capacitive elements C251 and C252, the pixel circuit 15G can be a 7Tr1C type pixel circuit.

[0501] In a pixel 17 having a pixel circuit 15G, one electrode of the light-emitting element 61 is connected to one of the source and drain of transistor Tr202, and one of the source and drain of transistor Tr253. The other source and drain of transistor Tr253 is connected to one of the source and drain of transistor Tr200, one of the source and drain of transistor Tr251, and one electrode of capacitive element C251. The other source and drain of transistor Tr200 is connected to one of the source and drain of transistor Tr201, and one of the source and drain of transistor Tr252. The gate of transistor Tr200 is connected to the other source and drain of transistor Tr251, one of the source and drain of transistor Tr254, and one electrode of capacitive element C200.

[0502] The source and drain of transistor Tr201, and one electrode of capacitive element C252, are connected to wiring 25. The source and drain of transistor Tr252, the other electrode of capacitive element C200, the other electrode of capacitive element C251, and the other electrode of capacitive element C252 are connected to wiring 27. The source and drain of transistor Tr202, and the source and drain of transistor Tr254, are connected to wiring 29. The gate of transistor Tr251 is connected to wiring 23_10. The gates of transistor Tr252 and transistor Tr253 are connected to wiring 23_11. The gate of transistor Tr254 is connected to wiring 23_12.

[0503] In the display device 70B shown in Figures 9 to 10B, it is preferable to use transistor 10d as transistors Tr200 to Tr202, Tr252, and Tr253, and transistor 20d as transistors Tr251 and Tr254. When transistor 20d is used as one or both of transistors Tr251 and Tr254, the capacitive element 27b shown in Figure 9 corresponds to the capacitive element C200.

[0504] The pixel 17 shown in Figure 32B has a pixel circuit 15H and a light-emitting element 61. The pixel circuit 15H has transistors Tr200, Tr201, Tr203, Tr261, Tr262, and Tr263. The pixel circuit 15H is a 6Tr1C type pixel circuit having six transistors and one capacitive element.

[0505] In a pixel 17 having a pixel circuit 15H, one electrode of the light-emitting element 61 is connected to one of the source and drain of transistor Tr263. The other source and drain of transistor Tr263 is connected to one of the source and drain of transistor Tr200, and to one of the source and drain of transistor Tr261. The other source and drain of transistor Tr200 is connected to one of the source and drain of transistor Tr201, and to one of the source and drain of transistor Tr262. The gate of transistor Tr200 is connected to one of the source and drain of transistor Tr203, the other source and drain of transistor Tr261, and one electrode of capacitive element C200.

[0506] The source and the other drain of transistor Tr203 are connected to wiring 26. The source and the other drain of transistor Tr262, as well as the other electrode of capacitive element C200, are connected to wiring 27. The source and the other drain of transistor Tr203 are connected to wiring 26. The gate of transistor Tr203 is connected to wiring 23_7. The gate of transistor Tr261 is connected to wiring 23_13. The gates of transistor Tr262 and transistor Tr263 are connected to wiring 23_14.

[0507] In the display device 70B shown in Figures 9 to 10B, it is preferable to use transistor 10d as transistors Tr200, Tr201, Tr262, and Tr263, and transistor 20d as transistors Tr203 and Tr261. When transistor 20d is used as transistor Tr261, the capacitive element 27b shown in Figure 9 corresponds to the capacitive element C200.

[0508] <Example of Memory Cell Configuration> One aspect of the present invention can also be applied to memory devices. Figures 33A and 33B are circuit diagrams showing an example of a memory cell configuration.

[0509] Figure 33A shows the memory cell 80A and the buffer circuit 90. The memory cell 80A has transistor Tr300 and transistor Tr301. The memory cell 80A is a 2Tr0C type memory cell that has two transistors and no capacitive elements.

[0510] One of the source and drain of transistor Tr300 is connected to wiring 81. The other of the source and drain of transistor Tr300 is connected to wiring 85. The gate of transistor Tr300 is connected to one of the source and drain of transistor Tr301. The other of the source and drain of transistor Tr301 is connected to wiring 83. The gate of transistor Tr301 is connected to wiring 87. Wiring 83 is connected to the output terminal of buffer circuit 90. Thus, the output terminal of buffer circuit 90 and the other of the source and drain of transistor Tr301 are connected via wiring 83. Note that memory cell 80A may have a capacitive element. In this case, one electrode of the capacitive element is connected to the gate of transistor Tr300 and one of the source and drain of transistor Tr301. Furthermore, a constant potential can be supplied to the other electrode of the capacitive element, for example, a ground potential can be supplied.

[0511] Wiring 81 functions as a read bit line. Wiring 83 functions as a write bit line. Wiring 87 functions as a word line.

[0512] Data is written to the memory cell 80A by supplying a high potential to the wiring 87, which causes transistor Tr301 to conduct. Specifically, when transistor Tr301 is conducting, a potential representing the data is supplied to the wiring 83 via the buffer circuit 90. This writes the potential representing the data to the gate of transistor Tr300. Subsequently, a low potential is supplied to the wiring 87, which causes transistor Tr301 to become non-conductive, thereby retaining the written potential. As a result, the data written to the memory cell 80A is retained.

[0513] Data from the memory cell 80A is read by supplying a predetermined potential to the wiring 85. The current flowing between the source and drain of transistor Tr300, and the potential of wiring 81, are determined by the potential of the gate of transistor Tr300 and the potential of wiring 85. Therefore, by reading the potential of wiring 81, the potential held at the gate of transistor Tr300 can be read. In other words, the data held in the memory cell 80A can be read based on the potential held at the gate of transistor Tr300.

[0514] The buffer circuit 90 may have a transistor corresponding to the transistor 10a shown in Figures 5A, 6, and 7A. It is also preferable to use the transistor 10d shown in Figures 9 and 10B as transistor Tr300, and transistor 20d as transistor Tr301.

[0515] Figure 33B shows the memory cell 80B and the buffer circuit 90. The memory cell 80B includes transistors Tr300 and Tr301, as well as transistor Tr302 and a capacitive element C300. The memory cell 80B is a 3Tr1C type memory cell having three transistors and one capacitive element. In the following, we will mainly describe the configuration that differs from that of the memory cell 80A, and will omit explanations of similar configurations as appropriate.

[0516] In memory cell 80B, the gate of transistor Tr300 is connected to one of the source and drain of transistor Tr301, and to one electrode of the capacitive element C300. One of the source and drain of transistor Tr300 is connected to one of the source and drain of transistor Tr302. The other of the source and drain of transistor Tr300, and the other electrode of the capacitive element C300, are connected to wiring 89. The other of the source and drain of transistor Tr302 is connected to wiring 81. The gate of transistor Tr302 is connected to wiring 88.

[0517] Wiring 88 functions as a read word line. Wiring 89 functions as a power line. Wiring 89 can be supplied with, for example, a low potential, specifically the ground potential.

[0518] Data can be written to memory cell 80B in the same way as data can be written to memory cell 80A. When reading data from memory cell 80B, first, a predetermined potential is precharged to wiring 81. Next, wiring 81 is made electrically floating, and a high potential is supplied to wiring 88. By supplying a high potential to wiring 88, transistor Tr302 becomes conductive. As a result, the potential of wiring 81 is supplied to one of the source and drain of transistor Tr302. The potential of one of the source and drain of transistor Tr302, as well as the potential of wiring 81, change according to the potential held by one electrode of capacitive element C300. Therefore, by reading the potential of wiring 81, the potential held by one electrode of capacitive element C300 can be read. In other words, data held in memory cell 80B can be read based on the potential held by one electrode of capacitive element C300.

[0519] As described above, the buffer circuit 90 may have a transistor corresponding to the transistor 10a shown in Figures 5A, 6, and 7A. Furthermore, it is preferable to use the transistors 10d shown in Figures 9 and 10B as transistors Tr300 and Tr302, and transistor 20d as transistor Tr301.

[0520] <Materials for Display Devices> The following describes the materials that can be used for each component of a display device.

[0521] [Semiconductor Layer] The metal oxides that can be used in the semiconductor layer will be described in detail. Examples of metal oxides include indium oxide, gallium oxide, and zinc oxide. It is preferable to use an oxide containing indium as the metal oxide. It is even more preferable that the metal oxide has a high indium content. By using a metal oxide with a high indium content in the semiconductor layer of a transistor, it is possible to make a transistor with a large on-current, and thus a transistor that can operate at high speed. Furthermore, a transistor using a metal oxide with a high indium content in the semiconductor layer has a high field-effect mobility, and a large on-current can be obtained even with a small channel width, so the occupied area of ​​the transistor can be reduced. By applying a transistor using a metal oxide with a high indium content in the semiconductor layer to the pixel circuit 15, the occupied area of ​​the pixel circuit 15 can be reduced, and a high-definition display device can be made. By applying a transistor using a metal oxide with a high indium content in the semiconductor layer to the circuit section 64, the occupied area of ​​the circuit section 64 can be reduced, and a narrow-bezel display device can be made. Indium oxide can be suitably used as the metal oxide.

[0522] The metal oxide preferably contains at least indium. Alternatively, the metal oxide preferably contains either or both indium and zinc. Alternatively, the metal oxide preferably has one or more elements selected from indium, element M, and zinc. Element M is a metallic or metalloid element with a high bond energy to oxygen, for example, a metallic or metalloid element with a higher bond energy to oxygen than indium. Specific examples of element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M present in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from gallium, aluminum, tin, and yttrium, and even more preferably one or more of gallium, aluminum, and tin. These elements are more preferred because they have high bonding energy with oxygen and their ionic radii are similar to those of indium or zinc. Furthermore, tin is more preferred because its tetravalent state can increase carrier mobility. In this specification, metal elements and metalloid elements are sometimes collectively referred to as "metal elements," and the "metal elements" described in this specification may include metalloid elements.

[0523] In this specification, the ratio of the number of indium atoms to the sum of the total number of atoms of all contained metal elements may be referred to as the indium content. The same applies to other metal elements. If element M contains multiple elements, the sum of the ratios of the number of atoms of element M to the sum of the total number of atoms of all contained metal elements may be referred to as the element M content.

[0524] Examples of metal oxides include indium zinc oxide (In-Zn oxide, also known as IZO®), indium tin oxide (In-Sn oxide, also known as ITO), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tungsten oxide (In-W oxide, also known as IWO), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide, also known as IGTO), gallium zinc oxide (Ga-Zn oxide, also known as GZO), and aluminum zinc oxide (Al-Zn oxide). Indium aluminum zinc oxide (also written as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also written as IAZO), indium tin zinc oxide (In-Sn-Zn oxide, also written as ITZO®), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as IGAZO, IGZAO, or IAGZO), etc. can be used. Alternatively, silicon-containing indium tin oxide (also written as ITSO), gallium tin oxide (Ga-Sn oxide), aluminum tin oxide (Al-Sn oxide), etc. can be used.

[0525] Furthermore, the metal oxide can be composed of one or more metal elements with high periodic numbers in the periodic table, either in place of indium or in addition to indium. The greater the overlap of the orbitals of the metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including metal elements with high periodic numbers, the field-effect mobility of the transistor can be increased. Examples of metal elements with high periodic numbers include those belonging to the 5th period and those belonging to the 6th period. Specifically, examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0526] Metal oxides may contain one or more nonmetallic elements. The presence of nonmetallic elements in metal oxides can increase carrier concentration or reduce the band gap, potentially improving the field-effect mobility of transistors. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0527] By increasing the zinc content in a metal oxide, a highly crystalline metal oxide is obtained, which suppresses the diffusion of impurities within the metal oxide. Therefore, fluctuations in the electrical characteristics of the transistor are suppressed, and reliability can be improved.

[0528] By increasing the content of element M in the metal oxide, a metal oxide with a large band gap can be produced. This allows for the formation of oxygen vacancies (V) in the metal oxide. Ｏ The formation of oxygen deficiency (V) is suppressed. ＯCarrier generation caused by () is suppressed. Therefore, the shift in the transistor's threshold voltage is suppressed, the cutoff current can be reduced, and a normally-off transistor can be made. In addition, a transistor with a small off-current can be made. Furthermore, fluctuations in the transistor's electrical characteristics are suppressed, and reliability can be improved.

[0529] In this specification, normally off refers to the state in which no current flows through a transistor when no potential is applied to the gate or when the gate-source voltage is 0V. Normally off can be evaluated by the threshold voltage (Vth) or shift value (Vsh) of the transistor. Unless otherwise specified, Vth shall be calculated using the constant current method. More specifically, Vth is the value of drain current (Id) × channel length (L) ÷ channel width (W) in the Id-Vg characteristic of the transistor, where the value is 1nA (1 × 10⁻¹⁶). −９ Let Vg be the gate voltage (Vg) when A) is true. Also, Vsh is defined as the tangent to the maximum slope when the drain current (Id) in the Id-Vg characteristic of the transistor is expressed logarithmically, and Id = 1pA (1 × 10⁻¹⁰). −１２ Vg is the gate voltage (Vg) at the intersection with the line in A), or the Vg at the intersection of the line extrapolated from the two points where the slope of Id is maximized when Id is expressed logarithmically in the transistor's Id-Vg characteristic, and the line where Id = 1 pA. For example, if either or both of Vth and Vsh are zero or positive values, it can be considered a normally-off transistor.

[0530] By using a metal oxide with a large band gap in the semiconductor layer, oxygen vacancies (V) can be created in the semiconductor layer by light. Ｏ The formation of ) is suppressed, and the shift in the transistor's threshold voltage can be suppressed. Therefore, a transistor with high reliability against light can be made. A metal oxide having element M can be suitably used in the semiconductor layer of a transistor provided in a region where light can be incident (for example, a display unit).

[0531] The semiconductor layer may contain a layered material that functions as a semiconductor. A layered material is a general term for a group of materials having a layered crystalline structure. Layered materials have high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0532] Examples of the above-mentioned layered materials include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogens (elements belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specifically, a transition metal chalcogenide applicable as a channel formation region in transistors is molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum tellurium (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ Examples include:

[0533] [Conductive Layers] The conductive layers of the display device (conductive layer 103, conductive layer 104, conductive layer 112, conductive layer 122, conductive layer 123, conductive layer 151, conductive layer 203, conductive layer 204, conductive layer 212, conductive layer 214, conductive layer 222, conductive layer 223, conductive layer 251, conductive layer 303, conductive layer 304, conductive layer 312, etc.) can each be a single layer or a laminated structure of two or more layers. Materials that can be used for these conductive layers include, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, as well as alloys composed of one or more of the aforementioned metals. Conductive materials with low electrical resistivity, each containing one or more of copper, silver, gold, and aluminum, can be suitably used for these conductive layers. Copper or aluminum are particularly preferred due to their excellent mass productivity.

[0534] Each conductive layer in the display device can be made of a conductive metal oxide (also called an oxide conductor (OC)). Examples of oxide conductors include indium oxide, zinc oxide, In-Sn oxide (ITO), In-Zn oxide, In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Sn-Si oxide (also called silicon-containing ITO or ITSO), zinc oxide with added gallium, and In-Ga-Zn oxide. Oxide conductors containing indium are particularly preferred due to their high conductivity.

[0535] When oxygen vacancies are formed in a metal oxide with semiconductor properties, and hydrogen is added to these vacancies, donor levels are formed near the conduction band. As a result, the metal oxide becomes highly conductive and turns into a conductor. A metal oxide that has become conductive can be called an oxide conductor.

[0536] Each conductive layer in the display device can have a laminated structure consisting of a conductive film containing the aforementioned oxide conductor (metal oxide) and a conductive film containing a metal or alloy. By using a conductive film containing a metal or alloy, wiring resistance can be reduced.

[0537] The conductive layers of the display device can also be made of nitride conductors. Examples of nitride conductors include tantalum nitride and titanium nitride.

[0538] The conductive layers of the display device can also be made of Cu-X alloy films (where X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti). Using Cu-X alloy films allows for processing by wet etching, thus reducing manufacturing costs.

[0539] Furthermore, the conductive layers of the display device may be made of the same material, or at least one of them may be made of a different material.

[0540] [Insulating Layers] The insulating layers of the display device (insulating layer 105, insulating layer 106, insulating layer 110, insulating layer 125, insulating layer 127, insulating layer 191, insulating layer 198, insulating layer 205, insulating layer 206, insulating layer 210, insulating layer 231, insulating layer 232, insulating layer 235, insulating layer 237, insulating layer 291, insulating layer 298, insulating layer 305, insulating layer 306, insulating layer 331, insulating layer 332, insulating layer 391, etc.) can each be a single-layer structure or a laminated structure of two or more layers. For example, insulating layer 105, insulating layer 106, insulating layer 205, insulating layer 206, insulating layer 305, and insulating layer 306 each preferably have one or more inorganic insulating layers. For materials that can be used for the inorganic insulating layers, refer to the above description. Furthermore, for materials that can be used for insulating layer 125, insulating layer 127, insulating layer 191, insulating layer 231, insulating layer 232, insulating layer 235, insulating layer 237, insulating layer 291, insulating layer 331, insulating layer 332, and insulating layer 391, please refer to the above description.

[0541] The insulating layers 105, 106, 205, 206, 305, and 306, which function as gate insulating layers, each have a region in contact with the semiconductor layer. When silicon or a metal oxide is used for the semiconductor layer, it is preferable that at least a portion of the region of the gate insulating layer in contact with the semiconductor layer contains oxygen in order to improve the interfacial characteristics between the semiconductor layer and the gate insulating layer. Specifically, it is preferable that the region of the gate insulating layer in contact with the channel-forming region contains oxygen. One or more oxides and oxiditrides can be suitably used in the region of the gate insulating layer in contact with the channel-forming region. For example, it is preferable that each gate insulating layer contains silicon and oxygen. It is preferable that each gate insulating layer contains silicon oxide or silicon oxiditride.

[0542] In the case of miniature transistors, if the thickness of the gate insulating layer is reduced, the leakage current may increase. By using a material with a high dielectric constant (also called a high-k material) for the gate insulating layer, it is possible to reduce the voltage during transistor operation while maintaining the physical film thickness. Examples of high-k materials that can be used for the gate insulating layer include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxides containing aluminum and hafnium, oxides containing silicon and hafnium, oxides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0543] In cross-sectional views showing examples of the configuration of a display device, such as Figure 6, the gate insulating layer is shown as a single-layer structure; however, the present invention is not limited to this. The gate insulating layer can be a laminated structure of two or more layers. When the gate insulating layer is a laminated structure, the insulating layer on the semiconductor layer side preferably has an oxide or oxidizride. The insulating layer on the semiconductor layer side can preferably be one or more of silicon oxide, silicon oxidizride, or aluminum oxide.

[0544] It is preferable to provide a barrier insulating layer on one or more of the layers constituting the gate insulating layer. By providing a barrier insulating layer, the diffusion of metal components contained in the gate electrode into the semiconductor layer via the gate insulating layer can be suppressed. Furthermore, when a metal oxide is used in the semiconductor layer, the diffusion of oxygen contained in the semiconductor layer to the gate electrode side via the gate insulating layer can be suppressed. This prevents oxygen vacancies (V) in the semiconductor layer. Ｏ This suppresses the formation of (a specific type of ion). Furthermore, it suppresses oxidation of the gate electrode by oxygen contained in the semiconductor layer, which increases the electrical resistance of the gate electrode. As a result, it is possible to create a transistor that exhibits good electrical characteristics and is highly reliable.

[0545] The first gate insulating layer can be, for example, a laminated structure of a silicon oxide nitride film and a silicon nitride film on the silicon oxide nitride film. Alternatively, the first gate insulating layer can be a laminated structure of a silicon oxide nitride film and an aluminum oxide film on the silicon oxide nitride film. Alternatively, the first gate insulating layer can be a laminated structure of an aluminum oxide film and a silicon oxide nitride film on the aluminum oxide film. Alternatively, the first gate insulating layer can be a laminated structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film.

[0546] The second gate insulating layer can be, for example, a laminated structure of a silicon nitride film and a silicon oxide nitride film on the silicon nitride film. Alternatively, the second gate insulating layer can be a laminated structure of an aluminum oxide film and a silicon oxide nitride film on the aluminum oxide film. Alternatively, the second gate insulating layer can be a laminated structure of a silicon oxide nitride film and an aluminum oxide film on the silicon oxide nitride film. Alternatively, the second gate insulating layer can be a laminated structure of a silicon nitride film and an aluminum oxide film on the silicon nitride film.

[0547] Here, an example is shown in which the gate insulating layer has a two-layer laminated structure, but the present invention is not limited to this. The gate insulating layer can also have a three-layer or more laminated structure.

[0548] The insulating layer 125 can be a single-layer structure or a laminated structure of two or more layers. Preferably, the insulating layer 125 has one or more inorganic insulating layers. The insulating layer 125 can be made of any material that can be used for the insulating layer 106. In particular, aluminum oxide is preferred because it has a high selectivity ratio with the EL layer during etching and has the function of protecting the EL layer during the formation of the insulating layer 127. In particular, by applying an inorganic insulating layer such as an aluminum oxide film, hafnium oxide film, or silicon oxide film formed by the ALD method to the insulating layer 125, an insulating layer 125 can be formed with fewer pinholes and excellent function in protecting the EL layer. Alternatively, the insulating layer 125 may be a laminated structure of a film formed by the ALD method and a film formed by the sputtering method. For example, the insulating layer 125 may be a laminated structure of an aluminum oxide film formed by the ALD method and a silicon nitride film formed by the sputtering method.

[0549] Preferably, the insulating layer 125 functions as a barrier insulating layer against at least one of water and oxygen. Preferably, the insulating layer 125 has the function of suppressing the diffusion of at least one of water and oxygen. Furthermore, preferably, the insulating layer 125 has the function of capturing or fixing (getting) at least one of water and oxygen.

[0550] The insulating layer 125 functions as a barrier insulating layer, thereby suppressing the intrusion of impurities (typically at least one of water and oxygen) that could diffuse from the outside into each light-emitting element. This configuration makes it possible to provide a highly reliable light-emitting element and, furthermore, a highly reliable display device.

[0551] The insulating layer 127 provided on the insulating layer 125 has the function of flattening the large height differences and irregularities in the insulating layer 125 formed between adjacent light-emitting elements. In other words, the presence of the insulating layer 127 has the effect of improving the flatness of the surface forming the common electrode 115.

[0552] As the insulating layer 127, an insulating layer having an organic material can be suitably used. Preferably, a photosensitive resin is used as the organic material; for example, a photosensitive resin composition containing an acrylic resin is preferred. In this specification, the term "acrylic resin" does not refer only to polymethacrylate esters or methacrylic resins, but may refer to acrylic polymers in a broad sense.

[0553] As the insulating layer 127, acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimidoamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins may be used. Alternatively, as the insulating layer 127, organic materials such as polyvinyl alcohol (PVA),...

Claims

It has a drive circuit and pixels, The drive circuit includes a plurality of first transistors provided in a first layer and a plurality of second transistors provided in a second layer overlapping the first layer. In at least one of the plurality of first transistors, the source or drain is electrically connected to the pixel. A display device in which the channel width of the first transistor is greater than the channel width of the second transistor. 　 In claim 1, The drive circuit has a buffer circuit, The plurality of first transistors are included in the buffer circuit, which is a display device. 　 In claim 1, The pixel has a third transistor provided in the first layer and a fourth transistor provided in the second layer. A display device in which the source or drain of at least one of the plurality of first transistors is electrically connected to the source, drain, or gate of the third transistor. 　 In claim 3, The aforementioned pixel has a light-emitting element, A display device in which the source or drain of the fourth transistor is connected to one electrode of the light-emitting element. 　 It has a drive circuit and pixels, The drive circuit is electrically connected to the pixel, The drive circuit is composed of a plurality of first transistors provided in a first layer, a plurality of second transistors provided in a second layer on the first layer, and a plurality of first capacitive elements provided in the second layer. A display device in which the source or drain of each of the plurality of second transistors is electrically connected to the electrode of one of the plurality of first capacitive elements. 　 In claim 5, A display device in which the semiconductor layers of each of the plurality of first transistors and the plurality of second transistors are made of the same material. 　 In claim 6, A display device wherein the off-current of the second transistor is lower than the off-current of the first transistor. 　 In claim 5, The pixel comprises a light-emitting element, a third transistor provided in the first layer, a fourth transistor provided in the second layer, and a second capacitive element provided in the second layer. One electrode of the light-emitting element is electrically connected to the source or drain of the third transistor. The source and drain of the fourth transistor are electrically connected to the drive circuit. A display device wherein the source and the other drain of the fourth transistor are electrically connected to one electrode of the second capacitive element. 　 In claim 8, A display device in which the semiconductor layers of each of the plurality of first transistors, the plurality of second transistors, the third transistor, and the fourth transistor are made of the same material. 　 In claim 9, A display device wherein the off-currents of the second transistor and the fourth transistor are lower than the off-currents of the first transistor and the third transistor, respectively. 　 In any one of claims 6, 7, 9, and 10, The semiconductor layer comprises indium and oxygen, and is a display device.

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