Semiconductor device, display device, and method for manufacturing semiconductor device

Abstract

Provided is a semiconductor device comprising micro-sized transistors. The present invention has first to third transistors, a first insulating layer, and a second insulating layer. The first to third transistors are all vertical transistors. The first transistor and the second transistor are connected in series. One of a source electrode and a drain electrode of each of the first to third transistors is located below the first insulating layer, and the other of the source electrode and the drain electrode is located above the first insulating layer. One of the source electrode and the drain electrode of the first transistor and the second transistor, and one of the source electrode and the drain electrode of the third transistor have regions overlapping each other with the second insulating layer interposed therebetween. The other of the source electrode and the drain electrode of the third transistor is connected to gate electrodes of the first transistor and the second transistor.

Description

Semiconductor device, display device, and method of manufacturing semiconductor device

[0001] One aspect of the present invention relates to transistors, semiconductor devices, display devices, display modules, and electronic devices. One aspect of the present invention relates to a method of manufacturing a transistor, a method of manufacturing a semiconductor device, and a method of manufacturing a display device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. Examples of the technical field of one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, power storage devices, storage devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), electronic devices having these, driving methods thereof, or manufacturing methods thereof.

[0003] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including semiconductor elements (transistors, diodes, photodiodes, etc.), a device having the circuit, and the like. It also refers to all devices that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip provided with an integrated circuit, and an electronic component in which a chip is housed in a package are examples of semiconductor devices. In addition, a storage device, a display device, a light-emitting device, a lighting device, and an electronic device may themselves be semiconductor devices and each may have a semiconductor device.

[0004] A semiconductor device having a transistor is widely applied to display devices and electronic devices, and higher integration and higher speed of the semiconductor device are required. For example, when applying a semiconductor device to a high-definition display device, a semiconductor device with a high degree of integration is required. As one means of increasing the integration degree of a semiconductor device, the development of transistors with a fine size is in progress.

[0005] In recent years, there has been a demand for display devices applicable to virtual reality (VR), augmented reality (AR), substitute reality (SR), or mixed reality (MR). VR, AR, SR, and MR are collectively referred to as XR (Extended Reality). Display devices for XR are desired to have high resolution and high color reproduction in order to enhance the sense of reality and immersion. Examples of such display devices include liquid crystal displays, organic EL (Electroluminescence) devices, and light-emitting devices (also called light-emitting elements) such as light-emitting diodes (LEDs).

[0006] Patent Document 1 discloses a display device for VR using an organic EL device (also called an organic EL element).

[0007] International Publication No. 2018 / 087625

[0008] One aspect of the present invention aims to provide a semiconductor device having a minutely sized transistor and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a miniature semiconductor device and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a semiconductor device having a transistor with a large on-current and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a semiconductor device with good electrical characteristics and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a highly integrated semiconductor device and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a novel semiconductor device and a method for manufacturing the same. Alternatively, one aspect of the present invention aims to provide a high-resolution display device.

[0009] Furthermore, the description of these problems does not preclude the existence of other problems. One aspect of the present invention does not necessarily have to solve all of these problems. It is possible to extract other problems from the description in the specification, drawings, and claims.

[0010] To further increase the integration of semiconductor devices, it is effective to miniaturize the transistors in the semiconductor device and to devise a better layout for those transistors.

[0011] One aspect of the present invention comprises a first conductive layer to a sixth conductive layer, a first insulating layer to a fourth insulating layer, a first semiconductor layer and a second semiconductor layer, wherein the first insulating layer is located on the first conductive layer, the second conductive layer is located on the first insulating layer, the second insulating layer is located on the second conductive layer and the first insulating layer, and has a groove that reaches the second conductive layer, the first and second sides of the second insulating layer within the groove are opposite to each other, the third and fourth conductive layers are located on the second insulating layer, the first side and the side of the third conductive layer are roughly coincide, the second side and the side of the fourth conductive layer are roughly coincide, and the first semiconductor layer has a second side within the groove The semiconductor device is configured such that the upper surface, first side surface, second side surface, upper and side surfaces of the third conductive layer, and upper and side surfaces of the fourth conductive layer are in contact with the upper surface, first side surface, second side surface, upper and side surfaces of the third conductive layer, and upper and side surfaces of the fourth conductive layer, the third insulating layer is located on the first semiconductor layer and the second insulating layer, the fifth conductive layer is located on the third insulating layer, the first insulating layer, the second insulating layer, the third insulating layer, and the fifth conductive layer have openings that reach the first conductive layer, the second semiconductor layer is in contact with the upper surface of the first conductive layer within the openings, the side surfaces of the second insulating layer within the openings, and the upper and side surfaces of the fifth conductive layer, the fourth insulating layer is located on the second semiconductor layer, and the sixth conductive layer is located on the fourth insulating layer such that it has a region that overlaps with the openings.

[0012] Furthermore, one aspect of the present invention includes a first conductive layer to a fourth conductive layer, a first insulating layer to a fourth insulating layer, a first semiconductor layer and a second semiconductor layer, wherein the first insulating layer is located on the first conductive layer, the second conductive layer is located on the first insulating layer, the second insulating layer is located on the second conductive layer and the first insulating layer and has a groove that reaches the second conductive layer, the third conductive layer is located on the second insulating layer, the first side surface of the second insulating layer and the side surface of the third conductive layer within the groove are substantially coincide, and the first semiconductor layer has the upper surface, first side surface, and groove within the groove The semiconductor device comprises a second insulating layer with a second side surface, a third conductive layer with an upper surface and side surface, and a third insulating layer in contact with the upper surface of the second insulating layer. The third insulating layer is located on the first semiconductor layer and the second insulating layer, and the first insulating layer, the second insulating layer, and the third insulating layer have openings that reach the first conductive layer. The second semiconductor layer is in contact with the upper surface of the first conductive layer within the opening, the side surface of the second insulating layer within the opening, and the upper surface of the third insulating layer within the groove. The fourth insulating layer is located on the second semiconductor layer, and the fourth conductive layer is located on the fourth insulating layer such that it has a region that overlaps with the opening.

[0013] Furthermore, one aspect of the present invention comprises a first conductive layer to a third conductive layer, a first insulating layer to a fourth insulating layer, a first semiconductor layer and a second semiconductor layer, wherein the first insulating layer is located on the first conductive layer, the second insulating layer is located on the first insulating layer and has a groove that reaches the first insulating layer, the second conductive layer is located on the second insulating layer, the first side surface of the second insulating layer and the side surface of the second conductive layer within the groove are substantially coincide, and the first semiconductor layer has the upper surface, first side surface of the first insulating layer within the groove, and the second side surface of the second insulating layer within the groove. The semiconductor device is configured such that the upper and side surfaces of the second conductive layer and the upper surface of the second insulating layer are in contact with the upper surface of the second insulating layer, the third insulating layer is located on the first semiconductor layer and the second insulating layer, the first insulating layer, the second insulating layer and the third insulating layer have openings that reach the first conductive layer, the second semiconductor layer is in contact with the upper surface of the first conductive layer within the opening, the side surfaces of the second insulating layer within the opening and the upper surface of the third insulating layer within the groove, the fourth insulating layer is located on the second semiconductor layer, and the third conductive layer is located on the fourth insulating layer such that it has a region that overlaps with the opening.

[0014] Furthermore, it is preferable that the first semiconductor layer and the second semiconductor layer each contain indium and oxygen, the first insulating layer contains silicon and nitrogen, the second insulating layer contains a fifth insulating layer, a sixth insulating layer on the fifth insulating layer, and a seventh insulating layer on the sixth insulating layer, the fifth insulating layer and the seventh insulating layer contain silicon and nitrogen, and the sixth insulating layer contains silicon and oxygen.

[0015] Furthermore, in the above, it is preferable that the third conductive layer has one or more of copper, silver, gold, or aluminum.

[0016] Furthermore, in the above, it is preferable that the second conductive layer has one or more of copper, silver, gold, or aluminum.

[0017] Furthermore, in the above, the first semiconductor layer preferably has a first region in the groove that is in contact with the first insulating layer, and the first region preferably has lower electrical resistance than the regions of the first semiconductor layer other than the first region.

[0018] Furthermore, one aspect of the present invention is a display device having two semiconductor devices adjacent to each other, wherein in each of the two semiconductor devices, the first conductive layer, the fourth conductive layer, and the fifth conductive layer each extend in a first direction in a plan view, the third conductive layer and the sixth conductive layer each extend in a second direction perpendicular to the first direction in a plan view, the width of the first conductive layer, the fourth conductive layer, and the fifth conductive layer in the second direction is 1.0 μm or more and 2.0 μm or less, the width of the third conductive layer and the sixth conductive layer in the first direction is 1.0 μm or more and 2.0 μm or less, and the spacing between adjacent first conductive layers, fourth conductive layers, and fifth conductive layers in the second direction is 1.0 μm or more and 2.0 μm or less.

[0019] Furthermore, in one aspect of the present invention, a first conductive layer, a first insulating film, a second conductive layer overlapping the first conductive layer, a second insulating film, and a third conductive layer overlapping the second conductive layer are formed in this order, and a portion of the third conductive layer and the second insulating film is removed to form a groove reaching the second conductive layer, and a fourth conductive layer and a fifth conductive layer are formed from the third conductive layer, and a first insulating layer is formed from the second insulating film, and a first semiconductor layer is formed in contact with the upper surface of the second conductive layer in the groove, the first side surface of the first insulating layer in the groove, the second side surface of the first insulating layer in the groove, the upper and side surfaces of the fourth conductive layer, and the upper and side surfaces of the fifth conductive layer, and a third insulating film and This is a method for manufacturing a semiconductor device, comprising forming a sixth conductive layer in this order, removing a portion of the sixth conductive layer, the third insulating film, the first insulating layer, and the first insulating film to form an opening that reaches the first conductive layer, forming a seventh conductive layer from the sixth conductive layer, a second insulating layer from the third insulating film, a third insulating layer from the first insulating layer, and a fourth insulating layer from the first insulating film, forming a second semiconductor layer in contact with the upper surface of the first conductive layer, the side surface of the third insulating layer, the side surface of the seventh conductive layer, and the upper surface of the seventh conductive layer within the opening, forming a fifth insulating layer on the second semiconductor layer and on the seventh conductive layer, and forming an eighth conductive layer on the fifth insulating layer that overlaps with the opening.

[0020] According to one aspect of the present invention, a semiconductor device having a minutely sized transistor and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a miniature semiconductor device and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device having a transistor with a large on-current and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a semiconductor device with good electrical characteristics and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a highly integrated semiconductor device and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a novel semiconductor device and a method for manufacturing the same can be provided. Alternatively, according to one aspect of the present invention, a high-definition display device can be provided.

[0021] Furthermore, the description of these effects does not preclude the existence of other effects. One aspect of the present invention does not necessarily have to possess all of these effects. Other effects can be extracted from the description, drawings, and claims.

[0022] Figure 1A is a plan view showing an example of a semiconductor device. Figure 1B is a cross-sectional view showing an example of a semiconductor device. Figure 2A is a plan view showing an example of a semiconductor device. Figure 2B is a cross-sectional view showing an example of a semiconductor device. Figure 3A is a plan view showing an example of a semiconductor device. Figure 3B is a cross-sectional view showing an example of a semiconductor device. Figures 4A, 4B, and 4C are circuit diagrams illustrating a semiconductor device. Figures 5A and 5B are perspective views showing an example of a semiconductor device. Figures 6A and 6B are plan views showing an example of a semiconductor device. Figures 7A and 7B are plan views showing an example of a semiconductor device. Figure 8A is a plan view showing an example of a method for manufacturing a semiconductor device. Figure 8B is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 9A is a plan view showing an example of a method for manufacturing a semiconductor device. Figure 9B is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 10A is a plan view showing an example of a method for manufacturing a semiconductor device. Figure 10B is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 11A is a plan view showing an example of a method for manufacturing a semiconductor device. Figure 11B is a cross-sectional view showing an example of a method for manufacturing a semiconductor device. Figure 12A is a plan view showing an example of a semiconductor device manufacturing method. Figure 12B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 13A is a plan view showing an example of a semiconductor device manufacturing method. Figure 13B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 14A is a plan view showing an example of a semiconductor device manufacturing method. Figure 14B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 15A is a plan view showing an example of a semiconductor device manufacturing method. Figure 15B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 16A is a plan view showing an example of a semiconductor device manufacturing method. Figure 16B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 17A is a plan view showing an example of a semiconductor device manufacturing method. Figure 17B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 18A is a plan view showing an example of a semiconductor device manufacturing method. Figure 18B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 19A is a plan view showing an example of a semiconductor device manufacturing method. Figure 19B is a cross-sectional view showing an example of a semiconductor device manufacturing method. Figure 20 is a block diagram of a display device.Figures 21A, 21B, 21C, and 21D are circuit diagrams of pixel circuits. Figures 22A, 22B, and 22C are plan views showing an example of a semiconductor device manufacturing method. Figures 23A and 23B are plan views showing an example of a semiconductor device manufacturing method. Figures 24A and 24B are plan views showing an example of a semiconductor device manufacturing method. Figures 25A and 25B are plan views showing an example of a semiconductor device manufacturing method. Figure 26 is a plan view showing an example of a semiconductor device. Figure 27 is a cross-sectional view showing an example of a semiconductor device. Figure 28 is a perspective view showing an example of a display device. Figure 29 is a cross-sectional view showing an example of a display device. Figure 30 is a cross-sectional view showing an example of a display device. Figure 31 is a cross-sectional view showing an example of a display device. Figure 32 is a cross-sectional view showing an example of a display device. Figures 33A, 33B, 33C, and 33D are diagrams showing an example of an electronic device. Figures 34A, 34B, 34C, 34D, 34E, and 34F are diagrams showing an example of an electronic device. Figures 35A, 35B, 35C, 35D, 35E, 35F, and 35G are diagrams showing examples of electronic devices.

[0023] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Therefore, the present invention shall not be construed as being limited to the descriptions of the embodiments shown below.

[0024] Furthermore, the ordinal numbers "first," "second," and "third" in this specification are used to avoid confusion of constituent elements. Therefore, they do not limit the number of constituent elements, nor do they limit the order of the constituent elements. For example, a constituent element referred to as "first" in one embodiment of this specification may be referred to as "second" in another embodiment or in the claims. Also, for example, a constituent element referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0025] In the invention described below, the same reference numerals are used in common across different drawings for identical parts or parts having similar functions, and repeated explanations are omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used, and reference numerals may not be assigned.

[0026] The positions, sizes, and extents of each component shown in the drawings may not represent their actual positions, sizes, and extents for the sake of ease of understanding. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, and extents disclosed in the drawings.

[0027] It should be noted that the terms "film" and "layer" can be interchanged depending on the context or situation. For example, the term "conductive layer" can be changed to "conductive film." Or, for example, the term "insulating film" can be changed to "insulating layer."

[0028] A transistor is a type of semiconductor device that can perform functions such as amplifying current or voltage, and switching operations that control conduction or non-conductivity. Transistors as used herein include IGFETs (Insulated Gate Field Effect Transistors) and thin-film transistors (TFTs).

[0029] The functions of "source" and "drain" may be reversed when transistors with different polarities are used, or when the direction of current changes during circuit operation. For this reason, in this specification, the terms "source" and "drain" may be used interchangeably. Furthermore, the names of the source and drain of a transistor can be appropriately rephrased as source region and drain region, source terminal and drain terminal, or source electrode and drain electrode, depending on the situation.

[0030] In this specification, "connection" includes, for example, "electrical connection." The term "electrical connection" is sometimes used to define the connection relationship of circuit elements as a physical object. Furthermore, "electrical connection" includes both "direct connection" and "indirect connection." "A and B are directly connected" means that A and B are connected without the use of circuit elements (e.g., transistors, switches, etc.; wiring is not considered a circuit element). On the other hand, "A and B are indirectly connected" means that A and B are connected through one or more circuit elements. A, B, and C (described later) refer to objects such as elements, circuits, wiring, electrodes, terminals, semiconductor layers, and conductive layers.

[0031] For example, assuming a circuit including A and B is in operation, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected" as physical objects. Furthermore, even if there is a timing during the circuit's operation when no electrical signals are exchanged or potential interactions occur between A and B, if there is a timing during the circuit's operation when electrical signals are exchanged or potential interactions occur between A and B, then it can be defined that "A and B are indirectly connected."

[0032] An example of a case where "A and B are indirectly connected" is when A and B are connected via the source and drain of one or more transistors. On the other hand, an example of a case where "A and B are not indirectly connected" is when an insulator is interposed in the path from A to B. Specifically, this includes cases where a capacitive element is connected between A and B, or where a transistor gate insulating film is interposed between A and B. Therefore, it cannot be said that "the gate (A) of a transistor and the source or drain (B) of a transistor are indirectly connected."

[0033] Another example of a situation where it cannot be said that "A and B are indirectly connected" is when multiple transistors are connected via source and drain in the path from A to B, and a constant potential V is supplied to the nodes between the transistors from a power supply, GND, etc.

[0034] In this specification, a structure in which at least the light-emitting layers are created separately for light-emitting devices with different emission wavelengths may be referred to as an SBS (Side By Side) structure. Because the SBS structure allows for the optimization of materials and configuration for each light-emitting device, it increases the degree of freedom in selecting materials and configurations, making it easier to improve brightness and reliability.

[0035] In this specification, holes or electrons may be referred to as "carriers." Specifically, a hole injection layer or electron injection layer may be called a "carrier injection layer," a hole transport layer or electron transport layer may be called a "carrier transport layer," and a hole block layer or electron block layer may be called a "carrier block layer." It should be noted that the above-mentioned carrier injection layer, carrier transport layer, and carrier block layer may not be clearly distinguishable by their cross-sectional shape or characteristics. Furthermore, a single layer may combine the functions of two or three of these layers.

[0036] In this specification, a light-emitting device has an EL layer between a pair of electrodes. The EL layer has at least a light-emitting layer. The layers (also called functional layers) of the EL layer include a light-emitting layer, a carrier injection layer (hole injection layer and electron injection layer), a carrier transport layer (hole transport layer and electron transport layer), and a carrier block layer (hole block layer and electron block layer).

[0037] In this specification, "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated. For example, an island-like metal oxide layer refers to a state in which the metal oxide layer and adjacent metal oxide layers are physically separated.

[0038] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it refers to a shape having a region in which the angle (also called the taper angle) between the inclined side surface and the substrate surface or the surface to be formed is less than 90 degrees. The side surface of the structure, the substrate surface, and the surface to be formed do not necessarily have to be perfectly flat, and may be substantially planar with a small curvature, or substantially planar with fine irregularities.

[0039] In this specification, "step breakage" refers to the phenomenon in which a layer, film, or electrode is divided due to the shape of the surface on which it is formed (for example, a step or other difference in height).

[0040] In this specification, "parallel" means a state in which two lines are positioned at an angle of -10 degrees or more and 10 degrees or less. Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Furthermore, "approximately parallel" means a state in which two lines are positioned at an angle of -30 degrees or more and 30 degrees or less. Furthermore, "perpendicular" means a state in which two lines are positioned at an angle of 80 degrees or more and 100 degrees or less. Therefore, the case of 85 degrees or more and 95 degrees or less is also included. Furthermore, "approximately perpendicular" means a state in which two lines are positioned at an angle of 60 degrees or more and 120 degrees or less.

[0041] In this specification, the top surface shape of a component refers to the contour shape of that component in a plan view. A plan view refers to a view from the direction normal to the surface on which the component is formed, or to the surface of the support (e.g., substrate) on which the component is formed.

[0042] In this specification, "approximately matching top surface shapes" means that at least a portion of the contours overlap between stacked layers. For example, this includes cases where the upper and lower layers are processed with the same mask pattern, or partially with the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or the upper layer may be located outside the lower layer; in these cases, it may also be said that the "top surface shapes are approximately matching."

[0043] Furthermore, in this specification, "approximately matching height" refers to a configuration in which the height from a reference surface (for example, a flat surface such as the substrate surface) is approximately equal in a cross-sectional view. For example, when a planarization treatment (typically chemical mechanical polishing (CMP) treatment) is performed, the treated surface will have approximately matching height. However, even after a planarization treatment, the height may not be exactly the same depending on the film material, but in this specification, this is also considered to be "approximately matching height".

[0044] (Embodiment 1) This embodiment describes a semiconductor device, a method for manufacturing a semiconductor device, and the like according to one aspect of the present invention.

[0045] One aspect of the present invention is a semiconductor device having a first transistor, a second transistor, a third transistor, a first insulating layer, and a second insulating layer.

[0046] The first transistor and the second transistor are arranged adjacent to each other. The first transistor and the second transistor share some components.

[0047] The third transistor is provided adjacent to the second transistor. Some components of the third transistor are shared with the first and second transistors, respectively. Other components of the third transistor can be arranged to overlap with the first and second transistors, respectively, in a plan view.

[0048] The first to third transistors are all vertical transistors in which the source electrode and drain electrode are located at different heights relative to the substrate surface, and the drain current flows in the vertical direction. Therefore, they can be miniaturized and have a smaller footprint than planar transistors in which the source electrode and drain electrode are located on the same plane.

[0049] A semiconductor device according to one aspect of the present invention, having the first to third transistors configured as described above, can be miniaturized and highly integrated as a whole.

[0050] Herein, in each of the first to third transistors, the electrode located closer to the substrate surface will be referred to as "one of the source electrodes or drain electrodes," and the electrode located further away from the substrate surface will be referred to as "the other of the source electrode or drain electrode."

[0051] The first insulating layer is provided such that it has a region sandwiched between the source electrode and drain electrode of the first to third transistors, respectively.

[0052] The first transistor has a semiconductor layer that functions as a channel-forming region, which is provided in contact with the upper surface of one of the source or drain electrodes, the first side surface of the first insulating layer, the other side surface of the source or drain electrode, and the upper surface of the other of the source or drain electrode. A gate insulating layer is provided in contact with the upper surface of the semiconductor layer, and a gate electrode is provided in contact with the upper surface of the gate insulating layer and has a region facing the semiconductor layer.

[0053] The second transistor has a semiconductor layer that functions as a channel-forming region, which is provided in contact with the upper surface of one of the source or drain electrodes, the second side surface of the first insulating layer, the other side surface of the source or drain electrode, and the upper surface of the other of the source or drain electrode. A gate insulating layer is provided in contact with the upper surface of the semiconductor layer, and a gate electrode is provided in contact with the upper surface of the gate insulating layer such that it has a region facing the semiconductor layer.

[0054] Furthermore, the first and second sides of the first insulating layer face each other.

[0055] An opening is provided in the source electrode or drain electrode of the third transistor, and in the first insulating layer, reaching one of the source electrode or drain electrode of the third transistor. The third transistor has a semiconductor layer that functions as a channel-forming region, which is provided in contact with the source electrode, the drain electrode, and the side surface of the first insulating layer, respectively, so as to encompass the opening. A gate insulating layer is provided in contact with the upper surface of the semiconductor layer, and a gate electrode is provided in contact with the upper surface of the gate insulating layer. The gate electrode is provided so as to have a region that overlaps with the opening. Within the opening, the semiconductor layer has a region that faces the gate electrode via the gate insulating layer.

[0056] Here, either the source electrode or the drain electrode of the first transistor can also function as either the source electrode or the drain electrode of the second transistor. In other words, the first transistor and the second transistor can share either their source electrode or drain electrode.

[0057] Furthermore, the semiconductor layer that functions as the channel formation region of the first transistor can also function as the semiconductor layer that functions as the channel formation region of the second transistor. In other words, the first transistor and the second transistor can share the semiconductor layer that functions as the channel formation region of the other.

[0058] Furthermore, the insulating layer that functions as the gate insulating layer of the first transistor can also function as the gate insulating layer of the second transistor. In other words, the first transistor and the second transistor can share each other's gate insulating layers.

[0059] Furthermore, the conductive layer (or semiconductor layer) that functions as the gate electrode of the first transistor can also function as the gate electrode of the second transistor. In other words, the first transistor and the second transistor can share each other's gate electrodes.

[0060] In other words, the first transistor and the second transistor can be said to be connected in series with each other. A configuration in which two transistors are connected in series can be considered equivalent to a single transistor whose channel length is the sum of the channel lengths of the two transistors. Therefore, by connecting the first and second transistors in series, the overall channel length of the transistor can be made longer than in the case of using only one transistor, and the current saturation can be improved (i.e., the change in current in the saturation region of the transistor's drain current (Id) - drain voltage (Vd) characteristic can be reduced).

[0061] For example, by applying a first transistor and a second transistor connected in series to a drive transistor included in the pixel circuit of a display device using an organic EL device, a drive transistor with excellent current saturation can be created. This stabilizes the luminescence brightness of the light-emitting device, thereby enabling the realization of a display device with extremely low display uniformity.

[0062] Furthermore, the other of the source or drain electrode of the third transistor can also function as the gate electrode of the first and second transistors. In other words, the other of the source or drain electrode of the third transistor is connected to the gate electrodes of the first and second transistors.

[0063] For example, a conductive layer that functions as either the source electrode or the drain electrode of a third transistor can be extended and used as the gate electrode of an adjacent second transistor and a first transistor facing the second transistor.

[0064] Alternatively, for example, the semiconductor layer of the third transistor can be extended and used as the gate electrode for the adjacent second transistor and the first transistor facing the second transistor.

[0065] Thus, in a semiconductor device according to one aspect of the present invention, the first transistor and the second transistor can share some of their components with each other. Furthermore, some of the components of the third transistor can be shared with the first transistor and the second transistor, respectively. Therefore, the number of manufacturing steps for the entire semiconductor device can be reduced compared to the case where each transistor is manufactured independently.

[0066] Furthermore, in a semiconductor device according to one aspect of the present invention, one of the source electrodes or drain electrodes of the first transistor and the second transistor, and one of the source electrodes or drain electrodes of the third transistor, can be arranged with a second insulating layer in between, so that they overlap. For example, a second insulating layer can be provided on a conductive layer that functions as one of the source electrodes or drain electrodes of the third transistor, and a conductive layer (or semiconductor layer) that functions as one of the source electrodes or drain electrodes of the first transistor and the second transistor can be provided on the second insulating layer so that it overlaps with the conductive layer. This reduces the overall occupied area of ​​the semiconductor device compared to the case where each transistor is arranged so that they do not overlap.

[0067] Furthermore, for example, when an oxide semiconductor is used for the semiconductor layer that functions as the channel formation region of the first transistor and the second transistor, the region of the oxide semiconductor that comes into contact with the second insulating layer can be made to have low resistance by using a material containing impurities (e.g., water and hydrogen) that lower the electrical resistance of the oxide semiconductor layer as the second insulating layer. This allows the region with reduced resistance to function as either the source electrode or the drain electrode of the first transistor and the second transistor, respectively.

[0068] In this case, the oxide semiconductor will have both regions that function as channel formation regions for the first and second transistors, and regions that function as either the source electrode or the drain electrode. Therefore, it will not be necessary to separately provide a conductive layer that functions as either the source electrode or the drain electrode for the first and second transistors, and the number of manufacturing steps for the entire semiconductor device can be further reduced.

[0069] In this way, by configuring the first to third transistors as described above, it is possible to realize an extremely compact semiconductor device with high integration density and excellent electrical characteristics.

[0070] For example, by using a semiconductor device according to one aspect of the present invention in the pixel circuit of a display device, an extremely high-definition and high-quality display device can be realized.

[0071] In the following section, a specific example of the configuration of a semiconductor device according to one aspect of the present invention will be described with reference to the drawings.

[0072] <Example of Semiconductor Device Configuration 1> Figure 1A shows a plan view (also called a top view) of the semiconductor device 100A. Figure 1B shows a cross-sectional view along the dashed line A1-A2 shown in Figure 1A. Figure 4A shows an equivalent circuit diagram of the semiconductor device 100A. Note that in Figure 1A, some components of the semiconductor device 100A (such as the insulating layer) are omitted. In subsequent drawings of semiconductor devices, some components may also be omitted in plan views, similar to Figure 1A.

[0073] The semiconductor device 100A is provided on a substrate 102. Although not shown in Figure 1B, etc., an insulating layer that functions as an underlay can also be provided between the substrate 102 and the semiconductor device 100A. The semiconductor device 100A includes a transistor 10A1, a transistor 10A2_1, a transistor 10A2_2, an insulating layer 110 (insulating layer 110a, insulating layer 110b, and insulating layer 110c), and an insulating layer 109.

[0074] Transistor 10A1 and transistor 10A2_1 are provided adjacent to each other. Also, transistor 10A2_1 and transistor 10A2_2 are provided adjacent to each other.

[0075] Transistor 10A2_1 and transistor 10A2_2 can share components with each other. Transistor 10A1 can also share some components with transistor 10A2_1 and transistor 10A2_2, respectively.

[0076] Furthermore, transistor 10A1, transistor 10A2_1, and transistor 10A2_2 can be arranged such that parts of their components overlap.

[0077] The transistor 10A1 has a conductive layer 104, an insulating layer 106_1, a semiconductor layer 108_1, a conductive layer 112a1, and a conductive layer 112b1. The conductive layer 104 functions as a gate electrode. A portion of the insulating layer 106_1 functions as a gate insulating layer. The conductive layer 112a1 functions as either a source electrode or a drain electrode. The conductive layer 112b1 functions as either a source electrode or a drain electrode. Of the semiconductor layer 108_1, the entire region that overlaps with the gate electrode via the gate insulating layer between the source electrode and the drain electrode functions as a channel forming region. Furthermore, of the semiconductor layer 108_1, the region in contact with the source electrode functions as a source region, and the region in contact with the drain electrode functions as a drain region.

[0078] The above description relating to transistor 10A1 can be applied to transistor 10A2_1 by replacing the conductive layer 104, insulating layer 106_1, semiconductor layer 108_1, conductive layer 112a1, and conductive layer 112b1 with conductive layer 112b1, insulating layer 106_2, semiconductor layer 108_2, conductive layer 112a2, and conductive layer 112b2_2, respectively.

[0079] Similarly, the above explanation relating to transistor 10A1 can be applied to transistor 10A2_2 by replacing the conductive layer 104, insulating layer 106_1, semiconductor layer 108_1, conductive layer 112a1, and conductive layer 112b1 with conductive layer 112b1, insulating layer 106_2, semiconductor layer 108_2, conductive layer 112a2, and conductive layer 112b2_2, respectively.

[0080] In other words, the conductive layer 112a2 functions as either the source electrode or the drain electrode of transistor 10A2_1, and can also function as either the source electrode or the drain electrode of transistor 10A2_2. The semiconductor layer 108_2 functions as the channel formation region of transistor 10A2_1, and can also function as the channel formation region of transistor 10A2_2. The insulating layer 106_2 functions as the gate insulating layer of transistor 10A2_1, and can also function as the gate insulating layer of transistor 10A2_2. The conductive layer 112b1 functions as either the source electrode or the drain electrode of transistor 10A1, and can also function as the gate electrodes of transistors 10A2_1 and 10A2_2, respectively.

[0081] Therefore, transistor 10A2_1 and transistor 10A2_2 can be said to be connected in series with each other. Transistors 10A2_1 and 10A2_2 connected in series can be considered as a single transistor whose channel length is the sum of the channel lengths of each transistor. Since this single transistor has a longer channel length than both transistor 10A2_1 and transistor 10A2_2, it can be a transistor with higher current saturation than both transistor 10A2_1 and transistor 10A2_2.

[0082] Furthermore, the three transistors constituting the semiconductor device 100A (transistor 10A1, transistor 10A2_1, and transistor 10A2_2) can share some of their respective components with each other. Therefore, the number of manufacturing steps for the entire semiconductor device can be reduced compared to manufacturing each transistor independently.

[0083] The detailed configuration of the semiconductor device 100A will now be explained.

[0084] A conductive layer 112a1 is provided on the substrate 102. An insulating layer 109 is provided on the conductive layer 112a1. A conductive layer 112a2 is provided on the insulating layer 109. An insulating layer 110a is provided on the conductive layer 112a2 and the insulating layer 109. An insulating layer 110b is provided on the insulating layer 110a. An insulating layer 110c is provided on the insulating layer 110b. Conductive layers 112b2_1 and 112b2_2 are provided on the insulating layer 110c, respectively. Note that insulating layers 110a, 110b, and 110c are sometimes collectively referred to as insulating layer 110.

[0085] The conductive layer 112a2, insulating layer 110a, insulating layer 110b, insulating layer 110c, and conductive layer 112b2_1 have overlapping regions (first regions). In the first region, insulating layers 110a, 110b, and 110c have regions sandwiched between conductive layer 112a2 and conductive layer 112b2_1.

[0086] Similarly, the conductive layer 112a2, insulating layer 110a, insulating layer 110b, insulating layer 110c, and conductive layer 112b2_2 have overlapping regions (second regions). In the second region, insulating layers 110a, 110b, and 110c have regions sandwiched between the conductive layer 112a2 and the conductive layer 112b2_2.

[0087] Between the first region and the second region, there is a region (groove 137) where the insulating layer 110 is not provided. The groove 137 is provided so as to reach the conductive layer 112a2. Within the groove 137, the side surface of the insulating layer 110 in the first region (first side surface) and the side surface of the insulating layer 110 in the second region (second side surface) face each other.

[0088] Furthermore, the first side surface and the side surface of the conductive layer 112b2_1 are in approximate agreement, and the second side surface and the side surface of the conductive layer 112b2_2 are in approximate agreement.

[0089] A semiconductor layer 108_2 is provided on the groove 137. The semiconductor layer 108_2 is provided so as to straddle the groove 137 in a plan view. The semiconductor layer 108_2 has regions that are in contact with the upper surface, first side surface, second side surface of the conductive layer 112a2 within the groove 137, the side surface of the conductive layer 112b2_1 within the groove 137, the side surface of the conductive layer 112b2_2 within the groove 137, the upper surface of the conductive layer 112b2_1, and the upper surface of the conductive layer 112b2_2, respectively.

[0090] Although Figure 1B and other figures show a configuration in which the semiconductor layer 108_2 is in contact with the upper surface of the conductive layer 112b2_1 and the upper surface of the conductive layer 112b2_2, this is not limited to this configuration. Preferably, the semiconductor layer 108_2 has regions that are in contact with at least the side surfaces of the conductive layer 112b2_1 and the side surfaces of the conductive layer 112b2_2 that are opposite to each other. This makes it possible to suppress the formation of steps on the conductive layer 112b2_1 and the conductive layer 112b2_2, respectively, due to the edges of the semiconductor layer 108_2. Therefore, the coverage of the film (for example, the insulating layer 106_2) whose surface is the upper surface of the conductive layer 112b2_1 and the upper surface of the conductive layer 112b2_2 can be improved.

[0091] On the other hand, by using the configuration shown in Figure 1B, the contact area between the semiconductor layer 108_2 and the conductive layer 112b2_1, and the contact area between the semiconductor layer 108_2 and the conductive layer 112b2_2 can be increased, which may allow for an increase in the on-current of transistors 10A2_1 and 10A2_2. Furthermore, delamination of the semiconductor layer 108_2 can be suppressed.

[0092] An insulating layer 106_2 is provided on the semiconductor layer 108_2. The insulating layer 106_2 has regions that are in contact with the upper and side surfaces of the semiconductor layer 108_2, the upper and side surfaces of the conductive layer 112b2_1, the upper and side surfaces of the conductive layer 112b2_2, and the upper surface of the insulating layer 110, respectively.

[0093] A conductive layer 112b1 is provided on the insulating layer 106_2 such that it has a region that overlaps with the semiconductor layer 108_2. The conductive layer 112b1 has a region that faces the first side surface region of the semiconductor layer 108_2 via the insulating layer 106_2, and also has a region that faces the second side surface region of the semiconductor layer 108_2.

[0094] In Figure 1B, etc., the thickness of the conductive layer 112a2 in the region overlapping with the groove 137 is shown to be approximately equal to the thickness of the region not overlapping with the groove 137, but this is not limited to this configuration. The thickness of the conductive layer 112a2 in the region overlapping with the groove 137 can also be thinner than the thickness of the region not overlapping with the groove 137.

[0095] In this case, the electric field from the conductive layer 112b1 (i.e., the gate electric field of transistor 10A2_1 and the gate electric field of transistor 10A2_2) can be applied to the channel formation region of the semiconductor layer 108_2 near the conductive layer 112a2. Therefore, the effect of the gate electric field on carriers in the channel formation region can be strengthened compared to when the thickness of the conductive layer 112a2 is uniform.

[0096] Furthermore, the conductive layer 112b1 can also be formed to embed the groove 137. For example, depending on the depth of the groove 137 or the width of the groove 137 in a plan view (specifically, when the aspect ratio of the groove 137 is small), the conductive layer 112b1 may be formed to be embedded in the groove 137. In this case, the step or unevenness formed on the upper surface of the conductive layer 112b1 in the region overlapping with the groove 137 is reduced, which is preferable because it improves the coverage of the layer formed on top of it.

[0097] In the regions of the insulating layer 109, insulating layer 110, insulating layer 106_2, and conductive layer 112b1 that do not overlap with conductive layer 112a2, an opening 144 reaching the conductive layer 112a1 is provided.

[0098] The top surface shape of the opening 144 can be, for example, circular or elliptical. The top surface shape of the opening 144 can also be a polygon such as a triangle, quadrilateral (including rectangle, rhombus, and square), pentagon, or a polygon with rounded corners. As shown in Figure 1A, the top surface shape of the opening 144 is preferably circular. By making the top surface shape of the opening 144 circular, the processing accuracy when forming the opening 144 can be improved, and a fine-sized opening 144 can be formed. In this specification, the term "circular" is not limited to a perfect circle.

[0099] A semiconductor layer 108_1 is provided on the opening 144. The semiconductor layer 108_1 is provided so as to encompass the opening 144 in a plan view. The semiconductor layer 108_1 has regions that are in contact with the upper surface of the conductive layer 112a1, the side surface of the insulating layer 109, the side surface of the insulating layer 110, the side surface of the insulating layer 106_2, the side surface of the conductive layer 112b1, and the upper surface of the conductive layer 112b1 within the opening 144.

[0100] Although Figure 1B and other figures show a configuration in which the semiconductor layer 108_1 is in contact with the upper surface of the conductive layer 112b1, this is not limited to this configuration. Preferably, the semiconductor layer 108_1 has at least a region in contact with the side surface of the conductive layer 112b1. This makes it possible to suppress the formation of a step on the conductive layer 112b1 by the edge of the semiconductor layer 108_1. Therefore, the coverage of the film (for example, the insulating layer 106_1) whose surface is the upper surface of the conductive layer 112b1 can be improved.

[0101] On the other hand, by using the configuration shown in Figure 1B, etc., the contact area between the semiconductor layer 108_1 and the conductive layer 112b1 can be increased, which may allow for an increase in the on-current of the transistor 10A1. Furthermore, delamination of the semiconductor layer 108_1 can be suppressed.

[0102] An insulating layer 106_1 is provided on the semiconductor layer 108_1. The insulating layer 106_1 has regions that are in contact with the upper and side surfaces of the semiconductor layer 108_1, the upper and side surfaces of the conductive layer 112b1, and the upper surface of the insulating layer 106_2, respectively.

[0103] A conductive layer 104 is provided on the insulating layer 106_1 such that it has a region that overlaps with the semiconductor layer 108_1. Within the opening 144, the conductive layer 104 has a region that faces the semiconductor layer 108_1 via the insulating layer 106_1.

[0104] Note that while Figure 1B and other figures show a configuration where the film thickness in the region of the conductive layer 112a1 overlapping with the opening 144 is approximately equal to the film thickness in the region not overlapping with the opening 144, this is not limited to this configuration. It is also possible to have a configuration where the film thickness in the region of the conductive layer 112a1 overlapping with the opening 144 is thinner than the film thickness in the region not overlapping with the opening 144.

[0105] In this case, the electric field from the conductive layer 104 (i.e., the gate electric field of transistor 10A1) can be applied to the channel formation region of the semiconductor layer 108_1 near the conductive layer 112a1. Therefore, the effect of the gate electric field on carriers in the channel formation region can be strengthened compared to when the thickness of the conductive layer 112a1 is uniform.

[0106] Furthermore, the conductive layer 104 can also be formed to embed the opening 144. For example, depending on the depth of the opening 144 or the size of its diameter in a plan view (specifically, when the aspect ratio of the opening 144 is small), the conductive layer 104 may be formed to be embedded in the opening 144. In this case, the step or unevenness formed on the upper surface of the conductive layer 104 in the region overlapping with the opening 144 is reduced, which is preferable because it improves the coverage of the layer formed on top of it.

[0107] Here, it is preferable that the insulating layer 110b of the insulating layer 110 is an insulating layer containing oxygen. Furthermore, it is preferable that it is an insulating layer that releases oxygen upon heating. This allows, for example, when metal oxides are used for semiconductor layer 108_1 and semiconductor layer 108_2, the oxygen contained in the insulating layer 110b can be supplied to the metal oxide. This allows oxygen deficiencies in the metal oxide to be repaired, thereby improving the electrical characteristics and reliability of transistors 10A1, 10A2_1, and 10A2_2, respectively.

[0108] On the other hand, it is preferable that insulating layer 110a and insulating layer 110c of the insulating layer 110 are insulating layers that have barrier properties against gases such as oxygen and hydrogen. This makes it possible to suppress the release of oxygen contained in insulating layer 110b to the outside through insulating layer 110a or insulating layer 110c.

[0109] In this specification, "barrier property" refers to the function of suppressing the diffusion of the corresponding substance (also known as low permeability), or the function of capturing or fixing the corresponding substance (also known as gettering). In this specification, "barrier film" refers to a film that has barrier properties. In this specification, "barrier insulating layer" refers to an insulating layer that has barrier properties.

[0110] Furthermore, it is possible to suppress the diffusion of hydrogen from outside the insulating layer 110 into the insulating layer 110b via the insulating layer 110a or insulating layer 110c, and the diffusion of said hydrogen into the semiconductor layer 108_1 and semiconductor layer 108_2. For example, when metal oxides are used for semiconductor layer 108_1 and semiconductor layer 108_2, hydrogen in the semiconductor layer can be a factor that degrades the electrical characteristics and reliability of transistors 10A1, 10A2_1, and 10A2_2.

[0111] For example, when hydrogen diffuses into semiconductor layer 108_1 and semiconductor layer 108_2, the hydrogen reacts with oxygen bonded to metal atoms to form water, creating oxygen vacancies (V) in semiconductor layer 108_1 and semiconductor layer 108_2. ＯIn some cases, an oxygen vacancy may be formed. Furthermore, a defect in which hydrogen enters the oxygen vacancy (hereinafter referred to as V) may form. Ｏ (Denoted as H.) Hydrogen functions as a donor, and electrons, which are carriers, may be generated. Therefore, if hydrogen diffuses into semiconductor layer 108_1 and semiconductor layer 108_2, transistors 10A1, 10A2_1, and 10A2_2 may become normally-on, and their reliability may deteriorate. Accordingly, by having insulating layer 110a and insulating layer 110c, the above-mentioned problems in transistors 10A1, 10A2_1, and 10A2_2 can be suppressed.

[0112] Furthermore, it is preferable that the insulating layer 109 provided between the conductive layer 112a1, which functions as either the source electrode or the drain electrode of transistor 10A1, and the conductive layer 112a2, which functions as either the source electrode or the drain electrode of transistors 10A2_1 and 10A2_2, is an insulating layer having the same properties as the insulating layers 110a and 110c described above. That is, it is preferable that it is an insulating layer that has barrier properties against gases such as oxygen and hydrogen. This prevents oxygen contained in the insulating layer 109 itself from diffusing into the conductive layers 112a1 and 112a2 that are in contact with the insulating layer 109, thereby preventing the conductive layers from being oxidized and becoming highly resistive.

[0113] In each of the transistors 10A1, 10A2_1, and 10A2_2, the source electrode and drain electrode are positioned at different heights relative to the surface of the substrate 102, which is the surface on which the semiconductor device 100A is formed, and the drain current flows perpendicular to the surface of the substrate 102. In other words, in each of the transistors 10A1, 10A2_1, and 10A2_2, the drain current flows in the vertical direction. Therefore, a transistor according to one aspect of the present invention can be called a vertical transistor, a vertical channel transistor, or a VFET (Vertical Field Effect Transistor).

[0114] Since transistors 10A1, 10A2_1, and 10A2_2 can all have their source and drain electrodes stacked on top of each other, they can be miniaturized compared to so-called planar transistors where the source and drain electrodes are arranged on the same plane. Furthermore, the area occupied by the transistors on the substrate can be significantly reduced.

[0115] Furthermore, in a semiconductor device 100A according to one aspect of the present invention, the conductive layer 112a1, which functions as either the source electrode or the drain electrode of transistor 10A1, and the conductive layer 112a2, which functions as either the source electrode or the drain electrode of transistors 10A2_1 and 10A2_2, can be arranged so as to have overlapping regions. This allows transistors 10A1, 10A2_1, and 10A2_2 to be arranged at a closer distance from each other compared to the case where they are arranged so as not to overlap. Therefore, the overall area occupied by the semiconductor device on the substrate can be further reduced.

[0116] As described above, in one embodiment of the present invention, the semiconductor device 100A has a configuration in which transistors 10A2_1 and 10A2_2 are connected in series with some components shared. Therefore, the combination of transistors 10A2_1 and 10A2_2 can be considered as a single transistor whose channel length is the sum of the channel lengths of the respective transistors. This makes it possible to make this single transistor a transistor with higher current saturation than transistors 10A2_1 and 10A2_2 individually.

[0117] For example, by applying transistors 10A2_1 and 10A2_2 to the drive transistors included in the pixel circuit of a display device using an organic EL device, it is possible to create a drive transistor with better current saturation than when only one of transistors 10A2_1 or 10A2_2 is present. This makes it possible to stabilize the luminescence brightness of the light-emitting device, thereby realizing a display device with extremely low display uniformity.

[0118] Furthermore, in one embodiment of the present invention, the conductive layer 112b1, which functions as the source electrode or drain electrode of transistor 10A1, can also function as the gate electrode of transistor 10A2_1 adjacent to transistor 10A1, and transistor 10A2_2 facing transistor 10A2_1. Therefore, the number of manufacturing steps for the entire semiconductor device can be reduced compared to the case where each transistor is manufactured independently.

[0119] The channel length and channel width of transistor 10A1 will be described below.

[0120] In the semiconductor layer 108_1, the region in contact with the conductive layer 112a1 functions as either a source region or a drain region, the region in contact with the conductive layer 112b1 functions as either a source region or a drain region, and the region between the source region and the drain region functions as a channel-forming region.

[0121] The channel length of transistor 10A1 is the distance between the source region and the drain region. In Figure 1B, the channel length L10A1 of transistor 10A1 is shown by a dashed double arrow. In Figure 1B, the distance along the semiconductor layer 108_1 in the region between the conductive layer 112a1 and the conductive layer 112b1 is shown as the channel length L10A1 of transistor 10A1.

[0122] In addition, the channel length L10A1 of transistor 10A1 may be the thickness of the insulating layer 110 in the region sandwiched between the upper surface of the conductive layer 112a1 and the lower surface of the conductive layer 112b1. Alternatively, the channel length L10A1 of transistor 10A1 may be the thickness of the insulating layer 110b. Or, the channel length L10A1 of transistor 10A1 may be the depth of the opening 144 (here, this corresponds to the sum of the thickness of the insulating layer 109, the thickness of the insulating layer 110 in the region that does not overlap with the conductive layer 112a2, the thickness of the insulating layer 106_2, and the thickness of the conductive layer 112b1).

[0123] Here, the channel length L10A1 of transistor 10A1 is determined by the thickness of the insulating layer 110, the angle θ110_1 between the surface of the semiconductor layer 108_1 within the opening 144 (here, the side surface of the insulating layer 109, the side surface of the insulating layer 110, the side surface of the insulating layer 106_2, and the side surface of the conductive layer 112b1) and the surface of the insulating layer 109 (here, the upper surface of the conductive layer 112a1), etc., and is not affected by the performance of the exposure apparatus used to manufacture the transistor. Therefore, the channel length L10A1 can be set to a value smaller than the limiting resolution of the exposure apparatus, and a transistor of a very small size can be realized.

[0124] The channel length L10A1 can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and 2.5 μm or less, 10 nm or more and 2 μm or less, 10 nm or more and 1.5 μm or less, 10 nm or more and 1.2 μm or less, 10 nm or more and 1 μm or less, 10 nm or more and 500 nm or less, 10 nm or more and 300 nm or less, 10 nm or more and 20 nm or less, 10 nm or more and 100 nm or less, 10 nm or more and 50 nm or less, 10 nm or more and 30 nm or less, or 10 nm or more and 20 nm or less. For example, the channel length L10A1 can also be 100 nm or more and 1 μm or less. By shortening the channel length L10A1, the on-current of transistor 10A1 can be increased.

[0125] The thickness of the insulating layer 110 can be, for example, 5 nm or more and less than 3 μm, 7 nm or more and 2.5 μm or less, 10 nm or more and 2 μm or less, 10 nm or more and 1.5 μm or less, 10 nm or more and 1.2 μm or less, 10 nm or more and 1 μm or less, 10 nm or more and 500 nm or less, 10 nm or more and 300 nm or less, 10 nm or more and 20 nm or less, 10 nm or more and 100 nm or less, 10 nm or more and 50 nm or less, 10 nm or more and 30 nm or less, or 10 nm or more and 20 nm or less.

[0126] The angle θ110_1 can be, for example, 30 degrees or more and less than 90 degrees, 35 degrees or more and 85 degrees or less, 40 degrees or more and 80 degrees or less, 45 degrees or more and 80 degrees or less, 50 degrees or more and 80 degrees or less, 55 degrees or more and 80 degrees or less, 60 degrees or more and 80 degrees or less, 65 degrees or more and 80 degrees or less, or 70 degrees or more and 80 degrees or less. The angle θ110_1 can also be 90 degrees. A smaller angle θ110_1 is preferable because it improves the coverage of the layer (semiconductor layer 108_1, etc.) formed along the side wall of the opening 144. On the other hand, a value closer to 90 degrees is preferable because it reduces the area occupied by the transistor on the substrate surface.

[0127] The channel width of transistor 10A1 is the length of the source region or the drain region in a plan view (Figure 1A). In other words, the channel width of transistor 10A1 is the length of the region where the semiconductor layer 108_1 and the conductive layer 112a1 are in contact, or the length of the region where the semiconductor layer 108_1 and the conductive layer 112b1 are in contact, in a plan view. Alternatively, the channel width of transistor 10A1 may be an intermediate value between the length of the region where the semiconductor layer 108_1 and the conductive layer 112a1 are in contact, and the length of the region where the semiconductor layer 108_1 and the conductive layer 112b1 are in contact, in a plan view.

[0128] Here, the channel width of transistor 10A1 is described as the circumference of the region where the semiconductor layer 108_1 and the side surface of the conductive layer 112b1 on the side of the opening 144 are in contact. In Figure 1A, the channel width W10A1 of transistor 10A1 is shown by a solid double arrow. The channel width W10A1 can also be described as the circumference of the opening 144 in a plan view.

[0129] The channel width W10A1 is determined by the shape of the top surface of the aperture 144, etc. The diameter of the aperture 144 refers to the shortest side of the smallest rectangle that circumscribes the aperture 144 in a plan view. When the aperture 144 is formed using photolithography, the diameter of the aperture 144 is greater than or equal to the limiting resolution of the exposure apparatus. This diameter is, for example, 0.20 μm or more and less than 5.0 μm. As shown in Figure 1A, if the top surface shape of the aperture 144 is circular, this diameter corresponds to the diameter of the aperture 144, and the channel width W10A1 is the value obtained by multiplying this diameter by pi (π).

[0130] Next, the channel length and channel width of transistor 10A2_2 will be described. Note that the information described below can also be applied to transistor 10A2_1 by appropriately substituting the reference numerals indicating the components of transistor 10A2_2.

[0131] The channel length of transistor 10A2_2 can be determined by appropriately substituting the components of the transistor, and the same principle described for transistor 10A1 can be applied. In Figure 1B, the channel length L10A2 of transistor 10A2_2 is shown by a dashed double arrow. The angle between the surface of the semiconductor layer 108_2 to be formed within the groove 137 (here, the side surface of the insulating layer 110 and the side surface of the conductive layer 112b2_2) and the surface of the insulating layer 110 to be formed (here, the upper surface of the conductive layer 112a2) is shown as angle θ110_2.

[0132] The channel width of transistor 10A2_2 is the length of the region where the semiconductor layer 108_2 and the conductive layer 112a2 are in contact, or the length of the region where the semiconductor layer 108_2 and the conductive layer 112b2_2 are in contact, in a plan view. Alternatively, the channel width of transistor 10A2_2 may be an intermediate value between the length of the region where the semiconductor layer 108_2 and the conductive layer 112a2 are in contact, and the length of the region where the semiconductor layer 108_2 and the conductive layer 112b2_2 are in contact, in a plan view.

[0133] Here, the channel width of transistor 10A2_2 is described as the length of the side in the region where the semiconductor layer 108_2 and the side surface of the conductive layer 112b2_2 on the groove 137 side are in contact. In Figure 1A, the channel width W10A2 of transistor 10A2_2 is indicated by a double-headed arrow.

[0134] The following describes the materials that can be used for each component of semiconductor devices.

[0135] [Semiconductor layer 108_1, semiconductor layer 108_2] The semiconductor material that can be used for semiconductor layer 108_1 and semiconductor layer 108_2 is not particularly limited. For example, a single semiconductor or a compound semiconductor can be used. For example, silicon or germanium can be used as a single semiconductor. For example, gallium arsenide and silicon germanium can be used as compound semiconductors. For example, organic materials having semiconductor properties or metal oxides having semiconductor properties (also called oxide semiconductors) can be used as compound semiconductors. In addition, these semiconductor materials can also be configured to contain impurities that function as dopants (for example, when silicon is used as the semiconductor material, typical examples include elements such as phosphorus and boron).

[0136] The crystallinity of the semiconductor material used in semiconductor layer 108_1 and semiconductor layer 108_2 is not particularly limited, and either an amorphous semiconductor or a crystalline semiconductor (single-crystal semiconductor, polycrystalline semiconductor, microcrystalline semiconductor, or semiconductor having a crystalline region in part) can be used. Using a crystalline semiconductor is preferable because it can suppress the degradation of transistor characteristics.

[0137] Semiconductor layer 108_1 and semiconductor layer 108_2 can be made of silicon. Examples of silicon include single-crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon. An example of polycrystalline silicon is low-temperature polysilicon (LTPS).

[0138] Transistors using amorphous silicon for semiconductor layers 108_1 and 108_2 can be formed on a large glass substrate and manufactured at low cost. Transistors using polycrystalline silicon for semiconductor layers 108_1 and 108_2 have high field-effect mobility and can operate at high speed. Furthermore, transistors using microcrystalline silicon for semiconductor layers 108_1 and 108_2 have higher field-effect mobility than transistors using amorphous silicon and can operate at high speed.

[0139] The semiconductor layer 108_1 and semiconductor layer 108_2 preferably have a metal oxide (oxide semiconductor) having semiconductor properties. Examples of metal oxides that can be used in semiconductor layer 108_1 and semiconductor layer 108_2 respectively include indium oxide, gallium oxide, and zinc oxide. The metal oxide preferably contains at least indium (In) or zinc (Zn). Furthermore, the metal oxide preferably contains two or three elements selected from indium, element M, and zinc. Element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, and magnesium. In particular, element M is preferably one or more selected from aluminum, gallium, yttrium, and tin. Gallium is more preferred for element M.

[0140] For semiconductor layer 108_1 and semiconductor layer 108_2, for example, indium oxide, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium tungsten oxide (In-W oxide, also written as IWO), indium aluminum zinc oxide (In-Al-Zn oxide, also written as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also written as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also written as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also written as IGAZO or IAGZO), etc. can be used. Alternatively, indium tin oxide containing silicon can be used.

[0141] For the formation of metal oxides, sputtering or atomic layer deposition (ALD) can be suitably used. However, when forming metal oxides by sputtering, the atomic ratio of the target material may differ from that of the metal oxide. In particular, with zinc, the atomic ratio of the metal oxide may be lower than that of the target material. Specifically, it may be between 40% and 90% of the zinc content in the target material.

[0142] When forming semiconductor layers 108_1 and 108_2 by ALD, it is preferable to use a film deposition method such as thermal ALD or PEALD (Plasma Enhanced ALD). Thermal ALD is preferred because it exhibits extremely high step coverage. PEALD is also preferred because, in addition to exhibiting high step coverage, it allows for low-temperature film deposition.

[0143] The composition of the metal oxides in semiconductor layers 108_1 and 108_2 significantly affects the electrical characteristics and reliability of transistors 10A1, 10A2_1, and 10A2_2.

[0144] For example, by increasing the indium content of the metal oxide, a transistor with a large on-current can be realized. Also, for example, by using metal oxides that do not contain gallium or have a low gallium content in each of the semiconductor layers 108_1 and 108_2, a transistor with high reliability against positive bias application can be made. Also, for example, by applying metal oxides with a low content of element M to each of the semiconductor layers 108_1 and 108_2, a transistor with high reliability against positive bias application can be made. Also, for example, by increasing the content of element M in the metal oxide, a transistor with high reliability against light can be made.

[0145] Details regarding the composition of the metal oxides in semiconductor layer 108_1 and semiconductor layer 108_2 will be described later.

[0146] It is preferable to use crystalline metal oxide layers for semiconductor layer 108_1 and semiconductor layer 108_2. For example, metal oxide layers having a CAAC (C-Axis Aligned Crystal) structure, a polycrystalline (poly-crystal) structure, a nanocrystalline (nc: nano-crystal) structure, etc., can be used. By using crystalline metal oxide layers for semiconductor layer 108_1 and semiconductor layer 108_2, the defect level density in semiconductor layer 108_1 and semiconductor layer 108_2 can be reduced, and a highly reliable transistor can be realized. The CAAC structure is a crystalline structure in which multiple nanocrystals (typically multiple IGZO nanocrystals) have c-axis orientation, and in the a-b plane, the multiple nanocrystals are linked without orientation. In the CAAC structure, the crystal grains are not as clearly visible in the a-b plane as in the polycrystalline structure, thus enabling the realization of a highly reliable transistor.

[0147] The higher the crystallinity of the metal oxide layers used in semiconductor layers 108_1 and 108_2, the lower the defect level density in semiconductor layers 108_1 and 108_2 can be. On the other hand, by using metal oxide layers with low crystallinity, it is possible to realize transistors that can carry large currents.

[0148] The semiconductor layer 108_1 and semiconductor layer 108_2 can each be a laminated structure of two or more metal oxide layers with different crystallinity. For example, a laminated structure can be formed of a first metal oxide layer and a second metal oxide layer provided on the first metal oxide layer, wherein the second metal oxide layer has regions with higher crystallinity than the first metal oxide layer. Alternatively, the second metal oxide layer can have regions with lower crystallinity than the first metal oxide layer. The two or more metal oxide layers in semiconductor layer 108_1 and semiconductor layer 108_2 can also have the same or substantially the same composition. By forming a laminated structure of metal oxide layers with the same composition, for example, they can be formed using the same sputtering target, thereby reducing manufacturing costs. For example, by using the same sputtering target and varying the ratio of the flow rate of oxygen gas to the total film deposition gas used during formation (hereinafter also referred to as the oxygen flow rate ratio), a laminated structure of two or more metal oxide layers with different crystallinity can be formed. Furthermore, the two or more metal oxide layers in semiconductor layer 108_1 and semiconductor layer 108_2 may have different compositions.

[0149] The thickness of semiconductor layer 108_1 and semiconductor layer 108_2 is preferably 3 nm to 100 nm, more preferably 5 nm to 100 nm, more preferably 10 nm to 100 nm, more preferably 10 nm to 70 nm, more preferably 15 nm to 70 nm, more preferably 15 nm to 50 nm, more preferably 20 nm to 50 nm, more preferably 20 nm to 40 nm, and more preferably 25 nm to 40 nm.

[0150] Here, we will explain the oxygen vacancies that may be formed in semiconductor layer 108_1 and semiconductor layer 108_2.

[0151] As described above, when oxide semiconductors are used for semiconductor layer 108_1 and semiconductor layer 108_2, hydrogen contained in the oxide semiconductor may react with oxygen bonded to metal atoms to form water, thus forming oxygen vacancies in the oxide semiconductor. Furthermore, a defect called V can form when hydrogen is added to the oxygen vacancy. Ｏ H can function as a donor, generating electrons, which are carriers. Additionally, some hydrogen can combine with oxygen atoms bonded to metal atoms, also generating electrons. Therefore, transistors using oxide semiconductors with a high hydrogen content are prone to becoming normally-on. Furthermore, because hydrogen in oxide semiconductors is easily affected by stresses such as heat and electric fields, a high hydrogen content in the oxide semiconductor may degrade the reliability of the transistor.

[0152] V Ｏ H can function as a donor in oxide semiconductors. However, it is difficult to quantitatively evaluate such defects. Therefore, in oxide semiconductors, evaluation is sometimes done using carrier concentration rather than donor concentration. Accordingly, in this specification, the carrier concentration assuming no electric field is applied may be used as a parameter for oxide semiconductors, rather than the donor concentration. In other words, "carrier concentration" as described in this specification may sometimes be rephrased as "donor concentration".

[0153] Based on the above, when oxide semiconductors are used for semiconductor layer 108_1 and semiconductor layer 108_2, the V in semiconductor layer 108_1 and semiconductor layer 108_2 Ｏ It is preferable to reduce H as much as possible to achieve high-purity intrinsic or substantially high-purity intrinsic. In this way, V Ｏ To obtain an oxide semiconductor with sufficiently reduced H, it is necessary to remove impurities such as water and hydrogen from the oxide semiconductor (sometimes referred to as dehydration and dehydrogenation treatment) and to supply oxygen to the oxide semiconductor to create oxygen vacancies (V Ｏ It is important to repair ). ＯBy using an oxide semiconductor with sufficiently reduced defects such as H in the channel formation region of a transistor, stable electrical characteristics can be imparted. In addition, the supply of oxygen to the oxide semiconductor to repair oxygen deficiencies (V Ｏ ), may be referred to as an oxygen addition treatment.

[0154] When an oxide semiconductor is used for the semiconductor layer 108_1 and the semiconductor layer 108_2, the carrier concentration of the oxide semiconductor in the region functioning as the channel formation region is preferably 1×10 １８ cm −３ or less, more preferably less than 1×10 １７ cm −３ still more preferably less than 1×10 １６ cm −３ still more preferably less than 1×10 １３ cm −３ still more preferably less than 1×10 １２ cm −３ still more preferably less than 1×10 −９ cm −３ can be used. Regarding the lower limit value of the carrier concentration of the oxide semiconductor in the region functioning as the channel formation region, there is no particular limitation. For example, it can be 1×10 −９ cm −３ .

[0155] A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has an extremely high field-effect mobility as compared with a transistor using amorphous silicon. In addition, the OS transistor has a significantly small leakage current between the source and drain in the off state (hereinafter also referred to as the off current), and can hold the charges accumulated in the capacitor connected in series with the transistor for a long period of time. In addition, by applying the OS transistor to a semiconductor device, the power consumption of the semiconductor device can be reduced.

[0156] OS transistors can be applied to display devices. To increase the luminescence brightness of a light-emitting device included in the pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of the drive transistor included in the pixel circuit. Compared to silicon transistors (hereinafter referred to as Si transistors), OS transistors have a higher breakdown voltage between the source and drain, so a higher voltage can be applied between the source and drain of an OS transistor. Therefore, by applying an OS transistor to the drive transistor of a pixel circuit, the amount of current flowing through the light-emitting device can be increased, and the luminescence brightness of the light-emitting device can be increased.

[0157] When a transistor operates in the saturation region, an OS transistor exhibits a smaller change in source-drain current in response to a change in gate-source voltage than a Si transistor. Therefore, by using an OS transistor as the driving transistor in a pixel circuit, the current flowing between the source and drain can be precisely controlled by the change in gate-source voltage, thus allowing for precise control of the current flowing to the light-emitting device. This allows for an increase in the number of grayscale levels in the pixel circuit.

[0158] In terms of the saturation characteristics of the current flowing when a transistor operates in the saturation region, OS transistors can supply a more stable current (saturation current) than Si transistors, even when the source-drain voltage gradually increases. Therefore, by using an OS transistor as a driving transistor, a stable current can be supplied to a light-emitting device, for example, even if there are variations in the current-voltage characteristics of the light-emitting device. In other words, when operating in the saturation region, the source-drain current remains almost unchanged even when the source-drain voltage is increased, thus stabilizing the luminescence brightness of the light-emitting device.

[0159] As described above, by using OS transistors in the drive transistors included in the pixel circuit, it is possible to achieve "suppression of black level floating," "increase in luminescence brightness," "multi-gradation," and "suppression of variations in light-emitting devices."

[0160] OS transistors exhibit small fluctuations in electrical properties due to radiation exposure, meaning they have high resistance to radiation, making them suitable for use in environments where radiation may be incident. OS transistors can also be said to have high reliability against radiation. For example, OS transistors can be suitably used in the pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, neutron rays, and proton rays).

[0161] [Insulating Layer] In a transistor according to one aspect of the present invention, a semiconductor device, a display device, etc. to which a transistor according to one aspect of the present invention is applied, an inorganic insulating material or an organic insulating material can be used as the insulating layer (insulating layer 109, insulating layer 110, insulating layer 106_1, and insulating layer 106_2). Furthermore, a laminated structure of an inorganic insulating material and an organic insulating material can also be used as the insulating layer.

[0162] As the inorganic insulating material, one or more oxides, oxidized nitrides, nitride oxides, and nitrides can be used.

[0163] In this specification, the term "oxide-nitride" refers to a material in which the oxygen content is greater than the nitrogen content. The term "nitride oxide" refers to a material in which the nitrogen content is greater than the oxygen content. For example, silicon oxide-nitride refers to a material in which the oxygen content is greater than the nitrogen content, and silicon nitride oxide refers to a material in which the nitrogen content is greater than the oxygen content.

[0164] For the analysis of oxygen and nitrogen content, for example, secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS) can be used. XPS is suitable when the content of the target element is high (e.g., 0.5 atomic% or more, or 1 atomic% or more). On the other hand, SIMS is suitable when the content of the target element is low (e.g., less than 0.5 atomic% or less than 1 atomic%). When comparing elemental content, it is more preferable to perform a combined analysis using both SIMS and XPS analytical methods.

[0165] Furthermore, for evaluating the film density of insulating layers, for example, Rutherford Backscattering Spectrometry (RBS) or X-ray Reflectivity (XRR) can be used. Differences in film density can also sometimes be evaluated using a cross-sectional transmission electron microscope (TEM) image. In TEM observation, a high film density results in a darker (more intense) transmission electron (TE) image, while a low film density results in a lighter (brighter) transmission electron (TE) image. Even when the same material is used for the insulating layer, differences in film density can sometimes be observed as differences in contrast at the boundaries between these densities in the cross-sectional TEM image.

[0166] The nitrogen content of an insulating layer can be confirmed, for example, by energy-dispersive X-ray spectroscopy (EDX). For example, when silicon nitride, silicon oxynitride, etc. are used for the insulating layer, the nitrogen content can be evaluated using the ratio of the peak height of nitrogen to the peak height of silicon. In EDX, the peak of a given element refers to the point where the count number of that element reaches its maximum value in a spectrum where the energy of the characteristic X-ray is shown on the horizontal axis and the count number (detection value) of the characteristic X-ray is shown on the vertical axis. Alternatively, the difference in nitrogen content can be confirmed by using the count number at the characteristic X-ray energy specific to that element and comparing it with the count number of nitrogen to the count number of silicon. For example, the count number at 1.739 keV (Si-Kα) can be used for silicon, and the count number at 0.392 keV (N-Kα) can be used for nitrogen.

[0167] The hydrogen concentration in the insulating layer can be evaluated, for example, using SIMS.

[0168] When hydrogen diffuses into semiconductor layer 108_1 and semiconductor layer 108_2, it reacts with oxygen atoms contained in the oxide semiconductor to form water, creating oxygen vacancies (V) in semiconductor layer 108_1 and semiconductor layer 108_2. Ｏ ) may be formed in semiconductor layer 108_1 and semiconductor layer 108_2. Ｏ H may be formed, and the carrier concentration in semiconductor layer 108_1 and semiconductor layer 108_2 may increase. By using a barrier film that suppresses hydrogen diffusion as an insulating layer in contact with semiconductor layer 108_1 and semiconductor layer 108_2, or as an insulating layer located around semiconductor layer 108_1 and semiconductor layer 108_2, oxygen vacancies (V) in semiconductor layer 108_1 and semiconductor layer 108_2 can be suppressed. Ｏ ) and V Ｏ This allows for a reduction in H, resulting in a transistor that exhibits good electrical characteristics and is highly reliable.

[0169] Oxygen deficiency (V) in the channel formation region of transistor 10A1, transistor 10A2_1, and transistor 10A2_2Ｏ ) and V Ｏ H is preferably low. In particular, when the channel length is short, oxygen deficiency (V) in the channel formation region is preferable. Ｏ ) and V Ｏ The effect of H on the electrical characteristics and reliability of transistors 10A1, 10A2_1, and 10A2_2 becomes significant. For example, if V flows from the source region or drain region to the channel formation region... Ｏ When H diffuses, the carrier concentration in the channel formation region increases, which may cause fluctuations in the threshold voltage of transistors 10A1, 10A2_1, and 10A2_2, or a decrease in reliability. Ｏ The effect of H diffusion on the electrical characteristics and reliability of transistors 10A1, 10A2_1, and 10A2_2 increases as the channel length decreases. Semiconductor layer 108_1 and semiconductor layer 108_2, in particular, oxygen vacancies (V) in the channel formation region. Ｏ ) and V Ｏ By reducing H, it is possible to realize transistors with short channel lengths that have good electrical characteristics and high reliability.

[0170] By using an oxygen-releasing insulating layer as an insulating layer in contact with semiconductor layer 108_1 and semiconductor layer 108_2, respectively (for example, insulating layer 106_1, insulating layer 106_2, and insulating layer 110b), oxygen can be supplied from the insulating layer to semiconductor layer 108_1 and semiconductor layer 108_2. By supplying oxygen to the channel formation regions of semiconductor layer 108_1 and semiconductor layer 108_2, oxygen vacancies (V) in semiconductor layer 108_1 and semiconductor layer 108_2 can be reduced. Ｏ ) and V Ｏ This allows for a reduction in H, resulting in a transistor that exhibits good electrical characteristics and is highly reliable. Other methods for supplying oxygen to semiconductor layers 108_1 and 108_2 include heating in an oxygen-containing atmosphere or plasma treatment in an oxygen-containing atmosphere.

[0171] It is preferable that insulating layers in contact with semiconductor layer 108_1 and semiconductor layer 108_2, or insulating layers located around semiconductor layer 108_1 and semiconductor layer 108_2, release little impurity (e.g., water and hydrogen) from themselves. The impurities referred to here are those that diffuse into semiconductor layer 108_1 and semiconductor layer 108_2, causing oxygen vacancies (V) in semiconductor layer 108_1 and semiconductor layer 108_2. Ｏ ) and V Ｏ This refers to substances that can adversely affect the electrical characteristics of a transistor, such as by generating H. By reducing the release of impurities, the diffusion of these impurities into semiconductor layer 108_1 and semiconductor layer 108_2 is suppressed, resulting in a transistor that exhibits good electrical characteristics and is highly reliable.

[0172] In processes following the formation of semiconductor layer 108_1 and semiconductor layer 108_2, heat may be applied, causing oxygen to detach from semiconductor layer 108_1 and semiconductor layer 108_2. However, oxygen is supplied to semiconductor layer 108_1 and semiconductor layer 108_2 from the insulating layer in contact with each of them, thereby preventing oxygen deficiencies (V) in semiconductor layer 108_1 and semiconductor layer 108_2. Ｏ ) and V Ｏ This makes it possible to suppress the increase in H. Furthermore, it is possible to increase the degree of freedom in the processing temperature in the process after the formation of semiconductor layer 108_1 and semiconductor layer 108_2. Specifically, the processing temperature can be increased even in the process after the formation of semiconductor layer 108_1 and semiconductor layer 108_2. Therefore, it is possible to form transistors that exhibit good electrical characteristics and are highly reliable.

[0173] [Insulating layer 110] Inorganic insulating material or organic insulating material can be used as the insulating layer 110 (insulating layer 110a, insulating layer 110b, and insulating layer 110c). The insulating layer 110 can also be a laminated structure of inorganic insulating material and organic insulating material.

[0174] As the insulating layer 110, an inorganic insulating material can be suitably used. As the inorganic insulating material, one or more oxides, oxidized nitrides, nitride oxides, and nitrides can be used. As the insulating layer 110, for example, one or more silicon oxide, silicon oxidized nitride, aluminum oxide, hafnium oxide, yttrium oxide, zirconium oxide, gallium oxide, tantalum oxide, magnesium oxide, lanthanum oxide, cerium oxide, neodymium oxide, silicon nitride, silicon nitride oxide, and aluminum nitride can be used.

[0175] The insulating layer 110 can also be a laminated structure of two or more layers. Figure 1B and others show a configuration in which the insulating layer 110 has a laminated structure of insulating layer 110a, insulating layer 110b on insulating layer 110a, and insulating layer 110c on insulating layer 110b. Note that the insulating layer 110a, insulating layer 110b, and insulating layer 110c can be made of the same material or different materials.

[0176] It is preferable that the insulating layer 110 releases little impurities (e.g., water and hydrogen) from itself.

[0177] The thickness of the insulating layer 110b can be made thicker than the thicknesses of the insulating layers 110a and 110c. As mentioned above, the insulating layer 110b is an insulating layer that contains oxygen to supply to the semiconductor layers 108_1 and 108_2. Therefore, by making the thickness of the insulating layer 110b the thickest of the three insulating layers (insulating layer 110a, insulating layer 110b, and insulating layer 110c) that make up the insulating layer 110, the amount of oxygen that the insulating layer 110 as a whole can have can be increased. It is preferable that the deposition rate of the insulating layer 110b is faster than the deposition rates of the insulating layers 110a and 110c. By increasing the deposition rate of thicker films, productivity can be increased.

[0178] The insulating layers 110a and 110c function as barrier films that suppress gas detachment from the insulating layer 110b. It is preferable to use materials that do not easily allow gas to diffuse for the insulating layers 110a and 110c. It is preferable that the insulating layers 110a and 110c have regions with a higher film density than the insulating layer 110b. By increasing the film density of the insulating layer, the barrier properties against gas can be improved. By slowing down the film deposition rate of the insulating layer, the film density can be increased, and the barrier properties against gas can be improved.

[0179] It is preferable to use an oxide or oxidized nitride as the insulating layer 110b. It is preferable to use a film that releases oxygen upon heating as the insulating layer 110b. For example, silicon oxide or silicon oxidized nitride can be suitably used as the insulating layer 110b.

[0180] The insulating layer 110b releases oxygen, which can then supply oxygen to the semiconductor layers 108_1 and 108_2. It is preferable that the insulating layer 110b has a high oxygen diffusion coefficient. A high oxygen diffusion coefficient allows oxygen to diffuse more easily through the insulating layer 110b, efficiently supplying oxygen to the semiconductor layers 108_1 and 108_2. Furthermore, as described above, by making the thickness of the insulating layer 110b thicker than the thicknesses of the insulating layers 110a and 110c, more oxygen can be supplied to the semiconductor layers 108_1 and 108_2.

[0181] The insulating layer 110 is preferably formed by a film deposition method such as sputtering, ALD, or plasma CVD (Chemical Vapor Deposition).

[0182] In particular, by using the sputtering method and a film deposition method that does not use a hydrogen-containing gas as the deposition gas, it is possible to create a film with an extremely low hydrogen content. Therefore, the supply of hydrogen to semiconductor layer 108_1 and semiconductor layer 108_2 is suppressed, and the electrical characteristics of transistors 10A1, 10A2_1, and 10A2_2 can be stabilized. When depositing silicon oxide by sputtering, for example, the film can be deposited using a silicon target in an atmosphere containing an oxygen-containing gas. Similarly, when depositing silicon nitride by sputtering, for example, the film can be deposited using a silicon target in an atmosphere containing a nitrogen-containing gas. Furthermore, when depositing aluminum oxide by sputtering, for example, the film can be deposited using an aluminum target in an atmosphere containing an oxidizing gas.

[0183] Furthermore, silicon oxide and silicon nitride can be deposited using, for example, the PEALD method. Aluminum oxide and hafnium oxide can also be deposited using, for example, the thermal ALD method. By depositing an insulating layer using the PEALD method and the thermal ALD method, a dense insulating film can be formed, thereby improving barrier properties against oxygen and hydrogen.

[0184] Each of the insulating layers 110a and 110c can be made of a material with a higher nitrogen content than insulating layer 110b. By increasing the nitrogen content of the insulating layer, the barrier properties against oxygen and hydrogen can be enhanced.

[0185] Furthermore, each of the insulating layer 110a and insulating layer 110c may have regions where the hydrogen concentration in the film is lower than that of insulating layer 110b.

[0186] It is preferable that insulating layers 110a and 110c are impermeable to oxygen. Furthermore, it is preferable that insulating layers 110a and 110c are impermeable to hydrogen. Insulating layers 110a and 110c function as barrier films that suppress the diffusion of hydrogen from outside the transistor to semiconductor layers 108_1 and 108_2. It is preferable that the film density of insulating layer 110a and insulating layer 110c is higher than the film density of insulating layer 110b. By increasing the film density of the insulating layers, the barrier properties against oxygen and hydrogen can be improved. When silicon oxide or silicon oxide nitride is used for insulating layer 110b, silicon nitride or silicon nitride oxide can be used for insulating layer 110a and insulating layer 110c, respectively. In addition, hafnium oxide or aluminum oxide can be suitably used as insulating layer 110a and insulating layer 110c, respectively.

[0187] Furthermore, the insulating layer 110a and insulating layer 110c can be constructed by laminating two or more materials selected from silicon nitride, silicon oxide nitride, hafnium oxide, and aluminum oxide, respectively.

[0188] If oxygen contained in the insulating layer 110b diffuses downward (towards the substrate 102), the amount of oxygen supplied from the insulating layer 110b to the semiconductor layers 108_1 and 108_2 may decrease. By providing an insulating layer 110a below the insulating layer 110b, the diffusion of oxygen contained in the insulating layer 110b downward can be suppressed. Similarly, if oxygen contained in the insulating layer 110b diffuses upward from the insulating layer 110b, the amount of oxygen supplied from the insulating layer 110b to the semiconductor layers 108_1 and 108_2 may decrease. By providing an insulating layer 110c above the insulating layer 110b, the diffusion of oxygen contained in the insulating layer 110b upward can be suppressed. Therefore, the amount of oxygen supplied from the insulating layer 110b to the semiconductor layer 108_1 and semiconductor layer 108_2 increases, resulting in oxygen deficiencies (V) in semiconductor layer 108_1 and semiconductor layer 108_2. Ｏ ) and V Ｏ H can be reduced.

[0189] Furthermore, by providing insulating layers 110a and 110c, the diffusion of hydrogen into semiconductor layers 108_1 and 108_2 is suppressed, and oxygen vacancies (V) in semiconductor layer 108_1 and semiconductor layer 108_2 are reduced. Ｏ ) and V Ｏ H can be reduced.

[0190] The insulating layer 110a and insulating layer 110c are preferably of a thickness that functions as a barrier film for oxygen and hydrogen. If the film thickness is too thin, the barrier function may be reduced. On the other hand, if the film thickness is too thick, the region of semiconductor layer 108_1 and semiconductor layer 108_2 that are in contact with insulating layer 110b becomes narrower, which may reduce the amount of oxygen supplied to semiconductor layer 108_1 and semiconductor layer 108_2. The film thickness of insulating layer 110a and insulating layer 110c is preferably 1 nm to 200 nm, 1 nm to 100 nm, 1 nm to 60 nm, 1 nm to 50 nm, 1 nm to 40 nm, 1 nm to 30 nm, 1 nm to 20 nm, 1 nm to 10 nm, 1 nm to 5 nm, or 2 nm to 5 nm, respectively.

[0191] [Insulating layer 106_1, insulating layer 106_2] It is preferable that insulating layers 106_1 and 106_2, which function as gate insulating layers, have a low defect density. A low defect density in insulating layers 106_1 and 106_2 allows for the creation of a transistor with good electrical characteristics. Furthermore, it is preferable that insulating layers 106_1 and 106_2 have a high dielectric breakdown voltage. A high dielectric breakdown voltage in insulating layers 106_1 and 106_2 allows for the creation of a highly reliable transistor.

[0192] Furthermore, it is preferable that insulating layer 106_1 and insulating layer 106_2 are insulating layers containing oxygen. It is also preferable that they are insulating layers that release oxygen upon heating. This allows, for example, when metal oxides are used for semiconductor layer 108_1 and semiconductor layer 108_2, to supply oxygen from insulating layer 106_1 and insulating layer 106_2 to the metal oxide. This allows for the repair of oxygen deficiencies in the metal oxide, thereby improving the electrical characteristics and reliability of transistors 10A1, 10A2_1, and 10A2_2.

[0193] For each of the insulating layers 106_1 and 106_2, one or more insulating oxides, oxidized nitrides, nitride oxides, and nitrides can be used. For each of the insulating layers 106_1 and 106_2, one or more silicon oxides, silicon oxidized nitrides, silicon oxide nitrides, silicon nitrides, aluminum oxides, aluminum oxidized nitrides, aluminum oxides, aluminum nitrides, hafnium oxide, hafnium oxidized nitrides, gallium oxide, gallium oxidized nitrides, yttrium oxide, yttrium oxidized nitride, and Ga-Zn oxide can be used. Each of the insulating layers 106_1 and 106_2 can be a single layer or a laminate. Each of the insulating layers 106_1 and 106_2 can also have a laminated structure of oxides and nitrides, for example.

[0194] In miniature transistors, if the thickness of the gate insulating layer becomes too thin, the leakage current may increase. By using a material with a high dielectric constant (also called a high-k material) for the gate insulating layer, it is possible to lower the voltage during transistor operation while maintaining the physical thickness. Examples of high-k materials include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxides containing aluminum and hafnium, oxides containing silicon and hafnium, oxides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0195] It is preferable that insulating layers 106_1 and 106_2 release little impurities (e.g., water and hydrogen) from themselves. By reducing the release of impurities from insulating layers 106_1 and 106_2, the diffusion of such impurities into semiconductor layers 108_1 and 108_2 is suppressed, resulting in a transistor that exhibits good electrical characteristics and is highly reliable.

[0196] Since the insulating layer 106_1 is formed on the semiconductor layer 108_1 and the insulating layer 106_2 is formed on the semiconductor layer 108_2, it is preferable that the films be formed under conditions that minimize damage to the semiconductor layer 108_1 and the semiconductor layer 108_2. For example, it is preferable to form them under conditions where the deposition rate (also called the deposition rate) is sufficiently slow. For example, when forming the insulating layer 106_1 and the insulating layer 106_2 by plasma CVD, forming them under low power conditions can reduce the damage to the semiconductor layer 108_1 and the semiconductor layer 108_2.

[0197] Here, we will specifically explain insulating layers 106_1 and 106_2, using a configuration in which metal oxides are used for semiconductor layers 108_1 and 108_2 as an example.

[0198] To improve the interfacial properties with semiconductor layer 108_1 and semiconductor layer 108_2, it is preferable to use one or more oxides and oxidized nitrides on at least the side of insulating layer 106_1 that contacts semiconductor layer 108_1, and on at least the side of insulating layer 106_2 that contacts semiconductor layer 108_2. For insulating layer 106_1 and insulating layer 106_2, for example, one or more silicon oxide and silicon oxidized nitride can be suitably used. Furthermore, it is even more preferable to use films that release oxygen upon heating for insulating layer 106_1 and insulating layer 106_2.

[0199] Furthermore, as shown in Figure 1B, the insulating layer 106_1, which functions as a gate insulating layer for transistor 10A1, is provided so as to cover transistors 10A2_1 and 10A2_2, and therefore can also function as a protective layer for transistors 10A2_1 and 10A2_2. For this reason, it is preferable to use a material for the insulating layer 106_1 that does not easily allow impurities to diffuse. By having the insulating layer 106_1 function as a protective layer, the diffusion of impurities from the outside into transistors 10A2_1 and 10A2_2 can be effectively suppressed, thereby improving the reliability of transistors 10A2_1 and 10A2_2. Examples of impurities include water and hydrogen. For example, inorganic materials such as oxides, oxidized nitrides, nitride oxides, or nitrides can be suitably used for the insulating layer 106_1. More specifically, one or more of silicon nitride, silicon nitride oxide, silicon oxidized nitride, aluminum oxide, aluminum oxidized nitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used. Furthermore, the above material can also be applied to the insulating layer 106_2.

[0200] The insulating layer 106_1 and the insulating layer 106_2 can each be configured as a laminated structure. The insulating layer 106_1 can be configured as a laminated structure of an oxide film or oxynitride film on the side in contact with the semiconductor layer 108_1 and a nitride film on the side in contact with the conductive layer 104. Similarly, the insulating layer 106_2 can be configured as a laminated structure of an oxide film or oxynitride film on the side in contact with the semiconductor layer 108_2 and a nitride film on the side in contact with the conductive layer 112b1. For example, silicon oxide and silicon oxynitride can be suitably used as the oxide film or the oxynitride film. For example, silicon nitride can be suitably used as the nitride film.

[0201] It is even more preferable that the film thickness of insulating layer 106_1 and insulating layer 106_2 be between 1 nm and 100 nm. It is preferable that insulating layer 106_1 and insulating layer 106_2 each have at least a portion of the above-mentioned film thickness region.

[0202] [Insulating layer 109] The insulating layer 109 provided between the conductive layer 112a1 and the conductive layer 112a2 can be made of the same material that can be used for the insulating layer 110 described above. In particular, it is preferable to use the same material that can be used for the insulating layer 110a and the insulating layer 110c. This makes it possible to suppress the oxidation of the conductive layer 112a1 and the conductive layer 112a2, which have regions in contact with the insulating layer 109, by the oxygen contained in the insulating layer 109, thereby preventing them from becoming highly resistive.

[0203] Furthermore, when metal oxides are used for conductive layers 112a1 and 112a2, an insulating material that releases impurities such as hydrogen can be used as the insulating layer 109. In this case, the impurities released from the insulating layer 109 diffuse through conductive layers 112a1 and 112a2, causing the conductive layers to contain impurities. This increases the carrier concentration of the conductive layer, thereby lowering its electrical resistance. In addition, since the conductive layer can function as wiring, a semiconductor device 100A with low wiring resistance can be realized. The impurities that lower the electrical resistance of the conductive layer can be the same as the impurities that lower the electrical resistance of semiconductor layers 108_1 and 108_2. Alternatively, these impurities can have different configurations. It is more preferable that the conductive layer is permeable to impurities. It is more preferable that the conductive layer is less likely to adsorb impurities.

[0204] The thickness of the insulating layer 109 is preferably, for example, 5 nm to 100 nm, more preferably 10 nm to 100 nm, more preferably 20 nm to 100 nm, and more preferably 20 nm to 50 nm.

[0205] If the thickness of the insulating layer 109 is too high and the amount of impurities released from the insulating layer 109 becomes too large, the amount of impurities that diffuse into the semiconductor layer 108_1 and semiconductor layer 108_2 will increase, resulting in oxygen vacancies (V) generated by these impurities. Ｏ ) and V Ｏ The amount of H is the oxygen deficiency (V) that is repaired by the oxygen supplied from the insulating layer 110b. Ｏ ) and V ＯThere is a risk that the amount of H will be greater than the amount of other substances. On the other hand, if the thickness of the insulating layer 109 is thin, the amount of impurities diffusing into the conductive layer 112a1, conductive layer 112a2, semiconductor layer 108_1, and semiconductor layer 108_2 will decrease, and there is a risk that the electrical resistance of the conductive layer, as well as the electrical resistance of either the source region or the drain region of each of the transistors 10A1, 10A2_1, and 10A2_2, will increase. By setting the thickness of the insulating layer 109 to the aforementioned range, the oxygen deficiency (V) in the channel formation region of the transistor can be reduced. Ｏ ) and V Ｏ This can suppress the increase in H and lower these electrical resistances. Note that the thickness of the insulating layer 109 is not limited to the range described above.

[0206] [Conductive layer 112a1, conductive layer 112b1, conductive layer 112a2, conductive layer 112b2_1, conductive layer 112b2_2] The conductive layers 112a1, 112b1, 112a2, 112b2_1, and 112b2_2, which function as source and drain electrodes, can be formed using one or more of chromium, copper, aluminum, gold, silver, zinc, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, molybdenum, and niobium, or an alloy containing one or more of the aforementioned metals. Low-resistance conductive materials containing one or more of copper, silver, gold, or aluminum can preferably be used for conductive layers 112a1, 112b1, 112a2, 112b2_1, and 112b2_2. Copper or aluminum are particularly preferred due to their excellent mass-producibility.

[0207] A metal oxide film (also called an oxide conductor) can be used for conductive layers 112a1, 112b1, 112a2, 112b2_1, and 112b2_2. Examples of oxide conductors (OC) include In-Sn oxide (ITO), In-W oxide, In-W-Zn oxide, In-Ti oxide, In-Ti-Sn oxide, In-Zn oxide, In-Sn-Si oxide (ITSO), and In-Ga-Zn oxide.

[0208] Here, we will explain oxide conductors (OCs). For example, when an oxygen vacancy is formed in a metal oxide with semiconductor properties, and hydrogen is added to the oxygen vacancy, a donor level is formed near the conduction band. As a result, the metal oxide becomes highly conductive and turns into a conductor. A metal oxide that has become conductive can be called an oxide conductor.

[0209] The conductive layers 112a1, 112b1, 112a2, 112b2_1, and 112b2_2 can also be a laminated structure of a conductive film containing the aforementioned oxide conductor (metal oxide) and a conductive film containing a metal or alloy. By using a conductive film containing a metal or alloy, the wiring resistance can be reduced.

[0210] The conductive layers 112a1, 112b1, 112a2, 112b2_1, and 112b2_2 can also be coated with a Cu-X alloy film (where X is Mn, Ni, Cr, Fe, Co, Mo, Ta, or Ti). By using a Cu-X alloy film, processing can be performed by wet etching, thus reducing manufacturing costs.

[0211] Furthermore, conductive layer 112a1 and conductive layer 112b1 can be made of the same material, or they can be made of different materials. The same applies to conductive layer 112a2, conductive layer 112b2_1, and conductive layer 112b2_2. The same also applies to conductive layer 112b2_1 and conductive layer 112b2_2.

[0212] In one embodiment of the present invention, the conductive layer 112b1 functions as the other source electrode or drain electrode of transistor 10A1, and also functions as the gate electrodes of transistors 10A2_1 and 10A2_2, respectively. Therefore, the conductive layer 112b1 can also be made of a material that can be used for the conductive layer 104 that functions as the gate electrode of transistor 10A1. The materials that can be used for the conductive layer 104 will be described in [Conductive Layer 104].

[0213] Here, we will take a configuration in which a metal oxide is used for semiconductor layer 108_1 and semiconductor layer 108_2 as an example and specifically explain conductive layer 112a1, conductive layer 112b1, conductive layer 112a2, conductive layer 112b2_1, and conductive layer 112b2_2.

[0214] When oxide semiconductors are used for semiconductor layers 108_1 and 108_2, the oxygen contained in semiconductor layers 108_1 and 108_2 may oxidize conductive layers 112a1, 112b1, 112a2, 112b2_1, and 112b2_2, potentially increasing their resistance. The oxygen contained in the insulating layer 110 may oxidize conductive layers 112a1, 112b1, 112a2, 112b2_1, and 112b2_2, potentially increasing their resistance.

[0215] Furthermore, the oxygen contained in semiconductor layer 108_1 and semiconductor layer 108_2 oxidizes conductive layer 112a1, conductive layer 112b1, conductive layer 112a2, conductive layer 112b2_1, and conductive layer 112b2_2, resulting in oxygen vacancies (V) in semiconductor layer 108_1 and semiconductor layer 108_2. Ｏ In some cases, the amount of oxygen supplied from the insulating layer 110 to the semiconductor layer 108_1 and semiconductor layer 108_2 may increase. This is because the oxygen contained in the insulating layer 110 oxidizes the conductive layer 112a1, conductive layer 112b1, conductive layer 112a2, conductive layer 112b2_1, and conductive layer 112b2_2, which may reduce the amount of oxygen supplied from the insulating layer 110 to the semiconductor layer 108_1 and semiconductor layer 108_2.

[0216] It is preferable to use materials that are resistant to oxidation for conductive layers 112a1, 112b1, 112a2, 112b2_1, and 112b2_2. It is preferable to use oxide conductors for conductive layers 112a1, 112b1, 112a2, 112b2_1, and 112b2_2. For example, In-Sn oxide (ITO) or In-Sn-Si oxide (ITSO) can be suitably used. Nitride conductors can also be used for conductive layers 112a1, 112b1, 112a2, 112b2_1, and 112b2_2. Examples of nitride conductors include tantalum nitride and titanium nitride. The conductive layers 112a1, 112b1, 112a2, 112b2_1, and 112b2_2 may also have a laminated structure of the aforementioned materials.

[0217] By using materials that are resistant to oxidation for conductive layers 112a1, 112b1, 112a2, 112b2_1, and 112b2_2, it is possible to suppress oxidation caused by oxygen contained in semiconductor layers 108_1 and 108_2, or oxygen contained in the insulating layer 110, which can increase resistance. Furthermore, oxygen vacancies (V) in semiconductor layers 108_1 and 108_2 can be suppressed. Ｏ This suppresses the increase in ), and also increases the amount of oxygen supplied from the insulating layer 110 to the semiconductor layer 108_1 and the semiconductor layer 108_2.

[0218] [Conductive Layer 104] The conductive layer 104, which functions as the gate electrode of transistor 10A1, can be formed using, for example, one or more of chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, and niobium, or an alloy composed of one or more of the aforementioned metals. The conductive layer 112b1, which functions as the gate electrode of transistor 10A2_1 and transistor 10A2_2 (and the other of the source electrode or drain electrode of transistor 10A1), can use the materials described above in [Conductive Layer 112a1, Conductive Layer 112b1, Conductive Layer 112a2, Conductive Layer 112b2_1, Conductive Layer 112b2_2]. Therefore, the conductive layer 104 can also be made using the materials that can be used for the conductive layers 112a1, 112b1, 112a2, 112b2_1, and 112b2_2. Conversely, the conductive layer 112b1 can also be made from the same material used for the conductive layer 104.

[0219] Although Figure 1B and other figures show the conductive layer 104 as a single layer, this is not limited to this. For example, the conductive layer 104 can also be a laminated structure of two or more layers. For example, when the conductive layer 104 is a two-layer laminated structure, the first conductive layer (the conductive layer on the insulating layer 106_1 side) can be made of a nitride or oxide, and the second conductive layer can be made of one or more of the following metals: chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, and niobium, or an alloy composed of one or more of the aforementioned metals. Furthermore, for example, when the conductive layer 104 has a three-layer laminated structure, the first conductive layer (the conductive layer on the insulating layer 106_1 side) can be an alloy composed of one or more of the above-mentioned metals, or a nitride of said metal or alloy; the second conductive layer can be an alloy composed of one or more of the above-mentioned metals; and the third conductive layer can be an alloy composed of one or more of the above-mentioned metals, or a nitride of said metal or alloy.

[0220] [Substrate 102] There are no major restrictions on the material of the substrate 102, but it must have at least enough heat resistance to withstand subsequent heat treatment. For example, single-crystal semiconductor substrates made of silicon or silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI (Silicon On Insulator) substrates, glass substrates, quartz substrates, sapphire substrates, ceramic substrates, or organic resin substrates can be used as the substrate 102. In addition, substrates on which semiconductor elements are provided can also be used as the substrate 102. The shape of the semiconductor substrate and insulating substrate can be circular or rectangular.

[0221] A flexible substrate can be used as the substrate 102, and the semiconductor device 100A, etc., can be formed directly on the flexible substrate. Alternatively, a release layer can be provided between the substrate 102 and the semiconductor device 100A, etc. The release layer can be used to separate the semiconductor device from the substrate 102 after it has been partially or completely completed on it, and to transfer it to another substrate. In this case, the semiconductor device 100A, etc., can be transferred to a substrate with poor heat resistance or to a flexible substrate.

[0222] [Composition of metal oxides in semiconductor layer 108_1 and semiconductor layer 108_2] The composition of metal oxides in semiconductor layer 108_1 and semiconductor layer 108_2 is described below.

[0223] The composition of the metal oxides in semiconductor layer 108_1 and semiconductor layer 108_2 significantly affects the electrical characteristics and reliability of transistor 10A1, transistor 10A2_1, and transistor 10A2_2, respectively.

[0224] For example, by increasing the indium content of the metal oxide, it is possible to realize a transistor with a large on-current.

[0225] When using In-Zn oxide for semiconductor layer 108_1 and semiconductor layer 108_2, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than the atomic ratio of zinc. For example, metal oxides with atomic ratios of metal elements of In:Zn=1:1, In:Zn=2:1, In:Zn=3:1, In:Zn=4:1, In:Zn=5:1, In:Zn=7:1, or In:Zn=10:1, or close to these, can be used.

[0226] When using In-Sn oxide for semiconductor layer 108_1 and semiconductor layer 108_2, it is preferable to use a metal oxide in which the atomic ratio of indium is equal to or greater than that of tin. For example, metal oxides with atomic ratios of metal elements of In:Sn = 1:1, In:Sn = 2:1, In:Sn = 3:1, In:Sn = 4:1, In:Sn = 5:1, In:Sn = 7:1, or In:Sn = 10:1, or close to these, can be used.

[0227] When using In-M-Zn oxide for semiconductor layer 108_1 and semiconductor layer 108_2, a metal oxide can be applied in which the atomic ratio of indium to the atomic number of metal elements is higher than the atomic ratio of element M. Furthermore, it is more preferable to use a metal oxide in which the atomic ratio of zinc is higher than the atomic ratio of element M. For example, in semiconductor layer 108_1 and semiconductor layer 108_2, the atomic ratios of metal elements can be In:M:Zn=2:1:3, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:3, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, In:M Metal oxides with the following ratios can be used: Zn = 6:1:6, In:M:Zn = 10:1:3, In:M:Zn = 10:1:6, In:M:Zn = 10:1:7, In:M:Zn = 10:1:8, In:M:Zn = 5:2:5, In:M:Zn = 10:1:10, In:M:Zn = 20:1:10, In:M:Zn = 40:1:10, or near these ratios.

[0228] Furthermore, if element M contains multiple metallic elements, the sum of the atomic ratios of those metallic elements can be used as the atomic ratio of element M. For example, in the case of an In-Ga-Al-Zn oxide having gallium and aluminum as elements M, the sum of the atomic ratios of gallium and aluminum can be used as the atomic ratio of element M. It is also preferable that the atomic ratios of indium, element M, and zinc are within the aforementioned ranges. For example, in the case of an In-Ga-Sn-Zn oxide having gallium and tin as elements M, the sum of the atomic ratios of gallium and tin can be used as the atomic ratio of element M. It is also preferable that the atomic ratios of indium, element M, and zinc are within the aforementioned ranges.

[0229] It is preferable to use a metal oxide in which the ratio of the number of indium atoms to the total number of metal elements contained in the metal oxide is 30 atomic% to 100 atomic%, preferably 30 atomic% to 95 atomic%, more preferably 35 atomic% to 95 atomic%, more preferably 35 atomic% to 90 atomic%, more preferably 40 atomic% to 90 atomic%, more preferably 45 atomic% to 90 atomic%, more preferably 50 atomic% to 80 atomic%, more preferably 60 atomic% to 80 atomic%, and more preferably 70 atomic% to 80 atomic%. For example, when using In-Ga-Zn oxide for semiconductor layer 108_1 and semiconductor layer 108_2, it is preferable that the ratio of the number of indium atoms to the total number of indium, gallium, and zinc atoms is within the above range.

[0230] In this specification, the ratio of indium atoms to the total number of atoms of other metal elements may be referred to as the indium content. The same applies to other metal elements.

[0231] By increasing the indium content of the metal oxide, a transistor with a high on-current can be created. Applying this transistor to a transistor requiring a high on-current results in a semiconductor device with excellent electrical characteristics.

[0232] For the analysis of the composition of metal oxides, for example, EDX, XPS, inductively coupled plasma mass spectrometry (ICP-MS), or inductively coupled high-frequency plasma atomic emission spectrometry (ICP-AES) can be used. Alternatively, a combination of these methods can be used for analysis. Note that for elements with low content, the actual content may differ from the content obtained by the analysis due to the effect of analytical accuracy. For example, if the content of element M is low, the content of element M obtained by the analysis may be lower than the actual content, it may be difficult to quantify the content of element M, or element M may not be detected.

[0233] In this specification, the term "nearby composition" includes a range of ±30% of the desired atomic ratio. For example, when describing an atomic ratio of In:M:Zn = 4:2:3 or a composition near that, it includes cases where the atomic ratio of indium is 4, the atomic ratio of M is 1 or more and 3 or less, and the atomic ratio of zinc is 2 or more and 4 or less. Also, when describing an atomic ratio of In:M:Zn = 5:1:6 or a composition near that, it includes cases where the atomic ratio of indium is 5, the atomic ratio of M is greater than 0.1 and 2 or less, and the atomic ratio of zinc is 5 or more and 7 or less. Furthermore, when describing an atomic ratio of In:M:Zn = 1:1:1 or a composition near that, it includes cases where the atomic ratio of indium is 1, the atomic ratio of M is greater than 0.1 and 2 or less, and the atomic ratio of zinc is greater than 0.1 and 2 or less.

[0234] <Example of Semiconductor Device Configuration 2> Figures 2A and 2B show an example of a semiconductor device 100B with a configuration different from that of semiconductor device 100A shown in Figures 1A and 1B. Figure 2A is a plan view of semiconductor device 100B. Figure 2B is a cross-sectional view of semiconductor device 100B along the dashed line A1-A2 shown in Figure 2A. Figure 4B shows an equivalent circuit diagram of semiconductor device 100B.

[0235] The semiconductor device 100B includes transistor 10B1, transistor 10B2_1, transistor 10B2_2, insulating layer 110, and insulating layer 109.

[0236] Transistor 10B1 in semiconductor device 100B corresponds to transistor 10A1 in semiconductor device 100A. Transistor 10B2_1 in semiconductor device 100B corresponds to transistor 10A2_1 in semiconductor device 100A. Transistor 10B2_2 in semiconductor device 100B corresponds to transistor 10A2_2 in semiconductor device 100A.

[0237] The semiconductor device 100B differs from the semiconductor device 100A in that it does not have conductive layers 112b1 and 112b2, and in the configuration of semiconductor layers 1081 and 1082.

[0238] As shown in Figure 1B and other figures, in the semiconductor device 100A, a conductive layer 112b2_2 is provided as the other source electrode or drain electrode of transistor 10A2_2. In addition, a conductive layer 112b1 is provided as the other source electrode or drain electrode of transistor 10A1, and as the gate electrodes of transistors 10A2_1 and 10A2_2, respectively.

[0239] In contrast, semiconductor device 100B does not have either the conductive layer 112b1 or the conductive layer 112b2_2. The end of semiconductor layer 108_1 in the X direction extends outward from semiconductor device 100A (towards A1 and A2), and the region extending towards A1 is provided to cover the groove 137. The end of semiconductor layer 108_2 on the A1 side extends further towards A1 than semiconductor device 100A. In semiconductor device 100B, semiconductor layer 108_1 is provided to cover both the opening 144 and the groove 137. In semiconductor layer 108_1, the region extending outward from the opening 144 (in this case, towards A1) is provided to cover the groove 137 via semiconductor layer 108_2 and insulating layer 106_2. Within the groove 137, the semiconductor layer 108_1 has a region provided along the A1 side surface of the insulating layer 110 and a region provided along the A2 side surface of the insulating layer 110 that face each other.

[0240] It can be said that the semiconductor layer 108_1 in semiconductor device 100B has a configuration that combines the semiconductor layer 108_1 and the conductive layer 112b1 in semiconductor device 100A. Furthermore, it can be said that the semiconductor layer 108_2 in semiconductor device 100B has a configuration that combines the semiconductor layer 108_2 and the conductive layer 112b2_2 in semiconductor device 100A.

[0241] Therefore, in semiconductor device 100B, semiconductor layer 108_1 functions as a channel formation region for transistor 10B1, and can also function as the other source electrode or drain electrode of transistor 10B1, as well as the gate electrodes of transistors 10B2_1 and 10B2_2, respectively. Furthermore, semiconductor layer 108_2 functions as a channel formation region for transistors 10B2_1 and 10B2_2, respectively, and can also function as the other source electrode or drain electrode of transistor 10B2_2.

[0242] In the case of semiconductor device 100B, the absence of conductive layers 112b1 and 112b2_2 allows for a reduction in the number of manufacturing steps compared to semiconductor device 100A, which is preferable. On the other hand, when the source electrode or drain electrode of a transistor in a semiconductor device is extended and used as wiring, it is preferable to use a conductive layer with lower resistance than the semiconductor layer as the wiring material in order to reduce the electrical resistance of the wiring. In this case, the configuration shown in semiconductor device 100A is preferable to the configuration shown in semiconductor device 100B. Thus, in one embodiment of the present invention, the configuration of semiconductor device 100A can be applied, or the configuration of semiconductor device 100B can be applied, depending on the application.

[0243] In semiconductor device 100B, the conductive layer 112b2_1, which functions as the source electrode or drain electrode of transistor 10B2_1, is provided in the same configuration as transistor 10A2_1 in semiconductor device 100A. For example, when semiconductor device 100B is applied to the pixel circuit of a display device using an organic EL device, transistor 10B1 can be applied as a selection transistor, and transistors 10B2_1 and 10B2_2 can be applied as drive transistors. In this case, the conductive layer 112b2_1 will function as wiring connected to a high-potential power supply (for example, wiring ANO shown in Figure 21A, etc.), so it is preferable that it be made of a low-resistance material. Therefore, for the conductive layer 112b2_1, it is preferable to use a low-resistance conductive material containing a metal or alloy as described above in [conductive layer 112a1, conductive layer 112b1, conductive layer 112a2, conductive layer 112b2_1, conductive layer 112b2_2], in particular copper, silver, gold, or aluminum, rather than using a semiconductor material such as the semiconductor layer 108_2. The conductive layer 112b2_1 can be a single-layer structure composed of the above-mentioned metal or alloy material, or it can be a laminated structure composed of the above-mentioned metal or alloy material and another material.

[0244] A specific example of a circuit configuration to which a semiconductor device according to one aspect of the present invention can be applied will be described in Embodiment 3.

[0245] Regarding semiconductor device 100B, other than the points mentioned above, you can refer to the content described in semiconductor device 100A.

[0246] <Example of semiconductor device configuration 3> Figures 3A and 3B show an example of a semiconductor device 100C with a configuration different from that of semiconductor device 100B shown in Figures 2A and 2B. Figure 3A is a plan view of semiconductor device 100C. Figure 3B is a cross-sectional view of semiconductor device 100C along the dashed line A1-A2 shown in Figure 3A. Figure 4C shows an equivalent circuit diagram of semiconductor device 100C.

[0247] The semiconductor device 100C includes a transistor 10C1, a transistor 10C2_1, a transistor 10C2_2, an insulating layer 110, and an insulating layer 109.

[0248] Transistor 10C1 in semiconductor device 100C corresponds to transistor 10B1 in semiconductor device 100B. Transistor 10C2_1 in semiconductor device 100C corresponds to transistor 10B2_1 in semiconductor device 100B. Transistor 10C2_2 in semiconductor device 100C corresponds to transistor 10B2_2 in semiconductor device 100B.

[0249] Semiconductor device 100C differs from semiconductor device 100B in that it does not have a conductive layer 112a2.

[0250] In semiconductor device 100C, the semiconductor layer 108_2, which functions as the channel formation region for transistor 10C2_1 and transistor 10C2_2 respectively, has a region within the groove 137 that is in contact with the upper surface of the insulating layer 109.

[0251] In the configuration shown in semiconductor device 100C, it is preferable that the insulating layer 109 contains impurities (e.g., water and hydrogen) that lower the electrical resistance of the semiconductor layer 108_2, and that a material that releases such impurities is used. The impurities released from the insulating layer 109 diffuse into the regions of the semiconductor layer 108_2, semiconductor layer 108_1, and conductive layer 112a1 that are in contact with the insulating layer 109. As a result, the electrical resistance of the regions of the semiconductor layer 108_2, semiconductor layer 108_1, and conductive layer 112a1 that are in contact with the insulating layer 109 can be made lower than the electrical resistance of the regions that are not in contact with the insulating layer 109. Therefore, the electrical resistance of either the source region or the drain region of transistors 10C1, 10C2_1, and 10C2_2 can be made lower.

[0252] In particular, for transistors 10C2_1 and 10C2_2, by making the region of the semiconductor layer 108_2 in contact with the insulating layer 109 low-resistance, this region can function as either the source electrode or the drain electrode of each transistor. In Figure 3B, this region is shown as the low-resistance region 108n. The low-resistance region 108n contains more impurities (e.g., water and hydrogen) than the other regions of the semiconductor layer 108_2 (e.g., the channel formation region), and can be said to be a low-resistance region. In this case, the semiconductor layer 108_2 can function as the respective channel formation region of transistors 10C2_1 and 10C2_2, and can also function as either the source electrode or the drain electrode. As a result, in semiconductor device 100C, the number of manufacturing steps can be reduced compared to semiconductor device 100B because the conductive layer 112a2 does not need to be provided, which is preferable. Also, by not providing the conductive layer 112a2, the unevenness in the cross-sectional view of the semiconductor device can be reduced compared to semiconductor device 100B. Therefore, it is possible to improve the coverage of structures provided on the upper layer of semiconductor devices, which is preferable.

[0253] On the other hand, in the case of semiconductor device 100B, the presence of a conductive layer 112a2 beneath the semiconductor layer 108_2 reduces the risk of short-circuiting between the semiconductor layer 108_2 and the conductive layer 112a1 compared to semiconductor device 100C. For example, in the case of semiconductor device 100C, when a groove 137 is formed, the thickness of the insulating layer 109 in the region overlapping with the groove 137 becomes thinner, and there is a risk of leakage occurring between the semiconductor layer 108_2 and the conductive layer 112a1 in that region. In contrast, in the case of semiconductor device 100B, the conductive layer 112a2 can function as an etching stopper when the groove 137 is formed, so there is no such concern. Therefore, semiconductor device 100B may be able to achieve a higher yield than semiconductor device 100C.

[0254] When metal oxides are used for semiconductor layers 108_1 and 108_2, an insulating material that releases hydrogen-containing impurities can be used as the insulating layer 109. In this case, the hydrogen contained in the insulating layer 109 diffuses into the semiconductor layer 108_1, causing the region of the semiconductor layer 108_1 in contact with the insulating layer 109 to contain hydrogen, and thus increasing the carrier concentration in that region. Similarly, the hydrogen contained in the insulating layer 109 diffuses into the semiconductor layer 108_2, causing the region of the semiconductor layer 108_2 in contact with the insulating layer 109 (low-resistance region 108n) to contain hydrogen, and thus increasing the carrier concentration in that region. In other words, the electrical resistance of either the source region or the drain region of each of the transistors 10C1, 10C2_1, and 10C2_2 can be reduced. The insulating layer 109 preferably contains, for example, silicon and hydrogen. Typically, silicon nitride containing hydrogen can be suitably used for the insulating layer 109.

[0255] Regarding semiconductor device 100C, other than the points mentioned above, you can refer to the contents described for semiconductor device 100A and semiconductor device 100B, respectively.

[0256] <Example of Semiconductor Device Configuration 4> Figure 5B shows an example of a semiconductor device configuration different from the semiconductor device 100A shown in Figures 1A and 1B. In Figure 5B, only two transistors connected in series (transistor 10D2_1 and transistor 10D2_2) of the three transistors in the semiconductor device are shown. Figure 5B is a perspective view of transistor 10D2_1 and transistor 10D2_2. In Figure 5B, for ease of viewing, some components (conductive layer 112b1 and insulating layer 106_2) are omitted, and only the outline of the insulating layer 110 is shown with a dashed line. Also, the insulating layer 110 is shown as a single layer without distinguishing between insulating layer 110a, insulating layer 110b, and insulating layer 110c.

[0257] The perspective view shown in Figure 5A is a perspective view that extracts only transistors 10A2_1 and 10A2_2 of the semiconductor device 100A, corresponding to the perspective views of transistors 10D2_1 and 10D2_2 shown in Figure 5B. As shown in Figure 5A, in the semiconductor device 100A, grooves 137 are formed not only in the region where transistors 10A2_1 and 10A2_2 are provided, but also in the entire region along the Y direction of the insulating layer 110.

[0258] In contrast, in the configuration shown in Figure 5B, the insulating layer 110 has openings 141 only in the areas that overlap with the semiconductor layers (semiconductor layer 108_2) that function as channel formation regions for transistors 10D2_1 and 10D2_2, respectively. The remaining areas are not processed and have a flat top surface. Therefore, the configuration shown in Figure 5B has a smaller processed area for the insulating layer 110 than the configuration shown in Figure 5A, and can be said to have superior flatness as a whole semiconductor device. This makes it possible to improve the coverage of structures formed on the upper layer of a semiconductor device having the configuration shown in Figure 5B. On the other hand, in the configuration shown in Figure 5B, processing precision is required to form the openings 141 only where the transistors are installed, whereas in the configuration shown in Figure 5A, the same level of processing precision is not required when forming the grooves 137 as when forming the openings 141. Therefore, the configuration shown in Figure 5A may be able to improve yield compared to the configuration shown in Figure 5B.

[0259] Regarding transistors 10D2_1 and 10D2_2, for points other than those mentioned above, refer to the explanations given for transistors 10A2_1 and 10A2_2.

[0260] <Example of Semiconductor Device Configuration 5> Figure 6A shows an example of a semiconductor device configuration different from the semiconductor device 100A shown in Figures 1A and 1B. In Figure 6A, only the transistor (transistor 10E2_2) located on the A1 side of the two series-connected transistors among the three transistors of the semiconductor device is shown. Figure 6A is a plan view of transistor 10E2_2. Transistor 10E2_2 corresponds to, for example, transistor 10A2_2 in semiconductor device 100A, transistor 10B2_2 in semiconductor device 100B, and transistor 10C2_2 in semiconductor device 100C. The description of transistor 10E2_2 described below can also be applied to the other series-connected transistor.

[0261] The upper surface shape of the conductive layer 112b2_2 and the insulating layer 110 on the side facing the groove 137 of transistor 10E2_2 is different from that of transistor 10A2_2.

[0262] As shown in Figure 6A, in transistor 10E2_2, the conductive layer 112b2_2 and the insulating layer 110 facing the groove 137 have a shape that is convex toward A2 in a plan view. In Figure 6A, the angle formed by the two sides constituting this convexity is shown as angle θ10E2. The semiconductor layer 108_2 is provided such that it has a region that overlaps with the side surface of the conductive layer 112b2_2 and the side surface of the insulating layer 110 corresponding to the two sides constituting angle θ10E2.

[0263] As a result, the channel width of transistor 10E2_2 is the length of the region along the two sides that constitute the angle θ10E2 of the semiconductor layer 108_2. In Figure 6A, the channel width W10E2 of transistor 10E2_2 is shown by the double-headed arrow of the dashed line.

[0264] This makes it possible to fabricate a transistor 10E2_2 with a different channel width from transistor 10A2_2 without affecting the occupied area. Furthermore, it increases the degree of freedom in fabricating the upper surface shape of the conductive layer 112b2_2 and the insulating layer 110.

[0265] Regarding transistor 10E2_2, for points other than those mentioned above, you can refer to the explanation given for transistor 10A2_2, etc.

[0266] <Example of semiconductor device configuration 6> Figure 6B shows an example of the configuration of transistor 10F2_2, which has a different configuration from transistor 10E2_2 shown in Figure 6A. Figure 6B is a plan view of transistor 10F2_2, which corresponds to the plan view of transistor 10E2_2 shown in Figure 6A.

[0267] The upper surface shape of the conductive layer 112b2_2 and the insulating layer 110 on the side facing the groove 137 of transistor 10F2_2 is different from that of transistor 10E2_2.

[0268] As shown in Figure 6B, in transistor 10F2_2, the conductive layer 112b2_2 and the insulating layer 110 have a concave shape on the A1 side when viewed from above. In Figure 6B, the angle formed by the two sides constituting this concave is shown as angle θ10F2. The semiconductor layer 108_2 is provided such that it has a region that overlaps with the side surfaces of the conductive layer 112b2_2 and the side surfaces of the insulating layer 110, which correspond to the two sides constituting angle θ10F2.

[0269] As a result, the channel width of transistor 10F2_2 is the length of the region along the two sides that constitute the angle θ10F2 of the semiconductor layer 108_2. In Figure 6B, the channel width W10F2 of transistor 10F2_2 is shown by the double-headed arrow in the dashed line.

[0270] This makes it possible to fabricate a transistor 10F2_2 with a different channel width from transistor 10A2_2 without affecting the occupied area. Furthermore, it increases the degree of freedom in fabricating the upper surface shape of the conductive layer 112b2_2 and the insulating layer 110.

[0271] Regarding transistor 10F2_2, for points other than those mentioned above, please refer to the explanations given for transistors 10A2_2, 10E2_2, etc.

[0272] <Semiconductor Device Configuration Example 7> Figure 7A shows a configuration example of transistor 10G2_2, which has a different configuration from transistor 10A2_2 shown in Figure 1A, transistor 10E2_2 shown in Figure 6A, transistor 10F2_2 shown in Figure 6B, etc. Figure 7A is a plan view of transistor 10G2_2, which corresponds to the plan view of transistor 10E2_2 shown in Figure 6A.

[0273] The upper surface shape of the conductive layer 112b2_2 and the insulating layer 110 on the side facing the groove 137 of transistor 10G2_2 differs from that of transistors 10A2_2, 10E2_2, 10F2_2, etc.

[0274] As shown in Figure 7A, in transistor 10G2_2, the conductive layer 112b2_2 and the insulating layer 110 have a curved shape that bulges towards A2 in a plan view. The semiconductor layer 108_2 is provided such that it has a region that overlaps with the side surface of the conductive layer 112b2_2 and the side surface of the insulating layer 110 that constitute the curve.

[0275] As a result, the channel width of transistor 10G2_2 is the length of the region of semiconductor layer 108_2 along the curve. In Figure 7A, the channel width W10G2 of transistor 10G2_2 is indicated by a double-headed arrow within a dashed line.

[0276] This makes it possible to fabricate a transistor 10G2_2 with a different channel width from transistor 10A2_2 without affecting the occupied area. Furthermore, it increases the degree of freedom in fabricating the upper surface shape of the conductive layer 112b2_2 and the insulating layer 110.

[0277] Regarding transistor 10G2_2, for points other than those mentioned above, you can refer to the explanations given for transistors 10A2_2, 10E2_2, 10F2_2, etc.

[0278] <Example of semiconductor device configuration 8> Figure 7B shows an example of the configuration of transistor 10H2_2, which has a different configuration from transistor 10G2_2 shown in Figure 7A. Figure 7B is a plan view of transistor 10H2_2, which corresponds to the plan view of transistor 10G2_2 shown in Figure 7A.

[0279] The upper surface shape of the conductive layer 112b2_2 and the insulating layer 110 on the side facing the groove 137 of transistor 10H2_2 is different from that of transistor 10G2_2.

[0280] As shown in Figure 7B, in transistor 10H2_2, the conductive layer 112b2_2 and the insulating layer 110 have a curved shape that is recessed towards A1 when viewed from above. The semiconductor layer 108_2 is provided such that it has a region that overlaps with the side surface of the conductive layer 112b2_2 and the side surface of the insulating layer 110 that constitute the curve.

[0281] As a result, the channel width of transistor 10H2_2 is the length of the region of semiconductor layer 108_2 along the curve. In Figure 7B, the channel width W10H2 of transistor 10H2_2 is shown by a double-headed arrow within a dashed line.

[0282] This makes it possible to fabricate a transistor 10H2_2 with a different channel width from transistor 10A2_2 without affecting the occupied area. Furthermore, it increases the degree of freedom in fabricating the upper surface shape of the conductive layer 112b2_2 and the insulating layer 110.

[0283] Regarding transistor 10H2_2, for points other than those mentioned above, you can refer to the explanations given for transistors 10A2_2, 10G2_2, etc.

[0284] <Example of Semiconductor Device Manufacturing Method> Below, an example of a semiconductor device manufacturing method according to one embodiment of the present invention will be described with reference to the drawings. Here, the semiconductor device 100A shown in Figures 1A and 1B will be used as an example.

[0285] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed using methods such as sputtering, chemical vapor deposition (CVD), vacuum deposition, pulsed laser deposition (PLD), and atomic layer deposition (ALD).

[0286] Sputtering methods include RF sputtering, which uses a high-frequency power supply for sputtering; DC sputtering, which uses a DC power supply; and pulsed DC sputtering, which changes the voltage applied to the electrodes in pulses. For film deposition using insulating targets, RF sputtering is preferable. DC sputtering is mainly used when depositing films using conductive targets. In addition to forming conductive films, DC sputtering can also be used to form insulating films by reactive sputtering using pulsed DC sputtering. Specifically, pulsed DC sputtering can be used when depositing compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0287] CVD methods can be classified into plasma CVD (PECVD), which utilizes plasma; thermal CVD (TCD), which utilizes heat; and photo CVD (Photo CVD), which utilizes light. Furthermore, depending on the source gas used, they can be divided into metal CVD (MCCVD) and metal-organic CVD (MOCVD).

[0288] Plasma CVD allows for the production of high-quality films at relatively low temperatures. Thermal CVD, on the other hand, does not use plasma, thus minimizing plasma damage to the workpiece. For example, wiring, electrodes, and components (transistors, capacitors, etc.) in semiconductor devices can become charged by receiving charge from the plasma. This accumulated charge can damage the wiring, electrodes, or components in the semiconductor device. In contrast, thermal CVD, which does not use plasma, avoids this plasma damage, resulting in a higher yield for semiconductor devices. Furthermore, thermal CVD produces films with fewer defects because it avoids plasma damage during deposition.

[0289] As ALD methods, thermal ALD, which carries out the reaction of the precursor and reactant using only thermal energy, and PEALD, which uses plasma-excited reactants, can be used.

[0290] CVD and ALD methods differ from sputtering, where particles emitted from a target or other source are deposited. Therefore, they are less affected by the shape of the workpiece and are film deposition methods that provide good step-level coverage. In particular, the ALD method has excellent step-level coverage and excellent thickness uniformity, making it suitable, for example, for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow deposition rate, it is sometimes preferable to use it in combination with other film deposition methods such as the CVD method, which has a faster deposition rate.

[0291] Furthermore, the CVD method allows for the deposition of films with any desired composition by changing the flow rate ratio of the source gases. For example, in the CVD method, by changing the flow rate ratio of the source gases while deposition is occurring, films with continuously changing compositions can be deposited. When deposition is performed while changing the flow rate ratio of the source gases, the deposition time can be shortened compared to deposition using multiple deposition chambers, because time required for transport or pressure adjustment is eliminated. Therefore, it may be possible to increase the productivity of semiconductor devices.

[0292] Furthermore, the ALD method allows for the deposition of films of any composition by using multiple different types of precursors. Alternatively, when multiple different types of precursors are introduced, films of any composition can be deposited by controlling the number of cycles for each precursor.

[0293] Thin films (insulating films, semiconductor films, conductive films, etc.) that constitute semiconductor devices can be formed by methods such as spin coating, dip coating, spray coating, inkjet printing, dispensing, screen printing, offset printing, doctor knife coating, slit coating, roll coating, curtain coating, and knife coating.

[0294] Thin films constituting semiconductor devices can be processed using methods such as photolithography. In addition, thin films can also be processed using nanoimprint lithography, sandblasting, and lift-off methods. Furthermore, island-like thin films can be directly formed using deposition methods that utilize shielding masks such as metal masks.

[0295] Photolithography typically involves two main methods. One method involves forming a resist mask on the thin film to be processed, then processing the thin film by etching or other means, and finally removing the resist mask. The other method involves forming a photosensitive thin film, followed by exposure and development, to process the thin film into the desired shape.

[0296] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture thereof. Other light sources such as ultraviolet light, KrF laser light, or ArF laser light can also be used. Exposure can also be performed using immersion lithography. Furthermore, extreme ultraviolet (EUV) light or X-rays can be used as the light source for exposure. An electron beam can also be used instead of light for exposure. Using extreme ultraviolet light, X-rays, or an electron beam is preferable because it allows for extremely fine processing. Note that a photomask is not required when exposure is performed by scanning a beam such as an electron beam.

[0297] For etching thin films, methods such as dry etching, wet etching, or sandblasting can be used.

[0298] For planarization of thin films, polishing methods such as the CMP method are typically suitable. Alternatively, the reflow method, which involves heat treatment of the conductive layer to fluidize it, can also be suitably used. Furthermore, a combination of the reflow method and the CMP method can be employed.

[0299] Furthermore, a process can be used in which a planarization film is formed on an uneven film surface, and a film with a flat top surface is formed by performing highly anisotropic etching (e.g., dry etching) on ​​the planarization film, or a process in which a planarization film and a photoresist are formed in this order on an uneven film surface, and a film with a flat top surface is formed by performing highly anisotropic etching on the planarization film and the photoresist, thereby filling only the planarization film into the depressions and flattening the entire top surface (these processes are sometimes called etch-back processes). When using an etch-back process, high-temperature heating (e.g., around 800°C) like that used in reflow methods is not required, so there is no need to worry about damage to the device during fabrication caused by such heating. In addition, an etch-back process is suitable because it can be applied to devices on large substrates that are difficult to process with the CMP method due to the effects of bending, etc.

[0300] Other thin film planarization processes that can be used include dry etching and plasma treatment. Polishing, dry etching, and plasma treatment can be performed multiple times, or they can be combined. When combining these processes, the order of the steps is not particularly limited and can be appropriately set according to the surface irregularities of the workpiece.

[0301] To precisely process a thin film to a desired thickness, for example, the CMP method can be used. In this method, first, the thin film is polished at a constant processing speed until a portion of its upper surface is exposed. Then, by polishing at a slower processing speed until the thin film reaches the desired thickness, high-precision processing becomes possible.

[0302] Methods for detecting the end point of polishing include optical methods that involve irradiating the surface of the workpiece with light and detecting changes in the reflected light, physical methods that involve detecting changes in the polishing resistance that the processing equipment receives from the workpiece, and methods that use changes in magnetic field lines caused by eddy currents generated when magnetic field lines are applied to the workpiece.

[0303] After the upper surface of the thin film is exposed, the thickness of the thin film can be precisely controlled by performing a polishing process at a slow processing speed while monitoring its thickness using an optical method such as a laser interferometer. If necessary, the polishing process can be repeated multiple times until the thin film reaches the desired thickness.

[0304] Figures 8A to 19B illustrate the method for manufacturing the semiconductor device 100A. Figure (A) in each figure shows a plan view corresponding to Figure 1A. Figure (B) in each figure shows a cross-sectional view along the dashed line A1-A2 in the plan view shown in Figure 1A.

[0305] First, a conductive film that will become the conductive layer 112a1 is formed on the substrate 102, and the conductive layer 112a1 is formed by removing a portion of the conductive film (Figures 8A and 8B). For example, sputtering can be used to form the conductive film. In addition, either or both of the wet etching method and the dry etching method can be used to process the conductive film.

[0306] Next, an insulating film 109f and a conductive film 112a2f are formed on the conductive layer 112a1 and the substrate 102 in that order (Figures 9A and 9B).

[0307] The insulating film 109f can be made from any material that can be used for the insulating layer 109 as described above. Furthermore, for forming the insulating film 109f, methods such as sputtering, PEALD, or PECVD can be used.

[0308] Furthermore, the conductive film 112a2f can be made from any material that can be used for the conductive layer 112a2 described above. Also, for example, sputtering can be used to form the conductive film 112a2f.

[0309] Next, a conductive layer 112a2 is formed by removing a portion of the conductive film 112a2f (Figures 10A and 10B). The conductive layer 112a2 is formed to have a region that overlaps with the conductive layer 112a1. Either a wet etching method or a dry etching method, or both, can be used to form the conductive layer 112a2.

[0310] Next, insulating films 110af, 110bf, and 110cf are formed on the conductive layer 112a2 and the insulating film 109f in this order.

[0311] The insulating film 110af can be made from any material that can be used for the insulating layer 110a described above.

[0312] As the insulating film 110af, for example, silicon nitride, silicon oxide nitride, aluminum oxide, or hafnium oxide can be suitably used.

[0313] Specifically, as the insulating film 110af, for example, silicon nitride can be deposited using the sputtering method. Alternatively, for example, silicon nitride can be deposited using the PEALD method. Alternatively, for example, aluminum oxide can be deposited using the sputtering method.

[0314] Furthermore, for example, a configuration in which aluminum oxide and silicon nitride are layered can be used. For instance, aluminum oxide deposited using the sputtering method and silicon nitride deposited using the PEALD method can be used in a layered configuration.

[0315] The insulating film 110bf can be made from any material that can be used for the insulating layer 110b described above.

[0316] For example, silicon oxide, silicon oxide, silicon nitride, etc., can be suitably used as the insulating film 110bf.

[0317] Specifically, as the insulating film 110bf, silicon oxide can be deposited using, for example, a sputtering method. Alternatively, silicon oxide can be deposited using, for example, a PECVD method. Alternatively, silicon oxynitride can be deposited using, for example, a PECVD method.

[0318] Furthermore, for example, silicon oxide deposited using the sputtering method and silicon oxide or silicon oxidnitride deposited using the PECVD method can be used in a layered configuration.

[0319] Furthermore, after forming the insulating film 110bf, a process (such as CMP treatment) can be performed to flatten the upper surface of the insulating film 110bf. This eliminates the steps that occur on the insulating film 110bf due to the conductive layer 112a2, and improves the coverage of structures later provided on the upper layer of the semiconductor device 100A.

[0320] On the other hand, if the step created on the insulating film 110bf due to the conductive layer 112a2 does not pose a problem in subsequent processes, the process of flattening the upper surface of the insulating film 110bf can be omitted. In this case, the number of processes involved in the manufacture of the semiconductor device can be reduced compared to when the above process is performed.

[0321] The insulating film 110bf can also be subjected to heat treatment after it has been formed. By performing heat treatment, water and hydrogen can be removed from the surface and within the insulating film 110bf.

[0322] The heat treatment temperature is preferably 150°C or higher and below the strain point of the substrate 102, more preferably 200°C to 450°C, more preferably 250°C to 450°C, more preferably 300°C to 450°C, more preferably 300°C to 400°C, and more preferably 350°C to 400°C. The heat treatment can be carried out in an atmosphere containing one or more noble gases, nitrogen, or oxygen. Dry air (CDA: Clean Dry Air) can also be used as the nitrogen-containing atmosphere or the oxygen-containing atmosphere. It is preferable that the content of hydrogen, water, etc. in the atmosphere be kept to a minimum. It is preferable to use a high-purity gas with a dew point of -60°C or lower, preferably -100°C or lower, as the atmosphere. By using an atmosphere with a very low content of hydrogen, water, etc., it is possible to prevent hydrogen, water, etc. from being incorporated into the insulating film 110bf as much as possible. Heat treatment can be performed using, for example, an oven or a rapid thermal annealing (RTA) device. Using an RTA device can shorten the heat treatment time.

[0323] After the above heat treatment, a step of supplying oxygen to the insulating film 110bf can also be performed. For example, after the insulating film 110bf is formed, a metal oxide layer can be formed on the insulating film 110bf to supply oxygen to the insulating film 110bf. Alternatively, the heat treatment can be performed after the formation of the metal oxide layer. By performing the heat treatment after the formation of the metal oxide layer, oxygen can be effectively supplied from the metal oxide layer to the insulating film 110bf, and oxygen can be contained in the insulating film 110bf. The oxygen supplied to the insulating film 110bf is then supplied to the semiconductor layer 108_1 and the semiconductor layer 108_2 in a later step, thereby eliminating oxygen vacancies (V) in the semiconductor layer 108_1 and the semiconductor layer 108_2. Ｏ ) and V Ｏ H can be reduced.

[0324] After forming the metal oxide layer, or after the aforementioned heat treatment, oxygen can be further supplied to the insulating film 110bf through the metal oxide layer. As a method of supplying oxygen, for example, ion implantation, ion doping, plasma immersion ion implantation, or plasma treatment can be used. As the plasma treatment, a device that converts oxygen gas into plasma using high-frequency power can be suitably used. Examples of devices that convert gas into plasma using high-frequency power include plasma etching devices and plasma ashing devices.

[0325] The metal oxide layer may be an insulating layer, a conductive layer, or a semiconductor layer. The metal oxide layer may be, for example, aluminum oxide, hafnium oxide, hafnium aluminate, indium oxide, indium tin oxide (ITO), or silicon-containing indium tin oxide (ITSO).

[0326] It is preferable to use an oxide material containing one or more of the same elements as semiconductor layer 108_1 and semiconductor layer 108_2 as the metal oxide layer. In particular, it is preferable to use an oxide semiconductor material applicable to semiconductor layer 108_1 and semiconductor layer 108_2. This allows the metal oxide layer to be formed using the same sputtering target as semiconductor layer 108_1 and semiconductor layer 108_2, thereby reducing manufacturing costs.

[0327] When using a metal oxide material containing indium and gallium in the metal oxide layer, a material with a higher gallium composition (content) than semiconductor layer 108_1 and semiconductor layer 108_2 can be used. By using a material with a high gallium composition (content) in the metal oxide layer, the barrier properties against oxygen can be further enhanced. This is preferable because it can suppress the detachment of oxygen contained in the insulating film 110bf to the outside.

[0328] The metal oxide layer is preferably formed in an oxygen-containing atmosphere, for example. In particular, it is preferable to form it by sputtering in an oxygen-containing atmosphere. This allows for a suitable supply of oxygen to the insulating film 110bf during the formation of the metal oxide layer.

[0329] Next, the metal oxide layer is removed. For example, a wet etching method can be suitably used to remove the metal oxide layer.

[0330] The process of supplying oxygen to the insulating film 110bf is not limited to the methods described above. For example, oxygen radicals, oxygen atoms, oxygen atomic ions, oxygen molecular ions, etc., can be supplied to the insulating film 110bf by ion doping, ion implantation, plasma treatment, etc. Alternatively, a film that suppresses oxygen desorption can be formed on the insulating film 110bf, and then oxygen can be supplied to the insulating film 110bf through this film. It is preferable to remove the film after supplying oxygen. As the film that suppresses oxygen desorption mentioned above, a conductive film or semiconductor film having one or more of indium, zinc, gallium, tin, aluminum, chromium, tantalum, titanium, molybdenum, nickel, iron, cobalt, or tungsten can be used.

[0331] For the insulating film 110cf, any material that can be used for the insulating layer 110c described above can be used as appropriate.

[0332] For materials and film formation methods that can be used for the insulating film 110cf, refer to the description of materials and film formation methods that can be used for the insulating film 110af mentioned above.

[0333] Next, a conductive film 112b2f is formed on the insulating film 110cf (Figures 11A and 11B). The conductive film 112b2f can be made from any of the materials previously used for the conductive layer 112b2. Furthermore, for the formation of the conductive film 112b2f, for example, sputtering can be used.

[0334] Next, a conductive layer 112b2e is formed by removing a portion of the conductive film 112b2f (Figures 12A and 12B). Either a wet etching method or a dry etching method, or both, can be used to form the conductive layer 112b2e. The conductive layer 112b2e is formed to have a region that overlaps with the conductive layer 112a2.

[0335] Next, a process is performed to remove a portion of each of the conductive layer 112b2e, insulating film 110cf, insulating film 110bf, and insulating film 110af, thereby forming a groove 137 that reaches the conductive layer 112a2. For example, a dry etching method can be suitably used for this process. Through this process, conductive layers 112b2_1 and 112b2_2 are formed from the conductive layer 112b2e, insulating layer 110ce is formed from the insulating film 110cf, insulating layer 110be is formed from the insulating film 110bf, and insulating layer 110ae is formed from the insulating film 110af (Figures 13A and 13B).

[0336] In one embodiment of the present invention, an example is shown in which conductive layers 112b2_1 and 112b2_2 are formed by forming grooves 137 after forming the conductive layer 112b2e, but this is not limited to this example. For example, after forming the conductive film 112b2f (Figures 11A and 11B), grooves 137 reaching the conductive layer 112a2 are formed in the conductive film 112b2f, insulating film 110cf, insulating film 110bf, and insulating film 110af. Subsequently, conductive layers 112b2_1 and 112b2_2 can also be formed by processing the conductive film 112b2f with the grooves 137 provided.

[0337] Next, a semiconductor film is formed to become the semiconductor layer 108_2, in contact with the upper surface of the conductive layer 112a2, the side surface of the insulating layer 110, the side surface of the conductive layer 112b2_1, the side surface of the conductive layer 112b2_2, the upper surface of the conductive layer 112b2_1, and the upper surface of the conductive layer 112b2_2 within the groove 137. Subsequently, a portion of the semiconductor film is removed by etching to form the semiconductor layer 108_2 (Figures 14A and 14B). The semiconductor layer 108_2 is provided to have a region that overlaps with the groove 137. Furthermore, the semiconductor layer 108_2 is provided to have a region at its end that is in contact with the conductive layer 112b2_1 and the conductive layer 112b2_2, respectively.

[0338] For the semiconductor film that becomes semiconductor layer 108_2, any material that can be used for semiconductor layer 108_1 and semiconductor layer 108_2 as described above can be used as appropriate.

[0339] For example, sputtering can be used to form the semiconductor film that will become the semiconductor layer 108_2. For example, when a metal oxide is used for the semiconductor layer 108_2, it can be formed by sputtering using a metal oxide target. Using sputtering is preferable because it allows for the relatively easy formation of films with low hydrogen content.

[0340] Furthermore, when a metal oxide is used for the semiconductor layer 108_2, it can also be formed by the ALD method using a precursor containing the constituent metal element and an oxidizing agent.

[0341] For example, when forming In-Ga-Zn oxide, three precursors can be used: an indium-containing precursor, a gallium-containing precursor, and a zinc-containing precursor. Alternatively, two precursors can be used: an indium-containing precursor and precursors containing both gallium and zinc.

[0342] Indium-containing precursors that can be used include triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)indium, cyclopentadienylindium, and indium(III) chloride.

[0343] Furthermore, gallium-containing precursors such as trimethylgallium, triethylgallium, gallium trichloride, tris(dimethylamide)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionic acid)gallium, dimethylchlorogallium, and diethylchlorogallium can be used.

[0344] Furthermore, zinc-containing precursors such as dimethylzinc, diethylzinc, bis(2,2,6,6-tetramethyl-3,5-heptanedionic acid) zinc, and zinc chloride can be used.

[0345] For example, ozone, oxygen, and water can be used as oxidizing agents.

[0346] Methods for controlling the composition of the resulting film include adjusting the flow ratio of the source gases, the duration of the source gas flow, and the order in which the source gases are flowed. By adjusting these factors, it is also possible to deposit films with continuously changing compositions. Furthermore, it becomes possible to deposit films with different compositions in succession.

[0347] Using the ALD method to form the semiconductor film that will become the semiconductor layer 108_2 is preferable because it allows the semiconductor layer 108_2 to be formed with a uniform thickness on the side surface of the insulating layer 110.

[0348] After forming the semiconductor film that will become the semiconductor layer 108_2, a heat treatment can also be performed. This heat treatment reduces the amount of water and hydrogen contained in the semiconductor film and allows oxygen to be supplied to the semiconductor film from the insulating layer 110be. Note that the heat treatment can also be performed after processing the semiconductor film.

[0349] The substrate temperature (stage temperature) during the formation of the semiconductor film that will become the semiconductor layer 108_2 is preferably between room temperature (e.g., 25°C) and 200°C, and more preferably between room temperature and 130°C. By setting the substrate temperature within the above range, bending or distortion of the substrate can be suppressed when using a large-area glass substrate.

[0350] The higher the substrate temperature during the formation of the metal oxide layer, the more crystalline the metal oxide layer can be formed. Furthermore, the higher the oxygen flow rate ratio, the more crystalline the metal oxide layer can be formed.

[0351] Next, an insulating film 106_2f is formed by covering the semiconductor layer 108_2, the conductive layer 112b2_1, the conductive layer 112b2_2, and the insulating layer 110ce. The insulating film 106_2f has regions that are in contact with the upper and side surfaces of the semiconductor layer 108_2, the upper and side surfaces of the conductive layer 112b2_1, the upper and side surfaces of the conductive layer 112b2_2, and the upper surface of the insulating layer 110ce.

[0352] The insulating film 106_2f can be made from any of the materials that can be used for the insulating layer 106_1 and insulating layer 106_2 described above.

[0353] For example, the ALD method can be used to form the insulating film 106_2f. The ALD method is preferable because it allows for good coverage of the insulating film 106_2f on the semiconductor layer 108_2 formed across the groove 137. However, if the semiconductor layer 108_2 can be sufficiently covered, methods other than the ALD method can be used to form the insulating film 106_2f. For example, the PECVD method or sputtering method can be used. This allows for a faster deposition rate of the insulating film 106_2f than when using the ALD method, thereby increasing productivity.

[0354] Next, a conductive film 112b1f is formed on the insulating film 106_2f (Figures 15A and 15B). Sputtering, CVD, PLD, ALD, and other methods can be used as appropriate for forming the conductive film 112b1f. Here, it is preferable that the conductive film 112b1f is formed within the groove 137, in contact with the upper surface of the insulating film 106_2f (particularly the upper surface of the region facing the side surface of the insulating layer 110). Therefore, it is preferable to use a formation method that provides good coverage or embedding properties for forming the conductive film 112b1f, and it is more preferable to use the CVD or ALD method.

[0355] Next, a conductive layer 112b1e is formed by removing a portion of the conductive film 112b1f (Figures 16A and 16B). Either a wet etching method or a dry etching method, or both, can be used to process the conductive film 112b1f. The conductive layer 112b1e is formed to have a region that overlaps with the groove 137.

[0356] Next, in a region different from the groove 137 on the conductive layer 112a1, a portion of each of the conductive layer 112b1e, insulating film 106_2f, insulating layer 110ce, insulating layer 110be, insulating layer 110ae, and insulating film 109f is removed to form an opening 144 that reaches the conductive layer 112a1. For example, a dry etching method can be suitably used for this process. This process forms the conductive layer 112b1, insulating layer 106_2, insulating layer 110 (insulating layer 110c, insulating layer 110b, and insulating layer 110a), and insulating layer 109, each having an opening (Figures 17A and 17B).

[0357] This forms transistors 10A2_1 and 10A2_2.

[0358] In one embodiment of the present invention, an example is shown in which the conductive layer 112b1 is formed by forming an opening 144 after forming the conductive layer 112b1e, but this is not limited to this. For example, after forming the conductive film 112b1f (Figures 15A and 15B), an opening 144 reaching the conductive layer 112a1 is formed in the conductive film 112b1f, insulating film 106_2f, insulating layer 110ce, insulating layer 110be, insulating layer 110ae, and insulating film 109f. Subsequently, the conductive layer 112b1 can also be formed by processing the conductive film 112b1f with the opening 144 provided.

[0359] Next, a semiconductor film that will become the semiconductor layer 108_1 is formed in contact with the upper surface of the conductive layer 112a1, the side surface of the insulating layer 109, the side surface of the insulating layer 110, the side surface of the insulating layer 106_2, the side surface of the conductive layer 112b1, and the upper surface of the conductive layer 112b1 within the opening 144. After that, a portion of the semiconductor film is removed by etching to form the semiconductor layer 108_1 (Figures 18A and 18B). The semiconductor layer 108_1 is provided so as to have a region that overlaps with the opening 144. In addition, the semiconductor layer 108_1 is provided so as to have a region where its end is in contact with the conductive layer 112b1.

[0360] For the semiconductor film that becomes semiconductor layer 108_1, any material that can be used for semiconductor layer 108_1 and semiconductor layer 108_2 as described above can be used as appropriate.

[0361] Furthermore, regarding the method for forming the semiconductor film that will become semiconductor layer 108_1, you can refer to the description above regarding the method for forming the semiconductor film that will become semiconductor layer 108_2.

[0362] Next, the semiconductor layer 108_1, the conductive layer 112b1, and the insulating layer 106_2 are covered to form the insulating layer 106_1 (Figures 19A and 19B). The insulating layer 106_1 has regions that are in contact with the upper and side surfaces of the semiconductor layer 108_1, the upper and side surfaces of the conductive layer 112b1, and the upper surface of the insulating layer 106_2.

[0363] The insulating layer 106_1 can be made from the materials described above as appropriate.

[0364] Next, a conductive film that will become the conductive layer 104 is formed on the insulating layer 106_1, and the conductive layer 104 is formed by removing a portion of the conductive film. Any material that can be used for the conductive layer 104 as described above can be used for the conductive film. Furthermore, for the processing method from the conductive film to the conductive layer 104, refer to the description of the processing method from the conductive film 112b1f to the conductive layer 112b1e mentioned above. The conductive layer 104 is formed to have a region that overlaps with the opening 144.

[0365] This forms transistor 10A1.

[0366] By following the above steps, the semiconductor device 100A can be manufactured (Figures 1A and 1B).

[0367] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0368] (Embodiment 2) This embodiment describes an indium oxide film that can be used in the semiconductor layer of a transistor in a semiconductor device according to one aspect of the present invention.

[0369] In this specification, indium oxide having at least a crystalline portion or crystalline region in the film is referred to as crystalline indium oxide (crystal IO) or crystalline indium oxide (crystalline IO). Examples of crystal IO or crystalline IO include single-crystal indium oxide, polycrystalline indium oxide, and microcrystalline indium oxide.

[0370] Indium oxide is a semiconductor material with completely different physical properties from oxide semiconductors such as In-Ga-Zn oxide (hereinafter also referred to as IGZO) and zinc oxide.

[0371] This paper describes the carrier concentration dependence of the hole mobility of indium oxide, silicon, and IGZO.

[0372] IGZO tends to exhibit higher hole mobility as the carrier concentration increases. On the other hand, single-crystal indium oxide tends to exhibit higher hole mobility as the carrier concentration decreases. This trend is similar to that of silicon, where lower dopant (impurity) concentrations in the material reduce impurity scattering and increase hole mobility. In other words, the higher the purity and intrinsic nature of single-crystal indium oxide, the higher its hole mobility. From these results, it can be said that single-crystal indium oxide, unlike IGZO, is a material with physical properties similar to silicon. Note that when indium oxide is not single-crystal (e.g., polycrystalline), the trend may differ from that of single-crystal indium oxide.

[0373] The range of carrier concentrations suitable for the channel formation region of a transistor is 1 × 10⁻⁶. １５ cm −３ This range includes, for example, 1 × 10 １４ cm −３ The above is 1 x 10 １８ cm −３ The range is as follows: By sufficiently reducing the carrier concentration, the hole mobility value can be increased to 270 cm⁻¹. ２ It can be expected to be raised to the level of / (V・s).

[0374] Indium oxide can contain elements that lower the carrier concentration. Examples of elements that lower the carrier concentration include magnesium, calcium, zinc, cadmium, and copper. These elements can lower the carrier concentration by substituting for indium. Other examples include nitrogen, phosphorus, arsenic, and antimony. These elements can lower the carrier concentration by substituting for oxygen.

[0375] On the other hand, electrical resistance can be reduced by increasing the carrier concentration. For example, the suitable carrier concentration range for the source and drain regions of a transistor, or for a resistor or transparent conductive film, is when the carrier concentration value is 1 × 10⁻⁶ ２０ cm −３ This range includes, for example, 1 × 10 １９ cm −３ The above is 1 x 10 ２２ cm −３ The range is as follows: By making the carrier concentration sufficiently high, the resistivity can be increased to 1 × 10⁻⁶. −４ It is expected that the level can be reduced to below Ω·cm.

[0376] Indium oxide may contain elements that increase the carrier concentration. For example, it is preferable to include elements common to the source and drain electrodes of the transistor. Examples of elements that increase the carrier concentration include titanium, zirconium, hafnium, tantalum, tungsten, molybdenum, tin, silicon, and boron. It is especially preferable to use elements in which the oxide is conductive or semiconducting.

[0377] Because indium oxide is an oxide whose valence electrons can be controlled, the region with a low carrier concentration can be used for the channel formation region of the transistor, and the region with a high carrier concentration can be used for the source and drain regions of the transistor. This makes it possible to create a so-called n-i-n junction (a junction between an n-type region, an i-type region, and an n-type region). Valence electron control in transistors using silicon is generally known. On the other hand, valence electron control in transistors using indium oxide is a novel technological concept that would not normally be conceived. By using this technological concept, it is possible to realize a transistor with high mobility, low off-current, normally-off capability, and high reliability.

[0378] The indium oxide film is preferably crystalline. In particular, the indium oxide film is preferably polycrystalline, and more preferably single-crystal. A single-crystal film does not have grain boundaries. By using a single-crystal film, carrier scattering at the grain boundaries can be suppressed, enabling the realization of a transistor exhibiting high field-effect mobility. Furthermore, it has the excellent effect of suppressing variations in transistor characteristics caused by the grain boundaries.

[0379] Furthermore, polycrystalline films are preferable because they can reduce carrier scattering and exhibit high field-effect mobility compared to microcrystalline or amorphous films. When using polycrystalline films, it is preferable to use films with the largest possible grain size and few grain boundaries. In a transistor to which a polycrystalline film is applied, if there are no grain boundaries in the channel formation region, or if no grain boundaries are observed, the channel formation region is located within the single-crystal region contained in the polycrystalline film, and therefore it can be considered a transistor to which a single-crystal film is applied.

[0380] The crystallinity of indium oxide can be analyzed, for example, by X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0381] Furthermore, in this specification, a semiconductor layer in which no grain boundaries are observed in the channel formation region, a semiconductor layer in which the channel formation region is contained within a single crystal grain, or a semiconductor layer in which the direction of the crystal axes is the same in at least two regions within the channel formation region can be considered as a single crystal film.

[0382] The channel formation region refers to the region of the semiconductor layer that overlaps with (or faces) the gate electrode via the gate insulating layer, and is located between the region in contact with the source electrode and the region in contact with the drain electrode. The crystal grains, grain boundaries, crystal axes, and crystal orientation in the channel formation region can be confirmed by cross-sectional observation including the semiconductor layer, source electrode, and drain electrode.

[0383] Impurities in the indium oxide film can act as a source of carrier scattering, thus potentially causing a decrease in field-effect mobility and inhibiting crystal growth. Examples of impurities in the indium oxide film include boron and silicon. In the channel-forming region of the indium oxide film, lower concentrations of these impurities are preferable. For example, the concentration of each of the above impurity elements should be 0.1% or less, more preferably 0.01% (100 ppm) or less. Note that elements such as carbon and hydrogen may be present in the deposition gas or precursor during film formation, and may remain in the indium oxide film in higher concentrations than the above impurities.

[0384] Furthermore, the indium oxide film may contain elements that can become trivalent cations like indium, as long as their crystals maintain a cubic crystal structure (Bixbite type). Examples include group 13 elements of the periodic table such as gallium and aluminum, and group 3 elements of the periodic table. Since these elements mainly exist as trivalent cations in the oxide, the carrier concentration of indium oxide can be kept low.

[0385] By using such an indium oxide film in a transistor, the field-effect mobility of the transistor can be increased to 50 cm². ２ / (V·s) or more, preferably 100 cm ２ / (V·s) or more, more preferably 150 cm ２ / (V·s) or more, more preferably 200 cm２ / (V·s) or more, more preferably 250 cm ２ / (V・s) or more is possible.

[0386] One of the characteristics of indium oxide films is their higher oxygen permeability (diffusivity) compared to IGZO films. For example, oxygen diffusing into an indium oxide film permeates the film and is released as oxygen molecules. In some cases, it may also be released as water molecules by reacting with hydrogen contained in the film. Furthermore, if there is an oxygen deficiency in the film, diffusing oxygen atoms will fill the deficiency. Because oxygen diffuses easily through indium oxide films, it can be said that oxygen deficiencies are more easily filled in compared to IGZO films.

[0387] Thus, because indium oxide films are more likely to reduce oxygen vacancies in the film compared to IGZO films, applying such indium oxide films to transistors makes it possible to realize transistors with extremely high reliability.

[0388] Furthermore, the indium oxide film diffuses hydrogen. Hydrogen diffusing into the indium oxide film from the outside permeates the film and is released as hydrogen molecules. Alternatively, it reacts with oxygen contained in the film and is released as water molecules.

[0389] Indium oxide is characterized by a small effective electron mass and a large effective hole mass. Furthermore, the effective electron mass of indium oxide is largely independent of the crystal orientation. Therefore, using crystalline indium oxide in transistors allows for the realization of transistors with high field-effect mobility and high frequency characteristics (also known as f-response). Additionally, due to the large effective hole mass, transistors with extremely low off-currents can be realized. For example, by applying an indium oxide film to a transistor, the off-current per 1 μm of channel width is 1 fA (1 × 10⁻¹⁶) at 125°C. −１５ A) Less than or equal to, or 1aA (1 × 10 −１８ A) is less than or equal to 1aA (1 × 10) under room temperature (25°C) conditions. −１８ A) Less than or equal to, or 1zA (1 × 10 −２１A) The following is possible. Furthermore, because indium oxide has a smaller effective electron mass and a larger effective hole mass than silicon, it may be possible to realize transistors with higher field-effect mobility and lower off-current than Si transistors.

[0390] It is preferable to provide a seed layer so as to be in contact with at least a portion of the crystalline indium oxide film. It is preferable to use a material containing crystals with a small difference in lattice constant (also called lattice mismatch) with the indium oxide for the seed layer. This can improve the crystallinity of the indium oxide film. A substrate (for example, a single-crystal substrate) may be used as one of the layers in contact with at least a portion of the crystalline indium oxide film.

[0391] One method for evaluating the degree of lattice mismatch is to use the following lattice mismatch value. The lattice mismatch Δa [%] of the crystals in the formed film (in this case, the indium oxide film) relative to the crystals in the seed layer is given by Δa = ((L １ -L ２ ) / L ２ It is calculated as ) × 100. Here L １ L is the length of the unit cell vector of the crystals in the formed film, or the lattice constant. ２ This is the length of the unit cell vector of the crystal in the seed layer, or the lattice constant.

[0392] The lattice mismatch Δa between the seed layer and the indium oxide film is preferably small in absolute value, and most preferably zero. For example, Δa can be -5% or more and 5% or less, preferably -4% or more and 4% or less, more preferably -3% or more and 3% or less, and even more preferably -2% or more and 2% or less.

[0393] Here, the indium oxide crystal has a cubic structure (bixbite type). For example, yttria-stabilized zirconia (YSZ) crystals can have a cubic structure (fluorite type). The lattice mismatch of the indium oxide crystal with respect to the cubic YSZ crystal is in the range of -2% to 2%, and a single crystal film of indium oxide can be epitaxially grown on a YSZ substrate.

[0394] Note that the crystal structure of the seed layer and the crystal structure of the indium oxide film may not have the same crystal system or crystal orientation. For example, a film having a crystal with a hexagonal crystal structure or a trigonal crystal structure can also be used under an indium oxide film having a crystal with a cubic crystal structure. For example, by setting the crystal orientation of the surface of the seed layer to

[001] and the crystal orientation of the lower surface of the indium oxide film to

[111] , requirements related to the crystal orientation necessary for epitaxial growth can be satisfied. As crystals of the hexagonal crystal system or the trigonal crystal system, for example, there are wurtzite-type structures, YbFe ２ O ４ -type structures, Yb ２ Fe ３ O ７ -type structures, and modified structures thereof. Examples of crystals having a YbFe ２ O ４ -type structure or a Yb ２ Fe ３ O ７ -type structure include IGZO and the like.

[0395] This embodiment can be implemented in appropriate combination with other embodiments described in this specification, at least in part.

[0396] (Embodiment 3) A semiconductor device according to an aspect of the present invention can be applied to, for example, a display device. In this embodiment, circuits, layouts, etc. applicable to the display device will be described.

[0397] FIG. 20 is a block diagram for explaining a display device 300 to which a semiconductor device according to an aspect of the present invention can be applied. The display device 300 includes a display unit 435, a first drive circuit unit 431, and a second drive circuit unit 432.

[0398] The display unit 435 includes a plurality of pixels 230 arranged in a matrix of m rows (m is an integer of 1 or more) and n columns (n is an integer of 1 or more).

[0399] The display unit 435 corresponds to, for example, the display unit 168 in FIG. 28 described in Embodiment 4, and the pixel 230 corresponds to, for example, the sub-pixel 11R, the sub-pixel 11G, or the sub-pixel 11B in FIG. 28 described in Embodiment 4.

[0400] In FIG. 20, the pixel 230 at the 1st row and nth column is denoted as pixel 230[1, n], the pixel 230 at the mth row and 1st column is denoted as pixel 230[m, 1], and the pixel 230 at the mth row and nth column is denoted as pixel 230[m, n]. Also, any pixel 230 included in the display unit 435 may be denoted as pixel 230[r, s]. r is an integer of 1 or more and m or less, and s is an integer of 1 or more and n or less.

[0401] The circuit included in the first drive circuit unit 431 functions as, for example, a scanning line drive circuit. The circuit included in the second drive circuit unit 432 functions as, for example, a signal line drive circuit. Note that some circuit may be provided at a position facing the first drive circuit unit 431 with the display unit 435 interposed therebetween. Some circuit may be provided at a position facing the second drive circuit unit 432 with the display unit 435 interposed therebetween. Note that the circuits included in the first drive circuit unit 431 and the second drive circuit unit 432 are collectively referred to as a peripheral drive circuit 433.

[0402] Various circuits such as a shift register circuit, a level shifter circuit, an inverter circuit, a latch circuit, an analog switch circuit, a multiplexer circuit, a demultiplexer circuit, and a logic circuit can be used for the peripheral drive circuit 433. A semiconductor device 100A or the like according to an aspect of the present invention can be used for the peripheral drive circuit 433. Note that the transistors included in the peripheral drive circuit and the transistors included in the pixel 230 can be formed in the same process.

[0403] The display device 300 also includes m wirings 436 that are each disposed substantially in parallel and whose potentials are controlled by the circuits included in the first drive circuit unit 431, and n wirings 437 that are each disposed substantially in parallel and whose potentials are controlled by the circuits included in the second drive circuit unit 432.

[0404] Note that FIG. 20 shows an example in which the wiring 436 and the wiring 437 are connected to the pixel 230. However, the wiring 436 and the wiring 437 are merely examples, and the wiring connected to the pixel 230 is not limited to the wiring 436 and the wiring 437.

[0405] <Configuration example of pixel circuit> Examples of the configuration of pixel 230 are shown in FIGS. 21A to 21D. Pixel 230 includes pixel circuit 51 (pixel circuit 51A, pixel circuit 51B, pixel circuit 51C, or pixel circuit 51D) and light-emitting element 61.

[0406] The light-emitting element described in this embodiment or the like refers to a self-emitting display element such as an organic EL element (also referred to as an OLED (Organic LED)). Note that the light-emitting element connected to the pixel circuit can be a self-emitting light-emitting element such as an LED, a micro LED, a QLED (Quantum-dot LED), or a semiconductor laser.

[0407] The pixel circuit 51A shown in FIG. 21A is a 2Tr1C type pixel circuit including transistor 52A, transistor 52B, and capacitor 53.

[0408] One of the source or drain of transistor 52A is connected to wiring SL, and the gate of transistor 52A is connected to wiring GL. The other of the source or drain of transistor 52A is connected to the gate of transistor 52B and one terminal of capacitor 53. One of the source or drain of transistor 52B is connected to wiring ANO. The other of the source or drain of transistor 52B is connected to the other terminal of capacitor 53 and the anode of light-emitting element 61. The cathode of light-emitting element 61 is connected to wiring VCOM. The region to which the other of the source or drain of transistor 52A, the gate of transistor 52B, and one terminal of capacitor 53 are connected functions as node ND.

[0409] Wiring GL corresponds to wiring 436, and wiring SL corresponds to wiring 437. Wiring VCOM is a wiring that provides a potential for supplying current to light-emitting element 61. Transistor 52A has a function of controlling the conduction state (a state in which current can flow) or non-conduction state between wiring SL and the gate of transistor 52B based on the potential of wiring GL. For example, VDD is supplied to wiring ANO, and VSS is supplied to wiring VCOM. Since transistor 52A functions as a switch for controlling selection and non-selection of pixel 230, it can also be called a selection transistor.

[0410] By turning transistor 52A ON, an image signal is supplied from wiring SL to node ND. Subsequently, by turning transistor 52A OFF, the image signal is held at node ND. To ensure reliable retention of the image signal supplied to node ND, it is preferable to use a transistor with low off-current for transistor 52A. For example, it is preferable to use an OS transistor as transistor 52A.

[0411] Transistor 52B has the function of controlling the amount of current flowing to the light-emitting element 61. Transistor 52B can also be called a driving transistor. Capacitor 53 has the function of maintaining the gate potential of transistor 52B. The intensity of the light emitted by the light-emitting element 61 is controlled according to the image signal supplied to the gate (node ​​ND) of transistor 52B.

[0412] The pixel circuit 51B shown in Figure 21B is a 3Tr1C type pixel circuit having transistors 52A, 52B, 52C, and a capacitor 53. The pixel circuit 51B shown in Figure 21B has a configuration in which transistor 52C is added to the pixel circuit 51A shown in Figure 21A.

[0413] One source or drain of transistor 52C is connected to the other source or drain of transistor 52B. The other source or drain of transistor 52C is connected to wiring V0. For example, wiring V0 is supplied with a reference potential. The gate of transistor 52C is connected to wiring GL.

[0414] Transistor 52C has the function of controlling the conduction or non-conduction state between the source or drain of transistor 52B and the wiring V0 based on the potential of the wiring GL. Wiring V0 is a wiring that provides a reference potential. When an n-channel transistor is used for transistor 52B, the reference potential of wiring V0 provided via transistor 52C can suppress variations in the gate-source voltage of transistor 52B.

[0415] Furthermore, the wiring V0 can be used to obtain current values ​​that can be used to set pixel parameters. More specifically, the wiring V0 can function as a monitor line for outputting the current flowing through transistor 52B or the current flowing through light-emitting element 61 to the outside. The current output to wiring V0 can be converted into a voltage by a source follower circuit or the like and output to the outside. Alternatively, it can be converted into a digital signal by an A-D converter or the like and output to the outside.

[0416] The pixel circuit 51C shown in Figure 21C has a configuration in which transistor 52D is added to the pixel circuit 51B shown in Figure 21B. The pixel circuit 51C shown in Figure 21C is a 4Tr1C type pixel circuit having transistors 52A, 52B, 52C, 52D, and capacitor 53.

[0417] One of the sources or drains of transistor 52D is connected to node ND, and the other source or drain is connected to wiring V0.

[0418] Wirings GL1, GL2, and GL3 are connected to the pixel circuit 51C. Wiring GL1 is connected to the gate of transistor 52A, wiring GL2 is connected to the gate of transistor 52C, and wiring GL3 is connected to the gate of transistor 52D. In this embodiment, wirings GL1, GL2, and GL3 are sometimes collectively referred to as wiring GL. Therefore, there may be more than one wiring GL.

[0419] By simultaneously making transistors 52C and 52D conduct, the source and gate of transistor 52B become at the same potential, making transistor 52B non-conducting. This allows the current flowing to the light-emitting element 61 to be forcibly interrupted. Such a pixel circuit is suitable when using a display method that alternates between display periods and off periods.

[0420] The pixel circuit 51D shown in Figure 21D is an example of the pixel circuit 51C shown in Figure 21C with the addition of a capacitor 53A. The capacitor 53A functions as a retaining capacitor. The pixel circuit 51C shown in Figure 21C is a 4Tr1C type pixel circuit. The pixel circuit 51D shown in Figure 21D is a 4Tr2C type pixel circuit.

[0421] For example, the semiconductor device 100A shown in Embodiment 1 (see Figures 1A, 1B, and 4A) can be applied to each of the pixel circuits 51A to 51D. In this case, transistor 10A1 can be applied to transistor 52A, and transistors 10A2_1 and 10A2_2 (two transistors connected in series) can be applied to transistor 52B.

[0422] For example, the semiconductor device 100B shown in Embodiment 1 (see Figures 2A, 2B, and 4B) can be applied to each of the pixel circuits 51A to 51D. In this case, transistor 10B1 can be applied to transistor 52A, and transistors 10B2_1 and 10B2_2 (two transistors connected in series) can be applied to transistor 52B.

[0423] For example, the semiconductor device 100C shown in Embodiment 1 (see Figures 3A, 3B, and 4C) can be applied to each of the pixel circuits 51A to 51D. In this case, transistor 10C1 can be applied to transistor 52A, and transistors 10C2_1 and 10C2_2 (two transistors connected in series) can be applied to transistor 52B.

[0424] In the following, specific layout examples of the aforementioned pixel circuit and examples of its manufacturing method, to which a semiconductor device according to one aspect of the present invention can be applied, will be described with reference to Figures 22A to 25B.

[0425] The figures 22A to 25B show examples of layouts and manufacturing methods for the pixel circuit 51A shown in Figure 21A.

[0426] Furthermore, in each layout shown in Figures 22A to 25B, the line-and-space pattern in each layer is designed to be 1.5 μm. For example, the minimum width of the island-shaped conductive layers (the same applies to insulating layers, semiconductor layers, etc.) in each layout is assumed to be 1.5 μm. Also, for example, the minimum spacing between adjacent island-shaped conductive layers (the same applies to insulating layers, semiconductor layers, etc.) is assumed to be 1.5 μm.

[0427] First, a conductive layer 112a1 is formed (Figure 22A). For details on how to form the conductive layer 112a1, please refer to the description in Figures 8A and 8B in the <Example of Semiconductor Device Manufacturing Method>.

[0428] Next, an insulating film 109f and a conductive film 112a2f (neither of which are shown) are formed on the conductive layer 112a1 in that order, and then the conductive film 112a2f is processed to form the conductive layer 112a2 (Figure 22B). The conductive layer 112a2 is formed to have a region that overlaps with the conductive layer 112a1. For information on how to form the conductive layer 112a2 and the like, refer to the description in Figures 9A to 10B in <Examples of Methods for Manufacturing Semiconductor Devices>.

[0429] Next, insulating films 110af, 110bf, 110cf, and 112b2f (none of which are shown) are formed on the conductive layer 112a2 and the insulating film 109f, respectively. Then, the conductive film 112b2f is processed to form a conductive layer 112b2e (Figure 22C). The conductive layer 112b2e is formed to have a region that overlaps with the conductive layer 112a2. For information on how to form the conductive layer 112b2e, etc., refer to the description in Figures 11A to 12B in <Examples of Semiconductor Device Manufacturing Methods>.

[0430] Next, a portion of the conductive layer 112b2e, insulating film 110cf, insulating film 110bf, and insulating film 110af is removed to form a groove 137 that reaches the conductive layer 112a2, and conductive layers 112b2_1 and 112b2_2 are formed from the conductive layer 112b2e, insulating layer 110ce (not shown) is formed from the insulating film 110cf, insulating layer 110be (not shown) is formed from the insulating film 110bf, and insulating layer 110ae (not shown) is formed from the insulating film 110af (Figure 23A). For details on how to form the groove 137, etc., refer to the description in Figures 13A and 13B in <Example of Semiconductor Device Manufacturing Method>.

[0431] Next, a semiconductor layer 108_2 is formed on the conductive layer 112a2, the conductive layer 112b2_1, and the conductive layer 112b2_2, such that it has a region that overlaps with the groove 137 (Figure 23B). For details on how to form the semiconductor layer 108_2, please refer to the description in Figures 14A to 14B in <Examples of Semiconductor Device Manufacturing Methods>.

[0432] Next, insulating film 106_2f and conductive film 112b1f (neither of which are shown) are formed in this order on the semiconductor layer 108_2, conductive layer 112b2_1, conductive layer 112b2_2, and insulating layer 110ce (not shown). Then, the conductive film 112b1f is processed to form conductive layer 112b1e (Figure 24A). The conductive layer 112b1e is formed to have a region that overlaps with the groove 137. For information on how to form the conductive layer 112b1e, etc., refer to the description in Figures 15A to 16B in <Example of Semiconductor Device Manufacturing Method>.

[0433] Next, an opening 144 reaching the conductive layer 112a1 is formed in a region that does not overlap with the groove portion 137 of the conductive layer 112b1e. Also, the conductive layer 112b1 is formed from the conductive layer 112b1e, the insulating layer 110c (not shown) is formed from the insulating layer 110ce, the insulating layer 110b (not shown) is formed from the insulating layer 110be, and the insulating layer 110a (not shown) is formed from the insulating layer 110ae (FIG. 24B). For the method of forming the opening 144 and the like, reference can be made to the descriptions in FIGS. 17A and 17B in <Example of Manufacturing Method of Semiconductor Device>. Thereby, the transistors 52B1 and 52B2 are formed.

[0434] Next, a semiconductor layer 108_1 is formed on the conductive layer 112a1 and on the conductive layer 112b1 so as to have a region overlapping with the opening 144 (FIG. 25A). For the method of forming the semiconductor layer 108_1 and the like, reference can be made to the descriptions in FIGS. 18A and 18B in <Example of Manufacturing Method of Semiconductor Device>.

[0435] Next, a conductive film (both not shown) that becomes the insulating layer 106_1 and the conductive layer 104 is formed in this order on the semiconductor layer 108_1, on the conductive layer 112b1, and on the insulating layer 106_2 (not shown). Then, the conductive film is processed to form the conductive layer 104 (FIG. 25B). The conductive layer 104 is formed so as to have a region overlapping with the opening 144. For the method of forming the conductive layer 104 and the like, reference can be made to the descriptions in FIGS. 19A and 19B in <Example of Manufacturing Method of Semiconductor Device>. Thereby, the transistor 52A is formed.

[0436] As described above, a semiconductor device including the transistors 52A and 52B in the pixel circuit 51A shown in FIG. 21A can be formed.

[0437] For example, when the semiconductor device 100A (see FIGS. 1A and 1B, and FIG. 4A) is applied to the pixel circuit 51A, the transistor 10A1 corresponds to the transistor 52A, and the transistors 10A2_1 and 10A2_2 (two transistors connected in series) correspond to the transistor 52B.

[0438] For example, when semiconductor device 100B (see Figures 2A, 2B, and 4B) is applied to pixel circuit 51A, transistor 10B1 corresponds to transistor 52A, and transistors 10B2_1 and 10B2_2 (two transistors connected in series) correspond to transistor 52B.

[0439] For example, when semiconductor device 100C (see Figures 3A, 3B, and 4C) is applied to pixel circuit 51A, transistor 10C1 corresponds to transistor 52A, and transistors 10C2_1 and 10C2_2 (two transistors connected in series) correspond to transistor 52B.

[0440] Figure 26 shows an example of a layout in which a conductive layer 111, which functions as a pixel electrode of a display device, is further formed on the upper layer of the semiconductor device shown in Figure 25B. In Figure 26, an example of a layout of two semiconductor devices that constitute two adjacent subpixels (subpixel 11_1 and subpixel 11_2) among the multiple subpixels that make up the pixels of a display device is shown. Subpixels 11_1 and 11_2 correspond to two adjacent subpixels among the three subpixels (subpixel 11R, subpixel 11G, and subpixel 11B) of the display device shown in Figure 28. Note that the semiconductor devices that constitute subpixels 11_1 and subpixel 11_2 can both be configured using the layout shown in Figure 25B. In addition, in the layout shown in Figure 26, the conductive layer 111 is formed with a design value of 1.5 μm line-and-space, similar to the other components.

[0441] Figure 27 shows a cross-sectional view of sub-pixel 11_1 along the dashed line B1-B2 in the layout shown in Figure 26. The cross-sectional view in Figure 27 shows an example in which a semiconductor device with the same configuration as semiconductor device 100A (see Figures 1A and 1B) is applied as the semiconductor device of sub-pixel 11_1. Therefore, in the cross-sectional view in Figure 27, transistor 52A corresponds to transistor 10A1 in semiconductor device 100A, transistor 52B1 corresponds to transistor 10A2_1 in semiconductor device 100A, and transistor 52B2 corresponds to transistor 10A2_2 in semiconductor device 100A. For details of the configuration of semiconductor device 100A, refer to Embodiment 1.

[0442] As shown in Figure 27, an insulating layer 195, which functions as a protective layer for the semiconductor device, is provided on the semiconductor device (here, semiconductor device 100A) of the subpixel 11_1, and an insulating layer 235, which functions as a planarization layer, is provided on the insulating layer 195. In the region overlapping with the conductive layer 112b2_2 extending towards B1, openings 147 reaching the conductive layer 112b2_2 are provided in the insulating layer 106_2, insulating layer 106_1, insulating layer 195, and insulating layer 235. A conductive layer 111 is provided on the conductive layer 112b2_2 and the insulating layer 235 so as to cover the openings 147.

[0443] The conductive layer 111 has regions within the opening 147 that are in contact with the upper surface of the conductive layer 112b2_2, the side surface of the insulating layer 106_2, the side surface of the insulating layer 106_1, the side surface of the insulating layer 195, and the side surface of the insulating layer 235, respectively. As described above, the conductive layer 111 is a conductive layer that functions as a pixel electrode of the display device (the anode of the light-emitting element 61 in the pixel circuit 51A shown in Figure 21A). Therefore, the sub-pixel 11_1 has the cross-sectional structure shown in Figure 27, which allows the source electrode or the other drain electrode (conductive layer 112b2_2) of the transistor 52B2 (transistor 52B in the pixel circuit 51A shown in Figure 21A) to be connected to the anode of the light-emitting element (conductive layer 111).

[0444] The layout shown in Figure 26 illustrates an example in which conductive layer 112a1, conductive layer 112b1, conductive layer 112b2_2, and conductive layer 111 each extend in the X direction, and conductive layer 112b2_1 and conductive layer 104 each extend in the Y direction. As mentioned above, this layout assumes that the line and space of each pattern is formed with a design value of 1.5 μm. Therefore, the width of each conductive layer (in a plan view, the width in the direction perpendicular to the extension direction of each conductive layer) is at least 1.5 μm.

[0445] Furthermore, the distance between conductive layers in adjacent subpixels (for example, the distance in the Y direction between the conductive layer 111 of subpixel 11_1 and the conductive layer 111 of subpixel 11_2) is at least 1.5 μm.

[0446] Therefore, in one aspect of the present invention, the conductive layer 112a1, conductive layer 112b1, conductive layer 112b2_2, and conductive layer 111 are each provided extending in the same direction (first direction), and the conductive layer 112b2_1 and conductive layer 104 are each provided extending in a direction perpendicular to the first direction (second direction) in a plan view.

[0447] Furthermore, the widths of conductive layer 112a1, conductive layer 112b1, conductive layer 112b2_2, and conductive layer 111 in the second direction, and the widths of conductive layer 112b2_1 and conductive layer 104 in the first direction, can be, for example, 1.0 μm or more and 2.0 μm or less, more preferably 1.2 μm or more and 1.8 μm or less, and even more preferably 1.5 μm. Also, the spacing (spacing in the second direction) between adjacent conductive layers 112a1, conductive layers 112b1, conductive layers 112b2_2, and conductive layers 111 can be, for example, 1.0 μm or more and 2.0 μm or less, more preferably 1.2 μm or more and 1.8 μm or less, and even more preferably 1.5 μm. By forming the width or spacing of the conductive layer, insulating layer, or semiconductor layer constituting the semiconductor device to satisfy the above numerical range, and by applying the layout of one embodiment of the present invention described above, for example, a display device having the pixel circuit 51A shown in Figure 21A can achieve a resolution of approximately 3000 ppi.

[0448] As described above, by using a semiconductor device according to one embodiment of the present invention in the pixel circuit of a display device, the occupied area of ​​the pixel circuit can be reduced. Therefore, the resolution of the display device can be increased. For example, a display device can be realized with a resolution of 1,000 ppi or more and 10,000 ppi or less, preferably 2,000 ppi or more and 9,000 ppi or less, more preferably 3,000 ppi or more and 8,000 ppi or less, even more preferably 4,000 ppi or more and 8,000 ppi or less, even more preferably 5,000 ppi or more and 8,000 ppi or less, and even more preferably 6,000 ppi or more and 8,000 ppi or less.

[0449] Furthermore, by reducing the area occupied by the pixel circuit, the number of pixels in the display device can be increased (higher resolution). For example, it becomes possible to realize display devices with extremely high resolutions such as HD (1280 x 720 pixels), FHD (1920 x 1080 pixels), WQHD (2560 x 1440 pixels), WQXGA (2560 x 1600 pixels), 4K2K (3840 x 2160 pixels), or 8K4K (7680 x 4320 pixels).

[0450] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments.

[0451] (Embodiment 4) In this embodiment, a display device according to one aspect of the present invention will be described with reference to Figures 28 to 32.

[0452] The display device of this embodiment can be a high-resolution display device or a large-screen display device. Therefore, the display device of this embodiment can be used in electronic devices with relatively large screens, such as television equipment, desktop or notebook personal computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as in the display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal information terminals, and audio playback devices.

[0453] Furthermore, the display device of this embodiment can be a high-definition display device. Therefore, the display device of this embodiment can be used, for example, as a display unit for information terminals (wearable devices) such as wristwatches and bracelets, and as a display unit for wearable devices that can be worn on the head, such as VR devices such as head-mounted displays (HMDs) and AR devices such as glasses.

[0454] A semiconductor device according to one aspect of the present invention can be used as a display device or a module having said display device. Examples of modules having said display devices include a module to which a connector such as a Flexible Printed Circuit (FPC) or TCP (Tape Carrier Package) is attached, and a module on which an Integrated Circuit (IC) is mounted using the COG (Chip On Glass) method or COF (Chip On Film) method.

[0455] [Display device 50A] Figure 28 shows a perspective view of the display device 50A.

[0456] The display device 50A has a configuration in which substrate 152 and substrate 151 are bonded together. In Figure 28, substrate 152 is shown with a dashed line.

[0457] The display device 50A includes a display unit 168, a connection unit 140, a circuit unit 164, wiring 165, etc. Figure 28 shows an example in which IC 173 and FPC 172 are mounted on the display device 50A. Therefore, the configuration shown in Figure 28 can also be described as a display module having the display device 50A, an IC, and an FPC.

[0458] The connection portion 140 is provided on the outside of the display unit 168. The connection portion 140 can be provided along one or more sides of the display unit 168. There may be one or more connection portions 140. Figure 28 shows an example in which the connection portion 140 is provided so as to surround all four sides of the display unit. The common electrode of the display element and the conductive layer are connected at the connection portion 140, and a potential can be supplied to the common electrode.

[0459] The circuit section 164 includes, for example, a scan line drive circuit (also called a gate driver). Alternatively, the circuit section 164 can be configured to include both a scan line drive circuit and a signal line drive circuit (also called a source driver).

[0460] The wiring 165 has the function of supplying signals and power to the display unit 168 and the circuit unit 164. These signals and power are input to the wiring 165 from an external source via the FPC 172, or from the IC 173.

[0461] Figure 28 shows an example in which IC 173 is provided on the substrate 151 using the COG method or COF method, etc. For example, IC 173 can be an IC having one or both of a scan line drive circuit and a signal line drive circuit. Note that the display device 50A and the display module can also be configured without an IC. Furthermore, the IC can be mounted on the FPC using the COF method, etc.

[0462] One embodiment of the present invention can be applied, for example, to one or both of the display unit 168 and the circuit unit 164 of a display device 50A.

[0463] For example, when a semiconductor device according to one aspect of the present invention is applied to the pixel circuit of a display device, the occupied area of ​​the pixel circuit can be reduced, resulting in a high-definition display device. Also, for example, when a semiconductor device according to one aspect of the present invention is applied to the drive circuit of a display device (for example, one or both of a gate line drive circuit and a source line drive circuit), the occupied area of ​​the drive circuit can be reduced, resulting in a narrow-bezel display device. Furthermore, because the semiconductor device according to one aspect of the present invention has good electrical characteristics, its use in a display device can improve the reliability of the display device.

[0464] The display unit 168 is the area in the display device 50A that displays images, and has a plurality of pixels 210 arranged periodically. Figure 28 shows an enlarged view of one pixel 210.

[0465] There are no particular limitations on the pixel arrangement in the display device of this embodiment, and various methods can be applied. Examples of pixel arrangements include stripe arrangements, S-stripe arrangements, matrix arrangements, delta arrangements, Bayer arrangements, and pentile arrangements.

[0466] The pixel 210 shown in Figure 28 has a sub-pixel 11R that emits red light, a sub-pixel 11G that emits green light, and a sub-pixel 11B that emits blue light.

[0467] Each sub-pixel 11R, sub-pixel 11G, and sub-pixel 11B includes a display element and a circuit that controls the driving of the display element.

[0468] Various elements can be used as display elements, such as liquid crystal elements and light-emitting elements. In addition, display elements using shutter-type or optical interference-type MEMS (Micro Electro Mechanical Systems), microcapsule-type, electrophoretic-type, electrowetting-type, or electronic powder fluid (registered trademark)-type methods can also be used. Furthermore, QLEDs using a light source and color conversion technology with quantum dot materials can also be used.

[0469] Examples of display devices using liquid crystal elements include transmissive liquid crystal display devices, reflective liquid crystal display devices, and semi-transmissive liquid crystal display devices.

[0470] Examples of light-emitting elements include self-emissive light-emitting elements such as LEDs, OLEDs, and semiconductor lasers. For example, mini-LEDs and micro-LEDs can be used as LEDs.

[0471] Examples of light-emitting materials for light-emitting devices include fluorescent materials, phosphorescent materials, thermally activated delayed fluorescence (TADF) materials, and inorganic compounds (such as quantum dot materials).

[0472] The light-emitting element can emit light in the following colors: infrared, red, green, blue, cyan, magenta, yellow, or white. Furthermore, the color purity can be improved by adding a microcavity structure to the light-emitting element.

[0473] Of the pair of electrodes in a light-emitting element, one electrode functions as the anode and the other electrode functions as the cathode.

[0474] In this embodiment, the explanation will mainly be given using the case where a light-emitting element is used as the display element.

[0475] Furthermore, a display device according to one aspect of the present invention may be any of the following: a top-emission type that emits light in the direction opposite to the substrate on which the light-emitting element is formed; a bottom-emission type that emits light toward the substrate on which the light-emitting element is formed; or a dual-emission type that emits light on both sides.

[0476] Figure 29 shows an example of a cross-section obtained by cutting a portion of the display device 50A, including the FPC 172, a portion of the circuit section 164, a portion of the display section 168, a portion of the connection section 140, and a portion of the end section.

[0477] The display device 50A shown in Figure 29 has transistors 205D, 205R1, 205R2, 205G1, 205G2, 205B1, 205B2, light-emitting elements 130R, 130G, 130B, etc. between substrates 151 and 152. Light-emitting element 130R is a display element of a sub-pixel 11R that emits red light, light-emitting element 130G is a display element of a sub-pixel 11G that emits green light, and light-emitting element 130B is a display element of a sub-pixel 11B that emits blue light.

[0478] The display device 50A employs an SBS structure. Because the SBS structure allows for the optimization of materials and configurations for each light-emitting element, it increases the freedom of material and configuration selection, making it easier to improve brightness and reliability.

[0479] Furthermore, the display device 50A is a top-emission type. In the top-emission type, transistors and the like can be arranged overlapping with the light-emitting region of the light-emitting element, which allows for a higher aperture ratio of pixels compared to the bottom-emission type.

[0480] Transistors 205D, 205R1, 205R2, 205G1, 205G2, 205B1, and 205B2 are all formed on substrate 151. These transistors can be manufactured using the same materials and the same process.

[0481] In this embodiment, an example is shown in which OS transistors are used for each of the transistors 205D, 205R1, 205R2, 205G1, 205G2, 205B1, and 205B2.

[0482] Of these, transistors 205R1 and 205R2, transistors 205G1 and 205G2, and transistors 205B1 and 205B2 can each be, for example, transistors 10A2_1 and 10A2_2 in semiconductor device 100A according to one aspect of the present invention. Alternatively, for example, transistors 10B2_1 and 10B2_2 in semiconductor device 100B according to one aspect of the present invention can be used. Alternatively, for example, transistors 10C2_1 and 10C2_2 in semiconductor device 100C according to one aspect of the present invention can be used.

[0483] Furthermore, for example, the transistor 10A1 in semiconductor device 100A according to one aspect of the present invention can be used for transistor 205D. Alternatively, for example, the transistor 10B1 in semiconductor device 100B according to one aspect of the present invention can be used. Alternatively, for example, the transistor 10C1 in semiconductor device 100C according to one aspect of the present invention can be used.

[0484] Figure 29 and others show examples in which transistors 205R1 and 205R2, 205G1 and 205G2, and 205B1 and 205B2 are replaced by transistors 10A2_1 and 10A2_2 from semiconductor device 100A. Furthermore, an example is shown in which transistor 205D is replaced by a transistor with the same configuration as transistor 10A1 from semiconductor device 100A. By using the two series-connected transistors described above as the transistors (more specifically, the driving transistors) in the display unit 168, current saturation can be improved compared to using a single transistor, thus enabling a display device with less display unevenness. On the other hand, by using a single transistor instead of two series-connected transistors as the transistors in the circuit unit 164, a transistor with a shorter channel length and larger on-current can be used, thus enabling a display device with faster operation speed.

[0485] Note that in Figure 29, etc., only two of the three transistors in the semiconductor device used for each sub-pixel of the display unit 168 are shown, which are connected in series (transistors 205R1 and 205R2, transistors 205G1 and 205G2, and transistors 205B1 and 205B2). The other transistor in the semiconductor device (corresponding to the selection transistor in this case) is assumed to be located on the back side of transistors 205R1 and 205R2, transistors 205G1 and 205G2, and transistors 205B1 and 205B2, and is not shown in the cross-sectional view in Figure 29, etc.

[0486] As described above, the display device 50A can apply a semiconductor device according to one aspect of the present invention to both the display unit 168 and the circuit unit 164. For example, by using a semiconductor device according to one aspect of the present invention in the display unit 168, the pixel size can be reduced, and higher resolution can be achieved. Furthermore, an extremely high-performance display device can be realized with a fast operating speed and minimal display unevenness.

[0487] Furthermore, by using a transistor in the circuit section 164 that has the same configuration as one of the transistors in the semiconductor device according to one aspect of the present invention (i.e., a vertical transistor separate from the two transistors connected in series), the area occupied by the circuit section 164 can be reduced, and a narrow bezel can be achieved. For a semiconductor device according to one aspect of the present invention, refer to the description of the earlier embodiment.

[0488] Transistors 205R1 and 205R2, 205G1 and 205G2, and 205B1 and 205B2 each have a conductive layer 112b1 that functions as a gate electrode, an insulating layer 106_2 that functions as a gate insulating layer, a conductive layer 112a2 that functions as one of the source electrode or drain electrode, a conductive layer 112b2_1 and a conductive layer 112b2_2 that functions as the other of the source electrode or drain electrode, and a semiconductor layer 108_2 having a metal oxide.

[0489] Furthermore, the transistors in the display device of this embodiment are not limited to those of one aspect of the present invention. For example, a configuration can be made that combines the transistors of one aspect of the present invention with transistors of other structures.

[0490] The display device of this embodiment may also have a configuration that includes, for example, one or more of a planar transistor, a staggered transistor, or an inverse staggered transistor. The transistors in the display device of this embodiment may be either top-gate or bottom-gate type. Alternatively, the device may have a configuration in which gates are provided above and below the semiconductor layer in which the channel is formed.

[0491] Furthermore, the display device of this embodiment may also have Si transistors.

[0492] Examples of silicon include single-crystal silicon, polycrystalline silicon, and amorphous silicon. In particular, transistors having an LTPS semiconductor layer (hereinafter also referred to as LTPS transistors) can be used. LTPS transistors have high field-effect mobility and good frequency characteristics.

[0493] The transistors in the circuit unit 164 and the transistors in the display unit 168 can have the same structure or different structures. The structures of the multiple transistors in the circuit unit 164 can all be the same or there can be two or more types. Similarly, the structures of the multiple transistors in the display unit 168 can all be the same or there can be two or more types.

[0494] All of the transistors in the display unit 168 can be OS transistors, all of the transistors in the display unit 168 can be Si transistors, and some of the transistors in the display unit 168 can be OS transistors and the rest can be Si transistors.

[0495] For example, by using both an LTPS transistor and an OS transistor in the display unit 168, a display device with low power consumption and high driving capability can be realized. Furthermore, a configuration combining an LTPS transistor and an OS transistor is sometimes referred to as LTPO. A more preferable example is a configuration in which an OS transistor is used for a transistor that functions as a switch to control conduction and non-conduction between wires, and an LTPS transistor is used for a transistor that controls current.

[0496] For example, one of the transistors in the display unit 168 functions as a transistor for controlling the current flowing to the light-emitting element, and can also be called a drive transistor. Either the source or the drain of the drive transistor is connected to the pixel electrode of the light-emitting element. It is preferable to use an LTPS transistor for the drive transistor. This makes it possible to increase the current flowing to the light-emitting element in the pixel circuit.

[0497] On the other hand, the other transistor in the display unit 168 functions as a switch for controlling the selection and deselection of pixels, and can also be called a selection transistor. The gate of the selection transistor is connected to the gate line, and either the source or the drain is connected to the source line (signal line). It is preferable to use an OS transistor for the selection transistor. This makes it possible to maintain the gradation of pixels even when the frame frequency is significantly reduced (for example, 1 fps or less), and thus power consumption can be reduced by stopping the driver when displaying a still image.

[0498] An insulating layer 106_1 is provided so as to cover transistors 205R1 and 205R2, transistors 205G1 and 205G2, and transistors 205B1 and 205B2, and an insulating layer 195 is provided on the insulating layer 106_1.

[0499] The insulating layer 195 preferably functions as a protective layer for the transistor. It is preferable to use a material for the insulating layer 195 that does not easily absorb impurities such as water and hydrogen. This allows the insulating layer 195 to function as a barrier insulating layer. This configuration effectively suppresses the diffusion of impurities into the transistor from the outside, thereby improving the reliability of the display device.

[0500] An insulating layer 235 is provided on the insulating layer 195. Preferably, the insulating layer 235 functions as a flattening layer that fills in steps or irregularities formed on transistors 205R1, 205R2, 205G1, 205G2, 205B1, and 205B2, and flattens the upper surface.

[0501] Furthermore, it is preferable that the outermost layer of the insulating layer 235 functions as an etching protection layer. This makes it possible to suppress the formation of recesses in the insulating layer 235 during processing of the pixel electrodes 111R, 111G, 111B, etc. Alternatively, the insulating layer 235 can be configured to have recesses when processing the pixel electrodes 111R, 111G, 111B, etc.

[0502] A light-emitting element 130R, a light-emitting element 130G, and a light-emitting element 130B are provided on the insulating layer 235.

[0503] The light-emitting element 130R has a pixel electrode 111R on an insulating layer 235, an EL layer 113R on the pixel electrode 111R, and a common electrode 135 on the EL layer 113R. The light-emitting element 130R shown in Figure 29 emits red light (R). The EL layer 113R has a light-emitting layer that emits red light.

[0504] The light-emitting element 130G has a pixel electrode 111G on an insulating layer 235, an EL layer 113G on the pixel electrode 111G, and a common electrode 135 on the EL layer 113G. The light-emitting element 130G shown in Figure 29 emits green light (G). The EL layer 113G has a light-emitting layer that emits green light.

[0505] The light-emitting element 130B has a pixel electrode 111B on an insulating layer 235, an EL layer 113B on the pixel electrode 111B, and a common electrode 135 on the EL layer 113B. The light-emitting element 130B shown in Figure 29 emits blue light (B). The EL layer 113B has a light-emitting layer that emits blue light.

[0506] In Figure 29, EL layers 113R, 113G, and 113B are all shown with the same film thickness, but this is not the only option. The film thicknesses of EL layers 113R, 113G, and 113B can also be different. For example, it is preferable to set the film thicknesses of EL layers 113R, 113G, and 113B to thicknesses corresponding to the optical path length that intensifies the light emitted by each layer. This enables the realization of a microcavity structure and improves the color purity of the light emitted from each light-emitting element.

[0507] The pixel electrode 111R is connected to the conductive layer 112b2_2 of the transistor 205R2 through openings provided in the insulating layers 106_2, 106_1, 195, and 235 located on the conductive layer 112b2_2.

[0508] Similarly, the pixel electrode 111G is connected to the conductive layer 112b2_2 of the transistor 205G2, and the pixel electrode 111B is connected to the conductive layer 112b2_2 of the transistor 205B2.

[0509] The ends of the pixel electrodes 111R, 111G, and 111B are covered by an insulating layer 237. The insulating layer 237 functions as a partition (also called a bank or spacer). The insulating layer 237 can be provided in a single-layer or multi-layer structure using one or both of an inorganic insulating material and an organic insulating material. For example, the insulating layer 237 can be made of a material that can be used for the insulating layer 235. The insulating layer 237 electrically insulates the pixel electrodes from the common electrode. In addition, the insulating layer 237 electrically insulates adjacent light-emitting elements from each other.

[0510] The common electrode 135 is a continuous film provided in common to the light-emitting element 130R, light-emitting element 130G, and light-emitting element 130B. The common electrode 135, which is common to multiple light-emitting elements, is connected to a conductive layer 123 provided at the connection portion 140. It is preferable to use a conductive layer for the conductive layer 123 that is made of the same material and formed by the same process as the pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B.

[0511] In a display device according to one aspect of the present invention, among the pixel electrodes and common electrodes, the electrode that extracts light is preferably made of a conductive film that transmits visible light. Furthermore, it is preferable that the electrode that does not extract light is made of a conductive film that reflects visible light.

[0512] Furthermore, a conductive film that transmits visible light can also be used on the electrode that does not extract light. In this case, it is preferable to place the electrode between the reflective layer and the EL layer. In other words, the light emitted from the EL layer can be reflected by the reflective layer and extracted from the display device.

[0513] As the material for forming the pair of electrodes of the light-emitting element, metals, alloys, electrically conductive compounds, and mixtures thereof can be used as appropriate. Specifically, such materials include metals such as aluminum, magnesium, titanium, chromium, manganese, iron, cobalt, nickel, copper, gallium, zinc, indium, tin, molybdenum, tantalum, tungsten, palladium, gold, platinum, silver, yttrium, and neodymium, and alloys containing these in appropriate combinations. Other examples of such materials include indium tin oxide (ITO), In-Si-Sn oxide (ITSO), indium zinc oxide (In-Zn oxide), and In-W-Zn oxide. Furthermore, such materials include aluminum-containing alloys (aluminum alloys) such as aluminum, nickel, and lanthanum alloys (Al-Ni-La), as well as silver-magnesium alloys and silver-containing alloys such as silver-palladium-copper alloys (Ag-Pd-Cu, also written as APC). Other materials include elements belonging to Group 1 or Group 2 of the periodic table not exemplified above (e.g., lithium, cesium, calcium, strontium), rare earth metals such as europium and ytterbium, alloys containing these in appropriate combinations, graphene, and the like.

[0514] It is preferable that the light-emitting element has a microcavity structure. Therefore, it is preferable that one of the pair of electrodes in the light-emitting element is a semitransmitting / semi-reflective electrode that transmits and reflects visible light, and the other is a reflective electrode that reflects visible light. By having a microcavity structure in the light-emitting element, the light emitted from the light-emitting layer can be resonated between the two electrodes, thereby strengthening the light emitted from the light-emitting element.

[0515] The light transmittance of the transparent electrode shall be 40% or more. For example, it is preferable to use an electrode with a visible light transmittance (light with a wavelength of 400 nm or more and less than 750 nm) of 40% or more for the transparent electrode of the light-emitting element. The visible light reflectance of the semi-transparent and semi-reflective electrodes shall be 10% or more and 95% or less, preferably 30% or more and 80% or less. The visible light reflectance of the reflective electrode shall be 40% or more and 100% or less, preferably 70% or more and 100% or less. The resistivity of these electrodes shall be 1 × 10⁻⁶ −２ A value of Ωcm or less is preferable.

[0516] The EL layers 113R, 113G, and 113B are each provided in an island-like configuration. In Figure 29, the edges of adjacent EL layers 113R and 113G overlap, the edges of adjacent EL layers 113G and 113B overlap, and the edges of adjacent EL layers 113R and 113B overlap. When forming island-like EL layers using a fine metal mask, the edges of adjacent EL layers may overlap as shown in Figure 29, but this is not the only case. In other words, adjacent EL layers can not overlap and can be configured to be separated from each other. Furthermore, in a display device, it is possible to have a configuration in which both adjacent EL layers overlap and adjacent EL layers do not overlap and are separated from each other.

[0517] Each of the EL layers 113R, 113G, and 113B has at least one light-emitting layer. The light-emitting layer has one or more types of light-emitting materials. As the light-emitting material, a material that exhibits a light-emitting color such as blue, purple, blue-violet, green, yellow-green, yellow, orange, or red can be used as appropriate. In addition, a material that emits near-infrared light can also be used as the light-emitting material.

[0518] Examples of luminescent materials include fluorescent materials, phosphorescent materials, TADF materials, and quantum dot materials.

[0519] The light-emitting layer may also consist of one or more types of organic compounds (host material, assist material, etc.) in addition to the light-emitting substance (guest material). The one or more types of organic compounds may include one or both of materials with high hole transport properties (hole transport materials) and materials with high electron transport properties (electron transport materials). Furthermore, bipolar materials (materials with high electron and hole transport properties) or TADF materials may be used as the one or more types of organic compounds.

[0520] The light-emitting layer preferably comprises, for example, a phosphorescent material and a combination of a hole-transporting material and an electron-transporting material that readily forms an excitation complex. This configuration allows for efficient emission using ExTET (Exciplex-Triplet Energy Transfer), which is energy transfer from the excitation complex to the light-emitting substance (phosphorescent material). By selecting a combination that forms an excitation complex that exhibits emission overlapping with the wavelength of the lowest-energy absorption band of the light-emitting substance, energy transfer becomes smoother, and light emission can be obtained efficiently. This configuration simultaneously achieves high efficiency, low-voltage operation, and a long lifespan for the light-emitting element.

[0521] The EL layer may have, in addition to the light-emitting layer, one or more of the following: a layer containing a material with high hole injection properties (hole injection layer), a layer containing a hole transport material (hole transport layer), a layer containing a material with high electron blocking properties (electron blocking layer), a layer containing a material with high electron injection properties (electron injection layer), a layer containing an electron transport material (electron transport layer), and a layer containing a material with high hole blocking properties (hole blocking layer). Furthermore, the EL layer may also have a configuration that includes either or both a bipolar material and a TADF material.

[0522] The light-emitting element can use either low-molecular-weight compounds or high-molecular-weight compounds, and may also contain inorganic compounds. The layers constituting the light-emitting element can be formed by methods such as vapor deposition (including vacuum deposition), transfer, printing, inkjet, and coating.

[0523] A light-emitting element can be configured as either a single structure (having only one light-emitting unit) or a tandem structure (having multiple light-emitting units). Each light-emitting unit has at least one light-emitting layer. In a tandem structure, multiple light-emitting units are connected in series via a charge generation layer. The charge generation layer has the function of injecting electrons into one of the two light-emitting units and holes into the other when a voltage is applied between a pair of electrodes. By using a tandem structure, a light-emitting element capable of high-brightness emission can be created. Furthermore, compared to a single structure, a tandem structure can reduce the current required to obtain the same brightness, thereby improving reliability. The tandem structure can also be called a stacked structure.

[0524] In Figure 29, when using a tandem light-emitting element, it is preferable that the EL layer 113R has a structure having multiple light-emitting units that emit red light, the EL layer 113G has a structure having multiple light-emitting units that emit green light, and the EL layer 113B has a structure having multiple light-emitting units that emit blue light.

[0525] A protective layer 131 is provided on the light-emitting element 130R, light-emitting element 130G, and light-emitting element 130B. The protective layer 131 and the substrate 152 are bonded via an adhesive layer 149. A light-shielding layer 117 is provided on the substrate 152. For sealing the light-emitting elements, for example, a solid sealing structure or a hollow sealing structure can be applied. In Figure 29, the space between the substrate 152 and the substrate 151 is filled with the adhesive layer 149, and a solid sealing structure is applied. Alternatively, the space can be filled with an inert gas (such as nitrogen or argon), and a hollow sealing structure can be applied. In this case, the adhesive layer 149 can be provided in a frame shape so as not to overlap with the light-emitting elements. Furthermore, the space can be filled with a resin different from the adhesive layer 149 provided in a frame shape.

[0526] The protective layer 131 is provided at least on the display section 168, and preferably so as to cover the entire display section 168. It is preferable that the protective layer 131 covers not only the display section 168, but also the connection section 140 and the circuit section 164. Furthermore, it is preferable that the protective layer 131 extends to the end of the display device 50A. On the other hand, in the connection section 204, there is a portion where the protective layer 131 is not provided in order to connect the FPC 172 and the conductive layer 167.

[0527] By providing a protective layer 131 on the light-emitting element 130R, the light-emitting element 130G, and the light-emitting element 130B, the reliability of the light-emitting element can be improved.

[0528] The protective layer 131 can be a single layer or a laminated structure of two or more layers. Furthermore, the conductivity of the protective layer 131 is not required. At least one of an insulating film, a semiconductor film, and a conductive film can be used as the protective layer 131.

[0529] The presence of an inorganic film in the protective layer 131 prevents oxidation of the common electrode 135 and suppresses the intrusion of impurities that induce degradation of the light-emitting element (e.g., water, oxygen, etc.), thereby suppressing degradation of the light-emitting element and improving the reliability of the display device.

[0530] For example, inorganic insulating films such as oxide insulating films, nitride insulating films, oxidogenic nitride insulating films, and nitride oxide insulating films can be used for the protective layer 131. Specific examples of these inorganic insulating films are as described above. In particular, the protective layer 131 preferably has a nitride insulating film or a nitride oxide insulating film, and more preferably has a nitride insulating film.

[0531] Furthermore, the protective layer 131 may also be an inorganic film containing ITO, In-Zn oxide, Ga-Zn oxide, Al-Zn oxide, or IGZO. The inorganic film is preferably highly resistive, and more specifically, it is preferably more resistive than the common electrode 135. The inorganic film may also contain nitrogen.

[0532] When the light emitted from a light-emitting element is extracted via a protective layer 131, it is preferable that the protective layer 131 has high transmittance to visible light. For example, ITO, IGZO, and aluminum oxide are preferred because they are inorganic materials with high transmittance to visible light.

[0533] As the protective layer 131, for example, a laminated structure of an aluminum oxide film and a silicon nitride film on the aluminum oxide film, or a laminated structure of an aluminum oxide film and an IGZO film on the aluminum oxide film can be used. By using this laminated structure, it is possible to suppress the intrusion of impurities (e.g., water, oxygen, etc.) that can induce degradation of the light-emitting element into the EL layer.

[0534] Furthermore, the protective layer 131 can also have an organic film. For example, the protective layer 131 can have both an organic film and an inorganic film.

[0535] A connection portion 204 is provided in the region of substrate 151 where substrate 152 does not overlap. At the connection portion 204, wiring 165 is connected to FPC 172 via conductive layer 166, conductive layer 167, and connection layer 242. Wiring 165 is an example of a single-layer conductive layer obtained by processing the same conductive film as conductive layer 112a2. Conductive layer 166 is an example of a single-layer conductive layer obtained by processing the same conductive film as conductive layer 112b2_1 and conductive layer 112b2_2. Conductive layer 167 is an example of a single-layer conductive layer obtained by processing the same conductive film as pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B. On the upper surface of the connection portion 204, conductive layer 167 is exposed. This allows the connection portion 204 and FPC 172 to be connected via the connection layer 242.

[0536] The display device 50A is of the top-emission type. The light emitted by the light-emitting element is emitted towards the substrate 152. It is preferable to use a material with high transmittance to visible light for the substrate 152. The pixel electrodes 111R, 111G, and 111B contain a material that reflects visible light, and the counter electrode (common electrode 135) contains a material that transmits visible light.

[0537] It is preferable to provide a light-shielding layer 117 on the surface of the substrate 152 that faces the substrate 151. The light-shielding layer 117 can be provided between adjacent light-emitting elements, in connection parts 140, circuit parts 164, etc.

[0538] Furthermore, a colored layer, such as a color filter, can be provided on the surface of the substrate 152 facing the substrate 151, or on the protective layer 131. By placing a color filter on top of the light-emitting element, the color purity of the light emitted from the pixel can be increased.

[0539] Furthermore, various optical components can be placed on the outside of the substrate 152 (the side opposite to the substrate 151). Examples of optical components include polarizing plates, phase difference plates, light diffusion layers (such as diffusion films), anti-reflective layers, and light-gathering films. Additionally, surface protection layers such as an antistatic film to suppress dust adhesion, a water-repellent film to make it difficult for dirt to adhere, a hard coat film to suppress the occurrence of scratches during use, and an impact absorption layer can be placed on the outside of the substrate 152. For example, a glass layer or a silica layer (SiO₂) can be used as a surface protection layer. ｘ By providing a protective layer, surface contamination and scratching can be suppressed, which is preferable. Furthermore, DLC (diamond-like carbon), aluminum oxide (AlO2) can be used as the surface protective layer. ｘ Polyester-based materials or polycarbonate-based materials may also be used. It is preferable to use a material with high transmittance to visible light for the surface protective layer. Furthermore, it is preferable to use a material with high hardness for the surface protective layer.

[0540] The substrates 151 and 152 can be made of glass, quartz, ceramics, sapphire, resin, metal, alloy, semiconductor, etc. The substrate on the side that extracts light from the light-emitting element should be made of a material that transmits the light. If flexible materials are used for substrates 151 and 152, the flexibility of the display device can be increased, and a flexible display can be realized. In addition, a polarizing plate can be used as at least one of substrates 151 and 152.

[0541] As substrates 151 and 152, polyester resins such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamide-imide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. can be used. At least one of substrates 151 and 152 may also be made of glass of a thickness sufficient to provide flexibility.

[0542] Furthermore, when a circular polarizing plate is superimposed on a display device, it is preferable to use a substrate with high optical isotropy for the substrate of the display device. A substrate with high optical isotropy has low birefringence (or a small amount of birefringence). Examples of films with high optical isotropy include triacetylcellulose (TAC, also called cellulose triacetate) film, cycloolefin polymer (COP) film, cycloolefin copolymer (COC) film, and acrylic film.

[0543] As the adhesive layer 149, various types of curing adhesives can be used, such as UV-curing adhesives, reaction-curing adhesives, thermosetting adhesives, and anaerobic adhesives. Examples of these adhesives include epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, imide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, and EVA (ethylene vinyl acetate) resins. Materials with low moisture permeability, such as epoxy resins, are particularly preferred. Two-component mixed resins can also be used. Adhesive sheets can also be used.

[0544] As the connecting layer 242, an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), or the like can be used.

[0545] [Display Device 50B] The display device 50B shown in Figure 30 differs from the display device 50A in that each sub-pixel of each color uses a light-emitting element having a common EL layer 113 and a coloring layer (such as a color filter). In the following description of the display device, parts that are the same as those described earlier may be omitted.

[0546] The display device 50B shown in Figure 30 has, between substrates 151 and 152, transistors 205D, 205R1, 205R2, 205G1, 205G2, 205B1, 205B2, light-emitting elements 130R, 130G, 130B, a colored layer 132R that transmits red light, a colored layer 132G that transmits green light, a colored layer 132B that transmits blue light, and the like.

[0547] The light-emitting element 130R includes a pixel electrode 111R, an EL layer 113 on the pixel electrode 111R, and a common electrode 135 on the EL layer 113. The light emitted from the light-emitting element 130R is extracted as red light to the outside of the display device 50B via the colored layer 132R.

[0548] The light-emitting element 130G includes a pixel electrode 111G, an EL layer 113 on the pixel electrode 111G, and a common electrode 135 on the EL layer 113. The light emitted from the light-emitting element 130G is extracted as green light to the outside of the display device 50B via the colored layer 132G.

[0549] The light-emitting element 130B includes a pixel electrode 111B, an EL layer 113 on the pixel electrode 111B, and a common electrode 135 on the EL layer 113. The light emitted from the light-emitting element 130B is extracted as blue light to the outside of the display device 50B via the colored layer 132B.

[0550] The light-emitting element 130R, light-emitting element 130G, and light-emitting element 130B each have a common EL layer 113 and a common electrode 135. Providing a common EL layer 113 for each sub-pixel of each color reduces the number of manufacturing steps compared to providing a different EL layer for each sub-pixel of each color.

[0551] For example, the light-emitting elements 130R, 130G, and 130B shown in Figure 30 emit white light. The white light emitted by the light-emitting elements 130R, 130G, and 130B passes through the colored layers 132R, 132G, and 132B, respectively, to obtain light of a desired color.

[0552] A light-emitting element that emits white light preferably includes two or more light-emitting layers. When obtaining white light emission using two light-emitting layers, the light-emitting layers should be selected such that their emission colors are complementary. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary, a configuration that emits white light as a whole can be obtained. Also, when obtaining white light emission using three or more light-emitting layers, the emission colors of the three or more light-emitting layers should combine to produce white light as a whole.

[0553] The EL layer 113 preferably has, for example, an emissive layer having a light-emitting material that emits blue light, and an emissive layer having a light-emitting material that emits visible light with a longer wavelength than blue. The EL layer 113 preferably has, for example, an emissive layer that emits yellow light and an emissive layer that emits blue light. Alternatively, the EL layer 113 preferably has, for example, an emissive layer that emits red light, an emissive layer that emits green light, and an emissive layer that emits blue light.

[0554] For light-emitting elements that emit white light, a tandem structure is preferable. Specifically, a two-stage tandem structure having a light-emitting unit that emits yellow light and a light-emitting unit that emits blue light, a two-stage tandem structure having a light-emitting unit that emits red and green light and a light-emitting unit that emits blue light, a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light and a light-emitting unit that emits blue light in that order, or a three-stage tandem structure having a light-emitting unit that emits blue light, a light-emitting unit that emits yellow, yellow-green, or green light and red light and a light-emitting unit that emits blue light in that order. For example, the number of layers and color order of the light-emitting unit can be, from the anode side, a two-layer structure of B and Y, a two-layer structure of B and light-emitting unit X, a three-layer structure of B, Y, B, or a three-layer structure of B, X, B. The number of layers and color order of the light-emitting layers in light-emitting unit X can be, from the anode side, a two-layer structure of R and Y, a two-layer structure of R and G, a two-layer structure of G and R, a three-layer structure of G, R, G, or a three-layer structure of R, G, R. It is also possible to have a configuration in which other layers are provided between the two light-emitting layers.

[0555] Alternatively, for example, the light-emitting elements 130R, 130G, and 130B shown in Figure 30 emit blue light. In this case, the EL layer 113 has one or more light-emitting layers that emit blue light. In the sub-pixel 11B that emits blue light, the blue light emitted by the light-emitting element 130B can be extracted. In addition, in the sub-pixel 11R that emits red light and the sub-pixel 11G that emits green light, by providing a color conversion layer between the light-emitting element 130R or light-emitting element 130G and the substrate 152, the blue light emitted by the light-emitting element 130R or light-emitting element 130G can be converted into longer wavelength light, and red or green light can be extracted. Furthermore, it is preferable to provide a coloring layer 132R between the color conversion layer and the substrate 152 on the light-emitting element 130R, and a coloring layer 132G between the color conversion layer and the substrate 152 on the light-emitting element 130G. Some of the light emitted by the light-emitting elements may be transmitted as is without being converted by the color conversion layer. By extracting the light that has passed through the color conversion layer via the colored layer, the colored layer absorbs light of colors other than the desired color, thereby increasing the color purity of the light exhibited by the subpixel.

[0556] [Display device 50C] The display device 50C shown in Figure 31 differs from the display device 50B mainly in that it is a bottom-emission type display device.

[0557] The light emitted by the light-emitting element is emitted towards the substrate 151. It is preferable to use a material with high transmittance to visible light for the substrate 151. On the other hand, the light transmittance of the material used for the substrate 152 is not a requirement.

[0558] It is preferable to form a light-shielding layer 117 between the substrate 151 and the transistors. Figure 31 shows an example in which a light-shielding layer 117 is provided on the substrate 151, an insulating layer 153 is provided on the light-shielding layer 117, and transistors 205D, 205G1 and 205G2, 205B1 and 205B2, etc. are provided on the insulating layer 153. In addition, a colored layer 132G and a colored layer 132B are provided on the insulating layer 195, and an insulating layer 235 is provided on the colored layer 132G and the colored layer 132B.

[0559] Although not shown in Figure 31, the display device 50C is also provided with transistors 205R1 and 205R2, and a coloring layer 132R.

[0560] The light-emitting element 130G, which overlaps with the colored layer 132G, has a pixel electrode 111G, an EL layer 113, and a common electrode 135.

[0561] The light-emitting element 130B, which overlaps with the colored layer 132B, has a pixel electrode 111B, an EL layer 113, and a common electrode 135.

[0562] The pixel electrodes 111G and 111B are made of materials with high transmittance to visible light. It is preferable to use a material that reflects visible light for the common electrode 135. In a bottom-emission type display device, a metal with low resistance can be used for the common electrode 135, which suppresses voltage drops caused by the resistance of the common electrode 135 and enables the realization of high display quality.

[0563] A transistor according to one aspect of the present invention can be miniaturized and have a reduced footprint, which allows for an increase in the aperture ratio of pixels or a reduction in the size of pixels in a display device with a bottom emission structure.

[0564] [Display Device 50D] The display device 50D shown in Figure 32 is an example of a display device to which an MML (metal maskless) structure is applied. In other words, the display device 50D has a light-emitting element manufactured without using a fine metal mask. Note that the laminated structure from the substrate 151 to the insulating layer 235 and the laminated structure from the protective layer 131 to the substrate 152 are the same as those of the display device 50A, so their explanation is omitted.

[0565] In Figure 32, light-emitting elements 130R, 130G, and 130B are provided on the insulating layer 235.

[0566] The light-emitting element 130R includes a conductive layer 124R on an insulating layer 235, a conductive layer 126R on the conductive layer 124R, a layer 133R on the conductive layer 126R, a common layer 134 on the layer 133R, and a common electrode 135 on the common layer 134. The light-emitting element 130R shown in Figure 32 emits red light (R). Layer 133R has a light-emitting layer that emits red light. In the light-emitting element 130R, layer 133R and the common layer 134 can be collectively called the EL layer. In addition, one or both of the conductive layer 124R and the conductive layer 126R can be called the pixel electrode.

[0567] The light-emitting element 130G includes a conductive layer 124G on an insulating layer 235, a conductive layer 126G on the conductive layer 124G, a layer 133G on the conductive layer 126G, a common layer 134 on the layer 133G, and a common electrode 135 on the common layer 134. The light-emitting element 130G shown in Figure 32 emits green light (G). Layer 133G has a light-emitting layer that emits green light. In the light-emitting element 130G, layer 133G and the common layer 134 can be collectively called the EL layer. In addition, one or both of the conductive layer 124G and the conductive layer 126G can be called the pixel electrode.

[0568] The light-emitting element 130B includes a conductive layer 124B on an insulating layer 235, a conductive layer 126B on the conductive layer 124B, a layer 133B on the conductive layer 126B, a common layer 134 on the layer 133B, and a common electrode 135 on the common layer 134. The light-emitting element 130B shown in Figure 32 emits blue light (B). Layer 133B has a light-emitting layer that emits blue light. In the light-emitting element 130B, layer 133B and the common layer 134 can be collectively called the EL layer. In addition, one or both of the conductive layer 124B and the conductive layer 126B can be called the pixel electrode.

[0569] In this specification, among the EL layers of a light-emitting element, layers provided in an island-like manner for each light-emitting element are referred to as layer 133B, layer 133G, or layer 133R, and a layer common to multiple light-emitting elements is referred to as common layer 134. In this specification, the common layer 134 may be omitted, and layers 133R, 133G, and 133B may be referred to as island-like EL layers, island-shaped EL layers, etc.

[0570] Layers 133R, 133G, and 133B are separated from each other. By providing the EL layer in an island-like configuration for each light-emitting element, leakage current between adjacent light-emitting elements can be suppressed. This prevents unintended light emission caused by crosstalk, enabling the realization of a display device with extremely high contrast.

[0571] Note that in Figure 32, layers 133R, 133G, and 133B are all shown with the same film thickness, but this is not the only option. The film thicknesses of layers 133R, 133G, and 133B can also be different.

[0572] The conductive layer 124R is connected to the conductive layer 112b2_2 of the transistor 205R2 through openings provided in the insulating layers 106_2, 106_1, 195, and 235 located on the conductive layer 112b2_2.

[0573] Similarly, conductive layer 124G is connected to conductive layer 112b2_2 of transistor 205G2, and conductive layer 124B is connected to conductive layer 112b2_2 of transistor 205B2.

[0574] The conductive layer 124R, conductive layer 124G, and conductive layer 124B are formed to cover openings provided in the insulating layer 106_2, insulating layer 106_1, insulating layer 195, and insulating layer 235, which are located on the conductive layer 112b2_2, respectively. Layer 128 is embedded in the recesses of the conductive layer 124R, conductive layer 124G, and conductive layer 124B, respectively.

[0575] Layer 128 has the function of flattening the recesses of conductive layers 124R, 124G, and 124B. Conductive layers 126R, 126G, and 126B are provided on conductive layers 124R, 124G, and 128, respectively, and are connected to conductive layers 124R, 124G, and 124B. Therefore, the regions overlapping with the recesses of conductive layers 124R, 124G, and 124B can also be used as light-emitting regions, thereby increasing the aperture ratio of the pixels. It is preferable to use conductive layers that function as reflective electrodes for conductive layers 124R and 126R.

[0576] Layer 128 may be an insulating layer or a conductive layer. Various inorganic insulating materials, organic insulating materials, and conductive materials can be used for layer 128 as appropriate. In particular, it is preferable that layer 128 be formed using an insulating material, and especially preferable that it be formed using an organic insulating material. For example, an organic insulating material that can be used for the insulating layer 237 described above can be applied to layer 128.

[0577] Figure 32 shows an example in which the upper surface of layer 128 has a flat portion, but the shape of layer 128 is not particularly limited. The upper surface of layer 128 can have at least one of a convex curved surface, a concave curved surface, and a flat surface.

[0578] Furthermore, the height of the upper surface of layer 128 and the height of the upper surface of the conductive layer 124R can be the same or approximately the same, or they can be different. For example, the height of the upper surface of layer 128 can be lower or higher than the height of the upper surface of the conductive layer 124R.

[0579] The end of the conductive layer 126R can be aligned with the end of the conductive layer 124R, or it can cover the side surface of the end of the conductive layer 124R. Preferably, the ends of both the conductive layer 124R and the conductive layer 126R have a tapered shape. Specifically, it is preferable that the ends of both the conductive layer 124R and the conductive layer 126R have a tapered shape with a taper angle of less than 90 degrees. When the end of the pixel electrode has a tapered shape, the layer 133R provided along the side surface of the pixel electrode has an inclined portion. By making the side surface of the pixel electrode tapered, the coverage of the EL layer provided along the side surface of the pixel electrode can be improved.

[0580] Since conductive layers 124G and 126G, and conductive layers 124B and 126B are the same as conductive layers 124R and 126R, a detailed explanation is omitted.

[0581] The top and sides of the conductive layer 126R are covered by layer 133R. Similarly, the top and sides of the conductive layer 126G are covered by layer 133G, and the top and sides of the conductive layer 126B are covered by layer 133B. Therefore, the entire regions where conductive layers 126R, 126G, and 126B are provided can be used as light-emitting regions for light-emitting elements 130R, 130G, and 130B, respectively, thereby increasing the aperture ratio of the pixels.

[0582] The upper surfaces and sides of layers 133R, 133G, and 133B are covered by insulating layers 125 and 127, respectively. A common layer 134 is provided on layer 133R, layer 133G, layer 133B, insulating layer 125, and insulating layer 127, and a common electrode 135 is provided on the common layer 134. The common layer 134 and the common electrode 135 are both continuous films provided in common to multiple light-emitting elements.

[0583] In Figure 32, the insulating layer 237 shown in Figure 29, etc., is not provided between the conductive layer 126R and layer 133R. In other words, the display device 50D does not have an insulating layer (also called a partition, bank, spacer, etc.) that is in contact with the pixel electrodes and covers the upper edges of the pixel electrodes. Therefore, the spacing between adjacent light-emitting elements can be made extremely narrow. Consequently, a high-definition or high-resolution display device can be made. In addition, a mask for forming the insulating layer is not required, and the manufacturing cost of the display device can be reduced.

[0584] As described above, layers 133R, 133G, and 133B each have an emissive layer. Preferably, layers 133R, 133G, and 133B each have an emissive layer and a carrier transport layer (electron transport layer or hole transport layer) on the emissive layer. Alternatively, preferably layers 133R, 133G, and 133B each have an emissive layer and a carrier block layer (hole block layer or electron block layer) on the emissive layer. Alternatively, preferably layers 133R, 133G, and 133B each have an emissive layer, a carrier block layer on the emissive layer, and a carrier transport layer on the carrier block layer. Since the surfaces of layers 133R, 133G, and 133B are exposed during the manufacturing process of the display device, providing one or both of the carrier transport layer and the carrier block layer on the emissive layer suppresses exposure of the emissive layer to the outermost surface and reduces damage to the emissive layer. This can improve the reliability of the light-emitting element.

[0585] The common layer 134 may have, for example, an electron injection layer or a hole injection layer. Alternatively, the common layer 134 may have a configuration in which an electron transport layer and an electron injection layer are stacked, or a configuration in which a hole transport layer and a hole injection layer are stacked. The common layer 134 is shared by the light-emitting element 130R, the light-emitting element 130G, and the light-emitting element 130B.

[0586] Each side of layer 133R, layer 133G, and layer 133B is covered by the insulating layer 125. The insulating layer 127 covers each side of layer 133R, layer 133G, and layer 133B via the insulating layer 125.

[0587] The sides (and even a portion of the top surface) of layers 133R, 133G, and 133B are covered by at least one of the insulating layers 125 and 127. This prevents the common layer 134 (or common electrode 135) from coming into contact with the pixel electrode and the respective sides of layers 133R, 133G, and 133B, thereby suppressing short circuits in the light-emitting element. This improves the reliability of the light-emitting element.

[0588] The insulating layer 125 is preferably in contact with the respective sides of layers 133R, 133G, and 133B. By configuring the insulating layer 125 to be in contact with layers 133R, 133G, and 133B, peeling of the layers 133R, 133G, and 133B can be prevented, thereby improving the reliability of the light-emitting element.

[0589] The insulating layer 127 is provided on the insulating layer 125 so as to fill any recesses in the insulating layer 125. Preferably, the insulating layer 127 covers at least a portion of the side surface of the insulating layer 125.

[0590] By providing insulating layers 125 and 127, the gaps between adjacent island-shaped layers can be filled, thereby reducing the large height differences and irregularities on the surface of layers formed on the island-shaped layers (e.g., carrier injection layers, common electrodes, etc.), making it flatter. Consequently, the coverage of carrier injection layers, common electrodes, etc. can be improved.

[0591] The common layer 134 and the common electrode 135 are provided on layer 133R, layer 133G, layer 133B, insulating layer 125, and insulating layer 127. Before the insulating layer 125 and insulating layer 127 are provided, a step difference occurs due to the region where the pixel electrode and island-shaped EL layer are provided and the region where the pixel electrode and island-shaped EL layer are not provided (the region between light-emitting elements). In one embodiment of the present invention, the presence of the insulating layer 125 and insulating layer 127 can flatten this step difference and improve the coverage of the common layer 134 and the common electrode 135. Therefore, connection failures due to step breaks in the common layer 134 or the common electrode 135 can be suppressed. In addition, it is possible to suppress the local thinning of the common electrode 135 due to the step difference, which would increase the electrical resistance.

[0592] The upper surface of the insulating layer 127 preferably has a shape that is more flat. The upper surface of the insulating layer 127 may also have a configuration that includes at least one of a flat surface, a convex curved surface, and a concave curved surface. For example, the upper surface of the insulating layer 127 preferably has a smooth, highly flat convex curved surface shape.

[0593] The insulating layer 125 can be an insulating layer having an inorganic material. For example, inorganic insulating films such as oxide insulating films, nitride insulating films, oxidogenic nitride insulating films, and nitride oxide insulating films can be used for the insulating layer 125. Specific examples of these inorganic insulating films are as described above. The insulating layer 125 can be a single-layer structure or a laminated structure. In particular, aluminum oxide is preferred because it has a high selectivity ratio with the EL layer during etching and has the function of protecting the EL layer in the formation of the insulating layer 127, which will be described later. In particular, by applying an inorganic insulating film such as an aluminum oxide film, hafnium oxide film, or silicon oxide film formed by the ALD method to the insulating layer 125, an insulating layer 125 with few pinholes and excellent function in protecting the EL layer can be formed. The insulating layer 125 can also be a laminated structure of a film formed by the ALD method and a film formed by the sputtering method. For example, the insulating layer 125 can be a laminated structure of an aluminum oxide film formed by the ALD method and a silicon nitride film formed by the sputtering method.

[0594] Preferably, the insulating layer 125 functions as a barrier insulating layer against at least one of water and oxygen. Furthermore, preferably, the insulating layer 125 has the function of suppressing the diffusion of at least one of water and oxygen. Also, preferably, the insulating layer 125 has the function of capturing or fixing (also called gettering) at least one of water and oxygen.

[0595] The insulating layer 125 has the function of a barrier insulating layer or a gettering function, thereby suppressing the diffusion of impurities (substances that can induce degradation of the light-emitting elements; typically, at least one of water and oxygen) that could diffuse from the outside to each light-emitting element. This configuration makes it possible to provide a highly reliable light-emitting element and, furthermore, a highly reliable display device.

[0596] Furthermore, it is preferable that the insulating layer 125 has a low impurity concentration. This suppresses the diffusion of impurities from the insulating layer 125 to the EL layer, thereby preventing the deterioration of the EL layer. In addition, by lowering the impurity concentration in the insulating layer 125, the barrier properties against at least one of water and oxygen can be improved. For example, it is desirable that the insulating layer 125 has a sufficiently low hydrogen concentration and a sufficiently low carbon concentration, preferably both.

[0597] The insulating layer 127, provided on the insulating layer 125, has the function of flattening the large height differences and irregularities in the insulating layer 125 formed between adjacent light-emitting elements. In other words, the presence of the insulating layer 127 has the effect of improving the flatness of the surface forming the common electrode 135.

[0598] As the insulating layer 127, an insulating layer having an organic material can be suitably used. Preferably, a photosensitive organic resin is used as the organic material; for example, a photosensitive resin composition containing an acrylic resin is preferred. In this specification, the term "acrylic resin" does not refer only to polymethacrylate esters or methacrylic resins, but may refer to acrylic polymers in a broad sense.

[0599] Furthermore, as the insulating layer 127, acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimidoamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenol resin, precursors of these resins, etc., can also be used. Additionally, as the insulating layer 127, organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin can also be used. Furthermore, as the photosensitive resin, photoresist can be used. As the photosensitive organic resin, either a positive-type material or a negative-type material can be used.

[0600] The insulating layer 127 can also be made of a material that absorbs visible light. By absorbing the light emitted from the light-emitting element, the insulating layer 127 can suppress light leakage (stray light) from the light-emitting element to adjacent light-emitting elements through the insulating layer 127. This improves the display quality of the display device. Furthermore, since the display quality can be improved without using a polarizing plate in the display device, the display device can be made lighter and thinner.

[0601] Examples of materials that absorb visible light include materials containing pigments such as black, materials containing dyes, light-absorbing resin materials (e.g., polyimide), and resin materials that can be used in color filters (color filter materials). In particular, it is preferable to use a resin material obtained by laminating or mixing two or more color filter materials, as this can enhance the visible light shielding effect. In particular, by mixing three or more color filter materials, it is possible to create a black or near-black resin layer.

[0602] This embodiment can be combined with other embodiments as appropriate.

[0603] (Embodiment 5) In this embodiment, an electronic device according to one aspect of the present invention will be described with reference to Figures 33A to 35G.

[0604] The electronic device of this embodiment has a display device according to one aspect of the present invention in its display unit. The display device according to one aspect of the present invention is easily made high-definition and high-resolution. Therefore, it can be used in the display units of various electronic devices.

[0605] Examples of electronic devices include television sets, desktop or notebook personal computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as other electronic devices with relatively large screens, digital cameras, digital video cameras, digital photo frames, mobile phones, portable game consoles, personal digital assistants, and audio playback devices.

[0606] In particular, a display device according to one aspect of the present invention can be used suitably in electronic devices having a relatively small display area because it can increase the resolution. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), as well as wearable devices that can be worn on the head, such as VR devices such as head-mounted displays, AR devices such as glasses, and MR devices.

[0607] The electronic device of this embodiment may have sensors (including functions for detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared radiation).

[0608] The electronic device of this embodiment can have a variety of functions. For example, it can have a function to display various information (still images, videos, text images, etc.) on the display unit, a touch panel function, a function to display a calendar, date or time, a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, and so on.

[0609] Figures 33A to 33D illustrate an example of a wearable device that can be worn on the head. These wearable devices have at least one of the following functions: a function to display AR content, a function to display VR content, a function to display SR content, and a function to display MR content. By having an electronic device that has the function to display at least one of AR, VR, SR, and MR content, it is possible to enhance the user's sense of immersion.

[0610] The electronic device 700A shown in Figure 33A and the electronic device 700B shown in Figure 33B each include a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.

[0611] A display device according to one embodiment of the present invention can be applied to the display panel 751. Therefore, an electronic device capable of displaying extremely high resolution can be created.

[0612] Electronic devices 700A and 700B can project an image displayed on the display panel 751 onto the display area 756 of the optical element 753. Because the optical element 753 is translucent, the user can see the image displayed on the display area superimposed on the transmitted image visible through the optical element 753. Therefore, electronic devices 700A and 700B are electronic devices capable of AR display.

[0613] Electronic devices 700A and 700B may each be equipped with a camera capable of capturing images of the area in front of them as an imaging unit. Furthermore, electronic devices 700A and 700B may each be equipped with an acceleration sensor such as a gyro sensor to detect the orientation of the user's head and display an image corresponding to that orientation in the display area 756.

[0614] The communications unit has a wireless communication device, which can supply video signals and the like. Alternatively, instead of the wireless communication device, or in addition to the wireless communication device, it may be equipped with a connector to which a cable supplying video signals and power potential can be connected.

[0615] Electronic devices 700A and 700B are each equipped with a battery (not shown) which can be charged wirelessly, wired, or both.

[0616] The housing 721 may be equipped with a touch sensor module. The touch sensor module has the function of detecting when the outer surface of the housing 721 is touched. The touch sensor module can detect the user's tap or slide operations and perform various processes. For example, a tap operation can be used to pause or resume the video, and a slide operation can be used to fast forward or rewind. Furthermore, by providing a touch sensor module in each of the two housings 721, the range of operations can be expanded.

[0617] Various types of touch sensors can be applied to the touch sensor module. For example, various methods such as capacitive, resistive, infrared, electromagnetic induction, surface acoustic wave, and optical sensors can be used. In particular, it is preferable to apply a capacitive or optical sensor to the touch sensor module.

[0618] When using an optical touch sensor, a photoelectric conversion element can be used as the light-receiving element. The active layer of the photoelectric conversion element can be made of either an inorganic semiconductor or an organic semiconductor, or both.

[0619] The electronic device 800A shown in Figure 33C and the electronic device 800B shown in Figure 33D each include a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.

[0620] A display device according to one embodiment of the present invention can be applied to the display unit 820. Therefore, an electronic device capable of displaying extremely high resolution can be created. This allows the user to experience a high level of immersion.

[0621] The display unit 820 is located inside the housing 821 in a position where it can be viewed through the lens 832. Furthermore, by displaying different images on a pair of display units 820, a three-dimensional display using parallax can also be performed.

[0622] Electronic devices 800A and 800B can each be described as electronic devices for VR. A user wearing electronic device 800A or electronic device 800B can view the image displayed on the display unit 820 through the lens 832.

[0623] It is preferable that electronic devices 800A and 800B each have a mechanism that allows adjustment of the left and right positions of the lens 832 and the display unit 820 so that they are in the optimal position according to the user's eye position. It is also preferable that they have a mechanism that adjusts the focus by changing the distance between the lens 832 and the display unit 820.

[0624] The attachment portion 823 allows the user to attach the electronic device 800A or 800B to their head. While the attachment portion 823 is exemplified in Figure 33C and other figures as resembling the temples of eyeglasses, it is not limited to this. The attachment portion 823 only needs to be wearable by the user; for example, it may be helmet-shaped or band-shaped.

[0625] The imaging unit 825 has the function of acquiring external information. The data acquired by the imaging unit 825 can be output to the display unit 820. An image sensor can be used in the imaging unit 825. In addition, multiple cameras may be provided to accommodate multiple angles of view, such as telephoto and wide-angle.

[0626] Although an example with an imaging unit 825 is shown here, any distance measuring sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object can be provided. In other words, the imaging unit 825 is one form of a detection unit. As the detection unit, for example, an image sensor or a distance image sensor such as LiDAR (Light Detection and Ranging) can be used. By using the image obtained by the camera and the image obtained by the distance image sensor, more information can be acquired, enabling more accurate gesture control.

[0627] The electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone. For example, a configuration having such a vibration mechanism can be applied to one or more of the display unit 820, housing 821, and mounting unit 823. This eliminates the need for separate audio equipment such as headphones, earphones, or speakers, allowing users to enjoy video and audio simply by wearing the electronic device 800A.

[0628] Electronic devices 800A and 800B may each have input terminals. Cables that supply video signals from video output devices, power for charging batteries provided in the electronic devices, etc., can be connected to the input terminals.

[0629] An electronic device according to one aspect of the present invention may have a function for wireless communication with an earphone 750. The earphone 750 has a communication unit (not shown) and has a wireless communication function. The earphone 750 can receive information (for example, voice data) from the electronic device through its wireless communication function. For example, the electronic device 700A shown in Figure 33A has a function for transmitting information to the earphone 750 through its wireless communication function. Also, for example, the electronic device 800A shown in Figure 33C has a function for transmitting information to the earphone 750 through its wireless communication function.

[0630] The electronic device may have an earphone section. The electronic device 700B shown in Figure 33B has an earphone section 727. For example, the earphone section 727 and the control unit can be connected to each other by a wire. Part of the wiring connecting the earphone section 727 and the control unit may be located inside the housing 721 or the mounting section 723.

[0631] Similarly, the electronic device 800B shown in Figure 33D has an earphone unit 827. For example, the earphone unit 827 and the control unit 824 can be connected to each other by a wire. Part of the wiring connecting the earphone unit 827 and the control unit 824 may be located inside the housing 821 or the mounting unit 823. Also, the earphone unit 827 and the mounting unit 823 may have mag...

Claims

It comprises a first conductive layer to a sixth conductive layer, a first insulating layer to a fourth insulating layer, a first semiconductor layer and a second semiconductor layer, The first insulating layer is located on the first conductive layer, The second conductive layer is located on the first insulating layer, The second insulating layer is located on the second conductive layer and the first insulating layer, and has grooves that reach the second conductive layer. The first side surface and the second side surface of the second insulating layer within the groove face each other. The third conductive layer and the fourth conductive layer are located on the second insulating layer. The first side surface and the side surface of the third conductive layer are approximately coincident, and the second side surface and the side surface of the fourth conductive layer are approximately coincident. The first semiconductor layer is in contact with the upper surface, first side surface, second side surface of the second conductive layer, the upper surface and side surface of the third conductive layer, and the upper surface and side surface of the fourth conductive layer within the groove. The third insulating layer is located on the first semiconductor layer and the second insulating layer. The fifth conductive layer is located on the third insulating layer, The first insulating layer, the second insulating layer, the third insulating layer, and the fifth conductive layer each have an opening that reaches the first conductive layer. The second semiconductor layer is in contact with the upper surface of the first conductive layer within the opening, the side surface of the second insulating layer within the opening, and the upper and side surfaces of the fifth conductive layer. The fourth insulating layer is located on the second semiconductor layer, The sixth conductive layer is located on the fourth insulating layer such that it has a region that overlaps with the opening. Semiconductor equipment. 　 It comprises a first conductive layer to a fourth conductive layer, a first insulating layer to a fourth insulating layer, a first semiconductor layer and a second semiconductor layer, The first insulating layer is located on the first conductive layer, The second conductive layer is located on the first insulating layer, The second insulating layer is located on the second conductive layer and the first insulating layer, and has grooves that reach the second conductive layer. The third conductive layer is located on the second insulating layer, The first side surface of the second insulating layer and the side surface of the third conductive layer within the groove are roughly coincide. The first semiconductor layer is in contact with the upper surface of the second conductive layer, the first side surface, the second side surface of the second insulating layer within the groove, the upper surface and side surface of the third conductive layer, and the upper surface of the second insulating layer. The third insulating layer is located on the first semiconductor layer and the second insulating layer. The first insulating layer, the second insulating layer, and the third insulating layer each have an opening that reaches the first conductive layer. The second semiconductor layer is in contact with the upper surface of the first conductive layer within the opening, the side surface of the second insulating layer within the opening, and the upper surface of the third insulating layer within the groove. The fourth insulating layer is located on the second semiconductor layer, The fourth conductive layer is located on the fourth insulating layer such that it has a region that overlaps with the opening. Semiconductor equipment. 　 It comprises a first conductive layer to a third conductive layer, a first insulating layer to a fourth insulating layer, a first semiconductor layer and a second semiconductor layer, The first insulating layer is located on the first conductive layer, The second insulating layer is located on the first insulating layer and has grooves that reach the first insulating layer. The second conductive layer is located on the second insulating layer, The first side surface of the second insulating layer and the side surface of the second conductive layer within the groove are roughly coincidental. The first semiconductor layer is in contact with the upper surface, the first side surface, the second side surface of the second insulating layer within the groove, the upper surface and the side surface of the second conductive layer, and the upper surface of the second insulating layer. The third insulating layer is located on the first semiconductor layer and the second insulating layer. The first insulating layer, the second insulating layer, and the third insulating layer each have an opening that reaches the first conductive layer. The second semiconductor layer is in contact with the upper surface of the first conductive layer within the opening, the side surface of the second insulating layer within the opening, and the upper surface of the third insulating layer within the groove. The fourth insulating layer is located on the second semiconductor layer, The third conductive layer is located on the fourth insulating layer such that it has a region that overlaps with the opening. Semiconductor equipment. 　 In any one of claims 1 to 3, The first semiconductor layer and the second semiconductor layer each contain indium and oxygen, The first insulating layer comprises silicon and nitrogen. The aforementioned second insulating layer comprises a fifth insulating layer, a sixth insulating layer on the fifth insulating layer, and a seventh insulating layer on the sixth insulating layer. The fifth insulating layer and the seventh insulating layer each contain silicon and nitrogen. The sixth insulating layer comprises silicon and oxygen. Semiconductor equipment. 　 In claim 1 or claim 2, The third conductive layer has one or more of copper, silver, gold, or aluminum. Semiconductor equipment. 　 In claim 3, The second conductive layer has one or more of copper, silver, gold, or aluminum. Semiconductor equipment. 　 In claim 3 or claim 6, The first semiconductor layer has a first region within the groove that is in contact with the first insulating layer. The first region has lower electrical resistance than the regions of the first semiconductor layer other than the first region. Semiconductor equipment. 　 The semiconductor device described in claim 1 is provided with two adjacent devices, In each of the two semiconductor devices, The first conductive layer, the fourth conductive layer, and the fifth conductive layer each extend in a first direction in a plan view, The third conductive layer and the sixth conductive layer each extend in a second direction perpendicular to the first direction in a plan view. The width of each of the first conductive layer, the fourth conductive layer, and the fifth conductive layer in the second direction is 1.0 μm or more and 2.0 μm or less. The width of the third conductive layer and the sixth conductive layer in the first direction is 1.0 μm or more and 2.0 μm or less. The spacing between adjacent first conductive layers, fourth conductive layers, and fifth conductive layers in the second direction is 1.0 μm or more and 2.0 μm or less. Display device. 　 A first conductive layer, a first insulating film, a second conductive layer overlapping the first conductive layer, a second insulating film, and a third conductive layer overlapping the second conductive layer are formed in this order. A portion of the third conductive layer and the second insulating film is removed to form a groove reaching the second conductive layer, and a fourth conductive layer and a fifth conductive layer are formed from the third conductive layer, and a first insulating layer is formed from the second insulating film. A first semiconductor layer is formed in contact with the upper surface of the second conductive layer within the groove, the first side surface of the first insulating layer within the groove, the second side surface of the first insulating layer within the groove, the upper and side surfaces of the fourth conductive layer, and the upper and side surfaces of the fifth conductive layer. A third insulating film and a sixth conductive layer are formed in this order on the first semiconductor layer and the first insulating layer. A portion of the sixth conductive layer, the third insulating film, the first insulating layer, and the first insulating film are removed to form an opening that reaches the first conductive layer, and a seventh conductive layer is formed from the sixth conductive layer, a second insulating layer from the third insulating film, a third insulating layer from the first insulating layer, and a fourth insulating layer from the first insulating film. A second semiconductor layer is formed in contact with the upper surface of the first conductive layer within the opening, the side surface of the third insulating layer within the opening, the side surface of the seventh conductive layer within the opening, and the upper surface of the seventh conductive layer. A fifth insulating layer is formed on the second semiconductor layer and the seventh conductive layer. An eighth conductive layer is formed on the fifth insulating layer, overlapping the opening. Method for manufacturing semiconductor devices.

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