Semiconductor storage device

Abstract

SRAM cells (C0, C1) are disposed adjacent to each other in a first direction. The SRAM cell (C0) is provided with a first word line that is formed in a backside wiring layer and that extends in a second direction. The SRAM cell (C1) is provided with a second word line that is formed in a metal wiring layer and that extends in the second direction. The first and second word lines are formed to straddle the cell boundary between the SRAM cell (C0) and the SRAM cell (C1).

Description

Semiconductor memory device

[0001] The present disclosure relates to a semiconductor memory device, and particularly to the layout structure of SRAM (Static Random Access Memory) cells (hereinafter, also simply referred to as cells as appropriate).

[0002] SRAM is widely used in semiconductor integrated circuits.

[0003] In addition, transistors, which are basic components of LSIs, have achieved improvements in integration density, reduction in operating voltage, and improvement in operating speed by reducing the gate length (scaling). However, in recent years, the off-current due to excessive scaling and the resulting significant increase in power consumption have become problems. To solve this problem, three-dimensional structure transistors with a transistor structure changed from the conventional planar type to a three-dimensional type have been actively studied. As an example of a three-dimensional structure transistor, there is a nanosheet FET (Field Effect Transistor).

[0004] In Patent Document 1, an SRAM is disclosed in which memory cells connected via wiring on the front surface side of the memory cell and memory cells connected via wiring on the back surface side of the memory cell are mixed with a word line signal output from a word line driver.

[0005] U.S. Patent Application Publication No. 2024 / 0251540

[0006] With the miniaturization of semiconductor integrated circuit devices, the wiring resistance has increased, resulting in a decrease in the operating speed of the semiconductor integrated circuit device. The technology of Patent Document 1 cannot cope with this.

[0007] An object of the present disclosure is to improve the operating speed of a semiconductor memory device in the layout structure of SRAM cells.

[0008] In aspects of the present disclosure, a semiconductor memory device comprising a plurality of SRAM cells, the plurality of SRAM cells comprising first and second SRAM cells arranged adjacent to each other in a first direction, wherein the first SRAM cell comprises a first transistor and a first word line formed on a back wiring layer on the back side of the first transistor and extending in a second direction perpendicular to the first direction, and the second SRAM cell comprises a second word line formed on a metal wiring layer above the first transistor and extending in the second direction, wherein the first and second word lines are formed across the cell boundary between the first SRAM cell and the second SRAM cell.

[0009] According to this disclosure, in first and second SRAM cells arranged adjacent to each other in a first direction, the first and second word lines can be arranged across the first and second SRAM cells. As a result, the wiring width of the word lines can be increased and the wiring resistance of the word lines can be suppressed, thereby improving the operating speed of the semiconductor memory device.

[0010] According to this disclosure, the operating speed of a semiconductor memory device can be improved in the layout structure of an SRAM cell.

[0011] A plan view showing an example of the layout structure of an SRAM cell according to the first embodiment. A cross-sectional view showing an example of the layout structure of an SRAM cell according to the first embodiment. A cross-sectional view showing an example of the layout structure of an SRAM cell according to the first embodiment. A circuit diagram showing the configuration of an SRAM cell according to the first embodiment. A plan view showing an example of the layout of a circuit block provided in a semiconductor memory device according to the first embodiment. A plan view showing another example of the layout structure of an SRAM cell according to the first embodiment. A plan view showing another example of the layout of a circuit block provided in a semiconductor memory device according to the first embodiment. A plan view showing an example of the layout structure of an SRAM cell according to the second embodiment. A circuit diagram showing the configuration of an SRAM cell according to the second embodiment.

[0012] Embodiments will be described below with reference to the drawings. In the following embodiments, the semiconductor memory device comprises a plurality of SRAM cells, and at least some of these SRAM cells are equipped with nanosheet FETs. A nanosheet FET is an FET that uses a thin sheet (nanosheet) through which electric current flows. The nanosheet is formed from, for example, silicon. In this disclosure, the transistors provided in the SRAM cells are not limited to nanosheet FETs.

[0013] Furthermore, in this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. Also, in this specification, expressions meaning that widths, etc., are the same, such as "same wiring width," include a range of manufacturing variations.

[0014] (First Embodiment) (Configuration of SRAM Cell) Figures 1 to 3 show examples of the layout structure of an SRAM cell according to the first embodiment, where Figures 1(a) and 1(b) are plan views, and Figures 2(a) and 2(b) and 3(a) and 3(b) are cross-sectional views in the lateral direction in a plan view. Specifically, Figure 1(a) shows the upper part of the cell, and Figure 1(b) shows the lower part of the cell. Figure 2(a) is a cross-section of line X1-X1', Figure 2(b) is a cross-section of line X2-X2', Figure 3(a) is a cross-section of line X3-X3', and Figure 3(b) is a cross-section of line X4-X4'.

[0015] In the following explanation, in plan views such as Figure 1, the vertical direction of the drawing is defined as the Y direction (first direction), the horizontal direction of the drawing (second direction) as the X direction, and the direction perpendicular to the substrate surface as the Z direction.

[0016] Furthermore, in the following explanation, the dashed lines running vertically and horizontally in plan views such as Figure 1, and the dashed lines running vertically in cross-sectional views such as Figure 2, indicate a grid used for arranging components during the design phase. The grid is arranged at equal intervals in the X direction and at equal intervals in the Y direction. Note that the grid spacing may be the same or different in the X and Y directions. Also, the grid spacing may differ from layer to layer. Moreover, each component does not necessarily have to be placed on the grid.

[0017] Furthermore, in plan views such as Figure 1, the dotted lines surrounding the cells indicate the cell frame (outer edge of the SRAM cell) of the SRAM cell. SRAM cells are arranged so that their cell frames touch the cell frames of adjacent cells in the X or Y direction.

[0018] Furthermore, in the plan view shown in Figure 1, etc., inverted versions of SRAM cells C0 and C1 are placed on both sides of SRAM cells C0 and C1 in the X direction. SRAM cell C1 is placed below SRAM cell C0 in the drawing, and SRAM cell C0 is placed above SRAM cell C1 in the drawing.

[0019] As shown in Figure 1, SRAM cells C0 and C1 are arranged side by side in the Y direction.

[0020] Figure 4 is a circuit diagram showing the configuration of an SRAM cell according to the first embodiment. As shown in Figure 4, the SRAM cell C0 is configured with an SRAM circuit consisting of load transistors PU10 and PU20, drive transistors PD10 and PD20, and access transistors PG10 and PG20. The load transistors PU10 and PU20 are P-type FETs, and the drive transistors PD10 and PD20 and access transistors PG10 and PG20 are N-type FETs.

[0021] The load transistor PU10 is located between the power supply VDD and the first node NA0, and the drive transistor PD10 is located between the first node NA0 and the power supply VSS. The gates of the load transistor PU10 and the drive transistor PD10 are connected to the second node NB0, forming the inverter INV10. The load transistor PU20 is located between the power supply VDD and the second node NB0, and the drive transistor PD20 is located between the second node NB0 and the power supply VSS. The gates of the load transistor PU20 and the drive transistor PD20 are connected to the first node NA0, forming the inverter INV20. That is, the output of one inverter is connected to the input of the other inverter, thereby forming a latch.

[0022] Access transistor PG10 is located between bit line BL0 and first node NA0, and its gate is connected to word line WL0. Access transistor PG20 is located between bit line BLB0 and second node NB0, and its gate is connected to word line WL0. Bit lines BL0 and BLB0 form a complementary bit line pair.

[0023] In the SRAM circuit of SRAM cell C0, when the bit lines BL0 and BLB0, which constitute a complementary bit line pair, are driven to a high level and a low level, respectively, and the word line WL0 is driven to a high level, a high level is written to the first node NA0 and a low level is written to the second node NB0. On the other hand, when the bit lines BL0 and BLB0 are driven to a low level and a high level, respectively, and the word line WL0 is driven to a high level, a low level is written to the first node NA0 and a high level is written to the second node NB0. Then, when the word line WL0 is driven to a low level while data is written to the first and second nodes NA0 and NB0 respectively, the latch state is established and the data written to the first and second nodes NA0 and NB0 is held.

[0024] Furthermore, by pre-charging bit lines BL0 and BLB0 to a high level and driving word line WL0 to a high level, the states of bit lines BL0 and BLB0 are determined according to the data written to the first and second nodes NA0 and NB0, respectively, allowing data to be read from the SRAM cells. Specifically, if the first node NA0 is at a high level and the second node NB0 is at a low level, bit line BL0 remains at a high level and bit line BLB0 is discharged to a low level. On the other hand, if the first node NA0 is at a low level and the second node NB0 is at a high level, bit line BL0 is discharged to a low level and bit line BLB0 remains at a high level.

[0025] As described above, SRAM cell C0 has the functions of writing data to SRAM cell C0, holding data, and reading data from SRAM cell C0 by controlling bit lines BL0, BLB0 and word line WL0.

[0026] SRAM cell C1 has an SRAM cell circuit that is almost the same as that of SRAM cell C0. Specifically, SRAM cell C1 has an SRAM circuit composed of load transistors PU11 and PU21, drive transistors PD11 and PD21, and access transistors PG11 and PG21. The load transistors PU11 and PU21 are P-type FETs, and the drive transistors PD11 and PD21 and access transistors PG11 and PG21 are N-type FETs.

[0027] The SRAM cell circuit configured in SRAM cell C1 has the same configuration as the SRAM cell circuit configured in SRAM cell C0, so a detailed explanation is omitted. SRAM cell C1 has the functions of writing data to SRAM cell C1, holding data, and reading data from SRAM cell C1 by controlling the bit lines BL0, BLB0 and word line WL1.

[0028] As shown in Figure 1(b), a BM0 (Backside Metal 0) wiring layer, which is a wiring layer, is formed on the back of the semiconductor chip on which the transistor is formed. The BM0 wiring layer corresponds to the back wiring layer.

[0029] A wiring 11 extending in the X direction is formed in the BM0 wiring layer. The wiring 11 corresponds to the word line WL0. The wiring 11 is formed across the cell boundaries of SRAM cells C0 and C1.

[0030] The N-type transistor region has multiple active regions that constitute the channel, source, and drain of the N-type transistor. Specifically, the N-type transistor region has active regions N1 and N2. In a plan view, the active regions N1 and N2 overlap with the wiring 11.

[0031] Access transistors PG10, PG11 and drive transistors PD10, PD11 are formed in the active region N1. Access transistors PG20, PG21 and drive transistors PD20, PD21 are formed in the active region N2. The drive transistors PD10, PD11, PD20, PD21 and the access transistors PG10, PG11, PG20, PG21 each consist of a channel made up of three overlapping sheet structures in a plan view, and each has nanosheets 21a, 21b, 22a, 22b, 23a, 23b, 24a, and 24b extending in the Y direction.

[0032] The P-type transistor region has multiple active regions that constitute the channel, source, and drain of the P-type transistor. Specifically, the P-type transistor region has active regions P1 to P3. In a plan view, active regions P1 to P3 overlap with the wiring 11.

[0033] A load transistor PU10 is formed in the active region P1. Load transistors PU20 and PU21 are formed in the active region P2. A load transistor PU11 is formed in the active region P3. The load transistors PU10, PU11, PU20, and PU21 each consist of a channel made up of three overlapping sheet structures in a plan view, and each has nanosheets 25a, 25b, 26a, and 26b extending in the Y direction.

[0034] Furthermore, the width in the X direction of nanosheets 21a-24a and 21b-24b is twice the width in the X direction of nanosheets 25a, 25b, 26a, and 26b.

[0035] Regarding the active region, the source and drain portions on both sides of the nanosheet are formed, for example, by epitaxial growth from the nanosheet.

[0036] Gate wirings 31a to 34a and 31b to 34b are formed extending in the X direction. Gate wiring 31a overlaps with nanosheets 21a and 25a in a plan view. Gate wiring 32a overlaps with nanosheet 24a in a plan view. Gate wiring 33a overlaps with nanosheet 23a in a plan view. Gate wiring 34a overlaps with nanosheets 26a and 22a in a plan view. Gate wiring 31b overlaps with nanosheets 21b and 25b in a plan view. Gate wiring 32b overlaps with nanosheet 24b in a plan view. Gate wiring 33b overlaps with nanosheet 23b in a plan view. Gate wiring 34b overlaps with nanosheets 26b and 22b in a plan view. Gate wiring 31a corresponds to the gate of drive transistor PD10 and load transistor PU10. Gate wiring 32a corresponds to the gate of access transistor PG20. Gate wiring 33a corresponds to the gate of access transistor PG10. Gate wiring 34a corresponds to the gates of load transistor PU20 and drive transistor PD20. Gate wiring 31b corresponds to the gates of drive transistor PD11 and load transistor PU11. Gate wiring 32b corresponds to the gate of access transistor PG21. Gate wiring 33b corresponds to the gate of access transistor PG11. Gate wiring 34a corresponds to the gates of load transistor PU21 and drive transistor PD21.

[0037] Gate wirings 31a-34a and 31b-34b overlap with wiring 11 in a plan view. Gate wiring 32a is connected to wiring 11 via via 41. Gate wiring 33a is connected to wiring 11 via via 42.

[0038] Local wiring layers have local wirings 51a to 58a and 51b to 55b that extend in the X direction. Local wiring 51a is connected to the source portion of the drive transistor PD10 in the active region N1. Local wiring 52a is connected to the source portion of the load transistor PU10 in the active region P1. Local wiring 53a is connected to the source portion of the access transistor PG20 in the active region N2. Local wiring 54a is connected to the drain portion of the drive transistor PD10 in the active region N1, the drain portion of the access transistor PG10 in the active region N1, and the drain portion of the load transistor PU10 in the active region P1. Local wiring 55a is connected to the drain portion of the load transistor PU20 in the active region P2, the drain portion of the access transistor PG20 in the active region N2, and the drain portion of the drive transistor PD20 in the active region N2. Local wiring 56a is connected to the source portion of access transistors PG10 and PG11 in the active region N1. Local wiring 57a is connected to the source portion of load transistors PU20 and PU21 in the active region P2. Local wiring 58a is connected to the source portion of drive transistors PD20 and PD21 in the active region N2. Local wiring 51b is connected to the source portion of drive transistor PD11 in the active region N1. Local wiring 52b is connected to the source portion of load transistor PU11 in the active region P3. Local wiring 53b is connected to the source portion of access transistor PG21 in the active region N2. Local wiring 54b is connected to the drain portion of drive transistor PD11 in the active region N1, the drain portion of access transistor PG11 in the active region N1, and the drain portion of load transistor PU11 in the active region P3.The local wiring 55b is connected to the drain portion of the load transistor PU21 in the active region P2, the drain portion of the access transistor PG21 in the active region N2, and the drain portion of the drive transistor PD21 in the active region N2.

[0039] Local wiring 54a is connected to gate wiring 34a via a shared contact 61a. Local wiring 55a is connected to gate wiring 31a via a shared contact 62a. Local wiring 54b is connected to gate wiring 34b via a shared contact 61b. Local wiring 55b is connected to gate wiring 31b via a shared contact 62b.

[0040] As shown in Figure 1(a), power supply wiring 71-73 and wiring 74-77 are formed on the M1 wiring layer, which is a metal wiring layer located above the local wiring layer, extending in the Y direction from the top and bottom ends of the cell in the diagram. Power supply wiring 71 supplies the power supply voltage VDD. Power supply wiring 72 and 73 supply the power supply voltage VSS. Wiring 74 and 75 correspond to the bit lines BL0 and BLB0, respectively.

[0041] Power wiring 71 is connected to local wiring 52a via via 63a, to local wiring 57a via via 64a, and to local wiring 52b via via 63b. Power wiring 72 is connected to local wiring 51a via via 65a and to local wiring 51b via via 65b. Power wiring 73 is connected to local wiring 58a via via 66a. Wiring 74 is connected to local wiring 56a via via 67a. Wiring 75 is connected to local wiring 53a via via 68a and to local wiring 53b via via 68b.

[0042] On the M2 wiring layer, which is the upper layer of the M1 wiring layer, a wiring 81 extending in the X direction is formed across both left and right ends of the cell in the drawing. The wiring 81 corresponds to the word line WL1. The wiring 81 is formed across the cell boundaries of the SRAM cells C0 and C1. The wiring 81 has the same wiring width as the wiring 11. In a plan view, the wiring 81 overlaps with the wiring 11 and the gate wirings 31a - 34a, 31b - 34b.

[0043] The wiring 81 is connected to the gate wiring 33b via the wiring 76 and the vias 69, 91, and is connected to the gate wiring 32b via the wiring 77 and the vias 70, 92.

[0044] With the above configuration, in the SRAM cells C0 and C1 arranged adjacent to each other in the Y direction, a wiring 11 corresponding to the word line WL0 is formed on the BM0 wiring layer, which is the wiring layer on the back side of the transistor, and a wiring 81 corresponding to the word line WL1 is formed on the M2 wiring layer, which is the upper metal wiring layer of the transistor. Thus, the wirings corresponding to the word lines WL0 and WL1 can be arranged across the SRAM cells C0 and C1. Therefore, the wiring width of the word line can be increased, the wiring resistance of the word line can be suppressed, and the operating speed of the semiconductor memory device can be improved.

[0045] Note that although both the wiring 11 (word line WL0) and the wiring 81 (word line WL1) overlap with the gate wirings 31a - 34a, 31b - 34b in a plan view, it is not limited to this. The wiring 11 only needs to overlap with at least a part of the gate wirings 31b - 34b in a plan view, and the wiring 81 only needs to overlap with at least a part of the gate wirings 31a - 34a in a plan view.

[0046] Also, although the wiring widths of the wirings 11 and 81 are the same, they may be different.

[0047] Also, although the wiring 11 is arranged on the BM0 wiring layer and the wiring 81 is arranged on the M2 wiring layer, it is not limited to this. The wiring 11 may be arranged on a back wiring layer other than the BM0 wiring layer, or the wiring 11 may be arranged on a metal wiring layer other than the M2 wiring layer.

[0048] (Block Layout) FIG. 5 is a plan view showing an example of the layout of circuit blocks included in the semiconductor memory device according to the first embodiment. Specifically, FIG. 5(a) shows the upper part of the cell, and FIG. 5(b) shows the lower part of the cell. In FIG. 5(a), only the word lines formed in the M2 wiring layer and the vias connected to the word lines are illustrated. In FIG. 5(b), only the word lines formed in the BM0 wiring layer and the vias connected to the word lines are illustrated. In addition, in the circuit block of FIG. 5, SRAM cells other than those illustrated are also arranged (for example, SRAM cells are arranged on both the upper and lower sides and both the left and right sides of the drawing), but the illustration is omitted.

[0049] In FIG. 5, eight SRAM cells (C0 to C7) are arranged side by side in the Y direction. Wiring corresponding to word lines WL0 to WL7 is connected to SRAM cells C0 to C7, respectively.

[0050] As shown in FIG. 5(b), wiring 11a to 11d extending in the X direction is formed in the BM0 wiring layer. Wiring 11a to 11d respectively correspond to word lines WL0, WL2, WL4, and WL6. Wiring 11a is arranged across the cell boundaries of SRAM cells C0 and C1. Wiring 11b is arranged across the cell boundaries of SRAM cells C2 and C3. Wiring 11c is arranged across the cell boundaries of SRAM cells C4 and C5. Wiring 11d is arranged across the cell boundaries of SRAM cells C6 and C7.

[0051] As shown in FIG. 5(a), wiring 81a to 81d extending in the X direction is formed in the M2 wiring layer. Wiring 81a to 81d respectively correspond to word lines WL1, WL3, WL5, and WL7. Wiring 81a is arranged across the cell boundaries of SRAM cells C0 and C1. Wiring 81b is arranged across the cell boundaries of SRAM cells C2 and C3. Wiring 81c is arranged across the cell boundaries of SRAM cells C4 and C5. Wiring 81d is arranged across the cell boundaries of SRAM cells C6 and C7.

[0052] Wiring 81a to 81d overlap wiring 11a to 11b in a plan view, respectively.

[0053] The block layout in Figure 5 allows the wiring corresponding to the word lines of two SRAM cells aligned in the Y direction to span across both SRAM cells. This increases the width of the word lines and suppresses the wiring resistance of the word lines, thereby improving the operating speed of the semiconductor memory device.

[0054] (Modification) (Configuration of SRAM cell) Figure 6 is a plan view showing another example of the layout structure of an SRAM cell according to the first embodiment. Specifically, Figure 6(a) shows the upper part of the cell, and Figure 6(b) shows the lower part of the cell. In Figure 6, the positions of the wiring 11 in the BM0 wiring layer and the wiring 81 in the M2 wiring layer are different compared to Figure 1.

[0055] As shown in Figure 6(b), in the BM0 wiring layer, the wiring 11 is formed spanning the cell boundaries of SRAM cells C0 and C1, and the cell boundary at the bottom of the drawing of SRAM cell C0. The center of the wiring 11 in the Y direction is located at the same position as the center of the SRAM cell C0 in the Y direction.

[0056] As shown in Figure 6(a), in the M2 wiring layer, the wiring 81 is formed spanning the cell boundary at the top of the drawing of SRAM cell C1 and the cell boundaries of SRAM cells C0 and C1. The center of the wiring 81 in the Y direction is located at the same position as the center of the drawing of SRAM cell C1 in the Y direction. The wiring 81 overlaps with a portion of the wiring 11 in a plan view.

[0057] The configuration shown in Figure 6 can achieve the same effect as shown in Figure 1.

[0058] (Block Layout) Figure 7 is a plan view showing another example of the layout of the circuit block of the semiconductor memory device according to the first embodiment. Specifically, Figure 7(a) shows the upper part of the cell, and Figure 7(b) shows the lower part of the cell. In Figure 7(a), only the word lines formed in the M2 wiring layer and the vias connected to the word lines are shown, and in Figure 7(b), only the word lines formed in the BM0 wiring layer and the vias connected to the word lines are shown. In addition, other SRAM cells are also arranged in the circuit block of Figure 7 (for example, SRAM cells are arranged on both the top and bottom sides of the drawing and on both the left and right sides of the drawing), but they are not shown.

[0059] As shown in Figure 7(b), in the BM0 wiring layer, wiring 11a is arranged across the cell boundary at the bottom of the drawing of SRAM cell C1, and the cell boundary between SRAM cells C0 and C1. Wiring 11b is arranged across the cell boundary between SRAM cells C1 and C2, and the cell boundary between SRAM cells C2 and C3. Wiring 11c is arranged across the cell boundary between SRAM cells C3 and C4, and the cell boundary between SRAM cells C4 and C5. Wiring 11d is arranged across the cell boundary between SRAM cells C5 and C6, and the cell boundary between SRAM cells C6 and C7.

[0060] As shown in Figure 7(a), in the M2 wiring layer, wiring 81a is arranged across the cell boundaries of SRAM cells C0 and C1, and the cell boundaries of SRAM cells C1 and C2. Wiring 81b is arranged across the cell boundaries of SRAM cells C2 and C3, and the cell boundaries of SRAM cells C3 and C4. Wiring 81c is arranged across the cell boundaries of SRAM cells C4 and C5, and the cell boundaries of SRAM cells C5 and C6. Wiring 81d is arranged across the cell boundaries of SRAM cells C6 and C7, and the cell boundary of SRAM cell C7 at the top of the drawing.

[0061] Wirings 81a to 81d overlap with parts of wirings 11a to 11b in a plan view.

[0062] The configuration shown in Figure 7 can achieve the same effect as shown in Figure 5.

[0063] (Second Embodiment) (Configuration of SRAM Cells) Figure 8 is a plan view showing an example of the layout structure of an SRAM cell according to the second embodiment. Specifically, Figure 8(a) shows the upper part of the cell, and Figure 8(b) shows the lower part of the cell. Compared with Figure 1, Figure 8 includes SRAM cells C10 and C11 in addition to SRAM cells C0 and C1. Note that SRAM cells C0 and C1 in Figure 8 are the same as SRAM cells C0 and C1 in Figure 1, but arranged inverted in the X direction.

[0064] Figure 9 is a circuit diagram showing the configuration of an SRAM cell according to the second embodiment. Compared to Figure 4, Figure 9 shows that SRAM cell circuits corresponding to SRAM cells C10 and C11 have been added.

[0065] The SRAM cell circuit configured in SRAM cell C10 has almost the same configuration as the SRAM cell circuit configured in SRAM cell C0, so a detailed explanation will be omitted. SRAM cell C10 has the functions of writing data to SRAM cell C10, holding data, and reading data from SRAM cell C10 by controlling bit lines BL1, BLB1 and word line WL0.

[0066] The SRAM cell circuit configured in SRAM cell C11 is almost identical in configuration to the SRAM cell circuit configured in SRAM cell C1, so a detailed explanation will be omitted. SRAM cell C11 has the functions of writing data to SRAM cell C11, holding data, and reading data from SRAM cell C11 by controlling bit lines BL1, BLB1 and word line WL1.

[0067] In Figure 8, SRAM cells C10 and C11 are positioned to the right of SRAM cells C0 and C1, respectively. SRAM cells C10 and C11 correspond to SRAM cells C0 and C1 in Figure 1, but wiring 12 is placed in the BM0 wiring layer instead of wiring 11, and wiring 82 is placed in the M2 wiring layer instead of wiring 81.

[0068] As shown in Figure 8(b), in SRAM cells C10 and C11, wiring 12 extending in the X direction is formed in the BM0 wiring layer. Wiring 12 corresponds to word line WL1. Wiring 12 is formed across the cell boundary of SRAM cells C10 and C11.

[0069] Wiring 12 is connected to gate wiring 32b via via 43. Wiring 12 is connected to gate wiring 33b via via 44.

[0070] As shown in Figure 8(a), a wiring 82 extending in the X direction is formed in the M2 wiring layer. The wiring 82 corresponds to the word line WL0. The wiring 82 is formed across the cell boundaries of SRAM cells C10 and C11. The wiring 82 has the same width as the wiring 12. In a plan view, the wiring 82 overlaps with the wiring 12.

[0071] Wiring 82 is connected to gate wiring 32a via wiring 78 and vias 70a and 7093, and is connected to gate wiring 33a via wiring 79 and vias 70b and 7094. Wirings 78 and 79 are wirings formed in the M1 wiring layer.

[0072] In Figure 8, region A1 is formed between SRAM cells C0 and C1 and SRAM cells C10 and C11.

[0073] In region A1, local wirings 151 and 152 extending in the X direction are formed in the local wiring layer, and wirings 171 and 172 extending in the Y direction are formed in the M1 wiring layer.

[0074] In region A1, wiring 81 is connected to wiring 12 via vias 191, 192, wiring 171, via 161, local wiring 151, and via 141. Wiring 82 is connected to wiring 11 via vias 193, 194, wiring 172, via 162, local wiring 152, and via 142.

[0075] The gate wiring 33a corresponds to the access transistor PG10 of SRAM cells C0 and C10, and the gate wiring 33b corresponds to the access transistor PG11 of SRAM cells C1 and C11.

[0076] With the above configuration, in region A1, wiring 11 corresponding to word line WL0, formed in the BM0 wiring layer, and wiring 82 corresponding to word line WL0, formed in the M2 wiring layer, are connected. In region A1, wiring 81 corresponding to word line WL1, formed in the M2 wiring layer, and wiring 12 corresponding to word line WL1, formed in the BM0 wiring layer, are connected. As a result, the load on the word lines is made uniform, and performance variations between adjacent SRAM cell rows in the Y direction can be suppressed.

[0077] In this embodiment, one SRAM cell connected to the same word line is placed on both the left and right sides of region A1, but this is not limited to this configuration. Multiple SRAM cells connected to the same word line may be placed on both the left and right sides of region A1. In this case, the number of SRAM cells placed on both the left and right sides of region A1 should be the same.

[0078] In the embodiments and modifications described above, each transistor is provided with three nanosheets, but some or all of the transistors may be provided with one, two, or four or more nanosheets.

[0079] Furthermore, while the cross-sectional shape of the nanosheet is rectangular in each of the embodiments and modifications described above, it is not limited to this. For example, it may be square, circular, elliptical, or the like.

[0080] Furthermore, in the embodiments and modifications described above, the width in the X direction of nanosheets 21a to 24a and 21b to 24b is twice the width in the X direction of nanosheets 25a, 25b, 26a, and 26b, but this is not limited to this. The width in the X direction of each nanosheet 21a to 26a and 21b to 26b can be determined considering the operational stability of the SRAM circuit, etc.

[0081] Furthermore, in each of the embodiments and modifications described above, the shared contacts 61a, 62a, 61b, and 62b may be manufactured in the same process as the contacts (Gate-Contact) and local wiring, or they may be manufactured in a separate process.

[0082] Furthermore, in each of the embodiments and modifications described above, the power supply that provides the power supply voltage VDD to the sources of the load transistors PU10, PU20, PU11, and PU21 is not limited to a power supply supplied from outside the semiconductor integrated circuit, but may be a power supply generated inside the semiconductor integrated circuit, or a power supply generated inside the semiconductor memory device, etc.

[0083] This disclosure describes how the layout structure of an SRAM cell can improve the operating speed of a semiconductor memory device.

[0084] 11, 12, 74, 75, 81, 82 Wiring 21a-26a, 21b-26b Nanosheet 31a-34a, 31b-34b Gate wiring 71-73 Power wiring PU10, PU20, PU11, PU21 Load transistors PD10, PD20, PD11, PD21 Drive transistors PG10, PG20, PG11, PG21 Access transistors BL0, BLB0, BL1, BLB1 Bit lines WL0, WL1 Word lines C0-C7, C10, C11 SRAM cell

Claims

1. A semiconductor memory device comprising a plurality of SRAM cells, wherein the plurality of SRAM cells include first and second SRAM cells arranged adjacent to each other in a first direction, the first SRAM cell comprising a first transistor and a first word line formed on the back wiring layer on the back side of the first transistor and extending in a second direction perpendicular to the first direction, the second SRAM cell comprising a second word line formed on the metal wiring layer above the first transistor and extending in the second direction, the first and second word lines being formed across the cell boundary between the first SRAM cell and the second SRAM cell.

2. A semiconductor memory device according to claim 1, wherein the second SRAM cell comprises a plurality of gate wirings, and the first word line overlaps with at least a portion of the plurality of gate wirings in a plan view.

3. A semiconductor memory device according to claim 1, wherein the first SRAM cell comprises a plurality of gate lines, and the second word line overlaps with at least a portion of the plurality of gate lines in a plan view.

4. A semiconductor memory device according to claim 1, wherein the first and second word lines overlap in a plan view.

5. A semiconductor memory device according to claim 1, wherein the plurality of SRAM cells include a third SRAM cell arranged adjacent to the second SRAM cell in the first direction, and a fourth SRAM cell arranged adjacent to the third SRAM cell in the first direction, wherein the third SRAM cell is formed in the back wiring layer and comprises a third word line extending in the second direction, the fourth SRAM cell is formed in the metal wiring layer and comprises a fourth word line extending in the second direction, and the third and fourth word lines are formed across the cell boundary between the third SRAM cell and the fourth SRAM cell.

6. A semiconductor memory device according to claim 1, wherein the central portion of the first word line in the first direction is located at the same position as the central portion of the first SRAM cell in the first direction.

7. A semiconductor memory device according to claim 1, wherein the central portion of the second word line in the first direction is located at the same position as the central portion of the second SRAM cell in the first direction.

8. A semiconductor memory device according to claim 1, wherein the plurality of SRAM cells include a third SRAM cell arranged adjacent to the second SRAM cell in the first direction, and the second word line is formed across the cell boundary between the second SRAM cell and the third SRAM cell.

9. A semiconductor memory device according to claim 1, wherein the plurality of SRAM cells include a third SRAM cell arranged side by side with the first SRAM cell in the second direction, and a fourth SRAM cell arranged side by side with the second SRAM cell in the second direction, the third SRAM cell being formed in the metal wiring layer and comprising a third word line extending in the second direction, the fourth SRAM cell being formed in the back wiring layer and comprising a fourth word line extending in the second direction, the third and fourth word lines being formed across the cell boundary between the third SRAM cell and the fourth SRAM cell, the first word line being connected to the third word line, and the second word line being connected to the fourth word line.

Images