Semiconductor storage device

Abstract

SRAM cells (C0, C1) are disposed adjacent to each other in the first direction. The SRAM cell (C0) is provided with a first word line that is formed in a first rear surface wiring layer and that extends in the second direction. The SRAM cell (C1) is provided with a second word line that is formed in a first metal wiring layer and that extends in the second direction. The first and second word lines are formed across the cell boundary between the SRAM cell (C0) and the SRAM cell (C1).

Description

Semiconductor memory device

[0001] This disclosure relates to the layout structure of a SRAM (Static Random Access Memory) cell (hereinafter also simply referred to as a cell) using a CFET (Complementary FET).

[0002] SRAM is widely used in semiconductor integrated circuits.

[0003] In addition, transistors, which are the basic components of LSIs, have achieved improvements in integration density, reduction of operating voltage, and improvement of operating speed by reducing the gate length (scaling). However, in recent years, the off-current due to excessive scaling and the resulting significant increase in power consumption have become problems. To solve this problem, three-dimensional structure transistors with a transistor structure changed from the conventional planar type to a three-dimensional type have been actively studied. Among them, nanosheet FET (Field Effect Transistor) has attracted attention.

[0004] In Patent Document 1, a SRAM is disclosed in which a memory cell connected via a wiring on the front surface side of the memory cell and a memory cell connected via a wiring on the back surface side of the memory cell are mixed with a word line signal output from a word line driver.

[0005] United States Patent Application Publication No. 2024 / 0251540

[0006] With the miniaturization of semiconductor integrated circuit devices, the wiring resistance has increased, resulting in a decrease in the operating speed of semiconductor integrated circuit devices. The technology of Patent Document 1 cannot cope with this.

[0007] An object of this disclosure is to improve the operating speed of a semiconductor memory device in the layout structure of a SRAM cell using a CFET.

[0008] In aspects of the present disclosure, a semiconductor memory device comprising a plurality of SRAM cells, wherein the plurality of SRAM cells include first and second SRAM cells arranged adjacent to each other in a first direction, the first SRAM cell comprising the channel, source and drain of a first transistor of a first conductivity type, the channel comprising a first active region including a first nanosheet extending in the first direction, and a second SRAM cell comprising a channel, source and drain of a second transistor of a second conductivity type different from the first conductivity type, formed above the first active region in the depth direction and overlapping with the first active region in a plan view, the channel comprising a second active region including a second nanosheet extending in the first direction, and a first word line extending in a second direction perpendicular to the first direction, the second SRAM cell being formed in the same layer as the first active region in the depth direction. The third transistor of the first conductivity type comprises a channel, source, and drain, the channel comprising a third active region including a third nanosheet extending in the first direction, and a fourth active region comprising a fourth nanosheet extending in the first direction, the channel comprising a second active region formed in the same layer as the second active region in the depth direction and overlapping with the third active region in a plan view, comprising a second word line extending in the second direction, the first word line being formed in a first back wiring layer on the back side of the first and third active regions, the second word line being formed in a first metal wiring layer above the second and fourth active regions, and the first and second word lines being formed across the cell boundary between the first SRAM cell and the second SRAM cell.

[0009] According to this disclosure, wiring corresponding to the first and second word lines can be arranged across the first and second SRAM cells. As a result, the wiring width of the word lines can be increased and the wiring resistance of the word lines can be suppressed, thereby improving the operating speed of the semiconductor memory device.

[0010] According to this disclosure, the operating speed of a semiconductor memory device can be improved in the layout structure of an SRAM cell using a CFET.

[0011] A plan view showing an example of the layout structure of an SRAM cell according to the first embodiment. A cross-sectional view showing an example of the layout structure of an SRAM cell according to the first embodiment. A cross-sectional view showing an example of the layout structure of an SRAM cell according to the first embodiment. A circuit diagram showing the configuration of an SRAM cell according to the first embodiment. A plan view showing an example of the layout of a circuit block provided in a semiconductor memory device according to the first embodiment. A plan view showing another example of the layout structure of an SRAM cell according to the first embodiment. A plan view showing another example of the layout structure of an SRAM cell according to the first embodiment. A plan view showing another example of the layout of a circuit block provided in a semiconductor memory device according to the first embodiment. A plan view showing an example of the layout structure of an SRAM cell according to the second embodiment. A circuit diagram showing the configuration of an SRAM cell according to the second embodiment.

[0012] The embodiments will be described below with reference to the drawings. In the following embodiments, the semiconductor memory device comprises a plurality of SRAM cells. At least some of these plurality of SRAM cells are equipped with nanosheet FETs, and furthermore, they are equipped with a CFET structure in which transistors with different conductivity types (in the embodiment, the lower part of the cell is P-conducting and the upper part of the cell is N-conducting) are stacked.

[0013] Furthermore, in this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. Also, in this specification, expressions meaning that widths, etc., are the same, such as "same wiring width," include a range of manufacturing variations.

[0014] (First Embodiment) (Configuration of SRAM Cell) Figures 1 to 3 show examples of the layout structure of an SRAM cell according to the first embodiment, where Figures 1(a) and 1(b) are plan views, and Figures 2(a) and 2(b) and 3(a) and 3(b) are cross-sectional views in the lateral direction in a plan view. Specifically, Figure 1(a) shows the upper part of the cell, and Figure 1(b) shows the lower part of the cell. Figure 2(a) is a cross-section of line X1-X1', Figure 2(b) is a cross-section of line X2-X2', Figure 3(a) is a cross-section of line X3-X3', and Figure 3(b) is a cross-section of line X4-X4'.

[0015] In the following explanation, in plan views such as Figure 1, the vertical direction of the drawing is referred to as the Y direction (first direction), the horizontal direction of the drawing as the X direction (second direction), and the direction perpendicular to the substrate surface as the Z direction (depth direction).

[0016] Furthermore, in the following explanation, the dashed lines running vertically and horizontally in plan views such as Figure 1, and the dashed lines running vertically in cross-sectional views such as Figure 2, indicate a grid used for arranging components during the design phase. The grid is arranged at equal intervals in the X direction and at equal intervals in the Y direction. Note that the grid spacing may be the same or different in the X and Y directions. Also, the grid spacing may differ from layer to layer. Moreover, each component does not necessarily have to be placed on the grid.

[0017] Furthermore, in plan views such as Figure 1, the dotted lines surrounding the cells indicate the cell frame (outer edge of the SRAM cell) of the SRAM cell. SRAM cells are arranged so that their cell frames touch the cell frames of adjacent cells in the X or Y direction.

[0018] Furthermore, in the plan view shown in Figure 1, etc., inverted versions of SRAM cells C0 and C1 are placed on both sides of SRAM cells C0 and C1 in the X direction. SRAM cell C1 is placed below SRAM cell C0 in the drawing, and SRAM cell C0 is placed above SRAM cell C1 in the drawing.

[0019] As shown in Figure 1, SRAM cells C0 and C1 are arranged side by side in the Y direction.

[0020] Figure 4 is a circuit diagram showing the configuration of an SRAM cell according to the first embodiment. As shown in Figure 4, the SRAM cell C0 is configured with an SRAM circuit consisting of drive transistors PU10, PU20, load transistors PD10, PD20, and access transistors PG10, PG20. The drive transistors PU10, PU20 and access transistors PG10, PG20 are P-type FETs, and the load transistors PD10, PD20 are N-type FETs.

[0021] The drive transistor PU10 is located between the power supply VDD and the first node NA0, and the load transistor PD10 is located between the first node NA0 and the power supply VSS. The gates of the drive transistor PU10 and the load transistor PD10 are connected to the second node NB0, forming the inverter INV10. The drive transistor PU20 is located between the power supply VDD and the second node NB0, and the load transistor PD20 is located between the second node NB0 and the power supply VSS. The gates of the drive transistor PU20 and the load transistor PD20 are connected to the first node NA0, forming the inverter INV20. That is, the output of one inverter is connected to the input of the other inverter, thereby forming a latch.

[0022] Access transistor PG10 is located between bit line BL0 and first node NA0, and its gate is connected to word line WL0. Access transistor PG20 is located between bit line BLB0 and second node NB0, and its gate is connected to word line WL0. Bit lines BL0 and BLB0 form a complementary bit line pair.

[0023] In the SRAM circuit, when the bit lines BL0 and BLB0, which constitute a complementary bit line pair, are driven to a high level and a low level, respectively, and the word line WL0 is driven to a low level, a high level is written to the first node NA0 and a low level is written to the second node NB0. On the other hand, when the bit lines BL0 and BLB0 are driven to a low level and a high level, respectively, and the word line WL0 is driven to a low level, a low level is written to the first node NA0 and a high level is written to the second node NB0. Then, with data written to the first and second nodes NA0 and NB0 respectively, when the word line WL0 is driven to a high level, the latch state is established and the data written to the first and second nodes NA0 and NB0 is held.

[0024] Furthermore, by pre-discharging bit lines BL0 and BLB0 to a low level and driving word line WL0 to a low level, the states of bit lines BL0 and BLB0 are determined according to the data written to the first and second nodes NA0 and NB0, respectively, allowing data to be read from the SRAM cells. Specifically, if the first node NA0 is at a high level and the second node NB0 is at a low level, bit line BL0 is charged to a high level and bit line BLB0 remains at a low level. On the other hand, if the first node NA0 is at a low level and the second node NB0 is at a high level, bit line BL0 remains at a low level and bit line BLB0 is charged to a high level.

[0025] As explained above, the SRAM cell has the functions of writing data to the SRAM cell, holding data, and reading data from the SRAM cell by controlling the bit lines BL0, BLB0 and the word line WL0.

[0026] SRAM cell C1 has an SRAM cell circuit similar to that of SRAM cell C0. Specifically, SRAM cell C1 has an SRAM circuit composed of drive transistors PU11 and PU21, load transistors PD11 and PD21, and access transistors PG11 and PG21. The drive transistors PU11 and PU21 and the access transistors PG11 and PG21 are P-type FETs, while the load transistors PD11 and PD21 are N-type FETs.

[0027] The SRAM cell circuit configured in SRAM cell C1 has the same configuration as the SRAM cell circuit configured in SRAM cell C0, so a detailed explanation is omitted. SRAM cell C1 has the functions of writing data to SRAM cell C1, holding data, and reading data from SRAM cell C1 by controlling the bit lines BL0, BLB0 and word line WL1.

[0028] As shown in Figure 1(b), a BM0 (Backside Metal 0) wiring layer, which is a wiring layer, is formed on the back of the semiconductor chip on which the transistor is formed. The BM0 wiring layer corresponds to the back wiring layer.

[0029] A wiring 11 extending in the X direction is formed in the BM0 wiring layer. The wiring 11 corresponds to the word line WL0. The wiring 11 is formed across the cell boundaries of SRAM cells C0 and C1.

[0030] Multiple active regions, which constitute the channel, source, and drain of the P-type transistor, are formed within the P-type transistor region. Specifically, active regions P1 and P2 are formed within the P-type transistor region. In a plan view, active regions P1 and P2 overlap with the wiring 11.

[0031] In the active region P1, drive transistors PU10, PU11 and access transistors PG10, PG11 are formed. In the active region P2, drive transistors PU20, PU21 and access transistors PG20, PG21 are formed. The drive transistors PU10, PU11, PU20, PU21 and access transistors PG10, PG11, PG20, PG21 each consist of a channel made up of two overlapping sheet structures in a plan view, and each has nanosheets 21a, 21b, 22a, 22b, 23a, 23b, 24a, and 24b extending in the Y direction.

[0032] As shown in Figure 1(a), multiple active regions constituting the channel, source, and drain of an N-type transistor are formed in the N-type transistor region. Specifically, active regions N1 to N3 are formed in the N-type transistor region. Active regions N1 to N3 are located above active regions P1 and P2 in the Z direction, respectively. Active regions N1 and N3 overlap with active region P1 in a plan view. Active region N2 overlaps with active region P2 in a plan view.

[0033] A load transistor PD10 is formed in the active region N1. Load transistors PD20 and PD21 are formed in the active region N2. A load transistor PD11 is formed in the active region N3. Load transistors PD10, PD11, PD20, and PD21 each consist of two overlapping sheet structures in a plan view as channels, and have nanosheets 25a, 25b, 26a, and 26b extending in the Y direction.

[0034] Regarding the active region, the source and drain portions on both sides of the nanosheet are formed, for example, by epitaxial growth from the nanosheet.

[0035] Gate wirings 31a to 34a and 31b to 34b are formed extending in the X direction. Gate wiring 31a overlaps with nanosheets 21a and 25a in a plan view. Gate wiring 32a overlaps with nanosheet 24a in a plan view. Gate wiring 33a overlaps with nanosheet 23a in a plan view. Gate wiring 34a overlaps with nanosheets 22a and 26a in a plan view. Gate wiring 31b overlaps with nanosheets 21b and 25b in a plan view. Gate wiring 32b overlaps with nanosheet 24b in a plan view. Gate wiring 33b overlaps with nanosheet 23b in a plan view. Gate wiring 34b overlaps with nanosheets 22b and 26b in a plan view. Gate wiring 31a corresponds to the gate of drive transistor PU 10 and load transistor PD 10. Gate wiring 32a corresponds to the gate of access transistor PG 20. Gate wiring 33a corresponds to the gate of access transistor PG10. Gate wiring 34a corresponds to the gates of drive transistor PU20 and load transistor PD20. Gate wiring 31b corresponds to the gates of drive transistor PU11 and load transistor PD11. Gate wiring 32b corresponds to the gate of access transistor PG21. Gate wiring 33b corresponds to the gate of access transistor PG11. Gate wiring 34b corresponds to the gates of drive transistor PU21 and load transistor PD21.

[0036] Gate wirings 31a-34a and 31b-34b overlap with wiring 11 in a plan view. Gate wiring 32a is connected to wiring 11 via via 41. Gate wiring 33a is connected to wiring 11 via via 42.

[0037] As shown in Figure 1(b), local interconnects (LI) 51a to 56a and 51b to 54b extending in the X direction are formed at the bottom of the cell. Local interconnect 51a is connected to the source portion of the drive transistor PU10 in the active region P1. Local interconnect 52a is connected to the source portion of the access transistor PG20 in the active region P2. Local interconnect 53a is connected to the drain portion of the drive transistor PU10 in the active region P1, and to the drain portion of the access transistor PG10 in the active region P1. Local interconnect 54a is connected to the drain portion of the access transistor PG20 in the active region P2, and to the drain portion of the drive transistor PU20 in the active region P2. Local interconnect 55a is connected to the source portions of the access transistors PG10 and PG11 in the active region P1. Local interconnect 56a is connected to the source portions of the drive transistors PU20 and PU21 in the active region P2. Local wiring 51b is connected to the source portion of the drive transistor PU11 in the active region P1. Local wiring 52b is connected to the source portion of the access transistor PG21 in the active region P2. Local wiring 53b is connected to the drain portion of the drive transistor PU11 in the active region P1, and to the drain portion of the access transistor PG11 in the active region P1. Local wiring 54b is connected to the drain portion of the access transistor PG21 in the active region P2, and to the drain portion of the drive transistor PU21 in the active region P2.

[0038] As shown in Figure 1(a), local wirings 61a to 68a and 61b to 65b extending in the X direction are formed on the upper part of the cell. Local wiring 61a is connected to the source portion of load transistor PD10 in the active region N1. Local wiring 64a is connected to the drain portion of load transistor PD10 in the active region N1. Local wiring 65a is connected to the drain portion of load transistor PD20 in the active region N2. Local wiring 68a is connected to the source portions of load transistors PD20 and PD21 in the active region N2. Local wiring 61b is connected to the source portion of load transistor PD11 in the active region N3. Local wiring 64b is connected to the drain portion of load transistor PD11 in the active region N3. Local wiring 65b is connected to the drain portion of load transistor PD21 in the active region N2.

[0039] Local wiring 64a is connected to gate wiring 34a via a shared contact 81a and to local wiring 53a via a via 71a. Local wiring 65a is connected to gate wiring 31a via a shared contact 82a and to local wiring 54a via a via 72a. Local wiring 64b is connected to gate wiring 34b via a shared contact 81b and to local wiring 53b via a via 71b. Local wiring 65b is connected to gate wiring 31b via a shared contact 82b and to local wiring 54b via a via 72b.

[0040] Power supply wirings 91-93 and 94-97 extending in the Y direction are formed on the M1 wiring layer, which is a metal wiring layer located above the active regions N1 and N2. Power supply wiring 91 supplies the power supply voltage VDD. Power supply wirings 92 and 93 supply the power supply voltage VSS. Wires 94 and 95 correspond to the bit lines BL0 and BLB0, respectively.

[0041] Power supply wiring 91 is connected to the source portion of drive transistor PU10 in active region P1 via local wiring 51a, 62a and vias 73a, 83a. Power supply wiring 91 is connected to the source portions of drive transistors PU20, PU21 in active region P2 via local wiring 56a, 67a and vias 74a, 84a. Power supply wiring 91 is connected to the source portion of drive transistor PU11 in active region P1 via local wiring 51b, 62b and vias 73b, 83b. Power supply wiring 92 is connected to the source portion of load transistor PD10 in active region N1 via local wiring 61a and via 85a. Power supply wiring 92 is connected to the source portion of load transistor PD11 in active region N3 via local wiring 61b and via 85b. Power supply wiring 93 is connected to the source portions of load transistors PD20, PD21 in active region N2 via local wiring 68a and via 86a. Wiring 94 is connected to the source portion of access transistors PG10 and PG11 in the active region P1 via local wires 55a and 66a and vias 75a and 87a. Wiring 95 is connected to the source portion of access transistor PG20 in the active region P2 via local wires 52a and 63a and vias 76a and 88a. Wiring 95 is connected to the source portion of access transistor PG21 in the active region P2 via local wires 52b and 63b and vias 76b and 88b.

[0042] A wiring 101 is formed in the M2 wiring layer, which is the upper layer of the M1 wiring layer, extending in the X direction across both the left and right ends of the cell drawing. The wiring 101 corresponds to the word line WL1. The wiring 101 is formed across the cell boundaries of SRAM cells C0 and C1. The wiring 101 has the same width as the wiring 11. In a plan view, the wiring 101 overlaps with the wiring 11 and the gate wirings 31a to 34a and 31b to 34b.

[0043] The wiring 101 is connected to the gate wiring 33b via the via 89a, the wiring 96, and the via 89b. The wiring 101 is connected to the gate wiring 32b via the via 90a, the wiring 97, and the via 90b.

[0044] With the above configuration, in the SRAM cells C0 and C1 arranged adjacent to each other in the Y direction, the wiring 11 corresponding to the word line WL0 is formed in the BM0 wiring layer which is the wiring layer on the back side of the transistor, and the wiring 101 corresponding to the word line WL1 is formed in the M2 wiring layer which is the upper metal wiring layer of the transistor. Thereby, the wirings corresponding to the word lines WL0 and WL1 can be arranged across the SRAM cells C0 and C1. For this reason, the wiring width of the word line can be increased, the wiring resistance of the word line can be suppressed, and thus the operating speed of the semiconductor memory device can be improved.

[0045] Note that although the wiring 11 (word line WL0) and the wiring 101 (word line WL1) are both assumed to overlap with the gate wirings 31a to 34a, 31b to 34b in a plan view, it is not limited thereto. The wiring 11 only needs to overlap with at least a part of the gate wirings 31b to 34b in a plan view, and the wiring 101 only needs to overlap with at least a part of the gate wirings 31a to 34a in a plan view.

[0046] Also, although the wiring widths of the wirings 11 and 101 are assumed to be the same, they may be different.

[0047] Also, although the wiring 11 is arranged in the BM0 wiring layer and the wiring 101 is arranged in the M2 wiring layer, it is not limited thereto.The wiring 11 may be arranged in a back wiring layer other than the BM0 wiring layer, and the wiring 101 may be arranged in a metal wiring layer other than the M2 wiring layer.

[0048] (Block Layout) FIG. 5 is a plan view showing an example of the layout of circuit blocks included in the semiconductor memory device according to the first embodiment. Specifically, FIG. 5(a) shows the upper part of the cells, and FIG. 5(b) shows the lower part of the cells. In FIG. 5(a), only the word lines formed in the M2 wiring layer and the vias connected to the word lines are shown, and in FIG. 5(b), only the word lines formed in the BM0 wiring layer and the vias connected to the word lines are shown. Also, in the circuit block of FIG. 5, SRAM cells other than those shown are also arranged (for example, SRAM cells are arranged on both the upper and lower sides and both the left and right sides of the drawing), but the illustration is omitted.

[0049] In FIG. 5, eight SRAM cells (C0 to C7) are arranged side by side in the Y direction. Word lines WL0 to WL7 are respectively connected to the SRAM cells C0 to C7.

[0050] As shown in FIG. 5(b), wiring 11a to 11d extending in the X direction are formed in the BM0 wiring layer. Wiring 11a to 11d respectively correspond to the word lines WL0, WL2, WL4, and WL6. Wiring 11a is arranged across the cell boundaries of SRAM cells C0 and C1. Wiring 11b is arranged across the cell boundaries of SRAM cells C2 and C3. Wiring 11c is arranged across the cell boundaries of SRAM cells C4 and C5. Wiring 11d is arranged across the cell boundaries of SRAM cells C6 and C7.

[0051] As shown in FIG. 5(a), wiring 101a to 101d extending in the X direction are formed in the M2 wiring layer. Wiring 101a to 101d respectively correspond to the word lines WL1, WL3, WL5, and WL7. Wiring 101a is arranged across the cell boundaries of SRAM cells C0 and C1. Wiring 101b is arranged across the cell boundaries of SRAM cells C2 and C3. Wiring 101c is arranged across the cell boundaries of SRAM cells C4 and C5. Wiring 101d is arranged across the cell boundaries of SRAM cells C6 and C7.

[0052] Wiring 101a to 101d overlap with wiring 11a to 11d in a plan view, respectively.

[0053] The block layout in Figure 5 allows the wiring corresponding to the word lines of two SRAM cells aligned in the Y direction to span across both SRAM cells. This increases the width of the word lines and suppresses the wiring resistance of the word lines, thereby improving the operating speed of the semiconductor memory device.

[0054] (Modification 1) Figure 6 is a plan view showing another example of the layout structure of the SRAM cell according to the first embodiment. Specifically, Figure 6(a) shows the upper part of the cell, and Figure 6(b) shows the lower part of the cell. In Figure 6, compared with Figure 1, power supply wiring 98 is formed in the M1 wiring layer instead of power supply wiring 92, 93 and wiring 94, 95, power supply wiring 12 and wiring 13-16 are formed in the BM0 wiring layer instead of wiring 11, and wiring 111 is formed in the BM1 (Backside Metal 1) wiring layer.

[0055] As shown in Figure 6(b), the BM1 wiring layer is formed on the back wiring layer, which is the wiring layer on the back side of the semiconductor chip on which the transistor is formed. The BM1 wiring layer is located below the BM0 wiring layer, that is, further away from the transistor.

[0056] A wiring 111 extending in the X direction is formed in the BM1 wiring layer. The wiring 111 corresponds to the word line WL0. The wiring 111 is formed across the cell boundaries of SRAM cells C0 and C1. In a plan view, the wiring 111 overlaps with the gate wirings 31a to 34a and 31b to 34b.

[0057] The BM0 wiring layer has power supply wiring 12 and wirings 13-16 that extend in the Y direction. Power supply wiring 12 supplies the power supply voltage VDD. Wirings 13 and 14 correspond to the bit lines BL0 and BLB0, respectively.

[0058] Wiring 111 is connected to gate wiring 33a (gate of access transistor PG10) via wiring 15 and vias 43a and 43b. Wiring 111 is connected to gate wiring 32a (gate of access transistor PG20) via wiring 16 and vias 44a and 44b.

[0059] Power supply wiring 12 is connected to the source portion of drive transistor PU10 in the active region P1 via via 45a and local wiring 51a. Power supply wiring 12 is connected to the source portions of drive transistors PU20 and PU21 in the active region P2 via via 46a and local wiring 56a. Power supply wiring 12 is connected to the source portion of drive transistor PU11 in the active region P1 via via 45b and local wiring 51b. Wiring 13 is connected to the source portions of access transistors PG10 and PG11 in the active region P1 via via 47a and local wiring 55a. Wiring 14 is connected to the source portion of access transistor PG20 in the active region P2 via via 48a and local wiring 52a. Wiring 14 is connected to the source portion of access transistor PG21 in the active region P2 via via 48b and local wiring 52b.

[0060] As shown in Figure 6(a), a power supply wiring 98 extending in the Y direction is formed in the M1 wiring layer. The power supply wiring 98 supplies the power supply voltage VSS.

[0061] Power supply wiring 98 is connected to the source portion of load transistor PD10 in the active region N1 via local wiring 61a and via 85a. Power supply wiring 98 is connected to the source portions of load transistors PD20 and PD21 in the active region N2 via local wiring 68a and via 86a. Power supply wiring 98 is connected to the source portion of load transistor PD11 in the active region N3 via local wiring 61b and via 85b.

[0062] In the configuration shown in Figure 6, power supply wiring 12 that supplies the power supply voltage VDD and wiring 13 and 14 corresponding to the bit lines BL0 and BLB0 are formed on the BM0 wiring layer. Power supply wiring 98 that supplies the power supply wiring VSS is formed on the M1 wiring layer. This allows for a larger wiring width for the wiring that supplies the power supply voltages VDD and VSS and the wiring corresponding to the bit lines BL0 and BLB0, thereby reducing the wiring resistance of the power supply wiring and bit lines. This improves the operating speed and stability of the semiconductor memory device.

[0063] In addition, the same effects as shown in Figure 1 can be obtained.

[0064] (Modification 2) (Configuration of SRAM cell) Figure 7 is a plan view showing another example of the layout structure of the SRAM cell according to the first embodiment. Specifically, Figure 7(a) shows the upper part of the cell, and Figure 7(b) shows the lower part of the cell. In Figure 7, the positions of the wiring 11 in the BM0 wiring layer and the wiring 101 in the M2 wiring layer are different compared to Figure 1.

[0065] As shown in Figure 7(b), in the BM0 wiring layer, the wiring 11 is formed spanning the cell boundary at the top of the drawing of the SRAM cell C0 and the cell boundary at the bottom of the drawing of the SRAM cell C0. The center of the wiring 11 in the Y direction is located at the same position as the center of the SRAM cell C0 in the Y direction.

[0066] As shown in Figure 7(a), in the M2 wiring layer, the wiring 101 is formed spanning the cell boundary at the top of the drawing of the SRAM cell C1 and the cell boundary at the bottom of the drawing of the SRAM cell C1. The center of the wiring 101 in the Y direction is located at the same position as the center of the SRAM cell C1 in the Y direction. The wiring 101 overlaps with a portion of the wiring 11 in a plan view.

[0067] The configuration shown in Figure 7 can achieve the same effect as shown in Figure 1.

[0068] (Block Layout) Figure 8 is a plan view showing another example of the layout of the circuit block of the semiconductor memory device according to the first embodiment. Specifically, Figure 8(a) shows the upper part of the cell, and Figure 8(b) shows the lower part of the cell. In Figure 8(a), only the word lines formed in the M2 wiring layer and the vias connected to the word lines are shown, and in Figure 8(b), only the word lines formed in the BM0 wiring layer and the vias connected to the word lines are shown. In addition, other SRAM cells are also arranged in the circuit block of Figure 8 (for example, SRAM cells are arranged on both the top and bottom sides of the drawing and on both the left and right sides of the drawing), but they are not shown.

[0069] As shown in Figure 8(b), in the BM0 wiring layer, wiring 11a is arranged across the cell boundary at the bottom of the drawing of SRAM cell C0, and the cell boundaries of SRAM cells C0 and C1. Wiring 11b is arranged across the cell boundaries of SRAM cells C1 and C2, and the cell boundaries of SRAM cells C2 and C3. Wiring 11c is arranged across the cell boundaries of SRAM cells C3 and C4, and the cell boundaries of SRAM cells C4 and C5. Wiring 11d is arranged across the cell boundaries of SRAM cells C5 and C6, and the cell boundaries of SRAM cells C6 and C7.

[0070] As shown in Figure 8(a), in the M2 wiring layer, wiring 101a is arranged across the cell boundaries of SRAM cells C0 and C1, and the cell boundaries of SRAM cells C1 and C2. Wiring 101b is arranged across the cell boundaries of SRAM cells C2 and C3, and the cell boundaries of SRAM cells C3 and C4. Wiring 101c is arranged across the cell boundaries of SRAM cells C4 and C5, and the cell boundaries of SRAM cells C5 and C6. Wiring 101d is arranged across the cell boundaries of SRAM cells C6 and C7, and the cell boundary of SRAM cell C7 at the top of the drawing.

[0071] Wirings 101a to 101d overlap with parts of wirings 11a to 11d in a plan view.

[0072] The configuration shown in Figure 8 can achieve the same effect as shown in Figure 5.

[0073] (Second Embodiment) (Configuration of SRAM Cells) Figure 9 is a plan view showing an example of the layout structure of an SRAM cell according to the second embodiment. Specifically, Figure 9(a) shows the upper part of the cell, and Figure 9(b) shows the lower part of the cell. Compared with Figure 1, Figure 9 shows that in addition to SRAM cells C0 and C1, SRAM cells C10 and C11 are also arranged.

[0074] Figure 10 is a circuit diagram showing the configuration of an SRAM cell according to the second embodiment. Compared to Figure 4, Figure 10 shows that SRAM cell circuits corresponding to SRAM cells C10 and C11 have been added.

[0075] The SRAM cell circuit configured in SRAM cell C10 has the same configuration as the SRAM cell circuit configured in SRAM cell C0, so a detailed explanation is omitted. SRAM cell C10 has the functions of writing data to SRAM cell C10, holding data, and reading data from SRAM cell C10 by controlling bit lines BL1, BLB1 and word line WL0.

[0076] The SRAM cell circuit configured in SRAM cell C11 has the same configuration as the SRAM cell circuit configured in SRAM cell C1, so a detailed explanation is omitted. SRAM cell C11 has the functions of writing data to SRAM cell C11, holding data, and reading data from SRAM cell C11 by controlling bit lines BL1, BLB1 and word line WL1.

[0077] In Figure 9, SRAM cells C10 and C11 are positioned to the right of SRAM cells C0 and C1, respectively. SRAM cells C10 and C11 correspond to SRAM cells C0 and C1 in Figure 1, but wiring 17 is placed in the BM0 wiring layer instead of wiring 11, and wiring 102 is placed in the M2 wiring layer instead of wiring 101.

[0078] As shown in Figure 9(b), in SRAM cells C10 and C11, wiring 17 extending in the X direction is formed in the BM0 wiring layer. Wiring 17 corresponds to word line WL1. Wiring 17 is formed across the cell boundary of SRAM cells C10 and C11.

[0079] Wiring 17 is connected to gate wiring 32b via via 49. Wiring 17 is also connected to gate wiring 33b via via 50.

[0080] As shown in Figure 9(a), a wiring 102 extending in the X direction is formed in the M2 wiring layer. Wiring 102 corresponds to the word line WL0. Wiring 102 is formed spanning the cell boundaries of SRAM cells C10 and C11. Wiring 102 has the same wiring width as wiring 17. In a plan view, wiring 102 overlaps with wiring 17.

[0081] Wiring 102 is connected to gate wiring 32a via wiring 99 and vias 99a and 99b, and is connected to gate wiring 33a via wiring 100 and vias 100a and 100b. Wirings 99 and 100 are wirings formed in the M1 wiring layer.

[0082] In Figure 9, region A1 is formed between SRAM cells C0 and C1 and SRAM cells C10 and C11.

[0083] In region A1, local wiring layers have local wirings 151, 152, 161, and 162 extending in the X direction, and wiring layers M1 have wirings 191 and 192 extending in the Y direction.

[0084] In region A1, wiring 101 is connected to wiring 17 via via 181, wiring 191, via 182, local wiring 161, via 171, local wiring 151, and via 141. Wiring 102 is connected to wiring 11 via via 183, wiring 192, via 184, local wiring 162, via 172, local wiring 152, and via 142.

[0085] With the above configuration, in region A1, wiring 11 corresponding to word line WL0, formed in the BM0 wiring layer, and wiring 102 corresponding to word line WL0, formed in the M2 wiring layer, are connected. In region A1, wiring 101 corresponding to word line WL1, formed in the M2 wiring layer, and wiring 17 corresponding to word line WL1, formed in the BM0 wiring layer, are connected. As a result, for example, by making the number of SRAM cells located to the left of region A1 in the drawing the same as the number of SRAM cells located to the right of region A1 in the drawing, the load on the word lines becomes uniform, and thus performance variations between adjacent SRAM cell rows in the Y direction can be suppressed.

[0086] In this embodiment, one SRAM cell connected to the same word line is placed on both the left and right sides of region A1, but this is not limited to this configuration. Multiple SRAM cells connected to the same word line may be placed on both the left and right sides of region A1. In this case, the number of SRAM cells placed on both the left and right sides of region A1 should be the same.

[0087] In the embodiments and modifications described above, each transistor is provided with two nanosheets, but some or all of the transistors may be provided with one or three or more nanosheets.

[0088] Furthermore, while the cross-sectional shape of the nanosheet is rectangular in each of the embodiments and modifications described above, it is not limited to this. For example, it may be square, circular, elliptical, or the like.

[0089] Furthermore, in each of the embodiments and modifications described above, the shared contacts 81a, 82a, 81b, and 82b may be manufactured in the same process as the gate contacts and local wiring, or they may be manufactured in a separate process.

[0090] Furthermore, in each of the embodiments and modifications described above, the power supply that provides the power supply voltage VDD to the sources of the drive transistors PU10, PU11, PU20, and PU21 is not limited to a power supply supplied from outside the semiconductor integrated circuit, but may be a power supply generated inside the semiconductor integrated circuit, or a power supply generated inside the semiconductor memory device, etc.

[0091] This disclosure describes how the operating speed of a semiconductor memory device can be improved in a layout structure of an SRAM cell using a CFET.

[0092] 11, 13, 14, 17, 101, 102 Wiring 21a-26a, 21b-26b Nanosheet 31a-34a, 31b-34b Gate Wiring 12, 91-93, 98 Power Wiring PU10, PU20, PU11, PU21 Drive Transistors PD10, PD20, PD11, PD21 Load Transistors PG10, PG20, PG11, PG21 Access Transistors BL0, BLB0, BL1, BLB1 Bit Lines WL0, WL1 Word Lines C0-C7, C10, C11 SRAM Cells

Claims

1. A semiconductor memory device comprising a plurality of SRAM cells, wherein the plurality of SRAM cells include first and second SRAM cells arranged adjacent to each other in a first direction, the first SRAM cell comprising a channel, source and drain of a first transistor of a first conductivity type, the channel comprising a first active region including a first nanosheet extending in the first direction, the channel comprising a second active region formed above the first active region in the depth direction and overlapping with the first active region in a plan view, comprising a channel, source and drain of a second transistor of a second conductivity type different from the first conductivity type, the channel comprising a second active region including a second nanosheet extending in the first direction, and a first word line extending in a second direction perpendicular to the first direction, the second SRAM cell comprising a channel, source and drain of a third transistor of the first conductivity type, the channel comprising a third active region including a third nanosheet extending in the first direction, A semiconductor memory device comprising: a fourth active region formed in the same layer as the second active region in the depth direction, overlapping with the third active region in a plan view, and constituting the channel, source, and drain of the fourth transistor of the second conductivity type, wherein the channel comprises a fourth active region including a fourth nanosheet extending in the first direction and a second word line extending in the second direction, the first word line being formed in a first back wiring layer on the back side of the first and third active regions, the second word line being formed in a first metal wiring layer above the second and fourth active regions, and the first and second word lines being formed across the cell boundary between the first SRAM cell and the second SRAM cell.

2. A semiconductor memory device according to claim 1, wherein the second SRAM cell comprises a plurality of gate wirings, and the first word line overlaps with at least a portion of the plurality of gate wirings in a plan view.

3. A semiconductor memory device according to claim 1, wherein the first SRAM cell comprises a plurality of gate lines, and the second word line overlaps with at least a portion of the plurality of gate lines in a plan view.

4. A semiconductor memory device according to claim 1, wherein the first and second word lines overlap in a plan view.

5. A semiconductor memory device according to claim 1, wherein the plurality of SRAM cells include a third SRAM cell arranged adjacent to the second SRAM cell in the first direction, and a fourth SRAM cell arranged adjacent to the third SRAM cell in the first direction, wherein the third SRAM cell is formed in the first back wiring layer and comprises a third word line extending in the second direction, the fourth SRAM cell is formed in the first metal wiring layer and comprises a fourth word line extending in the second direction, and the third and fourth word lines are formed across the cell boundary between the third SRAM cell and the fourth SRAM cell.

6. A semiconductor memory device according to claim 1, wherein the first and second SRAM cells are formed in a second back wiring layer on the back side of the first and third active regions and include a first bit line extending in the first direction, a second bit line formed in the second back wiring layer and extending in the first direction, and constituting a complementary bit line pair with the first bit line, a first power supply wiring formed in the second back wiring layer and supplying a first power supply voltage, and a second power supply wiring formed in a second metal wiring layer above the second and fourth active regions and supplying a second power supply voltage different from the first power supply voltage, wherein the first back wiring layer is formed below the second back wiring layer, and the first metal wiring layer is formed above the second metal wiring layer.

7. A semiconductor memory device according to claim 1, wherein the central portion of the first word line in the first direction is located at the same position as the central portion of the first SRAM cell in the first direction.

8. A semiconductor memory device according to claim 1, wherein the central portion of the second word line in the first direction is located at the same position as the central portion of the second SRAM cell in the first direction.

9. A semiconductor memory device according to claim 1, wherein the plurality of SRAM cells include a third SRAM cell arranged adjacent to the second SRAM cell in the first direction, and the second word line is formed across the cell boundary between the second SRAM cell and the third SRAM cell.

10. A semiconductor memory device according to claim 1, wherein the plurality of SRAM cells include a third SRAM cell arranged side by side with the first SRAM cell in the second direction, and a fourth SRAM cell arranged side by side with the second SRAM cell in the second direction, the third SRAM cell being formed in the first metal wiring layer and comprising a third word line extending in the second direction, the fourth SRAM cell being formed in the first back wiring layer and comprising a fourth word line extending in the second direction, the third and fourth word lines being formed across the cell boundary between the third SRAM cell and the fourth SRAM cell, the first word line being connected to the third word line, and the second word line being connected to the fourth word line.

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