Semiconductor storage device

Abstract

SRAM cells (C0, C1) are arranged adjacent to each other in a first direction. The SRAM cell (C0) is provided with a first bit line that extends in a second direction and is formed in a back surface wiring layer. The SRAM cell (C1) is provided with a second bit line that extends in the second direction and is formed in a metal wiring layer. The first and second bit lines are formed across the cell boundary between the SRAM cell (C0) and the SRAM cell (C1).

Description

Semiconductor memory device

[0008] ,

[0007] ,

[0001] The present disclosure relates to a semiconductor memory device, and particularly to the layout structure of SRAM (Static Random Access Memory) cells (hereinafter, also simply referred to as cells as appropriate).

[0002] SRAM is widely used in semiconductor integrated circuits.

[0003] In addition, transistors, which are basic components of LSIs, have achieved improved integration density, reduced operating voltage, and improved operating speed through gate length reduction (scaling). However, in recent years, the off-current due to excessive scaling and the resulting significant increase in power consumption have become problems. To solve this problem, three-dimensional structure transistors in which the transistor structure is changed from the conventional planar type to a three-dimensional type have been actively studied. An example of a three-dimensional structure transistor is a nanosheet FET (Field Effect Transistor).

[0004] Patent Documents 1 and 2 disclose an SRAM in which memory cells connected via front-side wiring of a bit line pair and memory cells connected via back-side wiring of the bit line pair are mixed.

[0005] U.S. Patent Application Publication No. 2021 / 0343332, U.S. Patent Application Publication No. 2024 / 0172409

[0006] With the miniaturization of semiconductor integrated circuit devices, the wiring resistance has increased, resulting in a decrease in the operating speed of semiconductor integrated circuit devices. The techniques of Patent Documents 1 and 2 cannot cope with this.

[0007] An object of the present disclosure is to improve the operating speed of a semiconductor memory device in the layout structure of SRAM cells. <00A part of the present disclosure relates to a semiconductor memory device comprising a plurality of SRAM cells, wherein the plurality of SRAM cells include first and second SRAM cells arranged adjacent to each other in a first direction, the first SRAM cell comprising a first transistor and a first bit line formed on a back wiring layer on the back side of the first transistor and extending in a second direction perpendicular to the first direction, the second SRAM cell comprising a second bit line formed on a metal wiring layer above the first transistor and extending in the second direction, the first and second bit lines being formed across the cell boundary between the first SRAM cell and the second SRAM cell.

[0009] According to this disclosure, in first and second SRAM cells arranged adjacent to each other in a first direction, a first bit line is formed in the back wiring layer and a second bit line is formed in the metal wiring layer. This allows the first and second bit lines to be arranged across the first and second SRAM cells. As a result, the wiring width of the bit lines can be increased and the wiring resistance of the bit lines can be suppressed, thereby improving the operating speed of the semiconductor memory device.

[0010] According to this disclosure, the operating speed of a semiconductor memory device can be improved in the layout structure of an SRAM cell.

[0011] A plan view showing an example of the layout structure of an SRAM cell according to the first embodiment. A cross-sectional view showing an example of the layout structure of an SRAM cell according to the first embodiment. A cross-sectional view showing an example of the layout structure of an SRAM cell according to the first embodiment. A cross-sectional view showing an example of the layout structure of an SRAM cell according to the first embodiment. A circuit diagram showing the configuration of an SRAM cell according to the first embodiment. A plan view showing an example of the layout of a circuit block provided in a semiconductor memory device according to the first embodiment. A plan view showing another example of the layout structure of an SRAM cell according to the first embodiment. A plan view showing an example of the layout structure of an SRAM cell according to the second embodiment. A circuit diagram showing the configuration of an SRAM cell according to the second embodiment.

[0012] Embodiments will be described below with reference to the drawings. In the following embodiments, the semiconductor memory device comprises a plurality of SRAM cells, and at least some of these SRAM cells are equipped with nanosheet FETs. A nanosheet FET is an FET that uses a thin sheet (nanosheet) through which electric current flows. The nanosheet is formed from, for example, silicon. In this disclosure, the transistors provided in the SRAM cells are not limited to nanosheet FETs.

[0013] Furthermore, in this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. Also, in this specification, expressions meaning that widths, etc., are the same, such as "same wiring width," include a range of manufacturing variations.

[0014] (First Embodiment) (Configuration of SRAM Cell) Figures 1 and 2A to 2C show examples of the layout structure of an SRAM cell according to the first embodiment, where Figures 1(a) and 1(b) are plan views and Figures 2A to 2C are cross-sectional views in the lateral direction in plan view. Specifically, Figure 1(a) shows the upper part of the cell and Figure 1(b) shows the lower part of the cell. Figure 2A is a cross-section of line X1-X1', Figure 2B is a cross-section of line X2-X2', and Figure 3C is a cross-section of line X3-X3'.

[0015] In the following explanation, in plan views such as Figure 1, the horizontal direction of the drawing is referred to as the X direction (first direction), the vertical direction of the drawing (second direction) as the Y direction, and the direction perpendicular to the substrate surface as the Z direction.

[0016] Furthermore, in the following explanation, the dashed lines running vertically and horizontally in plan views such as Figure 1, and the dashed lines running vertically in cross-sectional views such as Figure 2, indicate a grid used for arranging components during the design phase. The grid is arranged at equal intervals in the X direction and at equal intervals in the Y direction. Note that the grid spacing may be the same or different in the X and Y directions. Also, the grid spacing may differ from layer to layer. Moreover, each component does not necessarily have to be placed on the grid.

[0017] Furthermore, in plan views such as Figure 1, the dotted lines surrounding the cells indicate the cell frame (outer edge of the SRAM cell) of the SRAM cell. SRAM cells are arranged so that their cell frames touch the cell frames of adjacent cells in the X or Y direction.

[0018] Furthermore, in the plan view shown in Figure 1, etc., SRAM cells C0 and C1 are inverted in the Y direction and placed on either side of them in the Y direction. Also, SRAM cell C1 is placed to the left of SRAM cell C0 in the drawing, and SRAM cell C0 is placed to the right of SRAM cell C1 in the drawing.

[0019] As shown in Figure 1, SRAM cells C0 and C1 are arranged side by side in the X direction.

[0020] Figure 3 is a circuit diagram showing the configuration of an SRAM cell according to the first embodiment. As shown in Figure 3, the SRAM cell C0 is configured with an SRAM circuit consisting of load transistors PU10 and PU20, drive transistors PD10 and PD20, and access transistors PG10 and PG20. The load transistors PU10 and PU20 are P-type FETs, and the drive transistors PD10 and PD20 and access transistors PG10 and PG20 are N-type FETs.

[0021] The load transistor PU10 is located between the power supply VDD and the first node NA0, and the drive transistor PD10 is located between the first node NA0 and the power supply VSS. The gates of the load transistor PU10 and the drive transistor PD10 are connected to the second node NB0, forming the inverter INV10. The load transistor PU20 is located between the power supply VDD and the second node NB0, and the drive transistor PD20 is located between the second node NB0 and the power supply VSS. The gates of the load transistor PU20 and the drive transistor PD20 are connected to the first node NA0, forming the inverter INV20. That is, the output of one inverter is connected to the input of the other inverter, thereby forming a latch.

[0022] Access transistor PG10 is located between bit line BL0 and first node NA0, and its gate is connected to word line WL0. Access transistor PG20 is located between bit line BLB0 and second node NB0, and its gate is connected to word line WL0. Bit lines BL0 and BLB0 form a complementary bit line pair.

[0023] In the SRAM circuit of SRAM cell C0, when the bit lines BL0 and BLB0, which constitute a complementary bit line pair, are driven to a high level and a low level, respectively, and the word line WL0 is driven to a high level, a high level is written to the first node NA0 and a low level is written to the second node NB0. On the other hand, when the bit lines BL0 and BLB0 are driven to a low level and a high level, respectively, and the word line WL0 is driven to a high level, a low level is written to the first node NA0 and a high level is written to the second node NB0. Then, when the word line WL0 is driven to a low level while data is written to the first and second nodes NA0 and NB0 respectively, the latch state is established and the data written to the first and second nodes NA0 and NB0 is held.

[0024] Furthermore, by pre-charging bit lines BL0 and BLB0 to a high level and driving word line WL0 to a high level, the states of bit lines BL0 and BLB0 are determined according to the data written to the first and second nodes NA0 and NB0, respectively, allowing data to be read from the SRAM cells. Specifically, if the first node NA0 is at a high level and the second node NB0 is at a low level, bit line BL0 remains at a high level and bit line BLB0 is discharged to a low level. On the other hand, if the first node NA0 is at a low level and the second node NB0 is at a high level, bit line BL0 is discharged to a low level and bit line BLB0 remains at a high level.

[0025] As described above, SRAM cell C0 has the functions of writing data to SRAM cell C0, holding data, and reading data from SRAM cell C0 by controlling bit lines BL0, BLB0 and word line WL0.

[0026] SRAM cell C1 has an SRAM cell circuit that is almost the same as that of SRAM cell C0. Specifically, SRAM cell C1 has an SRAM circuit composed of load transistors PU11 and PU21, drive transistors PD11 and PD21, and access transistors PG11 and PG21. The load transistors PU11 and PU21 are P-type FETs, and the drive transistors PD11 and PD21 and access transistors PG11 and PG21 are N-type FETs.

[0027] The SRAM cell circuit configured in SRAM cell C1 has the same configuration as the SRAM cell circuit configured in SRAM cell C0, so a detailed explanation is omitted. SRAM cell C1 has the functions of writing data to SRAM cell C1, holding data, and reading data from SRAM cell C1 by controlling bit lines BL1, BLB1 and word line WL0.

[0028] As shown in Figure 1(b), a BM0 (Backside Metal 0) wiring layer, which is a wiring layer, is formed on the back of the semiconductor chip on which the transistor is formed. The BM0 wiring layer corresponds to the back wiring layer.

[0029] Wires 11 and 12 extending in the Y direction are formed on the BM0 wiring layer. Wires 11 and 12 correspond to the bit lines BL0 and BLB0, respectively. Wire 11 is formed across the cell boundary on the left side of the SRAM cell C0 in the diagram. Wire 12 is formed across the cell boundaries of SRAM cells C0 and C1. Wire 11 is connected via via 41 to the source portion of the access transistor PG10 in the active region N1. Wire 12 is connected via via 42 to the source portion of the access transistor PG20 in the active region N2.

[0030] The N-type transistor region has multiple active regions that constitute the channel, source, and drain of the N-type transistor. Specifically, the N-type transistor region has active regions N1 to N4. Active region N1 overlaps with wiring 11 in a plan view. Active regions N2 and N4 overlap with wiring 12 in a plan view.

[0031] An access transistor PG10 and a drive transistor PD10 are formed in the active region N1. An access transistor PG20 and a drive transistor PD20 are formed in the active region N2. An access transistor PG11 and a drive transistor PD11 are formed in the active region N3. An access transistor PG21 and a drive transistor PD21 are formed in the active region N4. The drive transistors PD10, PD11, PD20, PD21 and the access transistors PG10, PG11, PG20, PG21 each consist of a channel made up of three overlapping sheet structures in a plan view, and each has nanosheets 21a, 21b, 22a, 22b, 23a, 23b, 24a, and 24b extending in the Y direction.

[0032] The P-type transistor region has multiple active regions that constitute the channel, source, and drain of the P-type transistor. Specifically, the P-type transistor region has active regions P1 to P4.

[0033] A load transistor PU10 is formed in the active region P1. A load transistor PU20 is formed in the active region P2. A load transistor PU11 is formed in the active region P3. A load transistor PU21 is formed in the active region P4. The load transistors PU10, PU11, PU20, and PU21 each consist of a channel made up of three overlapping sheet structures in a plan view, and each has nanosheets 25a, 25b, 26a, and 26b extending in the Y direction.

[0034] Furthermore, the width in the X direction of nanosheets 21a-24a and 21b-24b is twice the width in the X direction of nanosheets 25a, 25b, 26a, and 26b.

[0035] Regarding the active region, the source and drain portions on both sides of the nanosheet are formed, for example, by epitaxial growth from the nanosheet.

[0036] Gate wirings 31a to 37a extending in the X direction are formed. Gate wiring 31a overlaps with nanosheets 21a and 25a in a plan view. Gate wiring 32a overlaps with nanosheets 24a and 24b in a plan view. Gate wiring 33a overlaps with nanosheets 25b and 21b in a plan view. Gate wiring 34a overlaps with nanosheet 23a in a plan view. Gate wiring 35a overlaps with nanosheets 26a and 22a in a plan view. Gate wiring 36a overlaps with nanosheets 22b and 26b in a plan view. Gate wiring 37a overlaps with nanosheet 23b in a plan view. Gate wiring 31a corresponds to the gates of drive transistor PD10 and load transistor PU10. Gate wiring 32a corresponds to the gates of access transistors PG20 and PG21. Gate wiring 33a corresponds to the gates of load transistor PU11 and drive transistor PD11. Gate wiring 34a corresponds to the gate of access transistor PG10. Gate wiring 35a corresponds to the gates of load transistor PU20 and drive transistor PD20. Gate wiring 36a corresponds to the gates of drive transistor PD21 and load transistor PU21. Gate wiring 37a corresponds to the gate of access transistor PG11.

[0037] Local wiring layers have local wirings 51a to 58a and 51b to 57b that extend in the X direction. Local wiring 51a is connected to the source portion of the drive transistor PD10 in the active region N1. Local wiring 52a is connected to the source portion of the load transistor PU10 in the active region P1. Local wiring 53a is connected to the source portion of the access transistor PG20 in the active region N2. Local wiring 54a is connected to the drain portion of the drive transistor PD10 in the active region N1, the drain portion of the access transistor PG10 in the active region N1, and the drain portion of the load transistor PU10 in the active region P1. Local wiring 55a is connected to the drain portion of the load transistor PU20 in the active region P2, the drain portion of the access transistor PG20 in the active region N2, and the drain portion of the drive transistor PD20 in the active region N2. Local wiring 56a is connected to the source portion of access transistor PG10 in active region N1. Local wiring 57a is connected to the source portion of load transistor PU20 in active region P2. Local wiring 58a is connected to the source portion of drive transistor PD20 in active region N2 and the source portion of drive transistor PD21 in active region N4. Local wiring 51b is connected to the source portion of drive transistor PD11 in active region N3. Local wiring 52b is connected to the source portion of load transistor PU11 in active region P3. Local wiring 53b is connected to the source portion of access transistor PG21 in active region N4. Local wiring 54b is connected to the drain portion of drive transistor PD11 in active region N3, the drain portion of access transistor PG11 in active region N3, and the drain portion of load transistor PU11 in active region P3.Local wiring 55b is connected to the drain portion of load transistor PU21 in active region P4, the drain portion of access transistor PG21 in active region N4, and the drain portion of drive transistor PD21 in active region N4. Local wiring 56b is connected to the source portion of access transistor PG11 in active region N3. Local wiring 57b is connected to the source portion of load transistor PU21 in active region P4.

[0038] Local wiring 54a is connected to gate wiring 35a via a shared contact 61a. Local wiring 55a is connected to gate wiring 31a via a shared contact 62a. Local wiring 54b is connected to gate wiring 36a via a shared contact 61b. Local wiring 55b is connected to gate wiring 33a via a shared contact 62b.

[0039] As shown in Figure 1(a), power supply wiring 71a, 71b and wiring 72, 73, 74a-77a, 74b-77b extending in the Y direction are formed on the M1 wiring layer, which is a metal wiring layer located above the local wiring layer. Power supply wiring 71a and 71b supply the power supply voltage VDD. Wiring 72 and 73 correspond to the bit lines BL1 and BLB1, respectively. Wiring 72 is formed spanning the cell boundary on the right side of the drawing of SRAM cell C1. Wiring 73 is formed spanning the cell boundaries of SRAM cells C0 and C1. Wirings 11, 12, 72, and 73 have the same wiring width. In a plan view, wiring 72 overlaps with the active region N3. In a plan view, wiring 73 overlaps with wiring 12 and the active regions N2 and N4.

[0040] Power wiring 71a is connected to local wiring 52a via via 63a and to local wiring 57a via via 64a. Power wiring 71b is connected to local wiring 52b via via 63b and to local wiring 57b via via 64b. Wiring 72 is connected to local wiring 56b via via 65. Wiring 73 is connected to local wiring 53b via via 66.

[0041] Power supply wiring 81, 82 and wiring 83 extending in the X direction are formed on the M2 wiring layer, which is the upper layer of the M1 wiring layer. Power supply wiring 81 and 82 supply the power supply voltage VSS. Wiring 83 corresponds to the word line WL0.

[0042] Power wiring 81 is connected to local wiring 58a via wirings 74a, 74b and vias 67a, 67b, 91a, 91b. Power wiring 82 is connected to local wiring 51a via wiring 75a and vias 68a, 92a. Power wiring 82 is connected to local wiring 51b via wiring 75b and vias 68b, 92b. Wiring 83 is connected to gate wiring 34a via wiring 76a and vias 69a, 93a. Wiring 83 is connected to gate wiring 32a via wirings 77a, 77b and vias 70a, 70b, 94a, 94b. Wiring 83 is connected to gate wiring 37a via wiring 76b and vias 69b, 93b.

[0043] With the above configuration, in SRAM cells C0 and C1 arranged adjacent to each other in the X direction, wirings 11 and 12 corresponding to bit lines BL0 and BLB0 are formed on the BM0 wiring layer, which is the wiring layer on the back of the transistor, and wirings 72 and 73 corresponding to bit lines BL1 and BLB1 are formed on the M1 wiring layer, which is the metal wiring layer above the transistor. This allows the wiring corresponding to the bit lines to be arranged across SRAM cells C0 and C1. As a result, the wiring width of the bit lines can be increased and the wiring resistance of the bit lines can be suppressed, thereby improving the operating speed of the semiconductor memory device.

[0044] Note that although the wiring 12 (bit line BLB0) and the wiring 73 (bit line BLB1) are both assumed to overlap with the active regions N2 and N4 in a plan view, it is not limited to this. The wiring 12 may overlap with at least a part of the active regions P3, P4, N3, and N4 in a plan view, and the wiring 73 may overlap with at least a part of the active regions P1, P2, N1, and N2 in a plan view.

[0045] Also, although the wiring widths of the wirings 11, 12, 72, and 73 are assumed to be the same, they may be different.

[0046] Also, although the wirings 11 and 12 are arranged in the BM0 wiring layer and the wirings 72 and 73 are arranged in the M1 wiring layer, it is not limited to this. The wirings 11 and 12 may both be arranged in a back wiring layer other than the BM0 wiring layer, and the wirings 72 and 73 may both be arranged in a metal wiring layer other than the M1 wiring layer.

[0047] (Block Layout) FIG. 4 is a plan view showing an example of the layout of circuit blocks included in the semiconductor memory device according to the first embodiment. Specifically, FIG. 4(a) shows the upper part of the cell, and FIG. 4(b) shows the lower part of the cell. In FIG. 4(a), only the bit lines formed in the M1 wiring layer and the vias connected to the bit lines are shown, and in FIG. 4(b), only the bit lines formed in the BM0 wiring layer and the vias connected to the bit lines are shown. Also, in the circuit blocks of FIG. 4, SRAM cells other than those shown are also arranged (for example, SRAM cells are arranged on both the upper and lower sides and both the left and right sides of the drawing), but the illustration is omitted.

[0048] In FIG. 4, four SRAM cells (C0 to C3) are arranged side by side in the X direction. Wires corresponding to the bit lines BL0 and BLB0 are connected to the SRAM cell C0. Wires corresponding to the bit lines BL1 and BLB1 are connected to the SRAM cell C1. Wires corresponding to the bit lines BL2 and BLB2 are connected to the SRAM cell C2. Wires corresponding to the bit lines BL3 and BLB3 are connected to the SRAM cell C3.

[0049] As shown in Figure 4(b), the BM0 wiring layer has wirings 11a, 12a, 11b, and 12b that extend in the Y direction. Wirings 11a, 12a, 11b, and 12b correspond to the bit lines BL0, BLB0, BL2, and BLB2, respectively. Wiring 11a is arranged across the cell boundary on the left side of the drawing of SRAM cell C0. Wiring 12a is arranged across the cell boundary of SRAM cells C0 and C1. Wiring 11b is arranged across the cell boundary of SRAM cells C1 and C2. Wiring 12b is arranged across the cell boundary of SRAM cells C2 and C3.

[0050] As shown in Figure 4(a), the M1 wiring layer has wirings 72a, 73a, 72b, and 73b that extend in the Y direction. 72a, 73a, 72b, and 73b correspond to the bit lines BL1, BLB1, BL3, and BLB3, respectively. Wiring 73a is arranged across the cell boundaries of SRAM cells C0 and C1. Wiring 72a is arranged across the cell boundaries of SRAM cells C1 and C2. Wiring 73b is arranged across the cell boundaries of SRAM cells C2 and C3. Wiring 72b is arranged across the cell boundary on the right side of the drawing of SRAM cell C3.

[0051] Wirings 12a, 11b, and 12b overlap with wirings 73a, 72a, and 73b in a plan view, respectively.

[0052] The block layout shown in Figure 4 allows the wiring corresponding to the bit lines of two SRAM cells aligned in the X direction to span across both SRAM cells. This increases the width of the bit lines and suppresses the wiring resistance of the bit lines, thereby improving the operating speed of the semiconductor memory device.

[0053] (Modification) Figure 5 is a plan view showing another example of the layout structure of the SRAM cell according to the first embodiment. Specifically, Figure 5(a) shows the upper part of the cell, and Figure 5(b) shows the lower part of the cell. In Figure 5, compared with Figure 1, wiring 13 is formed in place of wiring 12 in the BM0 wiring layer, and wiring 78 is formed in place of wiring 73 in the M1 wiring layer.

[0054] As shown in Figure 5(b), a wiring 13 extending in the Y direction is formed in the BM0 wiring layer. The wiring 13 corresponds to the bit line BLB1. The wiring 13 is formed across the cell boundaries of SRAM cells C0 and C1. In a plan view, the wiring 13 overlaps with the active regions N2 and N4. The wiring 13 is connected via a via 43 to the source portion of the access transistor PG21 in the active region N4.

[0055] As shown in Figure 5(a), a wiring 78 extending in the Y direction is formed in the M1 wiring layer. The wiring 78 corresponds to the bit line BLB0. The wiring 78 is formed across the cell boundaries of SRAM cells C0 and C1. In a plan view, the wiring 78 overlaps with the wiring 13 and active regions N2 and N4. The wiring 78 is connected to the source portion of the access transistor PG20 in the active region N2 via via 70c and local wiring 53a.

[0056] In the configuration shown in Figure 5, in SRAM cell C0, wiring 11 corresponding to bit line BL0 is formed in the BM0 wiring layer, and wiring 78 corresponding to bit line BLB0 is formed in the M1 wiring layer. In SRAM cell C1, wiring 72 corresponding to bit line BL1 is formed in the M1 wiring layer, and wiring 13 corresponding to bit line BLB1 is formed in the BM0 wiring layer. As a result, the bit lines constituting complementary bit line pairs are formed in different wiring layers, allowing the bit line pairs to be separated. This suppresses the coupling capacitance between bit line pairs, thereby improving the operating speed of the semiconductor memory device.

[0057] (Second Embodiment) Figures 6A and 6B are plan views showing an example of the layout structure of an SRAM cell according to the second embodiment. Specifically, Figure 6A shows the upper part of the cell, and Figure 6B shows the lower part of the cell. Compared with Figure 1, Figures 6A and 6B show SRAM cells C10 and C11 in addition to SRAM cells C0 and C1.

[0058] Figure 7 is a circuit diagram showing the configuration of an SRAM cell according to the second embodiment. Compared to Figure 3, Figure 7 shows that SRAM cell circuits corresponding to SRAM cells C10 and C11 have been added.

[0059] The SRAM cell circuit configured in SRAM cell C10 has almost the same configuration as the SRAM cell circuit configured in SRAM cell C0, so a detailed explanation will be omitted. SRAM cell C10 has the functions of writing data to SRAM cell C10, holding data, and reading data from SRAM cell C10 by controlling the bit lines BL0, BLB0 and the word line WL1.

[0060] The SRAM cell circuit configured in SRAM cell C11 is almost identical in configuration to the SRAM cell circuit configured in SRAM cell C1, so a detailed explanation will be omitted. SRAM cell C11 has the functions of writing data to SRAM cell C11, holding data, and reading data from SRAM cell C11 by controlling bit lines BL1, BLB1 and word line WL1.

[0061] In Figures 6A and 6B, SRAM cells C10 and C11 are positioned above SRAM cells C0 and C1, respectively. SRAM cells C10 and C11 correspond to SRAM cells C0 and C1 in Figure 1 when they are inverted in the Y direction, but wiring 111 and 112 are placed in the BM0 wiring layer instead of wiring 11 and 12, and wiring 171 and 172 are placed in the M1 wiring layer instead of wiring 72 and 73.

[0062] As shown in Figure 6B, in SRAM cells C10 and C11, wirings 111 and 112 extending in the Y direction are formed in the BM0 wiring layer. Wirings 111 and 112 correspond to bit lines BL1 and BLB1, respectively. Wiring 111 is formed across the cell boundary on the right side of the SRAM cell C11 drawing. Wiring 112 is formed across the cell boundary of SRAM cells C10 and C11.

[0063] Wiring 111 is connected via via 141 to the source portion of access transistor PG11 in the active region N7. Wiring 112 is connected via via 142 to the source portion of access transistor PG21 in the active region N8.

[0064] As shown in Figure 6A, wiring 171 and 172 extending in the Y direction are formed in the M1 wiring layer. Wires 171 and 172 correspond to bit lines BL0 and BLB0, respectively. Wires 111, 112, 171, and 172 have the same wiring width. Wire 172 overlaps with wire 112 in a plan view.

[0065] Wiring 171 is connected to the source portion of access transistor PG10 in the active region N5 via local wiring 151 and via 161. Wiring 172 is connected to the source portion of access transistor PG20 in the active region N6 via local wiring 152 and via 162.

[0066] In Figures 6A and 6B, region A1 is formed between SRAM cells C0 and C1 and SRAM cells C10 and C11.

[0067] In region A1, local wiring layers have local wirings 153 to 160 extending in the X direction, and wiring layers M1 have wirings 173 to 176 extending in the Y direction.

[0068] In region A1, wiring 171 is connected to wiring 11 via via 163a, local wiring 153, via 163b, wiring 173, via 163c, local wiring 154, and via 143. Wiring 172 is connected to wiring 12 via via 164a, local wiring 155, via 164b, wiring 174, via 164c, local wiring 156, and via 144. Wiring 73 is connected to wiring 112 via via 165a, local wiring 157, via 165b, wiring 175, via 165c, local wiring 158, and via 145. Wiring 72 is connected to wiring 111 via via 166a, local wiring 159, via 166b, wiring 176, via 166c, local wiring 160, and via 146.

[0069] With the above configuration, in region A1, wiring 11 corresponding to bit line BL0, formed in the BM0 wiring layer, and wiring 171 corresponding to bit line BL0, formed in the M1 wiring layer, are connected. In region A1, wiring 12 corresponding to bit line BLB0, formed in the BM0 wiring layer, and wiring 172 corresponding to bit line BLB0, formed in the M1 wiring layer, are connected. In region A1, wiring 111 corresponding to bit line BL1, formed in the BM0 wiring layer, and wiring 72 corresponding to bit line BL1, formed in the M1 wiring layer, are connected. In region A1, wiring 112 corresponding to bit line BLB1, formed in the BM0 wiring layer, and wiring 73 corresponding to bit line BLB1, formed in the M1 wiring layer, are connected. As a result, the load on each bit line is equalized, and performance variations between adjacent SRAM cell rows in the X direction can be suppressed.

[0070] In this embodiment, one SRAM cell connected to the same bit line pair is placed on the upper and lower sides of region A1, but this is not limited to this configuration. Multiple SRAM cells connected to the same bit line pair may be placed on the upper and lower sides of region A1. In this case, the number of SRAM cells placed on the upper and lower sides of region A1 should be the same.

[0071] In the embodiments and modifications described above, each transistor is provided with three nanosheets, but some or all of the transistors may be provided with one, two, or four or more nanosheets.

[0072] Furthermore, while the cross-sectional shape of the nanosheet is rectangular in each of the embodiments and modifications described above, it is not limited to this. For example, it may be square, circular, elliptical, or the like.

[0073] Furthermore, in the embodiments and modifications described above, the width in the X direction of nanosheets 21a to 24a and 21b to 24b is twice the width in the X direction of nanosheets 25a, 25b, 26a, and 26b, but this is not limited to this. The width in the X direction of each nanosheet 21a to 26a and 21b to 26b can be determined considering the operational stability of the SRAM circuit, etc.

[0074] Furthermore, in each of the embodiments and modifications described above, the shared contacts 61a, 62a, 61b, and 62b may be manufactured in the same process as the contacts (Gate-Contact) and local wiring, or they may be manufactured in a separate process.

[0075] Furthermore, in each of the embodiments and modifications described above, the power supply that provides the power supply voltage VDD to the sources of the load transistors PU10, PU20, PU11, and PU21 is not limited to a power supply supplied from outside the semiconductor integrated circuit, but may be a power supply generated inside the semiconductor integrated circuit, or a power supply generated inside the semiconductor memory device, etc.

[0076] This disclosure describes how the layout structure of an SRAM cell can improve the operating speed of a semiconductor memory device.

[0077] 11, 12, 13, 72, 73, 78, 83, 111, 112, 171, 172 Wiring 21a-26a, 21b-26b Nanosheet 31a-37a Gate wiring 71a, 71b, 81, 82 Power wiring PU10, PU20, PU11, PU21 Load transistors PD10, PD20, PD11, PD21 Drive transistors PG10, PG20, PG11, PG21 Access transistors BL0, BLB0, BL1, BLB1 Bit lines WL0, WL1 Word lines C0-C3, C10, C11 SRAM cells

Claims

1. A semiconductor memory device comprising a plurality of SRAM cells, wherein the plurality of SRAM cells include first and second SRAM cells arranged adjacent to each other in a first direction, the first SRAM cell comprising a first transistor and a first bit line formed on the back wiring layer on the back side of the first transistor and extending in a second direction perpendicular to the first direction, the second SRAM cell comprising a second bit line formed on the metal wiring layer above the first transistor and extending in the second direction, the first and second bit lines being formed across the cell boundary between the first SRAM cell and the second SRAM cell.

2. A semiconductor memory device according to claim 1, wherein the second SRAM cell comprises a plurality of active regions, and the first bit line overlaps with at least a portion of the plurality of active regions in a plan view.

3. A semiconductor memory device according to claim 1, wherein the first SRAM cell comprises a plurality of active regions, and the second bit line overlaps with at least a portion of the plurality of active regions in a plan view.

4. A semiconductor memory device according to claim 1, wherein the first and second bit lines overlap in a plan view.

5. A semiconductor memory device according to claim 1, wherein the plurality of SRAM cells further include a third SRAM cell arranged adjacent to the first SRAM cell in the first direction, the first SRAM cell further comprises a third bit line formed in the back wiring layer, extending in the second direction, and constituting a complementary bit line pair with the first bit line, the third bit line is formed across the cell boundary between the first SRAM cell and the third SRAM cell.

6. A semiconductor memory device according to claim 1, wherein the plurality of SRAM cells further include a fourth SRAM cell arranged adjacent to the second SRAM cell in the first direction, the second SRAM cell further comprises a fourth bit line formed in the metal wiring layer, extending in the second direction, and constituting a complementary bit line pair with the second bit line, the fourth bit line is formed across the cell boundary between the second SRAM cell and the fourth SRAM cell.

7. A semiconductor memory device according to claim 1, wherein the plurality of SRAM cells further include a fourth SRAM cell arranged adjacent to the second SRAM cell in the first direction, the second SRAM cell further comprises a fourth bit line formed in the metal wiring layer and extending in the second direction, which constitutes a complementary bit line pair with the second bit line, the fourth SRAM cell comprises a fifth bit line formed in the back wiring layer and extending in the second direction, and the fourth and fifth bit lines are formed across the cell boundary between the second SRAM cell and the fourth SRAM cell.

8. A semiconductor memory device according to claim 1, wherein the first SRAM cell further comprises a third bit line formed in the metal wiring layer, extending in the second direction, and constituting a complementary bit line pair with the first bit line, and the second SRAM cell further comprises a fourth bit line formed in the back wiring layer, extending in the second direction, and constituting a complementary bit line pair with the second bit line.

9. A semiconductor memory device according to claim 1, wherein the plurality of SRAM cells include a third SRAM cell arranged side by side with the first SRAM cell in the second direction, and a fourth SRAM cell arranged side by side with the second SRAM cell in the second direction, the third SRAM cell is formed in the metal wiring layer and comprises a third bit line extending in the second direction, the fourth SRAM cell is formed in the back wiring layer and comprises a fourth bit line extending in the second direction, the third and fourth bit lines are formed across the cell boundary between the third SRAM cell and the fourth SRAM cell, the first bit line is connected to the third bit line, and the second bit line is connected to the fourth bit line.

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