Semiconductor device and display device

Abstract

This semiconductor device comprises: a semiconductor substrate; a thin-film semiconductor provided above the semiconductor substrate and including an SD region and a channel region; and an impurity film provided so as to cover at least a part of the SD region of the thin-film semiconductor. The SD region and the impurity film contain the same impurity. The impurity film includes a lower impurity film provided so as to cover a lower surface of the SD region.

Description

Semiconductor and display devices

[0001] This disclosure relates to semiconductor devices and display devices.

[0002] For example, as disclosed in Patent Document 1, semiconductor devices such as display devices that include thin-film transistors (TFTs) are known.

[0003] International Publication No. 2017 / 183355

[0004] There is still room for improvement in the performance of devices, including thin-film transistors.

[0005] One aspect of this disclosure is to improve the performance of the device.

[0006] A semiconductor device relating to one aspect of this disclosure comprises a semiconductor substrate, a thin film semiconductor provided above the semiconductor substrate and including an SD region (source-drain region) and a channel region, and an impurity film provided to cover at least a portion of the SD region of the thin film semiconductor, wherein the SD region and the impurity film contain the same impurity, and the impurity film includes a lower impurity film provided to cover the lower surface of the SD region.

[0007] A display device relating to one aspect of this disclosure comprises a semiconductor substrate, a thin film semiconductor provided above the semiconductor substrate and including an SD region (source-drain region) and a channel region, and an impurity film provided to cover at least a portion of the SD region of the thin film semiconductor, wherein the SD region and the impurity film contain the same impurity, and the impurity film includes a lower impurity film provided to cover the lower surface of the SD region.

[0008] This figure shows an example of the schematic configuration of the semiconductor device 100 according to the embodiment. This figure shows an example of the schematic configuration of the pixel 115. This figure shows an example of the schematic configuration of the semiconductor device 100 according to the first embodiment. This figure shows an example of solid layer diffusion. This figure shows an example of a side cross-sectional layout planar layout. This figure shows an example of a planar layout. This figure shows an example of a planar layout. This figure shows an example of a schematic configuration of the semiconductor device 100. This figure shows an example of a manufacturing method for the semiconductor device 100. This figure shows an example of a manufacturing method for the semiconductor device 100. This figure shows an example of a manufacturing method for the semiconductor device 100. This figure shows an example of a manufacturing method for the semiconductor device 100. This figure shows an example of a method for manufacturing a semiconductor device 100.This is a diagram showing an example of a method for manufacturing the semiconductor device 100. This is a diagram showing an example of a method for manufacturing the semiconductor device 100. This is a diagram showing an example of a method for manufacturing the semiconductor device 100. This is a diagram showing an example of a method for manufacturing the semiconductor device 100. This is a diagram showing an example of a method for manufacturing the semiconductor device 100. This is a diagram showing an example of a method for manufacturing the semiconductor device 100. This is a diagram showing an example of a method for manufacturing the semiconductor device 100. This is a diagram showing an example of a schematic configuration of the semiconductor device 100 according to the second embodiment. This is a diagram showing an example of a schematic configuration of the semiconductor device 100. This is a diagram showing an example of a planar layout. This is a diagram showing an example of a schematic configuration of the semiconductor device 100. This is a diagram showing an example of a schematic configuration of the semiconductor device 100. This is a diagram showing an example of a schematic configuration of the semiconductor device 100. This is a diagram showing an example of a schematic configuration of the semiconductor device 100. This is a diagram showing an example of a schematic configuration of the semiconductor device 100. This is a diagram showing an example of a schematic configuration of the semiconductor device 100. This is a diagram showing an example of a positional relationship between the thin film semiconductor 50-2 and via 3v. This is a diagram showing an example of a positional relationship between the thin film semiconductor 50-2 and via 3v. This is a diagram showing an example of a positional relationship between the thin film semiconductor 50-2 and via 3v. This is a diagram showing an example of a planar layout design. This is a diagram showing an example of a planar layout design. This is a diagram showing an example of the arrangement of the thin film semiconductor 50-3. This is a diagram showing an example of the arrangement of the thin film semiconductor 50-3. This is a diagram showing an example of the arrangement of the thin film semiconductor 50-3. This is a diagram showing an example of the arrangement of the thin film semiconductor 50-3. This is a diagram showing an example of the schematic configuration of the semiconductor device 100. This is a diagram showing an example of the manufacturing methodThis is a diagram showing an example of a method for manufacturing a semiconductor device 100. This is a diagram showing an example of the schematic configuration of the semiconductor device 100 according to the third embodiment. manufacturing method of the semiconductor device 100. This is a diagram showing an example of the manufacturing method of the semiconductor device 100.This is a diagram illustrating an example of a method for manufacturing the semiconductor device 100. This is a diagram illustrating an example of a method for manufacturing the semiconductor device 100. This is a diagram illustrating an example of a method for manufacturing the semiconductor device 100. This is a diagram illustrating an example of a method for manufacturing the semiconductor device 100. This is a diagram illustrating an example of a method for manufacturing the semiconductor device 100. This is a diagram illustrating an example of a method for manufacturing the semiconductor device 100. This is a diagram illustrating an example of a method for manufacturing the semiconductor device 100. This is a diagram illustrating an example of a method for manufacturing the semiconductor device 100. This is a conceptual diagram (1) to explain the relationship between the normal LN passing through the center of the light-emitting part, the normal LN' passing through the center of the lens member, and the normal LN'' passing through the center of the wavelength-selecting part. This is a conceptual diagram (2) to explain the relationship between the normal LN passing through the center of the light-emitting part, the normal LN' passing through the center of the lens member, and the normal LN'' passing through the center of the wavelength-selecting part. This is a conceptual diagram (part 3) illustrating the relationship between the normal vector LN passing through the center of the light-emitting part, the normal vector LN' passing through the center of the lens member, and the normal vector LN" passing through the center of the wavelength-selecting part. This is a conceptual diagram (part 4) illustrating the relationship between the normal vector LN passing through the center of the light-emitting part, the normal vector LN' passing through the center of the lens member, and the normal vector LN" passing through the center of the wavelength-selecting part. This is a conceptual diagram (part 5) illustrating the relationship between the normal vector LN passing through the center of the light-emitting part, the normal vector LN' passing through the center of the lens member, and the normal vector LN" passing through the center of the wavelength-selecting part. This is a conceptual diagram (part 6) illustrating the relationship between the normal vector LN passing through the center of the light-emitting part, the normal vector LN' passing through the center of the lens member, and the normal vector LN" passing through the center of the wavelength-selecting part. This is a conceptual diagram (No. 7) illustrating the relationship between the normal vector LN passing through the center of the light-emitting part, the normal vector LN' passing through the center of the lens member, and the normal vector LN'' passing through the center of the wavelength selection part. This is a schematic cross-sectional view illustrating the first example of the resonator structure. This is a schematic cross-sectional view illustrating the second example of the resonator structure. This is a schematic cross-sectional view illustrating the third example of the resonator structure. This is a schematic cross-sectional view illustrating the fourth example of the resonator structure. This is a schematic cross-sectional view illustrating the fifth example of the resonator structure. This is a schematic cross-sectional view illustrating the sixth example of the resonator structure. This is a schematic cross-sectional view illustrating the seventh example of the resonator structure. This is a front view showing an example of the appearance of a digital still camera. This is a rear view showing an example of the appearance of a digital still camera.This is an external view of a head-mounted display. This is an external view of a see-through head-mounted display. This is an external view of a television system. This is an external view of a smartphone. This is a diagram (1) showing the internal configuration of a car. This is a diagram (2) showing the internal configuration of a car.

[0009] Embodiments of this disclosure will be described in detail below with reference to the drawings. In each of the following embodiments, the same elements will be denoted by the same reference numerals to avoid redundant descriptions.

[0010] This disclosure will be described in the following order of items: 0. Example of basic configuration 1. First embodiment 2. Second embodiment 3. Third embodiment 4. Other modifications 4.1 Modification 1 4.2 Modification 2 5. Application examples

[0011] 0. Example of Basic Configuration Figure 1 is a diagram showing an example of the schematic configuration of the semiconductor device 100 according to the embodiment. One specific example of the application of the semiconductor device 100 is a display device. Hereafter, the semiconductor device 100 will be described assuming it is a display device.

[0012] The semiconductor device 100 includes a pixel array unit 111, a light scanner 112, a drive scanner 113, and a horizontal selector 114. The XYZ coordinate system for the pixel array unit 111 is also shown. The X-axis direction and Y-axis direction (XY plane direction) correspond to the array direction. Light from the pixel array unit 111 is assumed to be output along the positive Z-axis direction. The positive Z-axis direction and the negative Z-axis direction are also referred to as the upward and downward directions.

[0013] The pixel array section 111 includes a plurality of pixels 115 arranged in a two-dimensional (matrix) manner. In this example, each pixel 115 is composed of an organic EL element (OLED).

[0014] When the pixel array 111 supports color display, one pixel 115 corresponds to one subpixel. Each pixel 115 outputs light of the corresponding color. Examples of colors include red (R), green (G), blue (B), etc. White (W) light may also be output.

[0015] Let m be the number of rows and n be the number of columns in the pixel array section 111. Multiple pixels 115 are arranged in m rows and n columns. Scan lines WS, power supply lines DS, and signal lines 116 are shown as examples of wiring passing through the pixel array section 111, indicated by their reference numerals. Scan lines WS and power supply lines DS are provided, for example, for each pixel row and extend in the direction of the pixel row (X-axis direction). Signal lines 116 are provided, for example, for each pixel column and extend in the direction of the pixel column (Y-axis direction).

[0016] The scan lines WS are connected to the ends of the corresponding rows of the light scanner 112. The power supply lines DS are connected to the ends of the corresponding rows of the drive scanner 113.

[0017] The write scanner 112 sequentially supplies write scan signals to the scan lines WS when writing the signal voltage of the video signal to each pixel 115 of the pixel array unit 111. As a result, each pixel 115 of the pixel array unit 111 is scanned sequentially in row units (sequential line scanning). The write scanner 112 is configured to include a shift register circuit, etc. This shift register circuit sequentially shifts (transfers) start pulses in synchronization with the clock pulse.

[0018] The drive scanner 113 supplies power potential to the power supply line DS in synchronization with the line sequential scanning by the light scanner 112. The power potential may be switchable between two different levels of potential. This switching controls the light-emitting and non-light-emitting states of each pixel 115. The drive scanner 113 is configured to include a shift register circuit, etc. This shift register circuit sequentially shifts the start pulses in synchronization with the clock pulse.

[0019] The horizontal selector 114 selectively outputs the signal voltage of the video signal and a reference voltage corresponding to the brightness information supplied from a signal source (not shown). The reference voltage is a potential that serves as a reference for the signal voltage (for example, a potential corresponding to the black level of the video signal) and is used, for example, during threshold correction processing.

[0020] The signal voltage and the reference voltage output from the horizontal selector 114 are written to each pixel 115 of the pixel array unit 111 via the signal line 116. This writing is performed in units of pixel rows selected by the scanning of the light scanner 112. That is, the horizontal selector 114 adopts a driving mode of line sequential writing in which the signal voltage is written in units of rows.

[0021] FIG. 2 is a diagram showing an example of the schematic configuration of the pixel 115. The pixel 115 includes an organic EL element OLED, one or more transistors 1, a holding capacitor Cs, and an auxiliary capacitor Cel. The transistor 1, the holding capacitor Cs, and the auxiliary capacitor Cel constitute a driving circuit for the organic EL element OLED.

[0022] As the transistor 1, two types of transistors 1 are exemplified. One of the transistors 1 is referred to as transistor ˈ1-1 and illustrated. The other transistor 1 is referred to as transistor ˈ1-2 and illustrated. When these are not particularly distinguished, they are simply called transistor 1.

[0023] In the following description, when the transistor 1 is connected between two elements, it may be understood to mean that one current terminal (drain or source) of the transistor 1 is connected to one element and the other current terminal (source or drain) is connected to the other element.

[0024] The anode of the organic EL element OLED is connected to the power supply line DS via the transistor 1-1. The cathode of the organic EL element OLED is connected to a power supply line common to all the pixels 115.

[0025] The transistor 1-1 is connected between the power supply line DS and the organic EL element OLED. The transistor 1-1 can also be called a driving transistor or the like. The back gate of the transistor 1-1 is grounded.

[0026] The transistor 1-2 is connected between the signal line 116 and the gate of the transistor 1-1. The transistor 1-2 can also be called a video signal writing transistor or the like. The gate of the transistor 1-2 is connected to the scanning line WS.

[0027] At least one of transistor 1-1 and transistor 1-2 is a thin film transistor (TFT (Thin Film Transistor)). For example, only transistor 1-1 may be a TFT, or both transistor 1-1 and transistor 1-2 may be TFTs. The TFT will be described again later by referring to FIG. 3 and subsequent figures. Note that the circuit configuration shown in FIG. 1 is merely an example, and various other circuit configurations may be used. For example, the circuit of one pixel 115 may include three or more transistors. The transistor may be a pMOS type transistor.

[0028] The holding capacitor Cs is connected between the gate of transistor 1-1 and the anode of the organic EL element OLED. The auxiliary capacitor Cel is provided to compensate for the shortage of the capacitance of the equivalent capacitance of the organic EL element OLED and to increase the writing gain of the video signal with respect to the holding capacitor Cs. In this example, the auxiliary capacitor Cel is connected between the anode and the cathode of the organic EL element OLED (in parallel with the organic EL element OLED).

[0029] The semiconductor device 100 having the above-described configuration includes a thin film transistor. There are problems specific to a semiconductor device including a thin film transistor, and by addressing these problems, the performance of the device can be improved. The problems and their solutions will be described separately for each embodiment. Hereinafter, unless otherwise specified, transistor 1 is assumed to be a thin film transistor.

[0030] 1. First Embodiment In transistor 1, while low resistance of the source-drain region is required, high resistance of the channel region is required. This means forming both a low resistance region and a high resistance region in one thin film semiconductor. Also, it is required to ensure an on-current necessary for operation and to ensure the distance between the gate contact and the source-drain contact.

[0031] To form a low-resistance source-drain region, methods such as plasma treatment and ion implantation can be used. However, in this case, challenges remain in controlling impurities in the depth direction, and roughness and damage may occur on the surface, or the impurities may spread into the channel region.

[0032] At least some of the above-mentioned problems are addressed by the first embodiment. In the first embodiment, solid-layer diffusion is used to reduce the resistance of the source-drain region. An impurity film is provided to cover at least a portion of the source-drain region. This will be explained in detail with reference to Figure 3 and subsequent figures.

[0033] Figure 3 shows an example of the schematic configuration of the semiconductor device 100 according to the first embodiment. A schematic cross-section of the transistor 1 and its surroundings is shown when viewed from the side (viewed in a direction perpendicular to the Z-axis). The semiconductor device 100 includes a semiconductor substrate 2, a wiring layer 3, and a light-emitting layer 8.

[0034] The semiconductor substrate 2 is, for example, a silicon (Si) semiconductor substrate. A transistor other than transistor 1 is formed on the semiconductor substrate 2. The transistor formed on the semiconductor substrate 2 may be a transistor other than a thin-film transistor (for example, a MOSFET).

[0035] The wiring layer 3 is provided above the semiconductor substrate 2. The wiring layer 3 includes various types of wiring. Wiring may be understood to include vias. Vias are also called contacts. Several contacts are referred to as contacts 3c and are shown in the diagram. The material of contacts 3c is, for example, a metallic material.

[0036] In this example, the wiring layer 3 includes an insulating layer 4, a thin film layer 5, and an insulating layer 6, and also includes an impurity film 7. The insulating layer 4, thin film layer 5, and insulating layer 6 are arranged in this order in the positive Z-axis direction. Various materials may be used for the insulating layer 4 and insulating layer 6, one example being an oxide film (such as SiO2). The insulating layer 4 can also be called an interlayer film.

[0037] The thin film layer 5 includes a thin film semiconductor 50. The thin film semiconductor 50 includes several components of the transistor 1, in this example, an SD region 51 and a channel region 52. The SD region 51 refers to either the source region or the drain region. When simply referred to as the SD region 51, it may be interpreted as meaning either the source region or the drain region.

[0038] The illustrated thin-film semiconductor 50 includes two SD regions 51, namely a source region and a drain region. The channel region 52 is located between the two SD regions 51. The two SD regions 51 are a pair of SD regions 51 located on opposite sides of the channel region 52.

[0039] The contacts 3c are connected to the SD region 51 of the thin-film semiconductor 50. There is a pair of contacts 3c corresponding to a pair of SD regions 51. In the example shown in Figure 3, both pairs of contacts 3c are connected to the lower surface 50b of the corresponding SD region 51, and they have a symmetrical layout across the channel region 52.

[0040] The thin-film semiconductor 50 may be, for example, an oxide semiconductor, in which case the thin-film semiconductor 50 can also be called an oxide thin-film semiconductor. Various materials may be used, one example being IGZO (In (indium), Ga (gallium), Zn (zinc), O (oxygen)). Unless otherwise specified, the thin-film semiconductor 50 will be assumed to be an oxide thin-film semiconductor hereafter.

[0041] The SD region 51 of the thin-film semiconductor 50 contains impurities, which result in low resistance. These impurities are the same as those contained in the impurity film 7 described later.

[0042] The surface of the thin-film semiconductor 50 facing the square Z-axis is referred to as the upper surface 50a and is shown in the figure. The surface facing the negative Z-axis is referred to as the lower surface 50b and is shown in the figure. The upper and lower surfaces of the SD region 51 and the channel region 52 are also referred to as the upper surface 50a and the lower surface 50b. When the upper surface 50a and the lower surface 50b are not specifically distinguished, they are simply referred to as the surface of the thin-film semiconductor 50, the surface of the SD region 51, the surface of the channel region 52, etc.

[0043] The insulating layer 6 is provided so as to cover the thin film layer 5. In the example shown in Figure 3, the gate oxide film 61 and gate electrode 62 of the transistor 1 are also included in the insulating layer 6. Various materials may be used. An example of the material for the gate oxide film 61 is SiO (silicon oxide). An example of the material for the gate electrode 62 is TaN (tantalum nitride).

[0044] The gate oxide film 61 is provided between the gate electrode 62 and the channel region 52. The gate electrode 62 is provided so as to face the upper surface 50a or lower surface 50b of the channel region 52 of the thin film semiconductor 50, with the gate oxide film 61 in between. In the example shown in Figure 3, the gate electrode 62 is provided so as to face the upper surface 50a of the channel region 52 of the thin film semiconductor 50 (top gate structure).

[0045] The side of the gate electrode 62 facing the thin-film semiconductor 50 is referred to as the lower surface 62b and is shown in the figure. The side opposite to the lower surface 62b is referred to as the upper surface 62a and is shown in the figure. The side surface is referred to as the side surface 62c and is shown in the figure.

[0046] The impurity film 7 is provided so as to cover at least a portion of the SD region 51 of the thin-film semiconductor 50. The impurity film 7 may be provided on the SD region 51 so as to be in contact with the SD region 51 (for example, surface contact), or it may be provided between the SD region 51 and the impurity film 7 via other elements, within a range where the solid layer diffusion effect described later can be obtained. In the example shown in Figure 3, the impurity film 7 is provided so as to be in contact with the SD region 51.

[0047] The impurity film 7 is composed of predetermined impurities. Examples of impurities include B (boron), P (phosphorus), etc., which may be included in the impurity film 7 during the film formation process. Alternatively, the impurities may be ion-implanted. Examples of ion-implanted impurities include argon (Ar), hydrogen (H), etc. At least one of the various impurities exemplified may be included as an impurity in the impurity film 7. The same impurities included in the impurity film 7 are also included in the SD region 51 described above. That is, the thin film semiconductor 50 and the impurity film 7 contain the same impurities.

[0048] In the example shown in Figure 3, the impurity film 7 has a symmetrical layout across the channel region 52. Furthermore, the impurity film 7 is provided to cover both the lower surface 50b and the upper surface 50a of the SD region 51. The impurity film 7 covering the lower surface 50b of the SD region 51 is referred to as the lower impurity film 7-1 and is shown in the figure. The impurity film 7 covering the upper surface 50a of the SD region 51 is referred to as the upper impurity film 7-2 and is shown in the figure. Unless otherwise specified, they are simply referred to as the impurity film 7.

[0049] In the example shown in Figure 3, the lower impurity film 7-1 is provided so as to cover the lower surface 50b of the SD region 51 (excluding the contact 3c portion) while not covering the lower surface 50b of the channel region 52. However, part or all of the lower surface 50b of the channel region 52 may also be covered by the lower impurity film 7-1. The upper impurity film 7-2 is provided so as to cover not only the upper surface 50a of the SD region 51 of the thin film semiconductor 50, but also the side surface 62c and upper surface 62a of the gate electrode 62.

[0050] The impurity concentrations of the lower impurity film 7-1 and the upper impurity film 7-2 may be the same or different.

[0051] One application of the impurity film 7 is solid-layer diffusion. Solid-layer diffusion is carried out so that the thin-film semiconductor 50 and the impurity film 7 contain the same impurities. This will be explained with reference to Figure 4.

[0052] Figure 4 shows an example of solid-layer diffusion. The material of the thin-film semiconductor 50 is referred to as thin-film semiconductor material 50m and is shown in the figure. During solid-layer diffusion, impurities contained in the impurity film 7 diffuse into the thin-film semiconductor 50, as schematically shown by the arrows on the left side of Figure 4. After solid-layer diffusion, an SD region 51 containing the same impurities as the impurity film 7 is obtained, as shown on the right side of Figure 4.

[0053] For solid-layer diffusion, low-temperature annealing is used, for example. Examples of temperatures are around 350°C to 400°C. Examples of high temperatures are around 800°C to 1000°C, but there may be cases where such high temperatures cannot be used. In low-temperature annealing, the diffusion range may be more limited than in high-temperature annealing, but by providing an impurity film 7, in this example a lower impurity film 7-1, on the contact 3c side of the SD region 51, the effect of reducing resistance can be easily obtained.

[0054] Returning to Figure 3, the light-emitting layer 8 is provided above the wiring layer 3. The light-emitting layer 8 includes a light-emitting element. An example of a light-emitting element is the organic EL element (OLED) described earlier with reference to Figure 2. Of the light emitted from the light-emitting layer 8, the light directed in the positive Z-axis direction is output as display light.

[0055] According to the semiconductor device 100 having the configuration described above, impurities are introduced into the thin-film semiconductor 50 by solid-layer diffusion from the impurity film 7, and an SD region 51 is formed. A low-resistance SD region 51 can be obtained by utilizing solid-layer diffusion.

[0056] By using solid-layer diffusion, it is possible to address issues that may arise when using other methods, such as the plasma treatment and ion implantation mentioned earlier, including impurity control in the depth direction, surface condition (roughness, damage, etc.), and spread to the channel region 52. For example, it is possible to improve the on-current of transistor 1 while lowering the resistance of the SD region 51. Compared to ion implantation, outward diffusion in subsequent processes is less. Also, it is possible to increase the concentration (n+) at shallow depths. It is easy to lower the resistance of the interface. Also, compared to plasma treatment, it is possible to suppress damage to the surface of the thin-film semiconductor 50. Contact resistance is stabilized, and the degree of freedom in contact design is increased. For example, it is easy to lower the resistance of the lower surface 50b of the thin-film semiconductor 50, and even when the contact 3c is connected to the lower surface 50b, the contact resistance can be reduced. The total number of wirings can be reduced. Even when a light-shielding layer is provided on top (see Figures 26 and 27 described later), layout becomes easier.

[0057] From the various viewpoints described above, the performance of the semiconductor device 100 can be improved. In the example shown in Figure 3 described earlier, both the upper surface 50a and the lower surface 50b of the SD region 51 are covered by the impurity film 7 (lower impurity film 7-1 and upper impurity film 7-2). By having the impurity film 7, which is a solid-layer diffusion source, present on both the upper and lower sides of the SD region 51, the effect of reducing resistance can be enhanced compared to when it is present on only one side.

[0058] <Modifications> Several modifications based on the technology according to the first embodiment described above are described below.

[0059] <Examples of Side Sectional Layouts> Figures 5 to 21 show examples of side sectional layouts. In the example shown in Figure 5, the upper impurity film 7-2 is provided so as to cover the side surface 62c of the gate electrode 62, but not the upper surface 62a of the gate electrode 62. The upper surface 50a of the SD region 51 is covered by the upper impurity film 7-2 only in the portion adjacent to the channel region 52. When viewed from above (in the negative Z-axis direction), parts of the lower impurity film 7-1 and the upper impurity film 7-2 overlap. Note that, as shown in Figure 5, the portion of the SD region 51 not covered by the upper impurity film 7-2 does not need to be made low-resistance.

[0060] In the example shown in Figure 6, the upper impurity film 7-2 is provided so as not to cover the gate oxide film 61 and the gate electrode 62. The gate oxide film 61 is provided between the channel region 52 of the thin-film semiconductor 50 and the impurity film 7 and the gate electrode 62.

[0061] More specifically, the gate oxide film 61 includes a first portion 611 and a second portion 612. The first portion 611 is located between the channel region 52 of the thin-film semiconductor 50 and the gate electrode 62. The second portion 612 is located between the first portion 611 and the gate electrode 62 and the impurity film 7 (upper impurity film 7-2 in this example). The second portion 612 extends upward from the edge (edge ​​in the XY plane) of the first portion 611 so as to cover a portion of the side surface 62c of the gate electrode 62.

[0062] Furthermore, the thin-film semiconductor 50 includes a high-concentration region 53 directly beneath the second portion 612 of the gate oxide film 61. The high-concentration region 53 is a region where the n+ concentration is higher than that of the surrounding region.

[0063] In the example shown in Figure 7, the gate electrode 62 is provided facing the lower surface 50b of the channel region 52 of the thin-film semiconductor 50 (bottom gate structure). In this case, the gate oxide film 61 and the gate electrode 62 may be included in the insulating layer 4 (Figure 3). The lower impurity film 7-1 is provided so as to cover the lower surface 50b of the SD region 51 of the thin-film semiconductor 50 via the gate oxide film 61, and further so as to cover the gate electrode 62 (in this example, the side surface 62c and the upper surface 62a). The upper impurity film 7-2 is provided so as to cover the upper surface 50a of the SD region 51 of the thin-film semiconductor 50, but not the upper surface 50a of the channel region 52 of the thin-film semiconductor 50. However, part or all of the upper surface 50a of the channel region 52 may also be covered by the upper impurity film 7-2.

[0064] In the configuration described so far, the impurity film 7 had a symmetrical cross-sectional layout, for example, with the center of the thin-film semiconductor 50 in between. The same applies to other elements such as the contact 3c. On the other hand, the impurity film 7, contact 3c, etc., may have an asymmetrical layout. For example, the shape of the impurity film 7 may differ between one SD region 51 and the other SD region 51 (source region and drain region), or the extension direction of the contact 3c may differ.

[0065] In the examples shown in Figures 8 to 10, the impurity film 7 has an asymmetrical layout with respect to the channel region 52. Also, in the examples shown in Figures 9 and 10, the pair of contacts 3c corresponding to the pair of SD regions 51 have an asymmetrical layout with respect to the channel region 52. One contact 3c is connected to the upper surface 50a of the corresponding SD region 51. The other contact 3c is connected to the lower surface 50b of the corresponding SD region 51.

[0066] In one embodiment, the thickness (length in the Z-axis direction) of the upper impurity film 7-2 may be less than the thickness of the lower impurity film 7-1, and its thickness may be zero, i.e., the lower impurity film 7-1 may be absent. In that case, the impurity film 7 consists only of the lower impurity film 7-1. Advantages such as structural simplification can be obtained. Figure 11 shows a top gate structure. Figure 12 shows a bottom gate structure.

[0067] <Example of an oxygen supply film> The semiconductor device 100 shown in Figures 13 to 21 differs from Figures 3 and 5 to 12 described earlier in that it further includes an oxygen supply layer 9. The oxygen supply layer 9 is provided so as to be in contact with the channel region 52 of the thin-film semiconductor 50. More specifically, the oxygen supply layer 9 is provided on the surface of the channel region 52 opposite to the gate electrode 62.

[0068] The oxygen supply layer 9 is configured to contain more oxygen than the surrounding region. By providing the oxygen supply layer 9, the decrease in oxygen concentration in the channel region 52 can be suppressed. In this respect as well, it can contribute to improving the performance of the semiconductor device 100.

[0069] <Examples of Planar Layouts> Figures 22 to 25 show examples of planar layouts. In the example shown in Figure 22, the impurity film 7 overlaps with the entire SD region 51, and more specifically, the impurity film 7 is provided over the entire transistor 1 (the gate electrode 62 may be excluded). The impurity film 7 and the contact 3c have a symmetrical layout across the channel region 52.

[0070] In the example shown in Figure 23, the impurity film 7 overlaps with a portion of the channel region 52, with the contact 3c enclosed inside. The impurity film 7 and the contact 3c have a symmetrical layout across the channel region 52.

[0071] In the example shown in Figure 24, for one SD region 51, the impurity film 7 overlaps with the entire SD region 51. For the other SD region 51, the impurity film 7 overlaps with a part of its channel region 52, including the contact 3c on the inside.

[0072] In the example shown in Figure 25, the channel region 52 and gate electrode 62 of the thin-film semiconductor 50 have an annular (ring-shaped) configuration, with SD regions 51 located inside and outside them. The impurity film 7 is provided over the entire transistor 1 (the gate electrode 62 may be excluded). The impurity film 7 and contact 3c have a symmetrical layout across the channel region 52.

[0073] Furthermore, various planar layouts may be adopted for the impurity film 7 and contact 3c, not limited to the examples described above.

[0074] <Example of a light-shielding layer> In one embodiment, the semiconductor device 100 may be configured to shield light that is directed downward (in the negative Z-axis direction) from the light-emitting layer 8. This will be explained with reference to Figures 26 and 27.

[0075] Figures 26 and 27 show examples of the schematic configuration of the semiconductor device 100. Figure 26 shows the side cross-sectional layout. Figure 27 shows the planar layout.

[0076] The semiconductor device 100 further includes a light-shielding layer 10. The light-shielding layer 10 is provided above the thin-film semiconductor 50, in this example, between the thin-film layer 5 and the light-emitting layer 8. The light-shielding layer 10 is configured to block (absorb, reflect, etc.) at least a portion of the light from the light-emitting layer 8. Various materials may be used.

[0077] <Examples of Manufacturing Methods> Figures 28 to 56 show examples of manufacturing methods for semiconductor device 100. In particular, the manufacturing process for transistor 1 is shown.

[0078] Figures 28 to 37 show the manufacturing process for obtaining the configurations shown in Figures 3 and 5, which were described earlier. The material for the insulating layer 4 is referred to as insulating layer material 4m and is shown. The material for the impurity film 7 is referred to as impurity film material 7m and is shown. The material for the thin film semiconductor 50 is referred to as thin film semiconductor material 50m and is shown. The material for the gate oxide film 61 is referred to as gate oxide film material 61m and is shown. The material for the gate electrode 62 is referred to as gate electrode material 62m and is shown. Unless otherwise specified, the impurities in the impurity film material 7m are assumed to be included in the impurity film material 7m during the film formation process.

[0079] As shown in Figure 28, an insulating layer material 4m is prepared. The insulating layer material 4m is processed by lithography to form a pattern so that voids (recesses) corresponding to the lower impurity film 7-1 are obtained. As shown in Figure 29, an insulating layer 4 is obtained.

[0080] As shown in Figure 30, an impurity film material 7m is formed to cover the insulating layer 4. The upper part of the impurity film material 7m is removed by etch-back or CMP (Chemical Mechanical Polishing). As shown in Figure 31, a lower impurity film 7-1 is obtained.

[0081] Although not shown in the diagram, contact 3c may be formed (contact formation step).

[0082] As shown in Figure 32, a thin-film semiconductor material 50m is deposited so as to cover the insulating layer 4 and the lower impurity film 7-1. The thin-film semiconductor material 50m is processed by lithography to form a pattern corresponding to the shape of the thin-film semiconductor 50. As shown in Figure 33, a thin-film semiconductor material 50m is obtained that is located on the lower impurity film 7-1.

[0083] As shown in Figure 34, the gate oxide film material 61m and the gate electrode material 62m are sequentially deposited so as to cover the insulating layer 4 and the thin-film semiconductor material 50m. The gate oxide film material 61m and the gate electrode material 62m are processed by lithography to form patterns so that the gate oxide film 61 and the gate electrode material 62 are obtained. As shown in Figure 35, the gate oxide film 61 and the gate electrode material 62 are obtained.

[0084] By forming an impurity film material 7m so as to cover the insulating layer 4, the thin-film semiconductor material 50m, the gate oxide film 61, and the gate electrode 62, an upper impurity film 7-2 is obtained as shown in Figure 36. By performing solid-layer diffusion, a configuration similar to that of Figure 3 described earlier can be obtained.

[0085] Based on the configuration shown in Figure 36, the configuration shown in Figure 37 is obtained by further processing to remove a portion of the upper impurity film 7-2. By performing solid layer diffusion, a configuration similar to the one shown in Figure 5, which was explained earlier, can be obtained.

[0086] Figures 38 to 46 show the manufacturing process for obtaining the configuration shown in Figure 6, which was described earlier. It is assumed that the process shown in Figure 33, which was described earlier, has been completed.

[0087] As shown in Figure 38, an impurity film material 7m is formed to cover the insulating layer 4 and the thin-film semiconductor material 50m. The impurity film material 7m is processed by lithography to form a pattern corresponding to the gate oxide film 61. As shown in Figure 39, an upper impurity film 7-2 is obtained, which is provided so as to expose a part of the upper surface of the thin-film semiconductor material 50m.

[0088] As shown in Figure 40, the gate oxide film material 61m and the gate electrode material 62m are sequentially deposited so as to cover the upper impurity film 7-2 and the thin-film semiconductor material 50m. The gate oxide film material 61m and the gate electrode material 62m are processed by lithography to form patterns so that the gate oxide film 61 and the gate electrode material 62 are obtained. As shown in Figure 41, the gate oxide film 61, which includes the first portion 611 and the second portion 612, and the gate electrode 62 are obtained. Although not shown in the figure, the material is deposited and processed so that an insulating layer 6 is obtained. By performing solid layer diffusion, a configuration similar to the one in Figure 6 described earlier can be obtained.

[0089] Alternative (alternative) manufacturing processes are also possible, different from those shown in Figures 38 to 41 above. As shown in Figure 42, an insulating layer material 4m is deposited on top of the insulating layer 4. As shown in Figure 43, an impurity film material 7m is deposited so as to cover the insulating layer 4 and the thin-film semiconductor material 50m. The impurity film material 7m is processed by lithography to form a pattern corresponding to the gate oxide film 61. As shown in Figure 44, an upper impurity film 7-2 is obtained, which is provided so as to expose a part of the upper surface of the thin-film semiconductor material 50m.

[0090] As shown in Figure 45, the gate oxide film material 61m and the gate electrode material 62m are sequentially deposited so as to cover the upper impurity film 7-2 and the thin-film semiconductor material 50m. The gate oxide film material 61m and the gate electrode material 62m are processed by lithography to form patterns so that the gate oxide film 61 and the gate electrode material 62 are obtained. As shown in Figure 46, the gate oxide film 61, which includes the first portion 611 and the second portion 612, and the gate electrode 62 are obtained. Although not shown in the figure, the material is deposited and processed so that an insulating layer 6 is obtained. By performing solid layer diffusion, a configuration similar to the one in Figure 6 described earlier can be obtained.

[0091] Figures 47 to 54 show the manufacturing process for obtaining the configuration shown in Figure 7, which was explained earlier. The material for the insulating layer 6 is referred to as insulating layer material 6m and is shown in the figure. It is assumed that the process shown in Figure 28, which was explained earlier, has been completed.

[0092] The insulating layer material 4m is processed by lithography to form a pattern corresponding to the gate electrode 62. As shown in Figure 47, the insulating layer 4 is obtained. An impurity film material 7m is deposited to cover the insulating layer 4. As shown in Figure 48, the lower impurity film 7-1 is obtained.

[0093] As shown in Figure 49, the gate electrode material 62m is deposited so as to cover the lower impurity film 7-1. The upper part of the gate electrode material 62m is removed by etch-back or CMP. As shown in Figure 50, the gate electrode 62 is obtained.

[0094] Although not shown in the diagram, a contact formation process may be performed.

[0095] As shown in Figure 51, the gate oxide film material 61m and the thin-film semiconductor material 50m are sequentially deposited to cover the lower impurity film 7-1 and the gate electrode 62. As shown in Figure 52, the gate oxide film material 61m and the thin-film semiconductor material 50m are processed by lithography to obtain shapes corresponding to the gate oxide film 61 and the thin-film semiconductor 50. As shown in Figure 53, the insulating layer material 6m is deposited. Further, the insulating layer material 6m and the impurity film material 7m are deposited or processed. As shown in Figure 54, the gate oxide film 61, the upper impurity film 7-2, and the insulating layer 6 are obtained. By performing solid-layer diffusion, a configuration similar to the one shown in Figure 7, which was described earlier, can be obtained.

[0096] As mentioned earlier, impurities may be ion-implanted. For example, an impurity film 7 can be obtained by ion-implanting impurities into the insulating layer material 4m. This will be explained with reference to Figures 55 and 56.

[0097] Figures 55 and 56 show examples of the formation of an impurity film 7 by ion implantation. It is assumed that the process shown in Figure 28, described earlier, has been completed.

[0098] As shown in Figure 55, a photoresist PR is provided so as to cover a portion of the insulating layer material 4m. The photoresist PR is patterned so that the portion of the insulating layer material 4m corresponding to the lower impurity film 7-1 is exposed. As shown in Figure 56, impurities are ion-implanted. A portion of the insulating layer material 4m becomes the lower impurity film 7-1. When the photoresist PR is removed, a configuration similar to that shown in Figure 31 is obtained.

[0099] By ion-implanting impurities into the insulating layer material 6m using a similar method, an upper impurity film 7-2 is obtained.

[0100] <Summary> The technology according to the first embodiment described above can be specified as follows, for example. One of the disclosed technologies is a semiconductor device 100 (for example, a display device). As described with reference to Figures 1 to 27, the semiconductor device 100 comprises a semiconductor substrate 2, a thin film semiconductor 50 (for example, an oxide thin film semiconductor) provided above the semiconductor substrate 2 (on the positive Z-axis side) and including an SD region 51 and a channel region 52, and an impurity film 7 provided so as to cover at least a part of the SD region 51 of the thin film semiconductor 50. The SD region 51 and the impurity film 7 contain the same impurity (for example, B, P, etc.). The impurity film 7 includes a lower impurity film 7-1 provided so as to cover the lower surface 50b of the SD region 51.

[0101] The semiconductor device 100 described above introduces impurities into the thin-film semiconductor 50 by solid-layer diffusion from the impurity film 7, thereby obtaining a low-resistance SD region 51. This avoids problems that may arise when using methods other than solid-layer diffusion, such as plasma treatment or ion implantation, and improves the performance of the semiconductor device 100.

[0102] As explained with reference to Figures 3 and 5 to 21, the impurity film 7 may be in contact with the SD region 51. This makes it easier to obtain a solid-layer diffusion effect.

[0103] As explained with reference to Figures 3, 5 to 10, and 13 to 19, the impurity film 7 may include an upper impurity film 7-2 provided so as to cover the upper surface 50a of the SD region 51. Solid-layer diffusion from both the lower impurity film 7-1 and the upper impurity film 7-2 (from both sides) can further enhance the effect of reducing the resistance of the SD region 51.

[0104] As explained with reference to Figures 3 and 5 to 27, the semiconductor device 100 may be provided with a contact 3c connected to the SD region 51. This can reduce contact resistance. The contact 3c may be connected to the lower surface 50b of the SD region 51. Since the contact 3c is connected to a region with a large solid-layer diffusion effect from the lower impurity film 7-1, it becomes easier to obtain a reduction in contact resistance.

[0105] As explained with reference to Figures 3, 5 to 11, 13 to 15, 17 to 20, and 22 to 27, the semiconductor device 100 may include a gate electrode 62 positioned opposite the upper surface 50a of the channel region 52 (top gate structure). The semiconductor device 100 may also include a gate oxide film 61 provided between the gate electrode 62 and the channel region 52. Various side cross-sectional layouts are possible. For example, as explained with reference to Figures 3, 9, 13, and 18, the upper impurity film 7-2 may be provided so as to cover the side surface 62c and the upper surface 62a of the gate electrode 62, while the lower impurity film 7-1 may be provided so as not to cover the lower surface 50b of the channel region 52. As explained with reference to Figures 5 and 14, the upper impurity film 7-2 may be provided so as to cover the side surface 62c of the gate electrode 62, while not covering the upper surface 62a of the gate electrode 62. As explained with reference to Figures 6 and 11, the upper impurity film 7-2 may be provided so as not to cover the gate oxide film 61 and the gate electrode 62.

[0106] As explained with reference to Figures 7, 12, 16, and 21, the semiconductor device 100 may include a gate electrode positioned opposite the lower surface of the channel region (bottom gate structure). Various side cross-sectional layouts are possible. For example, the upper impurity film 7-2 may be provided so as not to cover the upper surface 50a of the channel region 52. The lower impurity film 7-1 may be provided so as to cover the gate electrode 62.

[0107] As explained with reference to Figures 3 and 5 to 27, the SD region 51 may be a pair of SD regions 51 located on opposite sides of the channel region 52. The contacts 3c may be a pair of contacts 3c corresponding to the pair of SD regions 51. Various layouts are possible for the impurity film 7 and the contacts 3c. For example, as explained with reference to Figures 3, 5 to 7, 11 to 16, 20 to 23, and 25 to 27, the impurity film 7 may have a symmetrical layout across the channel region 52. As explained with reference to Figures 8 to 10, 17 to 19, and 24, the impurity film 7 may have an asymmetrical layout across the channel region 52. As explained with reference to Figures 3, 5 to 8, 11 to 17, and 20 to 27, the pair of contacts 3c may have a symmetrical layout across the channel region 52. As explained with reference to Figures 9, 10, 18, and 19, the pair of contacts 3c may have an asymmetrical layout with respect to the channel region 52.

[0108] As explained with reference to Figures 11 and 20, when the gate electrode 62 is provided facing the upper surface 50a of the channel region 52 (top gate structure), the impurity film 7 may consist only of the lower impurity film 7-1. As explained with reference to Figures 12 and 21, when the gate electrode 62 is provided facing the lower surface 50b of the channel region 52 (bottom gate structure), the impurity film 7 may also consist only of the lower impurity film 7-1. The structure can be simplified.

[0109] Various layouts are possible for the planar layout. For example, as explained with reference to Figures 22, 24, 25, and 27, the impurity film 7 may overlap with the entire SD region 51 when viewed from above (in the negative Z-axis direction). As explained with reference to Figures 23 and 24, the impurity film 7 may overlap with a part of the SD region 51, including the contact 3c on its inside.

[0110] As explained with reference to Figure 3, the semiconductor device 100 includes a wiring layer 3 provided above the semiconductor substrate 2 (on the positive Z-axis side), and the wiring layer 3 may include a thin-film semiconductor 50. A transistor other than the transistor 1 (a transistor that is not a thin-film transistor) containing the SD region 51 and channel region 52 of the thin-film semiconductor 50 may be formed on the semiconductor substrate 2. For example, the performance of a semiconductor device 100 having such a configuration can be improved.

[0111] As explained with reference to Figures 26 and 27, the semiconductor device 100 may include an emissive layer 8 provided above the thin film semiconductor 50 (on the positive Z-axis side) and a light-shielding layer 10 provided between the thin film semiconductor 50 and the emissive layer 8. This makes it possible to block light directed downward (on the negative Z-axis side) from the emissive layer 8.

[0112] As explained with reference to Figures 13 to 21, the semiconductor device 100 may include an oxygen supply layer 9 provided in contact with the channel region 52. The oxygen supply layer 9 may contain more oxygen than the surrounding region. This can suppress a decrease in the oxygen concentration of the channel region 52.

[0113] A method for manufacturing the semiconductor device 100 is also one of the disclosed technologies. As explained with reference to Figure 4, the manufacturing method includes a step of diffusing impurities contained in the impurity film 7 into the thin-film semiconductor 50 (solid layer diffusion step). Various other steps may also exist, some of which have been explained earlier with reference to Figures 28 to 56.

[0114] The effects described in this disclosure are merely illustrative and not limited to those disclosed. Other effects may also occur.

[0115] 2. Second Embodiment As described above, the thin-film semiconductor 50 of the transistor 1 is obtained by processing a thin-film semiconductor material 50m. An example of the material for the thin-film semiconductor 50 is IGZO, and such materials are difficult to etch. For example, many reaction products are deposited during dry etching, making it difficult to obtain the intended shape. If there are many deposits, the process may become unstable, which may lead to a decrease in the performance of the transistor 1. In particular, as the processing area increases, the amount of deposits increases, and the problem becomes apparent.

[0116] Instead of completely removing the portion of the thin-film semiconductor material 50m that is not used for the transistor 1, it is conceivable to process it slightly by separating the thin-film semiconductor 50 from the other portion with a slit. This can suppress the increase in the processing area. On the other hand, the thin-film semiconductor material 50m that is not used for the transistor 1 will remain. This will restrict the wiring design, such as the placement of vias passing through the thin-film layer 5.

[0117] At least some of the above-mentioned problems are addressed by the second embodiment. In the second embodiment, at least a portion of the thin-film semiconductor material 50m that was not used as transistor 1 is made low-resistance (n+) and effectively used, for example, as via relay wiring. This will be explained with reference to Figure 57 and subsequent figures. In addition, the configuration of the first embodiment described above may be appropriately combined with the second embodiment to the extent that it does not contradict the original.

[0118] Figure 57 is a diagram showing an example of the schematic configuration of the semiconductor device 100 according to the second embodiment. It mainly shows the wiring layer 3, and more specifically the side cross-sectional layout of the insulating layer 4, thin film layer 5, and insulating layer 6.

[0119] The insulating layer 4 is provided below the thin film layer 5. The insulating layer 4 includes wiring. Some of the wiring in the insulating layer 4 is referred to as the lower wiring 40 and is shown in the figure. The lower wiring 40 is located below the thin film layer 5.

[0120] The thin film layer 5 contains multiple thin film semiconductors 50. Multiple types of thin film semiconductors 50 exist, and two types of thin film semiconductors 50 are shown in Figure 3. The first thin film semiconductor is referred to as thin film semiconductor 50-1 and is shown in the figure. The second thin film semiconductor is referred to as thin film semiconductor 50-2 and is shown in the figure. When not specifically distinguished, they are simply called thin film semiconductors 50.

[0121] The thin-film semiconductor 50-1 is a component of the transistor 1 and corresponds to the thin-film semiconductor 50 in the first embodiment described above. The thin-film semiconductor 50-1 includes an SD region 51 and a channel region 52.

[0122] The thin-film semiconductor 50-2 is not a component of the transistor 1. The thin-film semiconductor 50-2 is provided spaced apart from the thin-film semiconductor 50-1. A slit is formed between the thin-film semiconductor 50-1 and the thin-film semiconductor 50-2, and this portion is filled with the material of the insulating layer 6.

[0123] The thin-film semiconductor 50-2 has been made low-resistance. For example, by adding various impurities to the thin-film semiconductor material 50m to increase its concentration (to n+), a low-resistance thin-film semiconductor 50-2 can be obtained. Ion implantation, plasma treatment, etc., may be used. For example, by creating an oxygen vacancy in the IGZO, that part becomes low-resistance.

[0124] The upper and lower surfaces of the thin-film semiconductor 50-2 are also referred to as the upper surface 50a and the lower surface 50b. Furthermore, the side surface of the thin-film semiconductor 50-2 is referred to as the side surface 50c and is shown in the figure.

[0125] The insulating layer 6 is provided above the thin film layer 5. Some of the wiring within the insulating layer 6 is referred to as the upper wiring 60 and is shown in the diagram. The upper wiring 60 is located above the thin film layer 5.

[0126] The wiring layer 3 includes not only the contacts 3c connected to the thin-film semiconductor 50-1, but also the vias 3v connected to the thin-film semiconductor 50-2. The names "contact" and "via" are used merely for distinction, and within reasonable limits, the terms "contact" and "via" may be interpreted differently as appropriate.

[0127] Via 3v is connected to the thin-film semiconductor 50-2. In this example, via 3v includes a lower via 31v and an upper via 32v. The lower via 31v is connected between the lower wiring 40 and the thin-film semiconductor 50-2. The upper via 32v is connected between the upper wiring 60 and the thin-film semiconductor 50-2. The upper wiring 60 and the lower wiring 40 are electrically connected via via 3v and the thin-film semiconductor 50-2.

[0128] Note that the wiring layer 3 may include only one of the lower via 31v and the upper via 32v.

[0129] The thin-film semiconductor 50-2 is obtained, for example, by reducing the resistance of at least a portion of the thin-film semiconductor material 50m separated by a slit. A portion that is not reduced in resistance may remain. See also Figure 58 for further explanation.

[0130] Figure 58 shows an example of the schematic configuration of the semiconductor device 100. A schematic planar layout of a part of the semiconductor device 100 is shown. In addition to thin film semiconductors 50-1 and 50-2, there is also a thin film semiconductor 50-3. Thin film semiconductor 50-3 is a third thin film semiconductor provided spaced apart from thin film semiconductors 50-1 and 50-2. Thin film semiconductor 50-3 differs from thin film semiconductor 50-2 in that it is not made low-resistance.

[0131] Of the thin-film semiconductor material 50m, the portion other than thin-film semiconductor 50-1 and thin-film semiconductor 50-2 can become thin-film semiconductor 50-3. In other words, if the resistance of thin-film semiconductor 50-3 is reduced, it becomes thin-film semiconductor 50-2. A via 3v (Figure 57) is connected to thin-film semiconductor 50-2, one of the thin-film semiconductors 50-2 and thin-film semiconductor 50-3.

[0132] According to the semiconductor device 100 having the configuration described above, the thin film layer 5 contains not only thin film semiconductor 50-1, but also thin film semiconductor 50-2, and may also contain thin film semiconductor 50-3. This reduces the processing area of ​​the thin film semiconductor material 50m and reduces deposits. This suppresses the performance degradation of the transistor 1 that may occur due to deposits. In addition, since vias 3v can be connected to the thin film semiconductor 50-2, the degree of freedom in wiring design can be improved. Using the thin film semiconductor 50-2 as a relay wiring eliminates the need to form deep vias, which has the advantage of making processing and metal embedding easier.

[0133] <Modifications> Several modifications based on the technology according to the second embodiment described above will be explained.

[0134] <Example of Planar Layout> Figure 59 shows an example of a planar layout. When viewed from above, the thin film semiconductor 50-2 is arranged to surround the thin film semiconductor 50-1. In this example, two thin film semiconductors 50-2, each having a roughly U-shape, are arranged to face each other with the thin film semiconductor 50-3 in between, and as a whole surround the thin film semiconductor 50-2.

[0135] One or more vias 3v may be connected to a single thin-film semiconductor 50-2. In the example shown in Figure 59, multiple vias 3v are connected to the thin-film semiconductor 50-2 on the left. One via 3v is connected to the thin-film semiconductor 50-2 on the right. This single via 3v may have a planar layout similar to that of the thin-film semiconductor 50-2.

[0136] The number of thin-film semiconductors 50-2 and 50-3, and the pattern (slit layout) of the separated portions of thin-film semiconductors 50-2 and 50-3, are not limited to the example shown in Figure 59.

[0137] <Suppression of High Resistance> In one embodiment, measures may be taken to suppress the increase in resistance of the thin-film semiconductor 50-2. This will be explained with reference to Figure 60.

[0138] Figure 60 shows an example of the schematic configuration of the semiconductor device 100. The insulating layer 4 includes an additional film 41. The additional film 41 is provided so as to be in contact with the thin-film semiconductor 50-2. In this example, the additional film 41 is provided so as to be in contact with the lower surface 50b of the thin-film semiconductor 50-2 (excluding the portion of the lower via 31v).

[0139] Examples of the additional film 41 are an oxygen blocking film and a hydrogen supply film, and one or both of these may be used as the additional film 41. Examples of materials for the oxygen blocking film are SiN (silicon nitride) and Al ２ O ３ Examples of materials for the oxygen-blocking membrane include aluminum oxide, and at least one of these may be used as the material for the oxygen-blocking membrane. Examples of materials for the hydrogen-supplying membrane include SiCN (silicon nitride carbide).

[0140] When the additional film 41 functions as an oxygen blocking film, the additional film 41 protects the thin-film semiconductor 50-2 from oxygen. When the additional film 41 functions as a hydrogen supply film, hydrogen is supplied from the additional film 41 to the thin-film semiconductor 50-2. In either case, the increase in resistance of the thin-film semiconductor 50-2 can be suppressed.

[0141] <Relay Wiring Embedding> In one embodiment, via 3v may be provided such that the thin film semiconductor 50-2 is embedded in via 3v. This can strengthen the electrical connection between the thin film semiconductor 50-2 and via 3v. This will be explained with reference to Figures 61 to 63.

[0142] Figures 61 to 63 show examples of the schematic configuration of the semiconductor device 100. In the example shown in Figure 61, the via 3v is provided so as to cover the upper surface 50a and side surface 50c of the thin film semiconductor 50-2. Specifically, the upper via 32v includes a metal film 321v and an extended portion 322v. Of these, the metal film 321v is provided so as to cover the upper surface 50a and side surface 50c of the thin film semiconductor 50-2. The extended portion 322v may be the portion of the upper via 32v other than the metal film 321v, and extends from the metal film 321v to the upper wiring 60.

[0143] Examples of materials for the metal film 321v include Ti (titanium), Ta (tantalum), TiN (titanium nitride), TaN (tantalum nitride), Cu (copper), W (tungsten), Al (aluminum), etc. At least one of these may be used as the material for the metal film 321v. Hydrogen supply from the metal film 321v to the thin-film semiconductor 50-2 can also be expected. The metal film 321v may be a multilayer film having a multilayer structure.

[0144] In the example shown in Figure 62, the metal film 321v is provided so as to cover not only the upper surface 50a and side surface 50c of the thin-film semiconductor 50-2, but also the lower surface 50b (excluding the portion of the lower via 31v). An additional film 41 may be provided as shown in Figure 63.

[0145] Figures 64 to 67 show examples of the positional relationship between the thin-film semiconductor 50-2 and the via 3v. The upper surface 50a, lower surface 50b, and side surface 50c of the thin-film semiconductor 50-2 are covered by the upper via 32v and the additional film 41. The side surface of the upper via 32v is referred to as side surface 32c and is shown in the figure. The side surface of the additional film 41 is referred to as side surface 41c and is shown in the figure.

[0146] In the example shown in Figure 64, the side surface 32c of the upper via 32v and the side surface 41c of the additional film 41 are adjacent surfaces (same surface) without any step difference. However, some positional misalignment, i.e., a step difference, is acceptable. In the example shown in Figure 65, the side surface 32c of the upper via 32v is located outside the side surface 41c of the additional film 41. In the example shown in Figure 66, the side surface 32c of the upper via 32v is located inside the side surface 41c of the additional film 41.

[0147] The position of the upper via 32v relative to the thin-film semiconductor 50-2 may be slightly misaligned. In the example shown in Figure 67, one side surface 32c of the left upper via 32v is located outside the side surface 50c of the thin-film semiconductor 50-2. The side surface 32c of the right upper via 32v is located inside the side surface 50c of the thin-film semiconductor 50-2.

[0148] <Examples of Planar Layout Design> Since thin-film semiconductors 50-1, 50-2, and 50-3 are obtained from the same thin-film semiconductor material 50m, various planar layout design methods are possible. Several examples will be explained with reference to Figures 68 and 69.

[0149] Figures 68 and 69 show examples of planar layout designs. In the example shown in Figure 68, the planar layout is designed based on a pattern in which thin film semiconductors 50-3 are repeatedly arranged. Specifically, a planar layout in which thin film semiconductors 50-3 are repeatedly arranged is prepared, as shown in Figure 68(A). A planar layout relating to thin film semiconductors 50-1 and 50-2 is prepared, as shown in Figure 68(B). As shown by the dashed line in Figure 68(C), a range of the planar layout in Figure 68(A) that corresponds to the planar layout in Figure 68(B) is defined. The thin film semiconductors 50-3 within this range are removed, and the planar layout in Figure 68(A) is incorporated into it. A planar layout as shown in Figure 68(D) is obtained.

[0150] In the example shown in Figure 69, thin film semiconductors 50-1, 50-2, and 50-3, as well as one element each related to thin film semiconductors 50-1 and 50-2, are arranged as cells to design a planar layout. Outside this planar layout (the area enclosed by the dashed line in the figure), thin film semiconductors 50-3 are repeatedly arranged.

[0151] Figures 70 to 73 show examples of arrangements of thin-film semiconductors 50-3. In the examples shown in Figures 70 to 72, multiple thin-film semiconductors 50-3 are arranged periodically. Specifically, multiple thin-film semiconductors 50-3 are arranged at equal intervals in the X-axis and Y-axis directions. Various arrangements are possible.

[0152] For example, as shown in Figure 70, multiple thin-film semiconductors 50-3 may be arranged in the Y-axis direction at the same position in the X-axis direction, and multiple thin-film semiconductors 50-3 may be arranged in the X-axis direction at the same position in the Y-axis direction.

[0153] As shown in Figure 71, adjacent thin-film semiconductors 50-3 positioned at the same location in the X-axis direction may be offset by half a portion in the Y-axis direction.

[0154] As shown in Figure 72, adjacent thin-film semiconductors 50-3 positioned at the same location in the Y-axis direction may be offset by half a portion in the X-axis direction. The thin-film semiconductors 50-3 may have any planar shape, and a hexagonal shape is exemplified in Figure 72.

[0155] In the example shown in Figure 73, the thin-film semiconductor 50-3 is arranged to have a shape that matches the shape of the array of transistors 1.

[0156] <Lamination of Gate Oxide Film 61> In one embodiment, the gate oxide film 61 may be laminated. This will be explained with reference to Figure 74.

[0157] Figure 74 shows an example of the schematic configuration of the semiconductor device 100. The gate oxide film 61 has a layered structure, and in this example specifically, it includes two layered oxide films. The first oxide film is referred to as oxide film 61a and is shown in the figure. The second oxide film is referred to as oxide film 61b and is shown in the figure. Oxide film 61a and oxide film 61b are layered in this order in the positive Z-axis direction. Various materials may be used.

[0158] <Examples of Manufacturing Methods> Figures 75 to 117 show examples of manufacturing methods for the semiconductor device 100.

[0159] In the examples shown in Figures 75 to 93, the thin-film semiconductor 50, the gate oxide film 61, and the gate electrode 62 are processed in sequence. The material for the oxide film 61a is referred to as oxide film material 61am and is shown in the figure. The material for the oxide film 61b is referred to as oxide film material 61bm and is shown in the figure. The material for the upper via 32v is referred to as upper via material 32vm and is shown in the figure.

[0160] As shown in Figure 75, an insulating layer 4 including the lower wiring 40 and lower via 31v is prepared. As shown in Figure 76, a thin film semiconductor material 50m is deposited so as to cover the insulating layer 4.

[0161] As shown in Figure 77, an oxide film material 61am is formed to cover the thin film semiconductor material 50m. As shown in Figure 78, a photoresist PR is provided to cover the portion of the oxide film material 61am corresponding to the thin film semiconductor 50.

[0162] The portion of the thin-film semiconductor material 50m and oxide film material 61am that is not covered by photoresist PR is processed. As shown in Figure 79, an oxide film 61a is obtained. As shown in Figure 80, the photoresist PR is removed.

[0163] As shown in Figure 81, an oxide film material 61bm is formed to cover the oxide film material 61am and the insulating layer 4. As shown in Figure 82, a gate electrode material 62m is formed to cover the oxide film material 61am.

[0164] As shown in Figure 83, a photoresist PR is provided so as to cover the portion of the gate electrode material 62m corresponding to the gate electrode 62. The portion of the gate electrode material 62m not covered by the photoresist PR is processed. As shown in Figure 84, the gate electrode 62 is obtained.

[0165] The portions of the oxide film material 61am and oxide film material 61bm that are not covered by the gate electrode 62 are processed. As shown in Figure 85, a gate oxide film 61 containing oxide film 61a and oxide film 61b is obtained. As shown in Figure 86, the photoresist PR is removed.

[0166] As shown in Figure 87, a portion of the thin-film semiconductor material 50m is made to have low resistance so that thin-film semiconductors 50-1 and 50-2 can be obtained. As shown in Figure 88, an insulating layer material 6m is formed to cover the thin-film semiconductor 50 and the insulating layer 4.

[0167] As shown in Figure 89, the photoresist PR is provided in such a way that it does not cover the lower via 31v of the insulating layer material 6m. As shown in Figure 90, the portion of the insulating layer material 6m that is not covered by the photoresist PR is processed.

[0168] As shown in Figure 91, the photoresist PR is removed. As shown in Figure 92, an upper via material 32vm is provided to fill the gap between the insulating layer material 6m. By flattening the top of the upper via material 32vm, a via 3v including the lower via 31v and the upper via 32v is obtained, as shown in Figure 93. Although not shown in the figure, by subsequently forming the upper wiring 60, the configuration shown in Figure 57, etc., described earlier, is obtained.

[0169] In the examples shown in Figures 94 to 112, the thin-film semiconductor 50, the gate oxide film 61, and the gate electrode 62 are processed together. It is assumed that the process shown in Figure 75, described earlier, has been completed.

[0170] As shown in Figure 94, a thin-film semiconductor material 50m, a gate oxide material 61m, and a gate electrode material 62m are deposited in this order to cover the lower via 31v and the insulating layer 4. As shown in Figure 95, a hard mask HM is provided to cover the gate electrode material 62m. In this example, the hard mask HM has a two-layer laminated structure.

[0171] As shown in Figure 96, a photoresist PR is provided on the hard mask HM so as to cover the portion corresponding to the slit between the thin-film semiconductors 50. As shown in Figure 97, the portion of the hard mask HM not covered by the photoresist PR is processed.

[0172] As shown in Figure 98, the photoresist PR is removed. The portions of the gate electrode material 62m, gate oxide film material 61m, and thin film semiconductor material 50m that are not covered by the hard mask HM are processed to form slits. As shown in Figure 99, the gate oxide film 61 is obtained. In the thin film semiconductor material 50m, portions corresponding to adjacent thin film semiconductors 50 are separated by the slits.

[0173] As shown in Figure 100, an insulating layer material 6m is provided to fill the space between the gate electrode material 62m, the gate oxide film 61, and the thin-film semiconductor material 50m. As shown in Figure 101, the upper part of the insulating layer material 6m is removed to flatten it.

[0174] As shown in Figure 102, the hard mask HM is removed. As shown in Figure 103, another gate electrode material 62m (shown by a dashed line) is deposited to cover the gate electrode material 62m.

[0175] As shown in Figure 104, photoresist PR is applied to cover only the portion of the gate electrode material 62m corresponding to the gate electrode 62. The portion of the gate electrode material 62m not covered by photoresist PR is processed. As shown in Figure 105, the gate electrode 62 is obtained.

[0176] The portion of the gate oxide film material 61m that is not covered by the photoresist PR is also processed. As shown in Figure 106, the gate oxide film 61 is obtained. As shown in Figure 107, the photoresist PR is removed.

[0177] A portion of the thin-film semiconductor material 50m is made to have low resistance. As shown in Figure 108, thin-film semiconductor 50-1 and thin-film semiconductor 50-2 are obtained. As shown in Figure 109, an insulating layer material 6m is further deposited so as to cover the thin-film semiconductor 50 and the insulating layer material 6m.

[0178] As shown in Figure 110, the photoresist PR is applied so as not to cover the portion of the insulating layer material 6m corresponding to the lower via 31v. As shown in Figure 111, the portion of the insulating layer material 6m that is not covered by the photoresist PR is processed.

[0179] Removing the photoresist PR yields the configuration shown in Figure 112. This configuration is the same as that shown in Figure 91, which was described earlier, except that the gate oxide film 61 has a single-layer structure. The subsequent steps are the same as those shown in Figures 92 and 93, which were described earlier.

[0180] Figures 113 to 116 show the manufacturing process for obtaining a configuration in which the thin-film semiconductor 50-2 is embedded in the upper via 32v, as described in Figure 61 and other figures. It is assumed that the process shown in Figure 88 has been completed.

[0181] As shown in Figure 113, the photoresist PR is applied so as not to cover the portion of the insulating layer material 6m corresponding to the lower via 31v. As shown in Figure 114, the portion of the insulating layer material 6m that is not covered by the photoresist PR is processed.

[0182] As shown in Figure 115, the photoresist PR is removed. As shown in Figure 116, an upper via material 32vm is provided so as to cover the thin film semiconductor 50-2 and the insulating layer material 6m.

[0183] The upper part of the upper via material 32vm is removed and flattened. As shown in Figure 117, a via 3v containing the lower via 31v and the upper via 32v is obtained. The thin film semiconductor 50-2 is embedded in the upper via 32v.

[0184] <Summary> The technology according to the second embodiment described above can be specified, for example, as follows. As described with reference to Figures 57 to 74, the semiconductor device 100 includes a thin film layer 5 including a thin film semiconductor 50-1 (first thin film semiconductor), which is the thin film semiconductor 50 described in the first embodiment, and a thin film semiconductor 50-2 (second thin film semiconductor) provided spaced apart from the thin film semiconductor 50-1, and vias 3v connected to the thin film semiconductor 50-2. The thin film semiconductor 50-2 may be made low-resistance (for example, n+). The semiconductor device 100 includes an upper wiring 60 located above the thin film layer 5 (on the positive Z-axis side), and vias 3v may be connected between the upper wiring 60 and the thin film semiconductor 50-2. The semiconductor device 100 includes a lower wiring 40 located below the thin film layer 5 (on the negative Z-axis side), and vias 3v may be connected between the lower wiring 40 and the thin film semiconductor 50-2. via 3v includes an upper via 32v connected between the upper wiring 60 and the thin-film semiconductor 50-2, and a lower via 31v connected between the lower wiring 40 and the thin-film semiconductor 50-2. The upper wiring 60 and the lower wiring 40 may be electrically connected via via 3v and the thin-film semiconductor 50-2.

[0185] In the semiconductor device 100 described above, the thin film layer 5 contains not only thin film semiconductor 50-1 but also thin film semiconductor 50-2. This reduces the processing area of ​​the thin film semiconductor material 50m. It also suppresses performance degradation of the transistor 1 caused by deposits generated during processing. For example, by using the thin film semiconductor 50-2 as a relay wiring for via 3v, the flexibility of wiring is improved. This contributes to improving the performance of the semiconductor device 100.

[0186] The via 3v can be connected to the thin-film semiconductor 50-2 in various ways. For example, as explained with reference to Figure 59, multiple vias 3v may be connected to one thin-film semiconductor 50-2. Alternatively, one via 3v may be connected to one thin-film semiconductor 50-2.

[0187] The planar shape of the thin-film semiconductor 50-2 can also be designed in various ways. For example, as explained with reference to Figure 59, when viewed from a planar perspective (viewed in the negative Z-axis direction), the thin-film semiconductor 50-2 may be arranged to surround the thin-film semiconductor 50-1.

[0188] As explained with reference to Figures 60 and 63 to 67, the semiconductor device 100 includes an additional film 41 provided in contact with the thin film semiconductor 50-2, and the additional film 41 is an oxygen blocking film (for example, SiN, Al ２ O ３ ) and may include at least one of a hydrogen supply film (e.g., SiCN). This can suppress the increase in resistance of the thin-film semiconductor 50-2.

[0189] As explained with reference to Figures 61 to 63, the via 3v may include a metal film 321v (e.g., Ti, Ta, TiN, TaN, Cu, W, Al) covering the upper surface 50a and side surface 50c of the thin-film semiconductor 50-2. This can strengthen the electrical connection between the thin-film semiconductor 50-2 and the via 3v.

[0190] As explained with reference to Figures 58, 59 and 70-72, the thin film layer 5 includes a thin film semiconductor 50-3 (a third thin film semiconductor) provided at a distance from the thin film semiconductors 50-1 and 50-2. While the thin film semiconductor 50-2 has low resistance, the thin film semiconductor 50-3 does not need to have low resistance. As shown in Figures 70-72, the thin film layer 5 may include a plurality of periodically arranged thin film semiconductors 50-3. The presence of the thin film semiconductors 50-3 allows for a further reduction in the processing area of ​​the thin film semiconductor material 50m.

[0191] A method for manufacturing the semiconductor device 100 is also one of the disclosed technologies. As described with reference to Figures 78, 79, 87, 98, 99, 107, and 108, the manufacturing method includes a step of processing the thin film semiconductor material 50m to reduce its resistance so that a thin film semiconductor 50-2 separated from the thin film semiconductor 50-1 is obtained. Various other steps may also exist, some of which have been described earlier with reference to Figures 75 to 117.

[0192] The effects described in this disclosure are merely illustrative and not limited to those disclosed. Other effects may also occur.

[0193] 3. Third Embodiment If the connection resistance of the contact 3c to the SD region 51, i.e., the contact resistance, is high, the parasitic resistance, including the contact resistance and the resistance up to the channel region 52, also increases, and the on-current of the transistor 1 decreases. In order to ensure proper operation, it is necessary to increase the applied voltage, which leads to an increase in power consumption. In particular, when the contact 3c is connected to the lower surface 50b of the SD region 51, controlling the parasitic resistance becomes difficult, and the problem becomes apparent.

[0194] At least some of the above-mentioned problems are addressed by the third embodiment. In the third embodiment, contact resistance and, consequently, parasitic resistance are reduced by devising the contact structure of the SD region 51. This will be explained with reference to Figure 118 and subsequent figures. In addition, the configurations of the first and second embodiments described above may be appropriately combined with the third embodiment to the extent that they do not contradict each other.

[0195] Figures 118 and 119 show an example of the schematic configuration of the semiconductor device 100 according to the third embodiment. The contact 3c is connected between the downward wiring 40 and the SD region 51. The contact 3c includes a semiconductor portion 35. The portion of the contact 3c other than the semiconductor portion 35 may be metal and is referred to as the metal portion 36 and shown in the figure. It can also be said that the contact 3c has a structure in which the semiconductor portion 35 is embedded on top of the metal portion 36 as a base.

[0196] The semiconductor portion 35 contacts the SD region 51. In the example shown in Figure 118, the contact 3c is connected to the lower surface 50b of the SD region 51, and therefore, the semiconductor portion 35 of the contact 3c contacts the lower surface 50b of the SD region 51.

[0197] The contact 3c and the gate electrode 62 may overlap. As shown in Figure 119, when viewed from above (in the negative Z-axis direction), at least a portion of the contact 3c overlaps with the gate electrode 62. By bringing the contact 3c closer to the channel region 52, parasitic resistance can be reduced.

[0198] The SD region 51 may include an LDD (Lightly Doped Drain) region. The LDD region is referred to as the LDD region 51L and is shown in the figure.

[0199] The resistivity of the semiconductor portion 35 of contact 3c is lower than the resistivity of the thin-film semiconductor 50 (of the thin-film semiconductor material 50m). More specifically, for example, the resistivity of the semiconductor portion 35 may be lower than the resistivity of the LDD region 51L of the SD region 51. Examples of materials for the semiconductor portion 35 of contact 3c are ITO (indium tin oxide), IZO (indium zinc oxide), IGO (indium gallium oxide), IBO (indium boron oxide), IMO (indium molybdenum oxide), ITO2 (indium tin oxide), IWO (indium tungsten oxide), and In ２ O ３(Indium oxide), etc. At least one of these may be included in the semiconductor portion 35. The semiconductor portion 35 and the thin film semiconductor 50 may contain different materials from each other, or they may contain a common predetermined material. The composition ratio of the predetermined material in the semiconductor portion 35 may differ from the composition ratio of the predetermined material in the thin film semiconductor 50. An example of a predetermined material is In.

[0200] By connecting the contact 3c, which includes the semiconductor portion 35 as described above, to the SD region 51, contact resistance can be reduced. For example, it is possible to suppress the decrease in the drain-source current of the transistor 1 and the deterioration of the threshold voltage. Increased power consumption can also be suppressed. The performance of the semiconductor device 100 can be improved.

[0201] This also suppresses HCI (Hot Carrier Injection) degradation that can occur in the LDD structure, i.e., localized degradation at the edges of the SD region 51, thereby suppressing a decrease in the reliability of the transistor 1. For example, if the semiconductor device 100 is a display device, it can suppress image quality defects.

[0202] Furthermore, since the interface between the thin-film semiconductor 50 and the gate oxide film 61 is a flat surface, it is possible to suppress the deterioration of the performance and reliability of the transistor 1 compared to the case where there is a step.

[0203] The LDD region 51L is formed, for example, by Vo diffusion from the semiconductor portion 35 of the contact 3c during the annealing process. In this case, the LDD region 51L has a concentration gradient in the direction away from the semiconductor portion 35. This can alleviate the gradient of resistance up to the channel region 52. The range of the LDD region 51L can be controlled by adjusting the size of the semiconductor portion 35. For example, the larger the area of ​​the semiconductor portion 35 (or its diameter in the case of a circular shape) when viewed from above (viewed in the Z-axis direction), the wider the LDD region 51L will be.

[0204] <Modifications> Several modifications based on the technology according to the third embodiment described above are described below.

[0205] Figures 120 to 130 show examples of the schematic configuration of the semiconductor device 100. In the example shown in Figure 120, the area of ​​the contact 3c is larger compared to Figure 119, which was explained earlier. This makes it easier to include (embed) the semiconductor portion 35 in the contact 3c.

[0206] In the examples shown in Figures 121 and 122, the SD region 51 includes a low-resistance layer 511. The low-resistance layer 511 is provided so as to be in contact with the semiconductor portion 35 of the contact 3c. In this example, the low-resistance layer 511 is exposed on the lower surface 50b of the SD region 51, and the contact 3c is connected to this lower surface 50b. The low-resistance layer 511 has a lower resistivity than the surrounding region. Contact resistance can be further reduced. In this configuration as well, the area of ​​the contact 3c can be increased, similar to Figure 120 described earlier. Figure 123 shows the planar layout in that case.

[0207] In the example shown in Figure 124, the entire contact 3c is composed of the semiconductor portion 35.

[0208] In one embodiment, the planar layout of the contact 3c and SD region 51 may be designed so that the contact 3c and gate electrode 62 reliably overlap even if misalignment occurs due to manufacturing variations or the like. In the example shown in Figures 125 to 127, the gate electrode 62 has a rectangular shape extending in the longitudinal direction. When viewed from above (in the negative Z-axis direction), the contact 3c is provided so as to extend in a direction intersecting the longitudinal direction of the gate electrode 62. Even if the position of the contact 3c is slightly misaligned, the contact 3c and gate electrode 62 can be reliably made to overlap.

[0209] The contact 3c can have various shapes. In the example shown in Figure 125, the contact 3c has a triangular shape. In the example shown in Figure 126, the contact 3c has a square shape. In the example shown in Figure 127, the contact 3c has a roughly L-shape (which can also be called a roughly T-shape).

[0210] Overlap between contact 3c and gate electrode 62 is not mandatory. For example, contact 3c connected to one or both of the pair of SD regions 51 does not need to overlap with gate electrode 62. In the examples shown in Figures 128 and 129, contact 3c connected to one of the SD regions 51 does not overlap with gate electrode 62. By moving contact 3c further away from gate electrode 62, the breakdown voltage between the source and drain of transistor 1 can be improved, and parasitic capacitance can be reduced.

[0211] As contact 3c moves away from gate electrode 62, parasitic resistance may increase. To address this, the SD region 51 may include a low-resistance layer 512. The low-resistance layer 512 is provided on the portion of the SD region 51 opposite to contact 3c. In this example, the low-resistance layer 512 is exposed on the upper surface 50a of the SD region 51. The low-resistance layer 512 is made low-resistance by, for example, doping, plasma treatment, etc.

[0212] In the example shown in Figure 130, the contact 3c connected to one of the SD regions 51 is connected between the upper wiring 60 and the SD region 51. This contact 3c does not include the semiconductor portion 35.

[0213] <Example of Manufacturing Method> Figures 131 to 142 show examples of manufacturing methods for semiconductor device 100. The material of the semiconductor part 35 is referred to as the semiconductor part material 35m and is shown in the figure. The material of the metal part 36 is referred to as the metal part material 36m and is shown in the figure.

[0214] As shown in Figure 131, an insulating layer material 4m is formed to cover the lower wiring 40. As shown in Figure 132, the portion of the insulating layer material 4m corresponding to the shape of the contact 3c is processed. The resulting void is referred to as the recess 4r and is shown in the figure. As shown in Figure 133, a metal part material 36m is formed to cover the lower wiring 40 and the insulating layer material 4m. The upper part of the metal part material 36m that is provided to fill the recess 4r has a recess. As shown in Figure 134, the upper part of the metal part material 36m is removed by CMP. The metal part 36 is obtained. In addition, there is a portion on the upper part of the metal part 36 that is lower than the surrounding insulating layer material 4m. This portion is referred to as the recess 35r and is shown in the figure.

[0215] As shown in Figures 135 and 136, a semiconductor material 35m is formed to cover the insulating layer material 4m and the metal part 36, thereby reducing the resistance of the semiconductor material 35m. For example, Vo is generated in the oxide film by doping, plasma treatment, etc., which reduces its resistance. The upper part of the semiconductor material 35m is planarized by CMP. Further Vo generation and resistance reduction may be achieved during CMP. As shown in Figure 137, a contact 3c including the semiconductor part 35 and the metal part 36 is obtained. The insulating layer 4 is also obtained.

[0216] As shown in Figures 138 and 139, the thin-film semiconductor material 50m and the gate oxide film material 61m are deposited in this order. As shown in Figure 140, Vo is diffused from the semiconductor portion 35 into the thin-film semiconductor material 50m by annealing. A thin-film semiconductor 50 is obtained, which includes an SD region 51 containing an LDD region 51L and a channel region 52.

[0217] As shown in Figure 141, the gate electrode material 62m is formed. When the gate electrode material 62m and the gate oxide film material 61m are processed, the gate oxide film 61 and the gate electrode 62 are obtained, as shown in Figure 142. The configuration of Figure 118 described earlier is obtained. Furthermore, when obtaining the configurations related to the various modifications described above, the manufacturing process may be changed as appropriate. For example, a step of forming a low-resistance layer 511 (Figure 121) or a step of forming a low-resistance layer 512 (Figure 128) may be added.

[0218] <Summary> The technology according to the third embodiment described above can be specified, for example, as follows: As described with reference to Figures 118 to 130, the contact 3c includes a semiconductor portion 35 that contacts the SD region 51. The resistivity of the semiconductor portion 35 of the contact 3c may be lower than the resistivity of the thin film semiconductor 50. Contact resistance can be reduced.

[0219] As explained with reference to Figure 118, the composition ratio of a predetermined material (e.g., In) in the semiconductor portion 35 of the contact 3c may differ from the composition ratio of a predetermined material in the thin-film semiconductor 50. The semiconductor portion 35 of the contact 3c and the thin-film semiconductor 50 may contain different materials from each other. Examples of materials for the thin-film semiconductor 50 include ITO, IZO, IGO, IBO, IMO, ITO2, IWO, and In ２ O ３ For example, contact resistance can be reduced by using such materials.

[0220] As explained with reference to Figures 121 and 122, the SD region 51 may include a low-resistance layer 511 provided to contact the semiconductor portion 35 of the contact 3c. This can further reduce the contact resistance.

[0221] As explained with reference to Figures 118 to 130, when viewed from above (in the negative Z-axis direction), at least a portion of the contact 3c may overlap with the gate electrode 62. By bringing the contact 3c closer to the channel region 52, parasitic resistance can be reduced. For example, as explained with reference to Figures 125 to 127, the contact 3c may extend in a direction intersecting the longitudinal direction of the gate electrode 62. Even if misalignment occurs due to manufacturing variations, the contact 3c and the gate electrode 62 can be reliably overlapped.

[0222] The manufacturing method of the semiconductor device 100 is also one of the disclosed technologies. As described with reference to FIGS. 132 to 140 and the like, the manufacturing method includes a step of forming a contact 3c including a semiconductor portion 35 that contacts the SD region 51. There may also be various other steps, and some examples are as described above with reference to FIGS. 131 to 142 and the like.

[0223] Note that the effects described in this disclosure are merely illustrative and are not limited to the disclosed content. There may be other effects.

[0224] 4. Other Modification Examples 4.1 Modification Example 1 As another modification example of the embodiment of the present disclosure, referring to FIGS. 143A to 143G, a modification example regarding the relationship between the normal line LN passing through the center of the light emitting portion (corresponding to the pixel 115 in the previous embodiment), the normal line LN' passing through the center of the lens structure, and the normal line LN'' passing through the center of the wavelength selection portion will be described. FIGS. 143A to 143G are conceptual diagrams for explaining the relationship between the normal line LN passing through the center of the light emitting portion, the normal line LN' passing through the center of the lens member, and the normal line LN'' passing through the center of the wavelength selection portion.

[0225] In the embodiment of the present disclosure, the size of the wavelength selection portion may be appropriately changed according to the light emitted from the pixel 115. Further, when a light absorption layer (black matrix layer) is provided between the wavelength selection portions of adjacent pixels 115, the size of the light absorption layer (black matrix layer) may be appropriately changed according to the light emitted from the pixel 115. Also, the size of the wavelength selection portion may be appropriately changed according to the distance (offset amount) d ０ between the normal line passing through the center of the pixel 115 and the normal line passing through the center of the wavelength selection portion. The planar shape of the wavelength selection portion may be the same as, similar to, or different from the planar shape of the lens member.

[0226] For example, as shown in FIG. 143A, the normal line LN passing through the center of the light emitting portion, the normal line LN'' passing through the center of the wavelength selection portion, and the normal line LN' passing through the center of the lens member may be made to coincide. In other words, the distance (offset amount) D ０The distance (offset amount) d between the normal vector passing through the center of the light-emitting part and the normal vector passing through the center of the wavelength-selecting part. ０ This is equivalent to 0 (zero).

[0227] Furthermore, for example, as shown in Figure 143B, the normal vector LN passing through the center of the light-emitting part and the normal vector LN'' passing through the center of the wavelength-selecting part coincide, but the normal vector LN passing through the center of the light-emitting part and the normal vector LN'' passing through the center of the wavelength-selecting part do not have to coincide with the normal vector LN' passing through the center of the lens member. In other words, D ０ ≠d ０ It may also be equal to 0.

[0228] Furthermore, for example, as shown in Figure 143C, the normal vector LN passing through the center of the light-emitting part, the normal vector LN'' passing through the center of the wavelength-selecting part, and the normal vector LN' passing through the center of the lens member do not coincide, but the normal vector LN'' passing through the center of the wavelength-selecting part and the normal vector LN' passing through the center of the lens member may coincide. In other words, D ０ = d ０ It can also be 0.

[0229] Furthermore, as shown in Figure 143D, for example, the normal vector LN passing through the center of the light-emitting part, the normal vector LN'' passing through the center of the wavelength-selecting part, and the normal vector LN' passing through the center of the lens member do not coincide, and the normal vector LN' passing through the center of the lens member does not coincide with the normal vector LN passing through the center of the surface of the light-emitting part and the normal vector LN'' passing through the center of the wavelength-selecting part. Here, it is preferable that the center of the wavelength-selecting part (shown as a black circle in Figure 143D) is located on a straight line LL connecting the center of the surface of the light-emitting part and the center of the lens member (shown as a black circle in Figure 143D). Specifically, the distance from the center of the surface of the light-emitting part in the thickness direction to the center of the wavelength-selecting part is LL. １ The distance from the center of the wavelength selection area in the thickness direction to the center of the lens material is LL ２ In that case, D ０ >d ０ > 0, and considering manufacturing variations, d ０ : D ０ =LL １ : (LL １ +LL ２ It is preferable that the following conditions be met.

[0230] Furthermore, the stacking relationship between the wavelength tip and the lens member may be reversed. In such a case, for example, as shown in Figure 143E, the normal LN passing through the center of the light-emitting part, the normal LN'' passing through the center of the wavelength-selecting part, and the normal LN' passing through the center of the lens member may be made to coincide. In other words, D ０ = d ０ It may also be equal to 0.

[0231] Furthermore, for example, as shown in Figure 143F, the normal vector LN passing through the center of the light-emitting part, the normal vector LN'' passing through the center of the wavelength-selecting part, and the normal vector LN' passing through the center of the lens member do not coincide, but the normal vector LN'' passing through the center of the wavelength-selecting part and the normal vector LN' passing through the center of the lens member may coincide. In other words, D ０ = d ０ It can also be 0.

[0232] Furthermore, as shown in the conceptual diagram Figure 143G, the normal vector LN passing through the center of the surface of the light-emitting part, the normal vector LN'' passing through the center of the wavelength-selecting part, and the normal vector LN' passing through the center of the lens member do not coincide, and the normal vector LN' passing through the center of the lens member does not coincide with the normal vector LN passing through the center of the surface of the light-emitting part and the normal vector LN'' passing through the center of the wavelength-selecting part. Here, it is preferable that the center of the wavelength-selecting part is located on the straight line LL connecting the center of the surface of the light-emitting part and the center of the lens member. Specifically, the distance from the center of the surface of the light-emitting part in the thickness direction to the center of the wavelength-selecting part (shown as a black circle in Figure 143G) is LL. １ The distance from the center of the wavelength selection area in the thickness direction to the center of the lens member (shown as a black circle in Figure 143G) is LL ２ When that happens, d ０ >D ０ > 0, and considering manufacturing variations, D ０ :d ０ =LL ２ : (LL １ +LL ２ It is preferable that the following conditions be met.

[0233] 4.2 Modification 2 The pixel 115 used in the semiconductor device 100 according to the embodiment of the present disclosure described above can be configured to have a resonator structure (microcavity structure) that resonates the light generated in the light-emitting layer 8. The above resonator structure will be described below with reference to Figures 144 to 150. Figure 144 is a schematic cross-sectional view for illustrating a first example of the resonator structure, Figure 145 is a schematic cross-sectional view for illustrating a second example of the resonator structure, and Figure 146 is a schematic cross-sectional view for illustrating a third example of the resonator structure. Furthermore, Figure 147 is a schematic cross-sectional view for illustrating a fourth example of the resonator structure, and Figure 148 is a schematic cross-sectional view for illustrating a fifth example of the resonator structure. Furthermore, Figure 149 is a schematic cross-sectional view for illustrating a sixth example of the resonator structure, and Figure 150 is a schematic cross-sectional view for illustrating a seventh example of the resonator structure. In the description of these figures, the pixel will be referred to as a sub-pixel 1100.

[0234] (Resonator structure: First example) Figure 144 is a schematic cross-sectional view illustrating the first example of a resonator structure. In the first example, the first electrode 1202 is formed with a common film thickness in each subpixel 1100. The same applies to the second electrode 1206.

[0235] As shown in Figure 144, a reflector 1401 is positioned below the first electrode 1202 of the subpixel 1100, with an optical adjustment layer 1402 in between. A resonator structure is formed between the reflector 1401 and the second electrode 1206, which resonates the light generated by the organic layer (corresponding to the light-emitting layer 8 in the previous embodiment) 1204.

[0236] The reflector 1401 is formed with a common film thickness for each subpixel 1100. The film thickness of the optical adjustment layer 1402 differs depending on the color that the subpixel 1100 is to display. By having optical adjustment layers 1402R, 1402G, and 1402B with different film thicknesses, it is possible to set the optical distance that produces the optimal resonance for the wavelength of light corresponding to the color to be displayed.

[0237] In the example shown in Figure 144, the upper surfaces of the reflectors 1401 for subpixels 1100R, 1100G, and 1100B are aligned. As described above, the thickness of the optical adjustment layer 1402 differs depending on the color that the subpixel 1100 should display, so the position of the upper surface of the second electrode 1206 differs depending on the type of subpixel 1100R, 1100G, and 1100B.

[0238] The reflector 1401 can be formed using, for example, a metal such as aluminum (Al), silver (Ag), or copper (Cu), or an alloy mainly composed of these metals.

[0239] The optical adjustment layer 1402 can be constructed using inorganic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiOxNy), or organic resin materials such as acrylic resin or polyimide resin. The optical adjustment layer 1402 may be a single layer or a laminated film of multiple materials. Furthermore, the number of layers may vary depending on the type of subpixel 1100.

[0240] The first electrode 1202 can be formed using, for example, a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO).

[0241] The second electrode 1206 preferably functions as a semi-transparent reflective film. The second electrode 1206 can be formed using magnesium (Mg), silver (Ag), or a magnesium-silver alloy (MgAg) mainly composed of these, or an alloy containing alkali metals or alkaline earth metals.

[0242] (Resonator structure: Second example) Figure 145 is a schematic cross-sectional view illustrating a second example of the resonator structure. In this second example as well, the first electrode 1202 and the second electrode 1206 are formed with a common film thickness in each subpixel 1100.

[0243] In the second example as well, a reflector 1401 is placed beneath the first electrode 1202 of the subpixel 1100, with an optical adjustment layer 1402 in between. A resonator structure is formed between the reflector 1401 and the second electrode 1206 to resonate the light generated by the organic layer 1204. Similar to the first example, the reflector 1401 is formed with a common film thickness for each subpixel 1100, while the film thickness of the optical adjustment layer 1402 differs according to the color that the subpixel 1100 should display.

[0244] In the first example shown in Figure 144, the upper surfaces of the reflectors 1401 for subpixels 1100R, 1100G, and 1100B were aligned, while the position of the upper surface of the second electrode 1206 differed depending on the type of subpixel 1100R, 1100G, and 1100B.

[0245] In contrast, in the second example shown in Figure 145, the upper surface of the second electrode 1206 is arranged to align with the subpixels 1100R, 1100G, and 1100B. In order to align the upper surfaces of the second electrode 1206, the upper surface of the reflector 1401 is arranged differently for the subpixels 1100R, 1100G, and 1100B, depending on the type of subpixel. As a result, the lower surface of the reflector 1401 has a stepped shape depending on the type of subpixel 1100R, 1100G, and 1100B.

[0246] The materials and other components constituting the reflector 1401, the optical adjustment layer 1402, the first electrode 1202, and the second electrode 1206 are the same as those described in the first example, so their explanation will be omitted.

[0247] (Resonator structure: Third example) Figure 146 is a schematic cross-sectional view illustrating a third example of the resonator structure. In this third example as well, the first electrode 1202 and the second electrode 1206 are formed with a common film thickness in each subpixel 1100.

[0248] In the third example, the reflector 1401 is positioned below the first electrode 1202 of the subpixel 1100, with the optical adjustment layer 1402 in between. A resonator structure is formed between the reflector 1401 and the second electrode 1206 to resonate the light generated by the organic layer 1204. Similar to the first and second examples, the thickness of the optical adjustment layer 1402 varies depending on the color that the subpixel 1100 should display. And, similar to the second example, the upper surface of the second electrode 1206 is positioned so that it aligns with the subpixels 1100R, 1100G, and 1100B.

[0249] In the second example shown in Figure 145, the lower surface of the reflector 1401 had a stepped shape corresponding to the type of sub-pixel 1100R, 1100G, and 1100B in order to align the upper surface of the second electrode 1206.

[0250] In contrast, in the third example shown in Figure 146, the film thickness of the reflector 1401 is set to differ depending on the type of sub-pixel 1100R, 1100G, and 1100B. More specifically, the film thickness is set so that the lower surfaces of the reflectors 1401R, 1401G, and 1401B are aligned.

[0251] The materials and other components constituting the reflector 1401, the optical adjustment layer 1402, the first electrode 1202, and the second electrode 1206 are the same as those described in the first example, so their explanation will be omitted.

[0252] (Resonator structure: 4th example) Figure 147 is a schematic cross-sectional view illustrating the 4th example of a resonator structure.

[0253] In the first example shown in Figure 144, the first electrode 1202 and the second electrode 1206 of the subpixel 1100 are formed with a common film thickness. A reflector 1401 is placed below the first electrode 1202 of the subpixel 1100, with an optical adjustment layer 1402 in between.

[0254] In contrast, in the fourth example shown in Figure 147, the optical adjustment layer 1402 is omitted, and the film thickness of the first electrode 1202 is set to differ depending on the type of subpixel 1100R, 1100G, and 1100B.

[0255] The reflector 1401 is formed with a common film thickness for each subpixel 1100. The film thickness of the first electrode 1202 differs depending on the color that the subpixel 1100 is to display. By having the first electrodes 1202R, 1202G, and 1202B have different film thicknesses, it is possible to set the optical distance that produces the optimal resonance for the wavelength of light corresponding to the color to be displayed.

[0256] The materials and other components constituting the reflector 1401, the first electrode 1202, and the second electrode 1206 are the same as those described in the first example, so their explanation will be omitted.

[0257] (Resonator structure: Fifth example) Figure 148 is a schematic cross-sectional view illustrating the fifth example of a resonator structure.

[0258] In the first example shown in Figure 144, the first electrode 1202 and the second electrode 1206 are formed with a common film thickness in each subpixel 1100. A reflector 1401 is placed below the first electrode 1202 of the subpixel 1100, with an optical adjustment layer 1402 in between.

[0259] In contrast, in the fifth example shown in Figure 148, the optical adjustment layer 1402 was omitted, and instead, an oxide film 1404 was formed on the surface of the reflector 1401. The thickness of the oxide film 1404 was set to differ depending on the type of subpixel 1100R, 1100G, and 1100B.

[0260] The thickness of the oxide film 1404 varies depending on the color that the subpixel 1100 is to display. By having oxide films 1404R, 1404G, and 1404B with different thicknesses, it is possible to set the optical distance that produces the optimal resonance for the wavelength of light corresponding to the color to be displayed.

[0261] The oxide film 1404 is a film obtained by oxidizing the surface of the reflector 1401, and is composed of, for example, aluminum oxide, tantalum oxide, titanium oxide, magnesium oxide, zirconium oxide, etc. The oxide film 1404 functions as an insulating film for adjusting the optical path length (optical distance) between the reflector 1401 and the second electrode 1206.

[0262] The oxide film 1404, which has a different thickness depending on the type of subpixel 1100R, 1100G, and 1100B, can be formed, for example, as follows.

[0263] First, the container is filled with electrolyte, and the substrate on which the reflector 1401 is formed is immersed in the electrolyte. Then, electrodes are positioned opposite the reflector 1401.

[0264] Then, a positive voltage is applied to the reflector 1401 with the electrode as the reference, and the reflector 1401 is anodized. The thickness of the oxide film formed by anodization is proportional to the voltage value applied to the electrode. Therefore, anodization is performed on each of the reflectors 1401R, 1401G, and 1401B with a voltage corresponding to the type of sub-pixel 1100R, 1100G, and 1100B applied. This makes it possible to form oxide films 1404 of different thicknesses all at once.

[0265] The materials and other components constituting the reflector 1401, the first electrode 1202, and the second electrode 1206 are the same as those described in the first example, so their explanation will be omitted.

[0266] (Resonator Structure: Sixth Example) Figure 149 is a schematic cross-sectional view illustrating the sixth example of a resonator structure. In the sixth example, the subpixel 1100 is constructed by stacking a first electrode 1202, an organic layer 1204, and a second electrode 1206. However, in the sixth example, the first electrode 1202 is formed to serve both as an electrode and a reflector. The first electrode (and reflector) 1202 is made of a material having optical constants selected according to the type of subpixel 1100R, 1100G, and 1100B. By different phase shifts caused by the first electrode (and reflector) 1202, it is possible to set an optical distance that produces optimal resonance for the wavelength of light corresponding to the color to be displayed.

[0267] The first electrode (and reflector) 1202 can be made from a single metal such as aluminum (Al), silver (Ag), gold (Au), or copper (Cu), or from an alloy mainly composed of these metals. For example, the first electrode (and reflector) 1202R of the subpixel 1100R can be made of copper (Cu), and the first electrode (and reflector) 1202G of the subpixel 1100G and the first electrode (and reflector) 1202B of the subpixel 1100B can be made of aluminum.

[0268] The materials and other components constituting the second electrode 1206 are the same as those described in the first example, so their explanation will be omitted.

[0269] (Resonator Structure: Seventh Example) Figure 150 is a schematic cross-sectional view illustrating the seventh example of the resonator structure. The seventh example basically applies the sixth example to subpixels 1100R and 1100G, and the first example to subpixel 1100B. In this configuration as well, it is possible to set the optical distance that produces optimal resonance for the wavelength of light corresponding to the color to be displayed.

[0270] The first electrodes (which also serve as reflectors) 1202R and 1202G used in the sub-pixels 1100R and 1100G can be made from elemental metals such as aluminum (Al), silver (Ag), gold (Au), and copper (Cu), or alloys in which these metals are the main components.

[0271] The materials and other components constituting the reflector 1401B, optical adjustment layer 1402B, and first electrode 1202B used in the subpixel 1100B are the same as those described in the first example, so their explanation will be omitted.

[0272] 5. Examples of Application For example, the technology relating to this disclosure may be applied to the display units of various electronic devices. Therefore, examples of electronic devices to which this technology can be applied will be described below.

[0273] (Specific Example 1) Figure 151A is a front view showing an example of the external appearance of the digital still camera 5000, and Figure 151B is a rear view showing an example of the external appearance of the digital still camera 5000. This digital still camera 5000 is a single-lens reflex type with interchangeable lenses, and has an interchangeable shooting lens unit (interchangeable lens) 5120 located approximately in the center of the front of the camera body 5110, and a grip portion 5130 for the photographer to hold on the left side of the front.

[0274] A monitor 5140 is provided on the back of the camera body 5110, slightly to the left of the center. An electronic viewfinder (eyepiece) 5150 is provided above the monitor 5140. The photographer can determine the composition by looking through the electronic viewfinder 5150 and visually confirming the light image of the subject guided by the shooting lens unit 5120. The semiconductor device 100 (display device) according to the embodiment of this disclosure can be used as the monitor 5140 and the electronic viewfinder 5150.

[0275] (Specific Example 2) Figure 152 is an external view of a head-mounted display 6000. The head-mounted display 6000 has, for example, an eyeglass-shaped display unit 6110 and ear hooks 6120 on both sides for attachment to the user's head. In this head-mounted display 6000, the semiconductor device 100 (display device) according to the embodiment of this disclosure can be used as the display unit 6110.

[0276] (Specific Example 3) Figure 153 is an external view of the see-through head-mounted display 6340. The see-through head-mounted display 6340 consists of a main body 6320, an arm 6330, and a lens barrel 6310.

[0277] The main body 6320 is connected to the arm 6330 and the eyeglasses 6300. Specifically, the long end of the main body 6320 is connected to the arm 6330, and one side of the main body 6320 is connected to the eyeglasses 6300 via a connecting member. The main body 6320 may also be directly attached to the head of a person.

[0278] The main body 6320 houses a control board for controlling the operation of the see-through head-mounted display 6340, as well as a display unit. The arm 6330 connects the main body 6320 to the lens barrel 6310 and supports the lens barrel 6310. Specifically, the arm 6330 is connected to the end of the main body 6320 and the end of the lens barrel 6310, respectively, and fixes the lens barrel 6310 in place. The arm 6330 also houses signal lines for communicating image-related data provided from the main body 6320 to the lens barrel 6310.

[0279] The lens barrel 6310 projects image light, provided from the main body 6320 via the arm 6330, through an eyepiece lens towards the eyes of the user wearing the see-through head-mounted display 6340. In this see-through head-mounted display 6340, the display unit of the main body 6320 can use the semiconductor device 100 (display device) according to the embodiment of this disclosure.

[0280] (Specific Example 4) Figure 154 shows an example of the appearance of a television device 7100. This television device 7100 has, for example, a video display screen section 7110 including a front panel 7120 and a filter glass 7130, and this video display screen section 7110 is composed of a semiconductor device 100 (display device) according to the embodiment of this disclosure.

[0281] (Specific Example 5) Figure 155 shows an example of the appearance of a smartphone 8000. The smartphone 8000 has a display unit 8020 that displays various information, and an operation unit consisting of buttons, etc. that accept user input. The display unit 8020 may be a semiconductor device 100 (display device) according to this embodiment.

[0282] (Specific Example 6) Figures 156A and 156B show the internal configuration of an automobile having a semiconductor device 100 (display device) according to an embodiment of this disclosure as a display device. More specifically, Figure 156A shows the interior of the automobile from the rear to the front, and Figure 156B shows the interior of the automobile from the diagonally rear to the diagonally front.

[0283] The automobile shown in Figures 156A and 156B includes a center display 9110, a console display 9120, a head-up display 9130, a digital rear mirror 9140, a steering wheel display 9150, and a rear entertainment display 9160. Some or all of these displays can be fitted with the semiconductor device 100 (display device) according to the embodiment of this disclosure.

[0284] The center display 9110 is positioned on the center console 9070, facing the driver's seat 9010 and the passenger seat 9020. Figures 156A and 156B show an example of a horizontally elongated center display 9110 extending from the driver's seat 9010 to the passenger seat 9020, but the screen size and placement of the center display 9110 are arbitrary. The center display 9110 can display information detected by various sensors (not shown). As a specific example, the center display 9110 can display images captured by an image sensor, distance images to obstacles in front of or to the side of the vehicle measured by a ToF (Time of Flight) sensor, and the body temperature of passengers detected by an infrared sensor. The center display 9110 can be used to display, for example, at least one of safety-related information, operation-related information, life logs, health-related information, authentication / identification-related information, and entertainment-related information.

[0285] Safety-related information includes information such as drowsiness detection, distraction detection, detection of mischief by a passenger, seatbelt fastening status, and detection of an unattended occupant. This information is detected, for example, by a sensor (not shown) placed on top of the back of the center display 9110. Operation-related information is detected by sensing occupant gestures using sensors. The detected gestures may include the operation of various equipment in the vehicle. For example, the sensor detects the operation of air conditioning equipment, navigation systems, AV (Audio / Visual) systems, lighting systems, etc. Lifelogs include lifelogs of all occupants. For example, lifelogs include records of each occupant's actions while riding in the vehicle. By acquiring and saving lifelogs, it is possible to confirm the state of the occupants at the time of an accident. Health-related information is detected by sensing the occupant's body temperature using a temperature sensor and inferring the occupant's health status based on the detected body temperature. Alternatively, the occupant's face may be captured using an image sensor, and the occupant's health status may be inferred from the captured facial expression. Furthermore, the system may engage in automated voice conversations with the occupants and infer their health status based on their responses. Authentication / identification-related information includes keyless entry functions that use sensors for facial recognition, and functions that automatically adjust seat height and position based on facial recognition. Entertainment-related information includes functions that use sensors to detect information on how the occupants operate the AV equipment, and functions that use sensors to recognize the occupants' faces and provide content suitable for the occupants through the AV equipment.

[0286] The console display 9120 can be used, for example, to display life log information. The console display 9120 is located near the shift lever 9080 on the center console 9070 between the driver's seat 9010 and the passenger seat 9020. The console display 9120 can also display information detected by various sensors (not shown). In addition, the console display 9120 may display images of the area around the vehicle captured by an image sensor, or it may display distance images to obstacles around the vehicle.

[0287] The head-up display 9130 is virtually displayed behind the windshield 9040 in front of the driver's seat 9010. The head-up display 9130 can be used to display, for example, at least one of safety-related information, operation-related information, life logs, health-related information, authentication / identification-related information, and entertainment-related information. Because the head-up display 9130 is often virtually positioned in front of the driver's seat 9010, it is suitable for displaying information directly related to the operation of the vehicle, such as the vehicle's speed and fuel (battery) level.

[0288] The digital rearview mirror 9140 can not only display the area behind the vehicle but also show the condition of the passengers in the rear seat. By placing a sensor (not shown) on top of the back of the digital rearview mirror 9140, it can be used, for example, to display life log information.

[0289] The steering wheel display 9150 is positioned near the center of the vehicle's steering wheel 9060. The steering wheel display 9150 can be used to display, for example, at least one of safety-related information, operation-related information, life logs, health-related information, authentication / identification-related information, and entertainment-related information. In particular, because the steering wheel display 9150 is located near the driver's hands, it is suitable for displaying life log information such as the driver's body temperature, or information related to the operation of AV equipment, air conditioning equipment, etc.

[0290] The rear entertainment display 9160 is mounted on the back of the driver's seat 9010 and the passenger seat 9020, and is intended for viewing by rear-seat passengers. The rear entertainment display 9160 can be used to display at least one of the following: safety-related information, operation-related information, life logs, health-related information, authentication / identification-related information, and entertainment-related information. In particular, because the rear entertainment display 9160 is in front of the rear-seat passengers, it displays information relevant to the rear-seat passengers. For example, it may display information related to the operation of AV equipment or air conditioning equipment, or it may display the results of measurements of the rear-seat passengers' body temperature etc., taken by a temperature sensor (not shown).

[0291] While embodiments of this disclosure have been described above, the technical scope of this disclosure is not limited to the embodiments described above, and various modifications are possible without departing from the spirit of this disclosure. Furthermore, components from different embodiments and modifications may be combined as appropriate.

[0292] Furthermore, this technology can also take the following configurations: (1) A semiconductor device comprising: a semiconductor substrate; a thin film semiconductor provided above the semiconductor substrate and including an SD region (source-drain region) and a channel region; and an impurity film provided so as to cover at least a part of the SD region of the thin film semiconductor, wherein the SD region and the impurity film contain the same impurity, and the impurity film includes a lower impurity film provided so as to cover the lower surface of the SD region. (2) The semiconductor device according to (1), wherein the thin film semiconductor is an oxide thin film semiconductor. (3) The semiconductor device according to (1) or (2), wherein the impurity contains at least one of B and P. (4) The semiconductor device according to any one of (1) to (3), further comprising a gate electrode provided so as to face the upper or lower surface of the channel region. (5) The semiconductor device according to any one of (1) to (4), wherein the impurity film is in contact with the SD region. (6) The semiconductor device according to any one of (1) to (5), wherein the impurity film includes an upper impurity film provided so as to cover the upper surface of the SD region. (7) A semiconductor device according to any one of (1) to (6), comprising a contact connected to the SD region. (8) A semiconductor device according to (7), wherein the contact is connected to the lower surface of the SD region. (9) A semiconductor device according to any one of (1) to (8), comprising a gate electrode provided facing the upper surface of the channel region, wherein the impurity film includes an upper impurity film provided to cover the upper surface of the SD region, the upper impurity film is provided to cover the side and upper surfaces of the gate electrode, and the lower impurity film is provided not to cover the lower surface of the channel region. (10) A semiconductor device according to any one of (1) to (8), comprising a gate electrode provided facing the upper surface of the channel region, wherein the impurity film includes an upper impurity film provided to cover the upper surface of the SD region, the upper impurity film is provided to cover the side surfaces of the gate electrode but not the upper surface of the gate electrode, and the lower impurity film is provided not to cover the lower surface of the channel region.(11) A semiconductor device according to any one of (1) to (8), comprising: (11) A gate electrode provided facing the upper surface of the channel region; and a gate oxide film provided between the gate electrode and the channel region, wherein the impurity film includes an upper impurity film provided to cover the upper surface of the SD region, the upper impurity film is provided so as not to cover the gate oxide film and the gate electrode, and the lower impurity film is provided so as not to cover the lower surface of the channel region. (12) A semiconductor device according to any one of (1) to (8), comprising: a gate electrode provided facing the lower surface of the channel region; the impurity film includes an upper impurity film provided to cover the upper surface of the SD region, the upper impurity film is provided so as not to cover the upper surface of the channel region, and the lower impurity film is provided so as to cover the gate electrode. (13) A semiconductor device according to any one of (1) to (12), wherein the SD region is a pair of SD regions located on opposite sides of the channel region, and the impurity film has a symmetrical layout across the channel region. (14) The SD region is a pair of SD regions located on opposite sides of the channel region, and the impurity film has an asymmetric layout across the channel region, according to any one of (1) to (12). (15) The semiconductor device according to any one of (1) to (14), comprising a contact connected to the SD region, wherein the SD region is a pair of SD regions located on opposite sides of the channel region, the contact is a pair of contacts corresponding to the pair of SD regions, and the pair of contacts has a symmetric layout across the channel region. (16) The semiconductor device according to any one of (1) to (14), comprising a contact connected to the SD region, wherein the SD region is a pair of SD regions located on opposite sides of the channel region, the contact is a pair of contacts corresponding to the pair of SD regions, and the pair of contacts has an asymmetric layout across the channel region.(17) A semiconductor device according to any one of (1) to (16), comprising a gate electrode provided facing the upper surface of the channel region, wherein the impurity film comprises only the lower impurity film. (18) A semiconductor device according to any one of (1) to (16), comprising a gate electrode provided facing the lower surface of the channel region, wherein the impurity film comprises only the lower impurity film. (19) A semiconductor device according to any one of (1) to (18), wherein, when viewed from above, the impurity film overlaps with the entire SD region. (20) A semiconductor device according to any one of (1) to (18), comprising a contact connected to the SD region, wherein, when viewed from above, the impurity film overlaps with a part of the SD region such that the contact is included inside. (21) A semiconductor device according to any one of (1) to (20), comprising a wiring layer provided above the semiconductor substrate, wherein the wiring layer comprises the thin film semiconductor. (22) A semiconductor device according to any one of (1) to (21), wherein a transistor other than the transistor including the SD region and the channel region of the thin film semiconductor is formed on the semiconductor substrate. (23) A semiconductor device according to any one of (1) to (22), comprising: an emitting layer provided above the thin film semiconductor; and a light-shielding layer provided between the thin film semiconductor and the emitting layer. (24) A semiconductor device according to any one of (1) to (23), comprising: an oxygen supply layer provided so as to be in contact with the channel region. (25) A semiconductor device according to (24), wherein the oxygen supply layer contains more oxygen than the surrounding region. (26) A semiconductor device according to any one of (1) to (25), comprising: a thin film layer including a first thin film semiconductor which is the thin film semiconductor; and a second thin film semiconductor provided spaced apart from the first thin film semiconductor; and vias connected to the second thin film semiconductor. (27) A semiconductor device according to (26), wherein the second thin film semiconductor is made low-resistance. (28) The semiconductor device according to (27), wherein the reduction in resistance includes the addition of n+.(29) A semiconductor device according to any one of (26) to (28), comprising an upper wiring located above the thin film layer, wherein the via is connected between the upper wiring and the second thin film semiconductor. (30) A semiconductor device according to any one of (26) to (29), comprising a lower wiring located below the thin film layer, wherein the via is connected between the lower wiring and the second thin film semiconductor. (31) A semiconductor device according to any one of (26) to (28), comprising an upper wiring located above the thin film layer and a lower wiring located below the thin film layer, wherein the via includes an upper via connected between the upper wiring and the second thin film semiconductor, and a lower via connected between the lower wiring and the second thin film semiconductor, wherein the upper wiring and the lower wiring are electrically connected via the via and the second thin film semiconductor. (32) A semiconductor device according to any one of (26) to (31), wherein a plurality of the vias are connected to one second thin film semiconductor. (33) The semiconductor device according to any one of (26) to (31), wherein one via is connected to one of the second thin film semiconductors. (34) The semiconductor device according to any one of (26) to (33), wherein, when viewed from the plan, the second thin film semiconductor is arranged to surround the first thin film semiconductor. (35) The semiconductor device according to any one of (26) to (34), further comprising an additional film provided in contact with the second thin film semiconductor, wherein the additional film includes at least one of an oxygen blocking film and a hydrogen supply film. (36) The oxygen blocking film is made of SiN and Al. ２ O ３A semiconductor device according to (35), comprising at least one of the following: (37) The semiconductor device according to (35) or (36), wherein the hydrogen supply film comprises SiCN. (38) The semiconductor device according to any one of (26) to (37), wherein the via comprises a metal film covering the top and side surfaces of the second thin film semiconductor. (39) The semiconductor device according to (38), wherein the metal film comprises at least one of Ti, Ta, TiN, TaN, Cu, W, and Al. (40) The semiconductor device according to any one of (26) to (39), wherein the thin film layer comprises a third thin film semiconductor spaced apart from the first thin film semiconductor and the second thin film semiconductor, the second thin film semiconductor being made low-resistance while the third thin film semiconductor is not made low-resistance. (41) The semiconductor device according to (40), wherein the thin film layer comprises a plurality of the third thin film semiconductors arranged periodically. (42) A semiconductor device according to any one of (1) to (41), comprising a contact connected to the SD region, wherein the contact includes a semiconductor portion that contacts the SD region. (43) A semiconductor device according to (42), wherein the resistivity of the semiconductor portion of the contact is lower than the resistivity of the thin film semiconductor. (44) A semiconductor device according to (42) or (43), wherein the composition ratio of a predetermined material in the semiconductor portion of the contact is different from the composition ratio of the predetermined material in the thin film semiconductor. (45) A semiconductor device according to (44), wherein the predetermined material includes In. (46) A semiconductor device according to any one of (42) to (45), wherein the semiconductor portion of the contact and the thin film semiconductor include different materials. (47) The semiconductor portion includes ITO, IZO, IGO, IBO, IMO, ITO2, IWO, and In ２ O ３A semiconductor device according to any one of (42) to (46), comprising at least one of the following: (48) A semiconductor device according to any one of (42) to (47), wherein the SD region includes a low-resistance layer provided to contact the semiconductor portion of the contact. (49) A semiconductor device according to any one of (42) to (48), comprising a gate electrode provided to face the upper or lower surface of the channel region, wherein, when viewed from above, at least a portion of the contact overlaps with the gate electrode. (50) A semiconductor device according to (49), wherein, when viewed from above, the contact extends in a direction intersecting the longitudinal direction of the gate electrode. (51) A display device comprising: a semiconductor substrate; a thin film semiconductor provided above the semiconductor substrate and including an SD region (source-drain region) and a channel region; and an impurity film provided to cover at least a portion of the SD region of the thin film semiconductor, wherein the SD region and the impurity film contain the same impurity, and the impurity film includes a lower impurity film provided to cover the lower surface of the SD region. (52) A method for manufacturing a semiconductor device according to any one of (1) to (25), comprising the step of diffusing impurities contained in the impurity film into the thin film semiconductor. (53) A method for manufacturing a semiconductor device according to any one of (26) to (41), comprising the step of processing the thin film semiconductor material to reduce its resistance so that a second thin film semiconductor separated from the first thin film semiconductor is obtained. (54) A method for manufacturing a semiconductor device according to any one of (42) to (50), comprising the step of forming the contact including the semiconductor portion that contacts the SD region.

[0293] 100 Semiconductor device 1 Transistor 1-1 Transistor 1-2 Transistor 2 Semiconductor substrate 3 Wiring layer 3c Contact 3v Via 31v Lower via 32v Upper via 321v Metal film 322v Extended portion 35 Semiconductor portion 36 Metal portion 4 Insulating layer 40 Lower wiring 41 Additional film 41c Side 5 Thin film layer 50 Thin film semiconductor 50-1 Thin film semiconductor 50-2 Thin film semiconductor 50-3 Thin film semiconductor 50a Top surface 50b Bottom surface 51 SD region 51L LDD region 511 Low resistance layer 512 Low resistance layer 52 Channel region 53 High density region 6 Insulating layer 60 Upper wiring 61 Gate oxide film 611 First portion 612 Second portion 61a Oxide film 61b Oxide film 62 Gate electrode 62a Top surface 62b Bottom surface 62c Side surface 7 Impurity film 7-1 Lower impurity film 7-2 Upper impurity film 8 Light-emitting layer 9 Oxygen supply layer Cel Auxiliary capacitance Cs Holding capacitance DS Power supply line WS Scanning line

Claims

1. A semiconductor device comprising: a semiconductor substrate; a thin film semiconductor provided above the semiconductor substrate and including an SD region (source-drain region) and a channel region; and an impurity film provided so as to cover at least a portion of the SD region of the thin film semiconductor, wherein the SD region and the impurity film contain the same impurity, and the impurity film includes a lower impurity film provided so as to cover the lower surface of the SD region.

2. The semiconductor device according to claim 1, wherein the thin film semiconductor is an oxide thin film semiconductor.

3. The semiconductor device according to claim 1, wherein the impurity comprises at least one of B (boron) and P (phosphorus).

4. The semiconductor device according to claim 1, wherein the impurity film is in contact with the SD region.

5. The semiconductor device according to claim 1, wherein the impurity film includes an upper impurity film provided so as to cover the upper surface of the SD region.

6. The semiconductor device according to claim 1, comprising a contact connected to the lower surface of the SD region.

7. The semiconductor device according to claim 1, wherein, when viewed from above, the impurity film overlaps with the entire SD region.

8. The semiconductor device according to claim 1, further comprising a wiring layer provided above the semiconductor substrate, wherein the wiring layer includes the thin-film semiconductor.

9. The semiconductor device according to claim 1, wherein a transistor other than the transistor including the SD region and the channel region of the thin-film semiconductor is formed on the semiconductor substrate.

10. The semiconductor device according to claim 1, comprising: an emissive layer provided above the thin film semiconductor; and a light-shielding layer provided between the thin film semiconductor and the emissive layer.

11. The semiconductor device according to claim 1, further comprising an oxygen supply layer provided so as to be in contact with the channel region, wherein the oxygen supply layer contains more oxygen than the surrounding region.

12. The semiconductor device according to claim 1, comprising: a thin film layer including a first thin film semiconductor which is the thin film semiconductor, and a second thin film semiconductor provided spaced apart from the first thin film semiconductor; and vias connected to the second thin film semiconductor, wherein the second thin film semiconductor is made low-resistance.

13. The semiconductor device according to claim 12, wherein, when viewed from above, the second thin-film semiconductor is arranged to surround the first thin-film semiconductor.

14. The semiconductor device according to claim 12, further comprising an additional film provided in contact with the second thin-film semiconductor, wherein the additional film includes at least one of an oxygen-blocking film and a hydrogen-supplying film.

15. The semiconductor device according to claim 12, wherein the thin film layer includes a third thin film semiconductor provided spaced apart from the first thin film semiconductor and the second thin film semiconductor, the second thin film semiconductor is made low-resistance, while the third thin film semiconductor is not made low-resistance.

16. The semiconductor device according to claim 1, comprising a contact connected to the SD region, wherein the contact includes a semiconductor portion that contacts the SD region, and the resistivity of the semiconductor portion of the contact is lower than the resistivity of the thin film semiconductor.

17. The semiconductor device according to claim 16, wherein the SD region includes a low-resistance layer provided so as to be in contact with the semiconductor portion of the contact.

18. The semiconductor device according to claim 1, wherein the SD region is a pair of SD regions located on opposite sides of the channel region.

19. A display device comprising: a semiconductor substrate; a thin film semiconductor provided above the semiconductor substrate and including an SD region (source-drain region) and a channel region; and an impurity film provided so as to cover at least a portion of the SD region of the thin film semiconductor, wherein the SD region and the impurity film contain the same impurity, and the impurity film includes a lower impurity film provided so as to cover the lower surface of the SD region.

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