Semiconductor storage device

Abstract

SRAM cells (C0, C1) are arranged adjacent to each other in a first direction. The SRAM cell (C0) is provided with a first bit line that extends in a second direction and is formed in a back surface wiring layer. The SRAM cell (C1) is provided with a second bit line that extends in the second direction and is formed in a metal wiring layer. The first and second bit lines are formed across the cell boundary between the SRAM cell (C0) and the SRAM cell (C1).

Description

Semiconductor memory device

[0001] This disclosure relates to the layout structure of a SRAM (Static Random Access Memory) cell (hereinafter, also simply referred to as a cell) using a CFET (Complementary FET).

[0002] SRAM is widely used in semiconductor integrated circuits.

[0003] In addition, transistors, which are basic components of LSIs, have achieved improved integration density, reduced operating voltage, and improved operating speed through gate length reduction (scaling). However, in recent years, the off-current due to excessive scaling and the resulting significant increase in power consumption have become problems. To solve this problem, three-dimensional structure transistors with a transistor structure changed from a conventional planar type to a three-dimensional type have been actively studied. As an example of a three-dimensional structure transistor, there is a nanosheet FET (Field Effect Transistor).

[0004] Patent Documents 1 and 2 disclose a SRAM composed of CFETs, in which a memory cell in which a pair of bit lines is connected via a wiring on the front surface side and a memory cell in which a pair of bit lines is connected via a wiring on the back surface side are mixed.

[0005] U.S. Patent Application Publication No. 2024 / 0251541, U.S. Patent Application Publication No. 2024 / 0302980

[0006] With the miniaturization of semiconductor integrated circuit devices, the wiring resistance has increased, resulting in a decrease in the operating speed of semiconductor integrated circuit devices. The techniques of Patent Documents 1 and 2 cannot cope with this.

[0007] An object of this disclosure is to improve the operating speed of a semiconductor memory device in the layout structure of a SRAM cell using a CFET.

[0008] In aspects of the present disclosure, a semiconductor memory device comprising a plurality of SRAM cells, the plurality of SRAM cells comprising first and second SRAM cells arranged adjacent to each other in a first direction, the first and second SRAM cells being connected to a first word line extending in the first direction, the first SRAM cell comprising the channel, source and drain of a first transistor of a first conductivity type, the channel comprising a first active region comprising a first nanosheet extending in a second direction perpendicular to the first direction, and a second transistor comprising the channel, source and drain of a second transistor of a second conductivity type different from the first conductivity type, formed above the first active region in the depth direction and overlapping with the first active region in a plan view, the channel comprising a second active region comprising a second nanosheet extending in the second direction, and a first bit line extending in the second direction, the second SRAM cell comprising the first a A semiconductor memory device comprising: a third active region formed in the same layer as the active region and constituting the channel, source, and drain of the third transistor of the first conductivity type, wherein the channel includes a third nanosheet extending in the second direction; a fourth active region formed in the same layer as the second active region in the depth direction and overlapping with the third active region in a plan view, constituting the channel, source, and drain of the fourth transistor of the second conductivity type, wherein the channel includes a fourth nanosheet extending in the second direction; and a second bit line extending in the second direction, wherein the first bit line is formed in the back wiring layer on the back side of the first and third active regions, and the second bit line is formed in the metal wiring layer above the second and fourth active regions, and the first and second bit lines are formed across the cell boundary between the first SRAM cell and the second SRAM cell.

[0009] According to this disclosure, in first and second SRAM cells arranged adjacent to each other in a first direction, a first bit line is formed in the back wiring layer and a second bit line is formed in the metal wiring layer. This allows the first and second bit lines to be arranged across the first and second SRAM cells. As a result, the wiring width of the bit lines can be increased and the wiring resistance of the bit lines can be suppressed, thereby improving the operating speed of the semiconductor memory device.

[0010] According to this disclosure, the operating speed of a semiconductor memory device can be improved in the layout structure of an SRAM cell using a CFET.

[0011] A plan view showing an example of the layout structure of an SRAM cell according to the first embodiment. A cross-sectional view showing an example of the layout structure of an SRAM cell according to the first embodiment. A cross-sectional view showing an example of the layout structure of an SRAM cell according to the first embodiment. A cross-sectional view showing an example of the layout structure of an SRAM cell according to the first embodiment. A circuit diagram showing the configuration of an SRAM cell according to the first embodiment. A plan view showing an example of the layout of a circuit block provided in a semiconductor memory device according to the first embodiment. A plan view showing another example of the layout structure of an SRAM cell according to the first embodiment. A plan view showing an example of the layout structure of an SRAM cell according to the second embodiment. A circuit diagram showing the configuration of an SRAM cell according to the second embodiment.

[0012] The embodiments will be described below with reference to the drawings. In the following embodiments, the semiconductor memory device comprises a plurality of SRAM cells. At least some of these plurality of SRAM cells are equipped with nanosheet FETs, and furthermore, they are equipped with a CFET structure in which transistors with different conductivity types (in the embodiment, the lower part of the cell is P-conducting and the upper part of the cell is N-conducting) are stacked.

[0013] Furthermore, in this specification, "VDD" and "VSS" refer to the power supply voltage or the power supply itself. Also, in this specification, expressions meaning that widths, etc., are the same, such as "same wiring width," include a range of manufacturing variations.

[0014] (First Embodiment) (Configuration of SRAM Cell) Figures 1 and 2A to 2C show examples of the layout structure of an SRAM cell according to the first embodiment, where Figures 1(a) and 1(b) are plan views and Figures 2A to 2C are cross-sectional views in the lateral direction in plan view. Specifically, Figure 1(a) shows the upper part of the cell, and Figure 1(b) shows the lower part of the cell. Figure 2A is a cross-section of line X1-X1', Figure 2B is a cross-section of line X2-X2', and Figure 2C is a cross-section of line X3-X3'.

[0015] In the following explanation, in plan views such as Figure 1, the horizontal direction of the drawing is referred to as the X direction (first direction), the vertical direction of the drawing as the Y direction (second direction), and the direction perpendicular to the substrate surface as the Z direction (depth direction).

[0016] Furthermore, in the following explanation, the dashed lines running vertically and horizontally in plan views such as Figure 1, and the dashed lines running vertically in cross-sectional views such as Figure 2, indicate a grid used for arranging components during the design phase. The grid is arranged at equal intervals in the X direction and at equal intervals in the Y direction. Note that the grid spacing may be the same or different in the X and Y directions. Also, the grid spacing may differ from layer to layer. Moreover, each component does not necessarily have to be placed on the grid.

[0017] Furthermore, in plan views such as Figure 1, the dotted lines surrounding the cells indicate the cell frame (outer edge of the SRAM cell) of the SRAM cell. SRAM cells are arranged so that their cell frames touch the cell frames of adjacent cells in the X or Y direction.

[0018] Furthermore, in the plan view shown in Figure 1, etc., SRAM cells C0 and C1 are inverted in the Y direction and placed on either side of them in the Y direction. SRAM cell C1 is placed to the left of SRAM cell C0 in the drawing, and SRAM cell C0 is placed to the right of SRAM cell C1 in the drawing.

[0019] As shown in Figure 1, SRAM cells C0 and C1 are arranged side by side in the X direction.

[0020] Figure 3 is a circuit diagram showing the configuration of an SRAM cell according to the first embodiment. As shown in Figure 3, the SRAM cell C0 is configured with an SRAM circuit consisting of drive transistors PU10, PU20, load transistors PD10, PD20, and access transistors PG10, PG20. The drive transistors PU10, PU20 and access transistors PG10, PG20 are P-type FETs, and the load transistors PD10, PD20 are N-type FETs.

[0021] The drive transistor PU10 is located between the power supply VDD and the first node NA0, and the load transistor PD10 is located between the first node NA0 and the power supply VSS. The gates of the drive transistor PU10 and the load transistor PD10 are connected to the second node NB0, forming the inverter INV10. The drive transistor PU20 is located between the power supply VDD and the second node NB0, and the load transistor PD20 is located between the second node NB0 and the power supply VSS. The gates of the drive transistor PU20 and the load transistor PD20 are connected to the first node NA0, forming the inverter INV20. That is, the output of one inverter is connected to the input of the other inverter, thereby forming a latch.

[0022] Access transistor PG10 is located between bit line BL0 and first node NA0, and its gate is connected to word line WL0. Access transistor PG20 is located between bit line BLB0 and second node NB0, and its gate is connected to word line WL0. Bit lines BL0 and BLB0 form a complementary bit line pair.

[0023] In the SRAM circuit, when the bit lines BL0 and BLB0, which constitute a complementary bit line pair, are driven to a high level and a low level, respectively, and the word line WL0 is driven to a low level, a high level is written to the first node NA0 and a low level is written to the second node NB0. On the other hand, when the bit lines BL0 and BLB0 are driven to a low level and a high level, respectively, and the word line WL0 is driven to a low level, a low level is written to the first node NA0 and a high level is written to the second node NB0. Then, with data written to the first and second nodes NA0 and NB0 respectively, when the word line WL0 is driven to a high level, the latch state is established and the data written to the first and second nodes NA0 and NB0 is held.

[0024] Furthermore, by pre-discharging bit lines BL0 and BLB0 to a low level and driving word line WL0 to a low level, the states of bit lines BL0 and BLB0 are determined according to the data written to the first and second nodes NA0 and NB0, respectively, allowing data to be read from the SRAM cells. Specifically, if the first node NA0 is at a high level and the second node NB0 is at a low level, bit line BL0 is charged to a high level and bit line BLB0 remains at a low level. On the other hand, if the first node NA0 is at a low level and the second node NB0 is at a high level, bit line BL0 remains at a low level and bit line BLB0 is charged to a high level.

[0025] As explained above, the SRAM cell has the functions of writing data to the SRAM cell, holding data, and reading data from the SRAM cell by controlling the bit lines BL0, BLB0 and the word line WL0.

[0026] SRAM cell C1 has an SRAM cell circuit similar to that of SRAM cell C0. Specifically, SRAM cell C1 has an SRAM circuit composed of drive transistors PU11 and PU21, load transistors PD11 and PD21, and access transistors PG11 and PG21. The drive transistors PU11 and PU21 and the access transistors PG11 and PG21 are P-type FETs, while the load transistors PD11 and PD21 are N-type FETs.

[0027] The SRAM cell circuit configured in SRAM cell C1 has the same configuration as the SRAM cell circuit configured in SRAM cell C0, so a detailed explanation is omitted. SRAM cell C1 has the functions of writing data to SRAM cell C1, holding data, and reading data from SRAM cell C1 by controlling bit lines BL1, BLB1 and word line WL0.

[0028] As shown in Figure 1(b), a BM0 (Backside Metal 0) wiring layer, which is a wiring layer, is formed on the back of the semiconductor chip on which the transistor is formed. The BM0 wiring layer corresponds to the back wiring layer.

[0029] The BM0 wiring layer has power supply wiring 11a, 11b and wiring 12, 13 extending in the Y direction. Power supply wiring 11a, 11b supplies the power supply voltage VDD. Wiring 12, 13 correspond to the bit lines BL0, BLB0, respectively. Wiring 12 is formed across the cell boundary on the left side of the SRAM cell C0 in the diagram. Wiring 13 is formed across the cell boundaries of SRAM cells C0 and C1.

[0030] Multiple active regions, which constitute the channel, source, and drain of the P-type transistor, are formed within the P-type transistor region. Specifically, active regions P1 to P4 are formed within the P-type transistor region.

[0031] In the active region P1, a drive transistor PU10 and an access transistor PG10 are formed. In the active region P2, a drive transistor PU20 and an access transistor PG20 are formed. In the active region P3, a drive transistor PU11 and an access transistor PG11 are formed. In the active region P4, a drive transistor PU21 and an access transistor PG21 are formed. The drive transistors PU10, PU11, PU20, PU21 and the access transistors PG10, PG11, PG20, PG21 each consist of a channel made of two overlapping sheet structures in a plan view, and each has nanosheets 21a, 21b, 22a, 22b, 23a, 23b, 24a, and 24b extending in the Y direction.

[0032] As shown in Figure 1(a), multiple active regions constituting the channel, source, and drain of an N-type transistor are formed in the N-type transistor region. Specifically, active regions N1 to N4 are formed in the N-type transistor region. Active regions N1 to N4 are each located above active regions P1 to P4 in the Z direction. Active regions N1 to N4 overlap with active regions P1 to P4 in a plan view.

[0033] A load transistor PD10 is formed in the active region N1. A load transistor PD20 is formed in the active region N2. A load transistor PD11 is formed in the active region N3. A load transistor PD21 is formed in the active region N4. Load transistors PD10, PD11, PD20, and PD21 each consist of a channel made up of two overlapping sheet structures in a plan view, and each has nanosheets 25a, 25b, 26a, and 26b extending in the Y direction.

[0034] Regarding the active region, the source and drain portions on both sides of the nanosheet are formed, for example, by epitaxial growth from the nanosheet.

[0035] Gate wirings 31a to 37a extending in the X direction are formed. Gate wiring 31a overlaps with nanosheets 21a and 25a in a plan view. Gate wiring 32a overlaps with nanosheets 24a and 24b in a plan view. Gate wiring 33a overlaps with nanosheets 21b and 25b in a plan view. Gate wiring 34a overlaps with nanosheet 23a in a plan view. Gate wiring 35a overlaps with nanosheets 22a and 26a in a plan view. Gate wiring 36a overlaps with nanosheets 22b and 26b in a plan view. Gate wiring 37a overlaps with nanosheet 23b in a plan view. Gate wiring 31a corresponds to the gates of drive transistor PU10 and load transistor PD10. Gate wiring 32a corresponds to the gates of access transistors PG20 and PG21. Gate wiring 33a corresponds to the gates of the drive transistor PU11 and the load transistor PD11. Gate wiring 34a corresponds to the gate of the access transistor PG10. Gate wiring 35a corresponds to the gates of the drive transistor PU20 and the load transistor PD20. Gate wiring 36a corresponds to the gates of the drive transistor PU21 and the load transistor PD21. Gate wiring 37a corresponds to the gate of the access transistor PG11.

[0036] As shown in Figure 1(b), local interconnects (LI) 51a to 56a and 51b to 56b extending in the X direction are formed at the bottom of the cell. Local interconnect 51a is connected to the source portion of the drive transistor PU10 in the active region P1. Local interconnect 52a is connected to the source portion of the access transistor PG20 in the active region P2. Local interconnect 53a is connected to the drain portion of the drive transistor PU10 in the active region P1, and to the drain portion of the access transistor PG10 in the active region P1. Local interconnect 54a is connected to the drain portion of the access transistor PG20 in the active region P2, and to the drain portion of the drive transistor PU20 in the active region P2. Local interconnect 55a is connected to the source portion of the access transistor PG10 in the active region P1. Local interconnect 56a is connected to the source portion of the drive transistor PU20 in the active region P2. Local wiring 51b is connected to the source portion of the drive transistor PU11 in the active region P3. Local wiring 52b is connected to the source portion of the access transistor PG21 in the active region P4. Local wiring 53b is connected to the drain portion of the drive transistor PU11 in the active region P3, and to the drain portion of the access transistor PG11 in the active region P3. Local wiring 54b is connected to the drain portion of the access transistor PG21 in the active region P4, and to the drain portion of the drive transistor PU21 in the active region P4. Local wiring 55b is connected to the source portion of the access transistor PG11 in the active region P3. Local wiring 56b is connected to the source portion of the drive transistor PU21 in the active region P4.

[0037] Local wiring 51a is connected to wiring 11a via via 41a. Local wiring 52a is connected to wiring 13 via via 42. Local wiring 55a is connected to wiring 12 via via 43. Local wiring 56a is connected to wiring 11a via via 44a. Local wiring 51b is connected to wiring 11b via via 41b. Local wiring 56b is connected to wiring 11b via via 44b.

[0038] As shown in Figure 1(a), local wiring 61a-64a, 61b-64b, 65, and 66 extending in the X direction are formed on the upper part of the cell. Local wiring 61a is connected to the source portion of load transistor PD10 in the active region N1. Local wiring 62a is connected to the drain portion of load transistor PD10 in the active region N1. Local wiring 63a is connected to the drain portion of load transistor PD20 in the active region N2. Local wiring 64a is connected to the source portion of load transistor PD20 in the active region N2. Local wiring 61b is connected to the source portion of load transistor PD11 in the active region N3. Local wiring 62b is connected to the drain portion of load transistor PD11 in the active region N3. Local wiring 63b is connected to the drain portion of load transistor PD21 in the active region N4. Local wiring 64b is connected to the source portion of load transistor PD21 in the active region N4.

[0039] Local wiring 62a is connected to gate wiring 35a via shared contact 81a and to local wiring 53a via via 71a. Local wiring 63a is connected to gate wiring 31a via shared contact 82a and to local wiring 54a via via 72a. Local wiring 62b is connected to gate wiring 36a via shared contact 81b and to local wiring 53b via via 71b. Local wiring 63b is connected to gate wiring 33a via shared contact 82b and to local wiring 54b via via 72b.

[0040] Power supply wirings 91a, 91b and wirings 92, 93, 94a, 94b, 95a, 95b extending in the Y direction are formed on the M1 wiring layer, which is a metal wiring layer located above the active regions N1 and N2. Power supply wirings 91a and 91b supply the power supply voltage VSS. Wirings 92 and 93 correspond to bit lines BL1 and BLB1, respectively. Wiring 92 is formed spanning the cell boundary on the right side of the SRAM cell C1 drawing. Wiring 93 is formed spanning the cell boundaries of SRAM cells C0 and C1. Wirings 12, 13, 92, and 93 have the same wiring width. Wiring 93 overlaps with wiring 13 in a plan view.

[0041] Power supply wiring 91a is connected to the source portion of load transistor PD10 in active region N1 via local wiring 61a and via 83a. Power supply wiring 91a is connected to the source portion of load transistor PD20 in active region N2 via local wiring 64a and via 84a. Power supply wiring 91b is connected to the source portion of load transistor PD11 in active region N3 via local wiring 61b and via 83b. Power supply wiring 91b is connected to the source portion of load transistor PD21 in active region N4 via local wiring 64b and via 84b. Wiring 92 is connected to the source portion of access transistor PG11 in active region P3 via local wiring 55b, 65 and via 73, 85. Wiring 93 is connected to the source portion of access transistor PG21 in active region P4 via local wiring 52b, 66 and via 74, 86.

[0042] A wiring 101 extending in the X direction is formed in the M2 wiring layer, which is the upper layer of the M1 wiring layer. The wiring 101 corresponds to the word line WL0.

[0043] Wiring 101 is connected to gate wiring 34a via wiring 94a and vias 87a and 102a. Wiring 101 is connected to gate wiring 32a via wirings 95a and 95b and vias 88a, 88b, 103a, and 103b. Wiring 101 is connected to gate wiring 37a via wiring 94b and vias 87b and 102b.

[0044] With the above configuration, in the SRAM cells C0 and C1 arranged adjacent to each other in the X direction, wirings 12 and 13 corresponding to bit lines BL0 and BLB0 respectively are formed in the BM0 wiring layer which is the wiring layer on the back side of the transistors, and wirings 92 and 93 corresponding to bit lines BL1 and BLB1 respectively are formed in the M1 wiring layer which is the metal wiring layer on the upper layer of the transistors. Thereby, the wirings corresponding to the bit lines can be arranged across the SRAM cells C0 and C1. For this reason, the wiring width of the bit lines can be increased, the wiring resistance of the bit lines can be suppressed, and thus the operating speed of the semiconductor memory device can be improved.

[0045] Although the wiring widths of the wirings 12, 13, 92, and 93 are assumed to be the same, they may be different.

[0046] Also, although the wirings 12 and 13 are arranged in the BM0 wiring layer and the wirings 92 and 93 are arranged in the M1 wiring layer, it is not limited to this. The wirings 12 and 13 may both be arranged in a back-side wiring layer other than the BM0 wiring layer, and the wirings 92 and 93 may both be arranged in a metal wiring layer other than the M1 wiring layer.

[0047] (Block Layout) FIG. 4 is a plan view showing an example of the layout of circuit blocks included in the semiconductor memory device according to the first embodiment. Specifically, FIG. 4(a) shows the upper part of the cell, and FIG. 4(b) shows the lower part of the cell. In FIG. 4(a), only the bit lines formed in the M1 wiring layer and the vias connected to the bit lines are illustrated, and in FIG. 4(b), only the bit lines formed in the BM0 wiring layer and the vias connected to the bit lines are illustrated. Also, in the circuit block of FIG. 4, SRAM cells other than those illustrated are also arranged (for example, SRAM cells are arranged on both the upper and lower sides and both the left and right sides of the drawing), but the illustration is omitted.

[0048] In FIG. 4, four SRAM cells (C0 to C3) are arranged side by side in the X direction. Wires corresponding to bit lines BL0 and BLB0 are connected to the SRAM cell C0. Wires corresponding to bit lines BL1 and BLB1 are connected to the SRAM cell C1. Wires corresponding to bit lines BL2 and BLB2 are connected to the SRAM cell C2. Wires corresponding to bit lines BL3 and BLB3 are connected to the SRAM cell C3.

[0049] As shown in FIG. 4(b), in the BM0 wiring layer, wires 12a, 13a, 12b, and 13b extending in the Y direction are formed. The wires 12a, 13a, 12b, and 13b respectively correspond to the bit lines BL0, BLB0, BL2, and BLB2. The wire 12a is arranged across the cell boundary on the left side of the drawing of the SRAM cell C0. The wire 13a is arranged across the cell boundaries of the SRAM cells C0 and C1. The wire 12b is arranged across the cell boundaries of the SRAM cells C1 and C2. The wire 13b is arranged across the cell boundaries of the SRAM cells C2 and C3.

[0050] As shown in FIG. 4(a), in the M1 wiring layer, wires 92a, 93a, 92b, and 93b extending in the Y direction are formed. 92a, 93a, 92b, and 93b respectively correspond to the bit lines BL1, BLB1, BL3, and BLB3. The wire 93a is arranged across the cell boundaries of the SRAM cells C0 and C1. The wire 92a is arranged across the cell boundaries of the SRAM cells C1 and C2. The wire 93b is arranged across the cell boundaries of the SRAM cells C2 and C3. The wire 92b is arranged across the cell boundary on the right side of the drawing of the SRAM cell C3.

[0051] The wires 13a, 12b, and 13b respectively overlap the wires 93a, 92a, and 93b in a plan view.

[0052] According to the block layout of FIG. 4, in two SRAM cells arranged side by side in the X direction, wires corresponding to the bit lines of both can be arranged across the two SRAM cells. Thereby, the wiring width of the bit line can be increased, and the wiring resistance of the bit line can be suppressed, so that the operating speed of the semiconductor memory device can be improved.

[0053] (Modification) Figure 5 is a plan view showing another example of the layout structure of the SRAM cell according to the first embodiment. Specifically, Figure 5(a) shows the upper part of the cell, and Figure 5(b) shows the lower part of the cell. In Figure 5, compared with Figure 1, wiring 14 is formed in place of wiring 13 in the BM0 wiring layer, and wiring 96 is formed in place of wiring 93 in the M1 wiring layer.

[0054] As shown in Figure 5(b), a wiring 14 extending in the Y direction is formed. The wiring 14 corresponds to the bit line BLB1. The wiring 14 is formed across the cell boundaries of SRAM cells C0 and C1. The wiring 14 is connected via a via 45 to the source portion of the access transistor PG21 in the active region P4.

[0055] As shown in Figure 5(a), a wiring 96 extending in the Y direction is formed in the M1 wiring layer. The wiring 96 corresponds to the bit line BLB0. The wiring 96 is formed across the cell boundaries of SRAM cells C0 and C1. In a plan view, the wiring 96 overlaps with the wiring 14. The wiring 96 is connected to the source portion of the access transistor PG20 in the active region P2 via local wirings 52a and 67 and vias 75 and 87.

[0056] In the configuration shown in Figure 5, in SRAM cell C0, wiring 12 corresponding to bit line BL0 is formed in the BM0 wiring layer, and wiring 96 corresponding to bit line BLB0 is formed in the M1 wiring layer. In SRAM cell C1, wiring 92 corresponding to bit line BL1 is formed in the M1 wiring layer, and wiring 14 corresponding to bit line BLB1 is formed in the BM0 wiring layer. As a result, the bit lines constituting complementary bit line pairs are formed in different wiring layers, allowing the bit line pairs to be separated. This suppresses the coupling capacitance between bit line pairs, thereby improving the operating speed of the semiconductor memory device.

[0057] (Second Embodiment) (Configuration of SRAM Cells) Figures 6A and 6B are plan views showing an example of the layout structure of an SRAM cell according to the second embodiment. Specifically, Figure 6A shows the upper part of the cell, and Figure 6B shows the lower part of the cell. Compared with Figure 1, Figures 6A and 6B show SRAM cells C10 and C11 in addition to SRAM cells C0 and C1.

[0058] Figure 7 is a circuit diagram showing the configuration of an SRAM cell according to the second embodiment. Compared to Figure 3, Figure 7 shows that SRAM cell circuits corresponding to SRAM cells C10 and C11 have been added.

[0059] The SRAM cell circuit configured in SRAM cell C10 has almost the same configuration as the SRAM cell circuit configured in SRAM cell C0, so a detailed explanation will be omitted. SRAM cell C10 has the functions of writing data to SRAM cell C10, holding data, and reading data from SRAM cell C10 by controlling the bit lines BL0, BLB0 and the word line WL1.

[0060] The SRAM cell circuit configured in SRAM cell C11 is almost identical in configuration to the SRAM cell circuit configured in SRAM cell C1, so a detailed explanation will be omitted. SRAM cell C11 has the functions of writing data to SRAM cell C11, holding data, and reading data from SRAM cell C11 by controlling bit lines BL1, BLB1 and word line WL1.

[0061] In Figures 6A and 6B, SRAM cells C10 and C11 are positioned above SRAM cells C0 and C1, respectively. SRAM cells C10 and C11 correspond to SRAM cells C0 and C1 in Figure 1 when they are inverted in the Y direction, but wiring 112 and 113 are placed in the BM0 wiring layer instead of wiring 12 and 13, and wiring 192 and 193 are placed in the M1 wiring layer instead of wiring 92 and 93.

[0062] As shown in Figure 6B, in SRAM cells C10 and C11, wirings 112 and 113 extending in the Y direction are formed in the BM0 wiring layer. Wirings 112 and 113 correspond to bit lines BL1 and BLB1, respectively. Wiring 112 is formed across the cell boundary on the right side of the drawing of SRAM cell C11. Wiring 113 is formed across the cell boundary of SRAM cells C10 and C11.

[0063] Wiring 112 is connected via via 141 and local wiring 151 to the source portion of access transistor PG11 in the active region P7. Wiring 113 is connected via via 142 and local wiring 152 to the source portion of access transistor PG21 in the active region P8.

[0064] As shown in Figure 6A, wiring layers M1 have wirings 192 and 193 extending in the Y direction. Wires 192 and 193 correspond to bit lines BL0 and BLB0, respectively. Wires 112, 113, 192, and 193 have the same wiring width. Wire 193 overlaps with wire 113 in a plan view.

[0065] Wiring 192 is connected to the source portion of access transistor PG10 in the active region P5 via local wires 153, 161 and vias 171, 181. Wiring 193 is connected to the source portion of access transistor PG20 in the active region P6 via local wires 154, 162 and vias 172, 182.

[0066] In Figures 6A and 6B, region A1 is formed between SRAM cells C0 and C1 and SRAM cells C10 and C11.

[0067] In region A1, local wiring layers have local wirings 155-158 and 163-170 extending in the X direction, and wiring layers M1 have wirings 194-197 extending in the Y direction.

[0068] In region A1, wiring 192 is connected to wiring 12 via via 183a, local wiring 163, via 183b, wiring 194, via 183c, local wiring 164, via 173, local wiring 155, and via 143. Wiring 193 is connected to wiring 13 via via 184a, local wiring 165, via 184b, wiring 195, via 184c, local wiring 166, via 174, local wiring 156, and via 144. Wiring 92 is connected to wiring 112 via via 185a, local wiring 167, via 185b, wiring 196, via 185c, local wiring 168, via 175, local wiring 157, and via 145. Wiring 93 is connected to wiring 113 via via 186a, local wiring 169, via 186b, wiring 197, via 186c, local wiring 170, via 176, local wiring 158, and via 146.

[0069] With the above configuration, in region A1, wiring 12 corresponding to bit line BL0, formed in the BM0 wiring layer, and wiring 192 corresponding to bit line BL0, formed in the M1 wiring layer, are connected. In region A1, wiring 13 corresponding to bit line BLB0, formed in the BM0 wiring layer, and wiring 193 corresponding to bit line BLB0, formed in the M1 wiring layer, are connected. In region A1, wiring 112 corresponding to bit line BL1, formed in the BM0 wiring layer, and wiring 92 corresponding to bit line BL1, formed in the M1 wiring layer, are connected. In region A1, wiring 113 corresponding to bit line BLB1, formed in the BM0 wiring layer, and wiring 93 corresponding to bit line BLB1, formed in the M1 wiring layer, are connected. As a result, the load on each bit line is equalized, and performance variations between adjacent SRAM cell rows in the X direction can be suppressed.

[0070] In this embodiment, one SRAM cell connected to the same bit line pair is placed on the upper and lower sides of region A1, but this is not limited to this configuration. Multiple SRAM cells connected to the same bit line pair may be placed on the upper and lower sides of region A1. In this case, the number of SRAM cells placed on the upper and lower sides of region A1 should be the same.

[0071] In the embodiments and modifications described above, each transistor is provided with two nanosheets, but some or all of the transistors may be provided with one or three or more nanosheets.

[0072] Furthermore, while the cross-sectional shape of the nanosheet is rectangular in each of the embodiments and modifications described above, it is not limited to this. For example, it may be square, circular, elliptical, or the like.

[0073] Furthermore, in each of the embodiments and modifications described above, the shared contacts 81a, 81b, 82a, and 82b may be manufactured in the same process as the contacts (Gate-Contact) and local wiring, or they may be manufactured in a separate process.

[0074] Furthermore, in each of the embodiments and modifications described above, the power supply that provides the power supply voltage VDD to the sources of the drive transistors PU10, PU20, PU11, and PU21 is not limited to a power supply supplied from outside the semiconductor integrated circuit, but may be a power supply generated inside the semiconductor integrated circuit, or a power supply generated inside the semiconductor memory device, etc.

[0075] This disclosure describes how the operating speed of a semiconductor memory device can be improved in a layout structure of an SRAM cell using a CFET.

[0076] 12, 13, 14, 92, 93, 96, 112, 113, 192, 193 Wiring 21a-26a, 21b-26b Nanosheet 31a-37a Gate Wiring 11a, 11b, 91a, 91b Power Wiring PU10, PU20, PU11, PU21 Drive Transistors PD10, PD20, PD11, PD21 Load Transistors PG10, PG20, PG11, PG21 Access Transistors BL0, BLB0, BL1, BLB1 Bit Lines WL0, WL1 Word Lines C0-C3, C10, C11 SRAM Cells

Claims

1. A semiconductor memory device comprising a plurality of SRAM cells, wherein the plurality of SRAM cells include first and second SRAM cells arranged adjacent to each other in a first direction, the first and second SRAM cells are connected to a first word line extending in the first direction, the first SRAM cell comprises a channel, source and drain of a first transistor of a first conductivity type, the channel comprising a first active region including a first nanosheet extending in a second direction perpendicular to the first direction, the channel comprising a second active region formed above the first active region in the depth direction and overlapping with the first active region in a plan view, and comprising a channel, source and drain of a second transistor of a second conductivity type different from the first conductivity type, the channel comprising a second active region including a second nanosheet extending in the second direction, and a first bit line extending in the second direction, the second SRAM cell, A semiconductor memory device comprising: a third active region formed in the same layer as the first active region in the depth direction, constituting the channel, source, and drain of the third transistor of the first conductivity type, and including a third nanosheet extending in the second direction as the channel; a fourth active region formed in the same layer as the second active region in the depth direction, overlapping with the third active region in a plan view, constituting the channel, source, and drain of the fourth transistor of the second conductivity type, and including a fourth nanosheet extending in the second direction as the channel; and a second bit line extending in the second direction, wherein the first bit line is formed in the back wiring layer on the back side of the first and third active regions, the second bit line is formed in the metal wiring layer above the second and fourth active regions, and the first and second bit lines are formed across the cell boundary between the first SRAM cell and the second SRAM cell.

2. A semiconductor memory device according to claim 1, wherein the first and second bit lines overlap in a plan view.

3. A semiconductor memory device according to claim 1, wherein the plurality of SRAM cells further include a third SRAM cell arranged adjacent to the first SRAM cell in the first direction, the first SRAM cell further comprises a third bit line formed in the back wiring layer, extending in the second direction, and constituting a complementary bit line pair with the first bit line, the third bit line is formed across the cell boundary between the first SRAM cell and the third SRAM cell.

4. A semiconductor memory device according to claim 1, wherein the plurality of SRAM cells further include a fourth SRAM cell arranged adjacent to the second SRAM cell in the first direction, the second SRAM cell further comprises a fourth bit line formed in the metal wiring layer, extending in the second direction, and constituting a complementary bit line pair with the second bit line, the fourth bit line is formed across the cell boundary between the second SRAM cell and the fourth SRAM cell.

5. A semiconductor memory device according to claim 1, wherein the plurality of SRAM cells further include a fourth SRAM cell arranged adjacent to the second SRAM cell in the first direction, the second SRAM cell further comprises a fourth bit line formed in the metal wiring layer, extending in the second direction, and constituting a complementary bit line pair with the second bit line, the fourth SRAM cell comprises a fifth bit line formed in the back wiring layer, extending in the second direction, and the fourth and fifth bit lines are formed across the cell boundary between the second SRAM cell and the fourth SRAM cell.

6. A semiconductor memory device according to claim 1, wherein the first SRAM cell further comprises a third bit line formed in the metal wiring layer, extending in the second direction, and constituting a complementary bit line pair with the first bit line, and the second SRAM cell further comprises a fourth bit line formed in the back wiring layer, extending in the second direction, and constituting a complementary bit line pair with the second bit line.

7. A semiconductor memory device according to claim 1, wherein the plurality of SRAM cells include a third SRAM cell arranged side by side with the first SRAM cell in the second direction, and a fourth SRAM cell arranged side by side with the second SRAM cell in the second direction, the third SRAM cell having a third bit line formed in the metal wiring layer and extending in the second direction, the fourth SRAM cell having a fourth bit line formed in the back wiring layer and extending in the second direction, the third and fourth bit lines being formed across the cell boundary between the third SRAM cell and the fourth SRAM cell, the first bit line being connected to the third bit line, and the second bit line being connected to the fourth bit line.

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