Clock monitoring device and clock monitoring method
Patent Information
- Application Number
- PCT/KR2026/002182
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2025-03-27
- Filing Date
- 2026-02-05
- Publication Date
- 2026-08-27
Smart Images
Figure KR2026002182_27082026_PF_FP_ABST
Abstract
Description
Clock monitoring device and clock monitoring method
[0001] The present invention relates to a clock monitoring device and a clock monitoring method, and more specifically, to a clock monitoring device and a clock monitoring method capable of detecting gating of a monitor clock that is a monitored object.
[0002] A System-on-Chip (SoC) refers to the technology of integrating various function blocks—such as a CPU (Central Processing Unit), memory, interfaces, digital signal processing circuits, and analog signal processing circuits—into a single semiconductor integrated circuit to implement computer systems or other electronic systems, or the single Integrated Circuit (IC) integrated according to this technology. SoCs are evolving into more complex systems that include various function blocks such as processors, multimedia, graphics, interfaces, and security. In such SoCs, clock design and clock monitoring are critical.
[0003] In semiconductor design, clock monitoring devices used in clock trees utilize a reference clock to monitor the quality, such as the clock frequency, of the monitor clock. For example, when the reference clock is counted a set number of times, a counter measures how many times the monitor clock has been counted, and the clock quality of the monitor clock can be monitored by comparing whether the measured count value falls between a high threshold value and a low threshold value.
[0004] FIG. 1 is a configuration diagram illustrating an exemplary clock monitoring device. FIG. 2 is a conceptual diagram illustrating a clock monitor constituting the clock monitoring device. FIG. 3 is an example diagram illustrating a method of detecting an error signal by the clock monitoring device. If, when the reference clock is counted by the reference clock counter (11) for a set number of clocks, the monitoring count value of the monitoring clock counter (12) is in an area greater than the upper limit value input to the upper limit comparator (15) constituting the comparator (13) or smaller than the lower limit value input to the lower limit comparator (16), the error determiner (17) outputs an error signal to the clock error management unit (18).
[0005] For example, if the reference clock is 30 MHz and the monitoring clock is 230 MHz, it can be determined that the monitoring clock frequency is normal when the reference clock is counted 3 times and the monitoring clock is counted 23 times. In this case, if the upper limit for clock monitoring is set to 23 and the lower limit is set to 22, no error signal is generated when the monitoring clock is counted 23 times while the reference clock is counted 3 times. However, if the monitoring clock is counted 24 times while the reference clock is counted 3 times, an error signal is generated because the count value of the monitoring clock is greater than the upper limit.
[0006] FIG. 4 is an example diagram illustrating the operation of a clock monitoring device when the monitoring clock is gated. When the monitoring clock is gated or cut off, the monitoring clock input to the clock monitor (10) becomes dead, and thus the function of the clock monitor (10) is completely stopped. Therefore, information regarding whether the clock frequency of the monitoring clock deviates from the upper and lower limits set by the user can be known, but the case where the monitoring clock is gated cannot be detected even by the state machine (14).
[0007] One objective of the present invention is to provide a clock monitoring device and a clock monitoring method capable of detecting not only error information of the clock frequency of a monitored clock but also clock gating.
[0008] The technical problems to be solved by the embodiments of the present invention are not limited to those described above, and other technical problems can be inferred from the following embodiments.
[0009] A clock monitoring device according to an embodiment of the present invention comprises: a reference clock counter for counting the clock of a reference clock; a monitoring clock counter for counting the clock of a monitoring clock to be monitored; a comparator for detecting an error in the monitoring clock by comparing a monitoring count value counted for the monitoring clock by the monitoring clock counter with a set reference count value at a monitoring point in time when the reference clock is counted by a count value set by the reference clock counter; a state machine for generating an enable request signal to detect gating of the monitoring clock in an enable state in which monitoring of the monitoring clock is performed; and a synchronizer for operating in synchronization with the monitoring clock and outputting an enable confirmation signal for the enable request signal to the state machine. The state machine is configured to generate a clock gating error signal related to the gating of the monitoring clock depending on whether the enable confirmation signal corresponding to the enable request signal is received.
[0010] The state machine may be configured to generate the clock gating error signal if, after transmitting the enable request signal to the synchronizer, the enable confirmation signal corresponding to the enable request signal is not received from the synchronizer until the set gating detection time expires.
[0011] The state machine may be configured to operate a gating detection counter when the enable confirmation signal corresponding to the enable request signal is not received from the synchronizer, and to generate a clock gating error signal when the set gating detection time of the gating detection counter expires.
[0012] The state machine can determine a gating error of the monitoring clock at the monitoring start time by comparing the signal level of a first enable request signal at the monitoring start time when the monitoring cycle begins with the signal level of a first enable confirmation signal of the synchronizer for the first enable request signal; and determine a gating error of the monitoring clock at the monitoring end time by comparing the signal level of a second enable request signal at the monitoring end time when the monitoring cycle ends with the signal level of a second enable confirmation signal of the synchronizer for the second enable request signal.
[0013] The above comparator may include: a first comparator that compares the monitoring coefficient value with an upper limit value corresponding to a first reference coefficient value at the monitoring point; a second comparator that compares the monitoring coefficient value with a lower limit value corresponding to a second reference coefficient value at the monitoring point; and an error determiner that outputs an error signal corresponding to an upper limit error or a lower limit error according to the comparison result of the first comparator and the second comparator.
[0014] The above error determination unit may include a logic operator that outputs the error signal by performing a logical OR operation or a logical NOR operation on the first comparison value of the first comparator and the second comparison value of the second comparator.
[0015] A clock monitoring method according to an embodiment of the present invention comprises: a step of counting the clock of a reference clock by a reference clock counter; a step of counting the clock of a monitoring clock to be monitored by a monitoring clock counter; a step of detecting an error in the monitoring clock by comparing the monitoring count value counted for the monitoring clock by the monitoring clock counter with the set reference count value by a comparator at a monitoring point in time when the reference clock is counted by a count value set by the reference clock counter; a step of generating an enable request signal to detect gating of the monitoring clock in an enable state in which monitoring of the monitoring clock is performed by a state machine; a step of operating in synchronization with the monitoring clock by a synchronizer and outputting an enable confirmation signal for the enable request signal to the state machine; and a step of generating a clock gating error signal related to the gating of the monitoring clock by the state machine according to whether the enable confirmation signal corresponding to the enable request signal is received.
[0016] The step of generating the clock gating error signal may include: generating the clock gating error signal if, after the state machine transmits the enable request signal to the synchronizer, the enable confirmation signal corresponding to the enable request signal is not received from the synchronizer until the set gating detection time expires.
[0017] The step of generating the clock gating error signal may include: if the enable confirmation signal corresponding to the enable request signal is not received from the synchronizer to the state machine, operating a gating detection counter, and generating the clock gating error signal when the set gating detection time of the gating detection counter expires.
[0018] The step of generating the clock gating error signal may include: a step of determining a gating error of the monitoring clock at the monitoring start time by comparing the signal level of a first enable request signal at the monitoring start time when the monitoring cycle begins with the signal level of a first enable confirmation signal of the synchronizer for the first enable request signal; and a step of determining a gating error of the monitoring clock at the monitoring end time by comparing the signal level of a second enable request signal at the monitoring end time when the monitoring cycle ends with the signal level of a second enable confirmation signal of the synchronizer for the second enable request signal.
[0019] The step of detecting an error in the above-mentioned monitoring clock may include: a step of comparing the monitoring coefficient value with an upper limit value corresponding to a first reference coefficient value at the monitoring point by a first comparator; a step of comparing the monitoring coefficient value with a lower limit value corresponding to a second reference coefficient value at the monitoring point by a second comparator; and a step of outputting an error signal corresponding to an upper limit error or a lower limit error according to the comparison result of the first comparator and the second comparator by an error determination unit.
[0020] The step of outputting the error signal may include the step of outputting the error signal by performing a logical OR operation or a logical NOR operation on the first comparison value of the first comparator and the second comparison value of the second comparator by a logical operator.
[0021] In addition, according to an embodiment of the present invention, a computer-readable non-transient recording medium is provided on which a computer program for executing the clock monitoring method is recorded.
[0022] According to an embodiment of the present invention, a clock monitoring device and a clock monitoring method are provided, which can detect not only error information of the clock frequency of a monitoring clock to be monitored, but also clock gating.
[0023] The effects that the present invention aims to achieve are not limited to those mentioned above, and other unmentioned effects can be clearly understood by those skilled in the art from the description below.
[0024] Figure 1 is a configuration diagram illustrating an exemplary clock monitoring device.
[0025] Figure 2 is a conceptual diagram showing a clock monitor that constitutes a clock monitoring device.
[0026] Figure 3 is an example diagram showing how to detect an error signal by a clock monitoring device.
[0027] Figure 4 is an example diagram illustrating the operation of a clock monitoring device when the monitoring clock is gated.
[0028] FIG. 5 is a configuration diagram showing a clock monitoring device according to an embodiment of the present invention.
[0029] FIG. 6 is a flowchart illustrating a clock monitoring method according to an embodiment of the present invention.
[0030] FIGS. 7a to 7c are illustrative diagrams for explaining the operation of a clock monitoring device according to an embodiment of the present invention.
[0031] FIG. 8 is a configuration diagram showing a comparator constituting a clock monitoring device according to an embodiment of the present invention.
[0032] FIG. 9 is a conceptual diagram showing a computing device for executing a clock monitoring method according to an embodiment of the present invention.
[0033] Hereinafter, specific details for implementing the present invention will be described in detail with reference to the attached drawings. However, in the following description, specific descriptions regarding well-known functions or configurations will be omitted if there is a risk that the essence of the present invention may be unnecessarily obscured. In the attached drawings, identical or corresponding components are assigned the same reference numerals whenever possible. In the description of the following embodiments, the description of identical or corresponding components may be omitted. However, even if a description of a component is omitted, it is not intended that such component is not included in any embodiment.
[0034] The advantages and features of the embodiments disclosed in this specification, and the methods for achieving them, will become clear by referring to the embodiments described below in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms, and these embodiments are provided merely to fully inform a person skilled in the art of the scope of the invention.
[0035] The terms used in this specification will be briefly explained, and the disclosed embodiments will be described in detail. The terms used in this specification have been selected to be as widely used as possible, taking into account their functions in the present invention; however, these terms may vary depending on the intent of those skilled in the relevant field, case law, or the emergence of new technologies. Additionally, in specific cases, terms may be arbitrarily selected by the applicant, and in such cases, their meanings will be described in detail in the relevant description of the invention. Therefore, the terms used in this invention should be defined not merely by their names, but based on their meanings and the overall content of the present invention.
[0036] In this specification, singular expressions include plural expressions unless the context clearly specifies them as singular. Additionally, plural expressions include singular expressions unless the context clearly specifies them as plural. Throughout the specification, when a part is described as including a certain component, this means that, unless specifically stated otherwise, it does not exclude other components but may include additional components. In the present invention, terms such as 'include' and 'include' may indicate the presence of features, steps, actions, elements, and / or components, and such terms do not exclude the addition of one or more other functions, steps, actions, elements, components, and / or combinations thereof.
[0037] In the present invention, where a specific component is described as being 'combined,' 'combined,' 'connected,' 'associated,' or 'reacting' with any other component, the specific component may be directly combined, combined, connected, and / or associated with, or react with the other component, but is not limited thereto. For example, one or more intermediate components may exist between the specific component and the other component. Additionally, in the present invention, "and / or" may include each of the one or more listed items or a combination of at least some of the one or more items. In the present invention, terms such as "first," "second," etc., are used to distinguish a specific component from another component, and the components described above are not limited by these terms. For example, the "first" component may be used to refer to an element of the same or similar form as the "second" component.
[0038] A clock monitoring device and a clock monitoring method according to an embodiment of the present invention include: a comparator that detects an error in a monitoring clock by comparing a monitoring count value counted for the monitoring clock by a monitoring clock counter with a set reference count value at a monitoring point in time when the reference clock is counted by a count value set by a reference clock counter; a state machine that generates an enable request signal to detect gating of the monitoring clock in an enable state in which monitoring of the monitoring clock is performed; and a synchronizer that operates in synchronization with the monitoring clock and outputs an enable confirmation signal for the enable request signal to the state machine. The state machine generates a clock gating error signal related to the gating of the monitoring clock depending on whether the enable confirmation signal corresponding to the enable request signal is received. According to an embodiment of the present invention, not only error information regarding the clock frequency of the monitoring clock to be monitored, but also clock gating can be detected.
[0039] FIG. 5 is a configuration diagram showing a clock monitoring device according to an embodiment of the present invention. FIG. 6 is a flowchart showing a clock monitoring method according to an embodiment of the present invention. FIG. 7a to 7c are illustrative diagrams for explaining the operation of a clock monitoring device according to an embodiment of the present invention. Referring to FIG. 5 to 7c, a clock monitoring device (100) according to an embodiment of the present invention may include a reference clock counter (110), a monitor clock counter (120), a comparator (130), a state machine (140), and a synchronizer (150).
[0040] The reference clock counter (110) can count the clock of the reference clock. For example, the reference clock counter (110) can output a counter output to the state machine (140) when the clock of the reference clock is counted by a set count value. As another example, the reference clock counter (110) may output a clock count value to the state machine (140) whenever the clock of the reference clock is counted, and may output a monitoring signal to the comparator (130) to compare the monitoring clock with the reference count value when the reference clock is counted by a set count value in the state machine (140).
[0041] The monitoring clock counter (120) can count the clock of the monitoring clock that is the subject of monitoring. The monitoring count value counted for the monitoring clock by the monitoring clock counter (120) can be input to the comparator (130). At the monitoring point where the reference clock is counted by the count value set by the reference clock counter (110), the comparator (130) can detect an error in the monitoring clock by comparing the monitoring count value counted for the monitoring clock by the monitoring clock counter (120) with the set reference count value. The comparator (130) may be provided as, for example, a digital comparator or an analog comparator. The comparator (130) can perform a comparison operation in a manner such as comparing the monitoring count value counted for the monitoring clock with the set reference count value, or comparing whether the two are the same value. The comparator (130) may include, for example, logic gate circuits such as AND, OR, XOR gates and / or analog circuits such as operational amplifiers.
[0042] For example, if the reference clock is 30 MHz and the monitor clock is 230 MHz, the monitor clock must be counted 23 times when the reference clock is counted 3 times. In this case, the upper limit can be set to 23 and the lower limit can be set to 22. If the monitor clock is counted 23 times while the reference clock is counted 3 times, no error signal is generated. Conversely, if the monitor clock is counted 24 times while the reference clock is counted 3 times, an error signal corresponding to an upper limit error may be generated because the monitor count value is greater than the upper limit. Also, if the monitor clock is counted 21 times while the reference clock is counted 3 times, an error signal corresponding to a lower limit error may be generated because the monitor count value is smaller than the lower limit.
[0043] A state machine (140) and a synchronizer (150) may be provided to monitor clock gating for a monitoring clock. The state machine (140) may generate an enable request signal (REQ) to detect gating of the monitoring clock in an enable state where monitoring of the monitoring clock is performed, and output (transmit) it to the synchronizer (150) (step S10 of FIG. 6). The enable request signal (REQ) may be transmitted from the state machine (140) to the synchronizer (150) at an initial point within the monitoring interval for each monitoring period set for the monitoring clock in the enable state.
[0044] The monitoring period can be set as a time interval in which the reference clock counter (110) counts the reference clock by a set count value. For example, in the example described above, the monitoring period may be the time in which the reference clock is counted by 3 clocks. That is, the monitoring period may be the value obtained by multiplying the period of the reference clock by a set count value (integer N). In the embodiment, the set count value (N) may be set as the value obtained by dividing the clock frequency of the reference clock (e.g., 30 MHz) by the greatest common divisor (10 MHz) of the clock frequency of the reference clock (e.g., 30 MHz) and the clock frequency of the monitoring clock (e.g., 230 MHz) (e.g., N = 3).
[0045] At this time, the reference coefficient value (an integer K or K-1, etc.) compared with the monitoring clock can be set based on the value obtained by dividing the monitoring clock frequency (e.g., 230 MHz) by the greatest common divisor (10 MHz) of the reference clock frequency (e.g., 30 MHz) and the monitoring clock frequency (e.g., 230 MHz) (e.g., K = 23, or K-1 = 22, etc., the upper / lower limit reference coefficient values are set). The value obtained by multiplying the reference clock period (or the reciprocal of the reference clock frequency) by the coefficient value N and the value obtained by multiplying the monitoring clock period (or the reciprocal of the monitoring clock frequency) by the reference coefficient value K can be set to be the same.
[0046] If the state machine (140) does not receive an enable acknowledgment signal (ACK) corresponding to the enable request signal (REQ) after the transmission time of the enable request signal (REQ), it may operate a gating detection counter and wait for an enable acknowledgment signal (ACK) from the synchronizer (150) until the set gating detection time of the gating detection counter expires. When an enable acknowledgment signal (ACK) is received from the synchronizer (150) in response to the enable request signal (REQ), the state machine (140) determines that clock gating has not been performed for the monitoring clock and may not generate a clock gating error signal. In this case, the state machine (140) does not operate the gating detection counter.
[0047] The synchronizer (150) can operate in synchronization with the monitoring clock. The synchronizer (150) acts as a buffer between two domains with different clock frequencies and can ensure the reliability of signal transmission by stably synchronizing asynchronous signals to transmit signals between them. When the monitoring clock is input, the synchronizer (150) can output an enable acknowledgment signal (ACK) for an enable request signal (REQ) received from the state machine (140) to the state machine (140).
[0048] Since the synchronizer (150) is synchronized with the monitoring clock and operates by the monitoring clock, it can operate so as not to output an enable acknowledgment signal (ACK) corresponding to an enable request signal (REQ) received from the state machine (140) to the state machine (140) when the monitoring clock is not being input. Therefore, since the synchronizer (150) does not send a response of an enable acknowledgment signal (ACK) corresponding to the enable request signal (REQ) to the state machine (140) when the monitoring clock is blocked to a low level state by clock gating, the state machine (140) can monitor whether the monitoring clock is clock gating depending on whether there is a response to the enable acknowledgment signal (ACK) corresponding to the enable request signal (REQ) of the synchronizer (150). According to an embodiment of the present invention, gating detection of the monitoring clock can be efficiently performed by using a synchronizer (150) that operates in synchronization with the monitoring clock and by using a method of comparing the signal levels of an enable request signal (REQ) and an enable acknowledgment signal (ACK).
[0049] The state machine (140) can generate a clock gating error signal related to the gating of the monitoring clock depending on whether it receives an enable acknowledgment signal (ACK) from the synchronizer (150). The state machine (140) can generate a clock gating error signal if, after transmitting an enable request signal (REQ) to the synchronizer (150), an enable acknowledgment signal (ACK) corresponding to the enable request signal (REQ) is not received from the synchronizer (150) until the set gating detection time expires (steps S20 and S30 of FIG. 6).
[0050] For example, the state machine (140) can generate a clock gating error signal when the set gating detection time of the gating detection counter expires while the enable acknowledgment signal (ACK) corresponding to the enable request signal (REQ) from the synchronizer (150) is not received (step S40 of FIG. 6). The gating detection time of the gating detection counter can be set shorter than the monitoring period (monitoring period) of the clock frequency error of the monitoring clock. Accordingly, the gating error of the monitoring clock can be monitored quickly.
[0051] The state machine (140) can generate and output a clock gating error signal before the expiration of the reference clock count of the reference clock counter (110) when the set clock gating error monitoring period elapses (gating detection time elapses). For example, the state machine (140) can send an enable request signal (REQ) to the synchronizer (150) at one or more gating monitoring points within the monitoring period and check whether an enable acknowledgment signal (ACK) corresponding to the enable request signal (REQ) is received from the synchronizer (150). The state machine (140) can output a clock gating error signal if the enable acknowledgment signal (ACK) corresponding to the enable request signal (REQ) is not received within the set period.
[0052] FIG. 7a is an example diagram illustrating the operation of a clock monitoring device when the monitoring clock is not clock-gated during the monitoring period. Referring to FIG. 5 and FIG. 7a, the state machine (140) is at the monitoring start time (T) when the monitoring period begins. 11 ) can output an enable request signal (REQ) to the synchronizer (150). If the monitoring clock is not gated, the synchronizer (150) can output an enable request signal (REQ) to the synchronizer (150) at the monitoring start time (T 11In response to a high-level enable request signal (an enable request signal transitioning from a low level to a high level) (REQ) received from the state machine (140) at ) the monitoring start response time (T 21 A high-level enable acknowledgment signal (an enable acknowledgment signal that transitions from a low level to a high level) (ACK) can be output to the state machine (140).
[0053] For example, as illustrated in FIG. 7a, when the enable request signal (REQ) is a high-level signal, the corresponding enable acknowledgment signal (ACK) is also a high-level signal, and conversely, when the enable request signal (REQ) is a low-level signal, the corresponding enable acknowledgment signal (ACK) may also be a low-level signal. As another example, it is also possible to set the enable acknowledgment signal (ACK) corresponding to the high-level enable request signal (REQ) to a low-level signal, and the enable acknowledgment signal (ACK) corresponding to the low-level enable request signal (REQ) to a high-level signal.
[0054] If the monitoring clock is not gated, the synchronizer (150) can transition between a low level and a high level to generate an enable acknowledgment signal (ACK). The synchronizer (150) monitors at the start time (T 11 In response to a high-level enable request signal (REQ) received from the state machine (140) at ) monitoring start response time (T 21 A high-level enable acknowledgment signal (ACK) can be output to the state machine (140). When the enable request signal (REQ) is received, if the monitoring clock is not gated, the synchronizer (150) can transition between a low level and a high level to generate an enable acknowledgment signal (ACK).
[0055] The state machine (140) is the monitoring end point (T) when the monitoring cycle ends. 12At ), a low-level enable request signal (REQ) can be output to the synchronizer (150). At this time, if the monitoring clock is not gated, the synchronizer (150) at the monitoring end time (T 12 In response to a low-level enable request signal (an enable request signal transitioning from a high level to a low level) (REQ) received from the state machine (140) at ) the monitoring end response time (T 22 A low-level enable acknowledgment signal (an enable acknowledgment signal transitioning from a high level to a low level) (ACK) can be output to the state machine (140).
[0056] The state machine (140) can determine the clock gating error state of the monitoring clock by comparing the enable request signal (REQ) and the enable acknowledgment signal (ACK) that responds to the enable request signal (REQ). For example, the state machine (140) can determine that there is no clock gating error of the monitoring clock if the enable request signal (REQ) output to the synchronizer (150) during the monitoring period and the enable acknowledgment signal (ACK) received from the synchronizer (150) in response to the enable request signal (REQ) have the same signal level (either both are high-level signals or both are low-level signals), and in this case, no clock gating error signal is generated.
[0057] FIG. 7b is an example diagram illustrating the operation of a clock monitoring device when the monitoring clock is clock-gated throughout the entire monitoring period. Referring to FIG. 5 and FIG. 7b, when the monitoring clock is in a gated state, the synchronizer (150) at the monitoring start time (T 11 A high-level enable acknowledgment signal (ACK) is not output in response to a high-level enable request signal (REQ) received from the state machine (140), and accordingly, the enable acknowledgment signal (ACK) is maintained at a low level.
[0058] The state machine (140) may activate the gating detection counter if a high-level enable acknowledgment signal (ACK) for a high-level enable request signal (REQ) is not received from the synchronizer (150). The gating detection counter waits for the reception of an enable acknowledgment signal (ACK) corresponding to the enable request signal (REQ) from the synchronizer (150) for a set gating detection time, and the gating detection end time (T) at which the gating detection time of the gating detection counter expires. 31 A clock gating error detection signal can be generated. If it is determined that the monitoring clock is gated, the enable request signal (REQ) and enable acknowledgment signal (ACK) can be reset (initialized) when a new monitoring cycle starts, thereby enabling subsequent clock monitoring.
[0059] FIG. 7c is an example diagram illustrating the operation of a clock monitoring device when the monitoring clock is clock-gated during a monitoring interval within a monitoring cycle. Monitoring start time (T 11 Since the monitoring clock is in an ungated state at ), the synchronizer (150) responds to a high-level enable request signal (REQ) received from the state machine (140) at the monitoring start response time (T 21 A high-level enable acknowledgment signal (ACK) in response to an enable request signal (REQ) can be output to the state machine (140). When an enable acknowledgment signal (ACK) corresponding to the enable request signal (REQ) is received, the state machine (140) does not operate the gating detection counter and moves on to a subsequent monitoring period.
[0060] If the monitoring clock is gated during the monitoring period, the monitoring end time (T 12 In ), a low-level enable request signal (REQ) is output from the state machine (140) to the synchronizer (150), but due to the gated monitoring clock, the synchronizer (150) at the monitoring end time (T 12At ), a low-level enable acknowledgment signal (ACK) in response to a low-level enable request signal (REQ) received from the state machine (140) is not output to the state machine (140), and at the monitoring end time (T 12 It outputs a high-level enable acknowledgment signal (ACK) that does not correspond to a low-level enable request signal (REQ) of ).
[0061] The state machine (140) can determine the clock gating error status of the monitoring clock by comparing an enable request signal (REQ) with an enable acknowledgment signal (ACK) responding to the enable request signal (REQ). If the state machine (140) does not receive a low-level enable acknowledgment signal (ACK) for a low-level enable request signal (REQ) from the synchronizer (150), it can operate a gating detection counter. The gating detection counter [receives] the monitoring end time (T) from the synchronizer (150) during the set gating detection time. 12 Waits for the reception of an enable acknowledgment signal (ACK) corresponding to the enable request signal (REQ) of ), and if the enable acknowledgment signal (ACK) corresponding to the enable request signal (REQ) is not received until the gating detection time of the gating detection counter expires, the gating detection end time (T 32 A clock gating error detection signal can be generated. If it is determined that the monitoring clock is gated, the enable request signal (REQ) and enable acknowledgment signal (ACK) can be reset (initialized) when a new monitoring cycle starts, thereby enabling subsequent clock monitoring.
[0062] Clock gating can be utilized, for example, as a technique to reduce dynamic power consumption by blocking the supply of unnecessary clock signals to reduce power consumption. When clock gating is applied, the corresponding clock becomes a blocked state corresponding to a low level. According to an embodiment of the present invention, when clock gating is applied to a monitoring clock, a clock gating error signal is output, thereby enabling real-time detection of not only the clock frequency of the monitoring clock but also the clock gating status.
[0063] FIG. 8 is a configuration diagram showing a comparator that constitutes a clock monitoring device according to an embodiment of the present invention. Referring to FIG. 8, the comparator (130) may include a first comparator (131) that compares a monitoring count value with an upper limit value corresponding to a first reference count value at a monitoring point in which the reference clock is counted by a set count value, a second comparator (132) that compares a monitoring count value with a lower limit value corresponding to a second reference count value at a monitoring point in time, and an error determination unit (133) that outputs an error signal corresponding to an upper limit error or a lower limit error according to the comparison result of the first comparator (131) and the second comparator (132). In the embodiment, the error determination unit (133) may include a logic operator (OR operator or NOR operator) that outputs an error signal by performing a logic OR operation or a logic NOR operation on the first comparison value of the first comparator (131) and the second comparison value of the second comparator (132).
[0064] The first comparator (131) can output a first logic value (e.g., a logic '1' value) if the monitoring count value counted for the monitoring clock at the monitoring time exceeds an upper limit value, and output a second logic value (e.g., a logic '0' value) if the monitoring count value counted for the monitoring clock at the monitoring time does not exceed an upper limit value. The upper limit value can be set to an integer value.
[0065] The second comparator (132) can output a first logic value (e.g., a logic '1' value) if the monitoring count value counted for the monitoring clock at the monitoring time is less than the lower limit value, and output a second logic value (e.g., a logic '0' value) if the monitoring count value counted for the monitoring clock at the monitoring time is greater than or equal to the lower limit value. The lower limit value can be set to an integer value that is 1 less than the upper limit value.
[0066] In an embodiment, the error determiner (133) may include a logic operator (OR operator or NOR operator) that outputs an error signal by performing a logic OR operation or a logic NOR operation on the first comparison value of the first comparator (131) and the second comparison value of the second comparator (132). The error determiner (133) may not output an error signal or may output a normal signal if the output value of the first comparator (131) and the output value of the second comparator (132) are the second logic values.
[0067] The error detector (133) can output an error signal if the output value of the first comparator (131) or the output value of the second comparator (132) is the first logic value. If the first logic value and the second logic value are set to logic '1' values, the error detector (133) can be implemented as an OR gate that performs an OR operation. As another example, if the first logic value and the second logic value are set to logic '0' values, the error detector (133) can be implemented as a NOR gate that performs a NOR operation.
[0068] According to the clock monitoring device and clock monitoring method of the embodiment of the present invention as described above, even if the monitoring clock is gated, monitoring of the gated monitoring clock becomes possible based on whether an enable acknowledgment signal (ACK) for an enable request signal (REQ) is received. Therefore, in addition to the function of monitoring the clock frequency of the monitoring clock through comparison with upper and lower limits for the monitoring clock, it is also possible to detect whether the monitoring clock is in a clock-gated state.
[0069] FIG. 9 is a conceptual diagram illustrating a computing device for executing a clock monitoring method according to an embodiment of the present invention. An exemplary computing device (900) for performing the above-described method and / or embodiment is described. According to one embodiment, the computing device (900) may be implemented using hardware and / or software configured to interact with a user. Here, the computing device (900) may include, but is not limited to, a laptop, a desktop, a workstation, a personal digital assistant, a server, a blade server, a main frame, etc. The components of the above-described computing device (1300), their connection relationships, and their functions are intended to be exemplary and are not intended to limit the embodiments of the present invention described and / or claimed herein.
[0070] The computing device (900) includes a processor (910), memory (920), storage device (930), communication device (940), a high-speed interface (950) connected to the memory (920) and a high-speed expansion port, and a low-speed interface (960) connected to a low-speed bus and storage device. Each of the components (910, 920, 930, 940, 950 and 960) may be interconnected using various buses and may be mounted on the same main board or connected in other suitable ways. The processor (910) may be configured to process instructions of a computer program by performing basic arithmetic, logic, and input / output operations. For example, the processor (910) may process instructions stored in memory (920), storage device (930), etc., and / or instructions executed within the computing device (900) to display graphic information on an external input / output device (970), such as a display device coupled to the high-speed interface (950).
[0071] The communication device (940) may provide a configuration or function for the input / output device (970) and the computing device (900) to communicate with each other via a network, and may provide a configuration or function to support the input / output device (970) and / or the computing device (900) communicating with other external devices, etc. For example, a request or data generated by the processor of an external device according to any program code may be transmitted to the computing device (900) via a network under the control of the communication device (940). Conversely, a control signal or command provided under the control of the processor (910) of the computing device (900) may be transmitted to another external device via the communication device (940) and the network.
[0072] In the illustration, the computing device (900) is described as including one processor (910), one memory (920), etc., but is not limited thereto, and the computing device (900) may be implemented using multiple memories, multiple processors and / or multiple buses, etc. Additionally, in the illustration, it is described as having one computing device (900), but is not limited thereto, and multiple computing devices may interact and perform operations necessary to execute the method described above.
[0073] Memory (920) can store information within a computing device (900). According to one embodiment, memory (920) may be composed of a volatile memory unit or a plurality of memory units. Additionally or alternatively, memory (920) may be composed of a non-volatile memory unit or a plurality of memory units. Furthermore, memory (920) may be composed of other forms of computer-readable media, such as a magnetic disk or an optical disk. Additionally, memory (920) may store an operating system and at least one program code and / or instruction.
[0074] The storage device (930) may be one or more mass storage devices for storing data for the computing device (900). For example, the storage device (930) may be a computer-readable medium including a magnetic disc such as a hard disk or removable disk, an optical disc, a semiconductor memory device such as an EPROM (Erasable Programmable Read-Only Memory), an EEPROM (Electrically Erasable PROM), or a flash memory device, or may be configured to include such a computer-readable medium. Additionally, a computer program may be tangibly implemented on such a computer-readable medium.
[0075] The high-speed interface (950) and the low-speed interface (960) may be means for interaction with an input / output device (970). For example, the input device may include a device such as a camera including an audio sensor and / or an image sensor, a keyboard, a microphone, a mouse, etc., and the output device may include a device such as a display, a speaker, a haptic feedback device, etc. In another example, the high-speed interface (950) and the low-speed interface (960) may be means for interfacing with a device in which the configuration or function for performing input and output is integrated into one, such as a touchscreen, etc.
[0076] According to one embodiment, the high-speed interface (950) manages bandwidth-intensive operations for the computing device (900), while the low-speed interface (960) may manage less bandwidth-intensive operations than the high-speed interface (950), but such function assignments are merely exemplary. According to one embodiment, the high-speed interface (950) may be coupled to high-speed expansion ports capable of accommodating memory (920), an input / output device (970), and various expansion cards (not shown). Additionally, the low-speed interface (960) may be coupled to a storage device (930) and a low-speed expansion port. Furthermore, the low-speed expansion port, which may include various communication ports (e.g., USB, Bluetooth, Ethernet, wireless Ethernet), may be coupled to one or more input / output devices (970), such as a keyboard, a pointing device, or a scanner, or to a networking device such as a router or a switch via a network adapter.
[0077] The computing device (900) may be implemented in a number of different forms. For example, the computing device (900) may be implemented as a standard server or as a group of such standard servers. Additionally or alternatively, the computing device (900) may be implemented as part of a rack server system or as a personal computer such as a laptop computer. In this case, components from the computing device (900) may be combined with other components within any mobile device (not shown). The computing device (900) may include one or more other computing devices or be configured to communicate with one or more other computing devices.
[0078] In the drawing, the input / output device (970) is depicted as not being included in the computing device (900), but is not limited thereto and may be configured as a single device with the computing device (900). Additionally, the high-speed interface (950) and / or low-speed interface (960) are depicted as elements configured separately from the processor (910), but are not limited thereto and the high-speed interface (950) and / or low-speed interface (960) may be configured to be included in the processor (910).
[0079] The methods and / or various embodiments described above may be realized in digital electronic circuits, computer hardware, firmware, software, and / or combinations thereof. Various embodiments of the present invention may be executed by a data processing device, for example, one or more programmable processors and / or one or more computing devices, or implemented as a computer program stored on a computer-readable medium and / or on a computer-readable medium. The computer program described above may be written in any form of programming language, including a compiled language or an interpreted language, and may be distributed in any form, such as a standalone program, a module, or a subroutine. The computer program may be distributed through a single computing device, a plurality of computing devices connected through the same network, and / or a plurality of computing devices distributed to be connected through a plurality of different networks.
[0080] The above-described methods and / or various embodiments may be performed by one or more processors configured to execute one or more computer programs that process, store, and / or manage any functions, functions, etc. by operating based on input data or generating output data. For example, the methods and / or various embodiments of the present invention may be performed by special-purpose logic circuits such as a Field Programmable Gate Array (FPGA) or an Application Specific Integrated Circuit (ASIC), and an apparatus and / or system for performing the methods and / or embodiments of the present invention may be implemented as a special-purpose logic circuit such as an FPGA or an ASIC.
[0081] One or more processors executing a computer program may include one or more processors of a general-purpose or special-purpose microprocessor and / or any type of digital computing device. The processor may receive instructions and / or data from each of read-only memory and random access memory, or receive instructions and / or data from read-only memory and random access memory. In the present invention, components of a computing device performing the methods and / or embodiments may include one or more processors for executing instructions and one or more memories for storing instructions and / or data.
[0082] According to one embodiment, a computing device may exchange data with one or more mass storage devices for storing data. For example, the computing device may receive and / or receive data from a magnetic disc or an optical disc, and may transfer data to a magnetic disc or an optical disc. A computer-readable medium suitable for storing instructions and / or data associated with a computer program may include, but is not limited to, any form of non-volatile memory including semiconductor memory devices such as EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable PROM), and flash memory devices. For example, the computer-readable medium may include magnetic discs such as internal hard disks or removable disks, photomagnetic discs, CD-ROMs, and DVD-ROMs.
[0083] To provide interaction with a user, the computing device may include, but is not limited to, a display device for providing or displaying information to the user (e.g., CRT (Cathode Ray Tube), LCD (Liquid Crystal Display), etc.) and a pointing device (e.g., keyboard, mouse, trackball, etc.) on which the user can provide input and / or commands, etc. on the computing device. That is, the computing device may further include any other type of device for providing interaction with the user. For example, the computing device may provide any form of sensory feedback to the user for interaction with the user, including visual feedback, auditory feedback and / or tactile feedback. In this regard, the user may provide input to the computing device through various gestures such as visual, vocal, and motion.
[0084] In the present invention, various embodiments may be implemented in a computing device comprising back-end components (e.g., data servers), middleware components (e.g., application servers), and / or front-end components. In this case, the components may be interconnected by any form or medium of digital data communication, such as a communication network. According to one embodiment, the communication network may be composed of a wired network such as Ethernet, Power Line Communication, telephone line communication devices, and RS-serial communication, a mobile communication network, a Wireless LAN (WLAN), a wireless network such as Wi-Fi, Bluetooth, and ZigBee, or a combination thereof. For example, the communication network may include a Local Area Network (LAN), a Wide Area Network (WAN), etc.
[0085] A computing device based on the exemplary embodiments described herein may be implemented using hardware and / or software configured to interact with a user, including a user device, a user interface (UI) device, a user terminal, or a client device. For example, the computing device may include a portable computing device such as a laptop computer. Additionally or alternatively, the computing device may include, but is not limited to, Personal Digital Assistants (PDAs), tablet PCs, game consoles, wearable devices, Internet of Things (IoT) devices, Virtual Reality (VR) devices, Augmented Reality (AR) devices, etc. The computing device may further include other types of devices configured to interact with a user. Additionally, the computing device may include a portable communication device suitable for wireless communication over a network such as a mobile communication network (e.g., a mobile phone, a smartphone, a wireless cellular phone, etc.). A computing device may be configured to communicate wirelessly with a network server using wireless communication technologies and / or protocols such as radio frequency (RF), microwave frequency (MWF) and / or infrared frequency (IRF).
[0086] Various embodiments of the present invention, including specific structural and functional details, are exemplary. Accordingly, the embodiments of the present invention are not limited to those described above and may be implemented in various other forms. Furthermore, the terms used in the present invention are intended to describe some embodiments and are not to be interpreted as limiting the embodiments. For example, a singular word may be interpreted to include the plural form unless the context clearly indicates otherwise.
[0087] In this invention, unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as generally understood by those skilled in the art to which such concepts belong. Furthermore, commonly used terms, such as those defined in advance, should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology.
[0088] Although the present invention has been described in relation to some embodiments, various modifications and changes may be made without departing from the scope of the invention as understood by a person skilled in the art to which the invention pertains. Furthermore, such modifications and changes should be considered to fall within the scope of the claims appended to this specification.
Claims
1. A reference clock counter that counts the clock of the reference clock; A monitoring clock counter that counts the clock of the monitoring clock being monitored; A comparator that detects an error in the monitoring clock by comparing the monitoring count value counted for the monitoring clock by the monitoring clock counter with the set reference count value at a monitoring point in time when the reference clock is counted by a count value set by the reference clock counter; A state machine that generates an enable request signal to detect gating of the monitoring clock in an enable state in which monitoring of the monitoring clock is performed; and A synchronizer that operates in synchronization with the above monitoring clock and outputs an enable confirmation signal for the above enable request signal to the state machine; The state machine is configured to generate a clock gating error signal related to the gating of the monitoring clock depending on whether the enable confirmation signal corresponding to the enable request signal is received. Clock monitoring device.
2. In Claim 1, The above state machine is, A device configured to generate the clock gating error signal if, after transmitting the enable request signal to the synchronizer, the enable confirmation signal corresponding to the enable request signal is not received from the synchronizer until the set gating detection time expires. Clock monitoring device.
3. In Claim 2, The above state machine is, If the enable confirmation signal corresponding to the enable request signal is not received from the synchronizer, the gating detection counter is operated, and when the set gating detection time of the gating detection counter expires, the clock gating error signal is generated. Clock monitoring device.
4. In Claim 2, The above state machine is A first enable request signal at the monitoring start time when the monitoring cycle begins, and a signal level of the first enable confirmation signal of the synchronizer for the first enable request signal are compared to determine a gating error of the monitoring clock at the monitoring start time; Determining a gating error of the monitoring clock at the monitoring end time by comparing the signal level of a second enable request signal at the monitoring end time when the monitoring cycle ends and the second enable confirmation signal of the synchronizer for the second enable request signal. Clock monitoring device.
5. In Claim 1, The above comparator is, A first comparator that compares the monitoring coefficient value with an upper limit value corresponding to a first reference coefficient value at the above monitoring point; At the above monitoring point, a second comparator that compares the monitoring coefficient value with a lower limit value corresponding to a second reference coefficient value; and An error determination unit that outputs an error signal corresponding to an upper limit error or a lower limit error according to the comparison result of the first comparator and the second comparator; A clock monitoring device including 6. In Claim 5, The above error determiner is, A logic operator that outputs the error signal by performing a logical OR operation or a logical NOR operation on the first comparison value of the first comparator and the second comparison value of the second comparator; A clock monitoring device including 7. A step of counting the clock of the reference clock by the reference clock counter; A step of counting the clock of the monitoring clock to be monitored by a monitoring clock counter; A step of detecting an error in the monitoring clock by comparing the monitoring count value counted for the monitoring clock by the monitoring clock counter with the set reference count value at a monitoring point in time when the reference clock is counted by the reference clock counter by the comparator; A step of generating an enable request signal to detect gating of the monitoring clock in an enable state in which monitoring of the monitoring clock is performed by a state machine; A step of operating in synchronization with the monitoring clock by means of a synchronizer to output an enable confirmation signal for the enable request signal to the state machine; and A step of generating a clock gating error signal related to the gating of the monitoring clock according to whether the enable confirmation signal corresponding to the enable request signal is received by the state machine; A clock monitoring method including 8. In Claim 7, The step of generating the above clock gating error signal is, A step of generating the clock gating error signal if, after the state machine transmits the enable request signal to the synchronizer, the enable confirmation signal corresponding to the enable request signal is not received from the synchronizer until the set gating detection time expires; A clock monitoring method including 9. In Claim 8, The step of generating the above clock gating error signal is, A step of generating the clock gating error signal when the gating detection time of the reference clock counter expires while the enable confirmation signal corresponding to the enable request signal is not received from the synchronizer to the state machine; A clock monitoring method including 10. In Claim 8, The step of generating the above clock gating error signal is, A step of determining a gating error of the monitoring clock at the monitoring start time by comparing the signal level of a first enable request signal at the monitoring start time when the monitoring cycle begins and a first enable confirmation signal of the synchronizer for the first enable request signal; and A step of determining a gating error of the monitoring clock at the monitoring termination point by comparing the signal level of a second enable request signal at the monitoring termination point when the monitoring cycle ends with the signal level of a second enable confirmation signal of the synchronizer for the second enable request signal; A clock monitoring method including 11. In Claim 7, The step of detecting an error in the above-mentioned monitoring clock is, A step of comparing the monitoring coefficient value with an upper limit value corresponding to a first reference coefficient value at the monitoring point by means of a first comparator; A step of comparing the monitoring coefficient value with a lower limit value corresponding to a second reference coefficient value at the monitoring point by means of a second comparator; and A step of outputting an error signal corresponding to an upper limit error or a lower limit error according to the comparison result of the first comparator and the second comparator by an error determination unit; A clock monitoring method including 12. In Claim 11, The step of outputting the above error signal is, A clock monitoring method comprising the step of outputting the error signal by performing a logical OR operation or a logical NOR operation on the first comparison value of the first comparator and the second comparison value of the second comparator by a logical operation unit.
13. A computer-readable non-transient recording medium having a computer program for executing the clock monitoring method of claim 7.