Laser bonding device, laser bonding method, and electronic device

Abstract

Provided are a laser bonding device, a laser bonding method, and an electronic device. According to an embodiment, the laser bonding apparatus comprises: a stage for supporting a first substrate; a pressing module for fixing a plurality of elements disposed on the first substrate, the elements being at least one of a light-emitting element, an integrated circuit, and a driving circuit; a laser emitter for emitting a laser beam to a conductive adhesive pattern disposed between the first substrate and the plurality of elements; and a mask disposed on the upper portion of the first substrate and having openings overlapping the plurality of elements. The laser emitter may emit a laser beam of first power for a first period of time and may emit a laser beam of second power higher than the first power for a second period of time.

Description

Laser bonding device, laser bonding method and electronic device

[0001] The present invention relates to a laser bonding device, a laser bonding method, and an electronic device.

[0002] As the information society develops, the demand for display devices to display images is increasing in various forms. Display devices may be flat panel displays such as Liquid Crystal Displays, Field Emission Displays, and Light Emitting Displays.

[0003] The light-emitting display device may include an organic light-emitting display device comprising an organic light-emitting diode element as a light-emitting element, and a micro light-emitting display device comprising a micro light-emitting diode element (hereinafter referred to as a micro light-emitting element) as a light-emitting element. Since the micro light-emitting diode element is made of inorganic material, it has the advantage of having a long lifespan with fewer degradation issues compared to organic light-emitting diode elements.

[0004] In the manufacturing process of a light-emitting display device, a process of bonding ultra-small light-emitting diode elements and electronic components to a display panel is required.

[0005] The problem that the present invention aims to solve is to provide a laser bonding apparatus and a laser bonding method using a conductive adhesive pattern that can minimize thermal damage to a backplane substrate during the bonding process.

[0006] The problems of the present invention are not limited to the technical problems mentioned above, and other unmentioned technical problems will be clearly understood by those skilled in the art from the description below.

[0007] A laser bonding device for solving the above problem comprises a stage supporting a first substrate, a pressure module for fixing a plurality of elements disposed on the first substrate (the elements are one or more of a light-emitting element, an integrated circuit, and a driving circuit), a laser irradiator for irradiating a laser beam onto a conductive adhesive pattern disposed between the first substrate and the plurality of elements, and a mask disposed on the upper part of the first substrate and having openings that overlap with the plurality of elements, wherein the laser irradiator can irradiate a laser beam of a first power for a first time period and irradiate a laser beam of a second power higher than the first power for a second time period.

[0008] In one embodiment, the conductive adhesive pattern may each include a polymer resin and conductive nanoparticles dispersed in the polymer resin.

[0009] In one embodiment, the conductive nanoparticles may be conductive carbon black.

[0010] In one embodiment, the height of the conductive adhesive pattern may be 1 μm or less.

[0011] In one embodiment, the mask may include a light-blocking or reflective material in an area other than the opening.

[0012] In one embodiment, the laser irradiator may be configured to enable area heating over a predetermined area.

[0013] In one embodiment, the laser irradiator can heat the process temperature to 140°C by irradiating a laser beam with a first power for a first time, and heat the process temperature to 260°C by irradiating a laser beam with a second power for a second time.

[0014] In one embodiment, a first electrode is disposed on the first substrate, a conductive adhesive pattern is disposed on the first electrode, and the openings of the mask may overlap with the conductive adhesive pattern.

[0015] In one embodiment, the light-emitting element includes a contact electrode disposed on one surface and a plurality of semiconductor layers disposed on the contact electrode, and the contact electrode may be disposed on the conductive adhesive pattern and electrically connected.

[0016] A laser bonding method according to another embodiment comprises the steps of forming a first electrode on a first substrate, forming a conductive adhesive pattern on the first electrode, and placing an element on the conductive adhesive pattern (the element being one or more of a light-emitting element, an integrated circuit, and a driving circuit); a laser irradiator irradiates the conductive adhesive pattern with a laser beam of a first power for a first time period and irradiates the conductive adhesive pattern with a laser beam of a second power higher than the first power for a second time period, and a mask having openings overlapping with a plurality of elements may be placed on the first substrate prior to the step of irradiating the laser beam of a second power higher than the first power for a second time period.

[0017] In one embodiment, the conductive adhesive pattern may each include a polymer resin and conductive nanoparticles dispersed in the polymer resin.

[0018] In one embodiment, the conductive nanoparticles may be conductive carbon black.

[0019] In one embodiment, in the step of forming the conductive adhesive pattern, a conductive adhesive material is applied to the front surface of the substrate to cover the first electrode, and the conductive adhesive pattern can be formed by patterning using a mask through a photolithography process.

[0020] In one embodiment, a pressurizing member is positioned between a laser irradiator and the light-emitting element and can pressurize the light-emitting element while irradiating the laser.

[0021] In one embodiment, the pressing member may press until the height of each conductive adhesive pattern becomes 1 μm or less.

[0022] In one embodiment, the mask may include a light-blocking or reflective material in an area other than the opening.

[0023] In one embodiment, the laser irradiator can perform area heating over a predetermined area.

[0024] In one embodiment, the laser irradiator can heat the process temperature to 140°C by irradiating a laser beam with a first power for a first time, and heat the process temperature to 260°C by irradiating a laser beam with a second power for a second time.

[0025] In one embodiment, in the step of placing an element on the conductive adhesive pattern, the light-emitting element is placed on a second substrate, and the contact electrode of the light-emitting element can be placed to face the conductive adhesive pattern.

[0026] In one embodiment, after the laser irradiation is completed, the second substrate can be separated from the light-emitting element and removed.

[0027] Specific details of other embodiments are included in the detailed description and drawings.

[0028] According to the laser bonding apparatus and method of the embodiments, thermal damage to the backplane substrate during the laser bonding process can be minimized.

[0029] The effects according to the embodiments are not limited to those exemplified above, and a wider variety of effects are included in this specification.

[0030] FIG. 1 is a perspective view showing a display device according to one embodiment.

[0031] FIG. 2 is a layout diagram showing a display device according to one embodiment.

[0032] FIG. 3 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to line I-I' of FIG. 2.

[0033] FIG. 4 is a block diagram showing a display device according to one embodiment.

[0034] FIG. 5 is an equivalent circuit diagram showing a subpixel according to one embodiment.

[0035] FIG. 6 is a layout diagram showing pixels of a display area according to one embodiment.

[0036] FIG. 7 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to the line II-II' of FIG. 6.

[0037] Figure 8 is a cross-sectional view showing in detail an example of area A of Figure 7.

[0038] FIG. 9 is a layout diagram showing pixels of a display area according to one embodiment.

[0039] FIG. 10 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to the line I2-I2' of FIG. 9.

[0040] Figure 11 is a cross-sectional view showing in detail an example of area B of Figure 10.

[0041] FIG. 12 is a diagram schematically illustrating the configuration of a laser bonding device according to one embodiment.

[0042] FIG. 13 is a plan view for schematically illustrating a mask according to one embodiment.

[0043] FIG. 14 is a method for explaining a method for manufacturing a display device using a conductive adhesive pattern.

[0044] FIGS. 15 to 18 are step-by-step cross-sectional views for explaining a method of manufacturing a display device according to one embodiment.

[0045] FIG. 19 is a graph showing the laser temperature according to time and the laser power of a laser bonding device according to one embodiment.

[0046] FIG. 20 is a cross-sectional view illustrating a method for manufacturing a display device according to one embodiment.

[0047] FIG. 21 is a diagram illustrating the bonding state according to the bonding temperature and bonding pressure in a bonding process by a laser bonding device according to one embodiment.

[0048] FIGS. 22 and FIGS. 23 are exemplary drawings showing a smart watch including a display device according to one embodiment.

[0049] FIG. 24 is an exploded perspective view of a smart watch including a display device according to one embodiment.

[0050] FIG. 25 is an exemplary drawing showing a virtual reality device including a display device according to one embodiment.

[0051] FIG. 26 is an example drawing showing a virtual reality device including a display device according to another embodiment.

[0052] FIG. 27 is an exemplary drawing showing an automobile instrument panel and center fascia including display devices according to one embodiment.

[0053] FIG. 28 is an exemplary drawing showing a transparent display device including a display device according to one embodiment.

[0054] The advantages and features of the present invention and the methods for achieving them will become clear by referring to the embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below but may be implemented in various different forms. These embodiments are provided merely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims.

[0055] When elements or layers are referred to as being "on" another element or layer, this includes cases where another layer or element is interposed directly on or in the middle of another element. Throughout the specification, the same reference numerals refer to the same components. Shapes, sizes, ratios, angles, numbers, etc., disclosed in the drawings for describing embodiments are exemplary and therefore the invention is not limited to the depicted details.

[0056] The features of each of the various embodiments of the present invention may be combined or combined with one another, either partially or wholly, and may technically enable various interlocking and operation. Each embodiment may be implemented independently of one another or may be implemented together in an associated relationship.

[0057] Specific embodiments will be described below with reference to the attached drawings.

[0058] FIG. 1 is a perspective view showing a display device according to one embodiment.

[0059] Referring to FIG. 1, the display device (10) is a device for displaying video or still images and can be used as a display screen for various products such as televisions, laptops, monitors, billboards, and the Internet of Things (IOT), as well as portable electronic devices such as mobile phones, smartphones, tablet PCs, smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, PMPs (portable multimedia players), navigation systems, and UMPCs (Ultra Mobile PCs).

[0060] The display device (10) may be a light-emitting display device such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a micro light-emitting display device using a micro or nano light-emitting diode (micro LED or nano LED). Hereinafter, the display device (10) has been described with a focus on being a micro light-emitting display device, but the present invention is not limited thereto. Meanwhile, for convenience of explanation, a micro light-emitting diode has been described as a light-emitting element below.

[0061] The display device (10) includes a display panel (100), a display driving circuit (250), a circuit board (300), and a power supply circuit (500).

[0062] The display panel (100) may be formed as a rectangular plane having a short side in a first direction (DR1) and a long side in a second direction (DR2) that intersects the first direction (DR1). The corner where the short side in the first direction (DR1) and the long side in the second direction (DR2) meet may be formed rounded to have a predetermined curvature or formed at a right angle. The plane shape of the display panel (100) is not limited to a rectangle and may be formed as other polygons, circles, or ellipses. The display panel (100) may be formed flat, but is not limited thereto. For example, the display panel (100) may include curved surfaces formed at the left and right ends that have a constant curvature or a changing curvature. In addition, the display panel (100) may be formed flexibly so that it can be bent, curved, folded, or rolled.

[0063] The display panel (100) may include a main area (MA) and a sub area (SBA).

[0064] The main area (MA) may include a display area (DA) that displays an image and a non-display area (NDA) which is a surrounding area of ​​the display area (DA). The display area (DA) may include a plurality of pixels that display an image. Each of the pixels may include a plurality of subpixels. For example, each of the pixels may include a first subpixel that emits a first light, a second subpixel that emits a second light, and a third subpixel that emits a third light, but the embodiments of the present specification are not limited thereto.

[0065] A sub-region (SBA) may protrude in a second direction (DR2) from one side of a main region (MA). Although FIG. 1 illustrates a sub-region (SBA) unfolded, the sub-region (SBA) may be bent, in which case it may be placed on the lower surface of the display panel (100). When the sub-region (SBA) is bent, it may overlap with the main region (MA) in a third direction (DR3), which is the thickness direction of the display panel (100). A display driving circuit (250) may be placed in the sub-region (SBA).

[0066] The display driving circuit (250) can generate signals and voltages to drive the display panel (100). The display driving circuit (250) may be formed as an integrated circuit (IC) and attached to the display panel (100) using a COG (chip on glass) method, a COP (chip on plastic) method, or an ultrasonic bonding method, but is not limited thereto. For example, the display driving circuit (250) may be attached to the circuit board (300) using a COF (chip on film) method.

[0067] A circuit board (300) can be attached to one end of a sub-region (SBA) of a display panel (100). As a result, the circuit board (300) can be electrically connected to the display panel (100) and the display driving circuit (250). The display panel (100) and the display driving circuit (250) can receive digital video data, timing signals, and driving voltages through the circuit board (300). The circuit board (300) may be a flexible printed circuit board, a printed circuit board, or a flexible film such as a chip-on-film.

[0068] The power supply circuit (500) can generate a plurality of panel driving voltages according to the power supply voltage from the outside. The power supply circuit (500) can be formed as an integrated circuit (IC) and attached to the circuit board (300) in a COF manner. In one embodiment, with reference to FIG. 1, an example is shown in which the power supply circuit (500) is placed on the circuit board (300) in a COF manner as an integrated circuit package, but this is not limited thereto, and each integrated circuit (IC) can be placed directly on the display panel. In addition, in this case, since the size of the integrated circuit (IC) becomes very small, the integrated circuit (IC) can be placed not only in the pad area (PA) but also in the display area (DA).

[0069] FIG. 2 is a layout diagram showing a display device according to one embodiment. FIG. 2 illustrates a sub-region (SBA) that is unfolded without being bent.

[0070] Referring to FIG. 2, the display panel (100) may include a main area (MA) and a sub area (SBA).

[0071] The main area (MA) may include a display area (DA) for displaying an image and a non-display area (NDA) which is the surrounding area of ​​the display area (DA). The display area (DA) may occupy most of the main area (MA). The display area (DA) may be positioned in the center of the main area (MA).

[0072] A display area (DA) includes a plurality of pixels (PX) for displaying an image, and each of the plurality of pixels (PX) may include a plurality of subpixels (SPX). A pixel (PX) may be defined as a minimum unit of subpixel group capable of expressing a white gradation.

[0073] The non-display area (NDA) may be positioned adjacent to the display area (DA). The non-display area (NDA) may be an outer area of ​​the display area (DA). The non-display area (NDA) may be positioned to surround the display area (DA). The non-display area (NDA) may be an edge area of ​​the display panel (100).

[0074] The first scan driver (SDC1) and the second scan driver (SDC2) may be placed in a non-display area (NDA). The first scan driver (SDC1) may be placed on one side (e.g., the left side) of the display panel (100), and the second scan driver (SDC2) may be placed on the other side (e.g., the right side) of the display panel, but is not limited thereto. Each of the first scan driver (SDC1) and the second scan driver (SDC2) may be electrically connected to the display driving circuit (250) through scan fan-out lines. Each of the first scan driver (SDC1) and the second scan driver (SDC2) may receive a scan control signal from the display driving circuit (250), generate scan signals according to the scan control signal, and output them to the scan lines.

[0075] A sub-region (SBA) may protrude in a second direction (DR2) from one side of a main region (MA). The length of the second direction (DR2) of the sub-region (SBA) may be shorter than the length of the second direction (DR2) of the main region (MA). The length of the first direction (DR1) of the sub-region (SBA) may be shorter than the length of the first direction (DR1) of the main region (MA) or substantially equal to the length of the first direction (DR1) of the main region (MA). The sub-region (SBA) may be bent and may be positioned at the bottom of the display panel (100). In this case, the sub-region (SBA) may overlap with the main region (MA) in a third direction (DR3).

[0076] The sub-region (SBA) may include a connection region (CA), a pad region (PA), and a bending region (BA).

[0077] The connection area (CA) is an area protruding in a second direction (DR2) from one side of the main area (MA). One side of the connection area (CA) is in contact with the non-display area (NDA) of the main area (MA), and the other side of the connection area (CA) may be in contact with the bending area (BA).

[0078] The pad area (PA) is an area where pads (PDs) and a display driving circuit (250) (also referred to as a driving circuit) are placed. The display driving circuit (250) can be attached to the driving pads of the pad area (PA) using a conductive adhesive pattern (CBP). A circuit board (300) can be attached to the pads (PDs) of the pad area (PA) using a conductive adhesive pattern (CBP). One side of the pad area (PA) may be in contact with a bending area (BA). In one embodiment, a circuit board (300) is attached, but is not limited thereto. An integrated circuit (IC) and a sensor can be directly attached to the pads (PDs) of the pad area (PA) using a conductive adhesive pattern (CBP).

[0079] The bending area (BA) is a bending area. When the bending area (BA) is bent, the pad area (PA) may be positioned below the connecting area (CA) and below the main area (MA). The bending area (BA) may be positioned between the connecting area (CA) and the pad area (PA). One side of the bending area (BA) is in contact with the connecting area (CA), and the other side of the bending area (BA) may be in contact with the pad area (PA).

[0080] Figure 3 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to the - ' line of Figure 2.

[0081] Referring to FIGS. 2 and 3, first pads (PDs) and second pads (250-PD) are disposed in the pad area (PA).

[0082] The first pads (PDs) can be bonded to and electrically connected to the circuit board (300) or the integrated circuit (IC) through the conductive adhesive pattern (CBP1). The second pads (250-PDs) can be bonded to and electrically connected to the display driving circuit (250) through the conductive adhesive pattern (CBP1).

[0083] The conductive adhesive pattern (CBP1) may be referred to as the first conductive adhesive pattern (CBP1). In one embodiment, the conductive adhesive pattern (CBP) is disposed on one surface of the first pads (PDs) and the second pad (250-PD). The first conductive adhesive pattern (CBP1) may completely overlap on one surface of each of the first pads (PDs) and the second pad (250-PD). The first conductive adhesive pattern (CBP1) may not be disposed between the first pads (PDs).

[0084] Additionally, the first conductive adhesive pattern (CBP1) may have an area equal to that of the first pads (PDs) and the second pad (250-PD), respectively. For example, the first conductive adhesive pattern (CBP1) may have a rectangular planar shape having a short side equal to the short side of the corresponding first pad (PD) and a long side equal to the long side of the corresponding first pad (PD). Additionally, the first conductive adhesive pattern (CBP1) may have a rectangular planar shape having a short side equal to the short side of the corresponding second pad (250-PD) and a long side equal to the long side of the corresponding second pad (250-PD).

[0085] The thickness (height) of the first conductive adhesive pattern (CBP1), that is, the interface distance (h-CBP1) between the first conductive adhesive pattern (CBP1) and the integrated circuit (IC) (or sensor) corresponding to the first conductive adhesive pattern (CBP1) is about 1 μm or less. If the thickness (height) of the first conductive adhesive pattern (CBP1) is 1 μm or more, a defect may occur in the electrical connection between the first pads (PDs) and the second pad (250-PD) and the integrated circuit (IC) (or sensor).

[0086] The first conductive adhesive pattern (CBP1) may be a conductive adhesive pattern containing conductive nanoparticles (CP).

[0087] The first conductive adhesive pattern (CBP1) may include a polymer resin and conductive nanoparticles (CP) dispersed in the polymer resin. The conductive nanoparticles (CP) are conductive particles with a particle size of 100 nm or less. The resistance of the conductive nanoparticles (CP) is 1 ohm or less. In one embodiment, the conductive nanoparticles (CP) may be conductive carbon black, but are not limited thereto. In addition to carbon black, the conductive nanoparticles (CP) may include one or more of the first materials selected from the group consisting of acetylene black, artificial graphite, natural graphite, copper powder, nickel powder, aluminum powder, indium powder, silver powder, and polyphenylene.

[0088] The polymer resin may be a photosensitive resin (PR), but is not limited thereto. The photosensitive resin (PR) may be an insulating material. As the photosensitive resin (PR), it may be an acrylic resin or a polyimide resin. The first conductive adhesive pattern (CBP1) can be patterned by a photolithography process. Therefore, the first conductive adhesive pattern (CBP1) can be finely patterned and is applicable to high-brightness display panels.

[0089] The first conductive adhesive pattern (CBP1) can be melted at less than 200°C, for example, 140°C, and used as an adhesive.

[0090] FIG. 4 is a block diagram showing a display device according to one embodiment.

[0091] Referring to FIG. 4, the display area (DA) includes a plurality of pixels (PX) (the pixel (PX) includes a plurality of subpixels (SPX)), a plurality of scan lines (SL), a plurality of light emission control lines (EL), and a plurality of data lines (DL).

[0092] Multiple pixels (PX) may be arranged in a matrix form in a first direction (DR1) and a second direction (DR2). For example, multiple pixels (PX) may be arranged in columns and rows of a matrix in the first direction (DR1) and the second direction (DR2). Multiple scan lines (SL) and multiple light emission control lines (EL) may extend in the first direction (DR1) and be arranged in the second direction (DR2). Multiple data lines (DL) may extend in the second direction (DR2) and be arranged in the first direction (DR1). Multiple scan lines (SL) include multiple write scan lines (GWL), multiple control scan lines, multiple initialization scan lines (GIL), and multiple bias scan lines (GBL).

[0093] Each of the plurality of subpixels (SPX) can be connected to one of the plurality of write scan lines (GWL), one of the plurality of control scan lines, one of the plurality of initialization scan lines (GIL), one of the plurality of bias scan lines (GBL), one of the plurality of light emission control lines (EL), and one of the plurality of data lines (DL). Each of the plurality of subpixels (SPX) receives a data voltage of the data line (DL) according to the write scan signal of the write scan line (GWL), and can emit light from the light-emitting element according to the data voltage.

[0094] The non-display area (NDA) includes a first scan drive unit (SDC1), a second scan drive unit (SDC2), and a display drive circuit (250).

[0095] Each of the first scan drive unit (SDC1) and the second scan drive unit (SDC2) may include a write scan signal output unit (611), an initial scan signal output unit (612), a bias scan signal output unit (613), and a light emission control signal output unit (614). Each of the write scan signal output unit (611), the initial scan signal output unit (612), the bias scan signal output unit (613), and the light emission control signal output unit (614) may receive a scan timing control signal (SCS) from the timing control circuit (251).

[0096] The write scan signal output unit (611) can generate write scan signals according to the scan timing control signal (SCS) of the timing control circuit (251) and output them sequentially to the write scan lines (GWL).

[0097] The initialization scan signal output unit (612) can generate initialization scan signals according to the scan timing control signal (SCS) and output them sequentially to the initialization scan lines (GIL).

[0098] The bias scan signal output unit (613) can generate bias scan signals according to the scan timing control signal (SCS) and output them sequentially to the bias scan lines (GBL). The light emission control signal output unit (614) can generate light emission control signals according to the scan timing control signal (SCS) and output them sequentially to the light emission control lines (EL).

[0099] The display driving circuit (250) includes a timing control circuit (251) and a data driving circuit (252).

[0100] The data driving circuit (252) can receive digital video data (DATA) and a data timing control signal (DCS) from the timing control circuit (251). The data driving circuit (252) converts the digital video data (DATA) into analog data voltages according to the data timing control signal (DCS) and outputs them to the data lines (DL). In this case, subpixels (SPX) are selected by the write scan signals of the first scan driving unit (SDC1) and the second scan driving unit (SDC2), and data voltages can be supplied to the selected subpixels (SPX).

[0101] The timing control circuit (251) can receive digital video data (DATA) and timing signals from an external source. The timing control circuit (251) can generate a scan timing control signal (SCS) and a data timing control signal (DCS) to control the display panel (100) according to the timing signals. The timing control circuit (251) can output the scan timing control signal (SCS) to the first scan driving unit (SDC1) and the second scan driving unit (SDC2). The timing control circuit (251) can output the digital video data (DATA) and the data timing control signal (DCS) to the data driving circuit (252).

[0102] The power supply circuit (500) can generate a plurality of panel driving voltages according to the power voltage supplied from the outside. For example, the power supply circuit (500) can generate a first power voltage (VDD), a second power voltage (VSS), a third power voltage (VINT), and a fourth power voltage (VAINT) and supply them to the display panel (100).

[0103] FIG. 5 is an equivalent circuit diagram showing a subpixel according to one embodiment.

[0104] Referring to FIG. 5, a subpixel (SPX) according to one embodiment may be connected to scan lines (GWL, GIL, GBL), a light emission control line (EL), and a data line (DL). For example, the subpixel (SPX) may be connected to a write scan line (GWL), an initialization scan line (GIL), a bias scan line (GBL), a light emission control line (EL), and a data line (DL).

[0105] A subpixel (SPX) according to one embodiment includes a driving transistor (DT), switching elements, a capacitor (C1), and a light-emitting element (LE). The switching elements include first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6).

[0106] The driving transistor (DT) includes a gate electrode, a first electrode, and a second electrode. The driving transistor (DT) controls the drain-source current (Ids, hereinafter referred to as "driving current") flowing between the first electrode and the second electrode according to the data voltage applied to the gate electrode.

[0107] The light-emitting element (LE) can be a micro light-emitting diode.

[0108] The light-emitting element (LE) emits light according to the driving current (Ids). The amount of light emitted by the light-emitting element (LE) may be proportional to the driving current (Ids). The anode electrode of the light-emitting element (LE) is connected to the first electrode of the fourth transistor (ST4) and the second electrode of the sixth transistor (ST6), and the cathode electrode may be connected to the second power line (VSL) to which the second power supply voltage is applied.

[0109] A capacitor (C1) is formed between the gate electrode of a driving transistor (DT) and a first power line (VDL) to which a first power supply voltage is applied. The first power supply voltage may be a voltage level higher than the second power supply voltage. One electrode of the capacitor (C1) may be connected to the gate electrode of the driving transistor (DT), and the other electrode may be connected to the first power line (VDL).

[0110] As shown in FIG. 5, the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) can all be formed as p-type MOSFETs. In this case, the active layer of each of the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) can be formed of polysilicon.

[0111] The gate electrode of the first transistor (ST1) and the gate electrode of the second transistor (ST2) may be connected to the write scan line (GWL), the gate electrode of the third transistor (ST3) may be connected to the initialization scan line (GIL), and the gate electrode of the fourth transistor (ST4) may be connected to the bias scan line (GBL). Since the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) are formed as p-type MOSFETs, they may be turned on when a scan signal of gate low voltage and a light emission control signal are applied to the initialization scan line (GIL), the write scan line (GWL), the bias scan line (GBL), and the light emission control line (EL), respectively. One electrode of the third transistor (ST3) may be connected to a first initialization voltage line (VIL) to which a third power supply voltage (VINT in FIG. 3) is applied, and one electrode of the fourth transistor (ST4) may be connected to a second initialization voltage line (VAIL) to which a fourth power supply voltage (VAINT in FIG. 3) is applied. The third power supply voltage (VINT in FIG. 3) and the fourth power supply voltage (VAINT in FIG. 3) may be different voltages. Additionally, the third power supply voltage (VINT in FIG. 3) and the fourth power supply voltage (VAINT in FIG. 3) may be voltages at a lower level than the first power supply voltage (VDD) and voltages at a higher level than the second power supply voltage (VSS).

[0112] Alternatively, the driving transistor (DT), the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) may be formed as p-type MOSFETs, and the first transistor (ST1) and the third transistor (ST3) may be formed as n-type MOSFETs. In this case, the active layer of each of the driving transistor (DT), the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) formed as p-type MOSFETs may be formed of polysilicon, and the active layer of each of the first transistor (ST1) and the third transistor (ST3) formed as n-type MOSFETs may be formed of oxide semiconductor. Additionally, since the first transistor (ST1) and the third transistor (ST3) are formed as n-type MOSFETs, the first transistor (ST1) may be turned on when a gate high voltage scan signal is applied, and the third transistor (ST3) may be turned on when an initialization scan signal of a gate high voltage is applied. In contrast, the second transistor (ST2), the fourth transistor (ST4), the fifth transistor (ST5), and the sixth transistor (ST6) are formed as p-type MOSFETs, so they can be turned on when a scan signal of the gate low voltage and a light emission control signal are applied.

[0113] Alternatively, if the fourth transistor (ST4) is formed as an n-type MOSFET and the remaining transistors (DT, ST1, ST2, ST3, ST5, ST6) are formed as p-type MOSFETs, the active layer of the fourth transistor (ST4) may be formed as an oxide semiconductor, and the active layer of each of the remaining transistors (DT, ST1, ST2, ST3, ST5, ST6) may be formed as polysilicon. In addition, the fourth transistor (ST4) may be turned on when a scan signal of gate high voltage is applied, whereas the remaining transistors (DT, ST1, ST2, ST3, ST5, ST6) may be turned on when a scan signal of gate low voltage and a light emission control signal are applied.

[0114] Alternatively, the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) may all be formed as n-type MOSFETs. In this case, the active layer of each of the first to sixth transistors (ST1, ST2, ST3, ST4, ST5, ST6) and the driving transistor (DT) is formed of an oxide semiconductor and can be turned on when a scan signal of gate high voltage and a light emission control signal are applied.

[0115] FIG. 6 is a layout diagram showing pixels of a display area according to one embodiment.

[0116] Referring to FIG. 6, each of the plurality of pixels (PX) of the display area (DA) may include three subpixels (SPX1, SPX2, SPX3), but the embodiments of the present specification are not limited thereto and may include four subpixels. Each of the plurality of pixels (PX) may include three subpixels. The three subpixels may include a first subpixel (SPX1), a second subpixel (SPX2), and a third subpixel (SPX3).

[0117] Multiple pixels (PX) can be arranged in a matrix form. In each of the multiple pixels (PX), the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3) can be arranged in a first direction (DR1).

[0118] In the case where each of the plurality of pixels (PX) includes three subpixels (SPX1, SPX2, SPX3), the first subpixel (SPX1) may emit light of a first color, the second subpixel (SPX2) may emit light of a second color, and the third subpixel (SPX3) may emit light of a third color. Here, the first color light may be light in the red wavelength band, the second color light may be light in the green wavelength band, and the third color light may be light in the blue wavelength band. For example, the blue wavelength band may refer to a wavelength band in which the main peak wavelength of the light is included in the wavelength band of approximately 370 nm to 460 nm, the green wavelength band may refer to a wavelength band in which the main peak wavelength of the light is included in the wavelength band of approximately 480 nm to 560 nm, and the red wavelength band may refer to a wavelength band in which the main peak wavelength of the light is included in the wavelength band of approximately 600 nm to 750 nm.

[0119] Alternatively, if each of the plurality of pixels (PX) includes four subpixels, the first subpixel may emit light of a first color, the second subpixel and the fourth subpixel may emit light of a second color, and the third subpixel may emit light of a third color. Alternatively, the first subpixel may emit light of a first color, the second subpixel may emit light of a second color, the third subpixel may emit light of a third color, and the fourth subpixel may emit light of a fourth color. In this case, the light of the fourth color may be white light.

[0120] The first subpixel (SPX1) includes a first pixel electrode (PXE1) and a plurality of light-emitting elements (LE). The second subpixel (SPX2) includes a second pixel electrode (PXE2) and a plurality of light-emitting elements (LE). The third subpixel (SPX3) includes a third pixel electrode (PXE3) and a plurality of light-emitting elements (LE).

[0121] The light-emitting element (LE1) of the first subpixel (SPX1) emits light of the first color, the light-emitting element (LE2) of the second subpixel (SPX2) emits light of the second color, and the light-emitting element (LE3) of the third subpixel (SPX3) can emit light of the third color.

[0122] Each of the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3) may have a rectangular planar shape having a short side in the first direction (DR1) and a long side in the second direction (DR2). The area of ​​the first subpixel (SPX1), the area of ​​the second subpixel (SPX2), and the area of ​​the third subpixel (SPX3) may be set according to the light emission efficiency of the light-emitting element (LE) included in each subpixel (SPX). For example, the area of ​​the subpixel may be larger as the light conversion efficiency is lower.

[0123] For example, as shown in FIG. 5, when the light emission efficiency of the light-emitting element (LE2) of the second subpixel (SPX2) is lower than the light emission efficiency of the light-emitting element (LE) of the first subpixel (SPX1) and the light-emitting element (LE) of the third subpixel (SPX2), the area of ​​the second pixel electrode (PXE2) may be larger than the area of ​​the first pixel electrode (PXE1) and larger than the area of ​​the third pixel electrode (PXE2).

[0124] Each of the pixel electrodes (PXE1, PXE2, PXE3) can be electrically connected to at least one transistor through a pixel connection hole (CT1 / CT2 / CT3). For example, each of the pixel electrodes (PXE1, PXE2, PXE3) can be electrically connected to the first electrode of the fourth transistor (ST4 in FIG. 4) and the second electrode of the sixth transistor (ST6 in FIG. 4) of the corresponding subpixel.

[0125] A plurality of light-emitting elements (LEs) may be disposed on each of the pixel electrodes (PXE1, PXE2, PXE3). An equal number of light-emitting elements (LEs) may be disposed on each of the pixel electrodes (PXE1, PXE2, PXE3). For example, two light-emitting elements (LEs) may be disposed on each of the pixel electrodes (PXE1, PXE2, PXE3). The plurality of light-emitting elements (LEs) may emit light of a third color, namely light in the blue wavelength band, but the embodiments of this specification are not limited thereto.

[0126] Each of the plurality of light-emitting elements (LEs) may have a circular planar shape, but the embodiments of this specification are not limited thereto. For example, each of the plurality of light-emitting elements (LEs) may have a rectangular planar shape.

[0127] FIG. 7 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to the line II-II' of FIG. 6. FIG. 8 is a cross-sectional view showing in detail an example of area A of FIG. 7.

[0128] Referring to FIGS. 7 and 8, the substrate (SUB) may be made of an insulating material such as glass or a polymer resin. If the substrate (SUB) is made of a polymer resin, it may be a stretchable flexible substrate. The polymer resin may be an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0129] A barrier film (BR) may be disposed on the substrate (SUB). The barrier film (BR) is a film intended to protect the thin-film transistor layer (TFTL) from moisture penetrating through the substrate (SUB), which is susceptible to moisture permeability. The barrier film (BR) may be composed of multiple inorganic films stacked alternately.

[0130] A thin-film transistor (TFT1) may be disposed on the barrier film (BR). The thin-film transistor (TFT1) may be either the fourth transistor (ST4) or the sixth transistor (ST6) shown in FIG. 4. The thin-film transistor (TFT1) may include a first active layer (ACT1) and a first gate electrode (G1).

[0131] A first active layer (ACT1) of a thin-film transistor (TFT1) may be disposed on a barrier film (BR). The first active layer (ACT1) of the thin-film transistor (TFT1) may include polycrystalline silicon, single-crystal silicon, low-temperature polycrystalline silicon, or amorphous silicon. Alternatively, the first active layer (ACT1) of the thin-film transistor (TFT1) may be made of an oxide semiconductor including IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)), or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)).

[0132] The first active layer (ACT1) may include a first channel region (CHA1), a first source region (S1), and a first drain region (D1). The first channel region (CHA1) may be a region that overlaps with the first gate electrode (G1) in the third direction (DR3), which is the thickness direction of the substrate (SUB). The first source region (S1) may be disposed on one side of the first channel region (CHA1), and the first drain region (D1) may be disposed on the other side of the first channel region (CHA1). The first source region (S1) and the first drain region (D1) may be regions that do not overlap with the first gate electrode (G1) in the third direction (DR3). The first source region (S1) and the first drain region (D1) may be regions that have conductivity by doping ions into a semiconductor material.

[0133] A first gate insulating film (131) may be disposed on the first channel region (CHA1), the first source region (S1), the first drain region (D1), and the barrier film (BR) of the thin film transistor (TFT1).

[0134] A first gate metal layer may be disposed on the first gate insulating film (131). The first gate metal layer may include a first gate electrode (G1) and a first capacitor electrode (CAE1) of a thin-film transistor (TFT1). The first gate electrode (G1) may overlap with the first active layer (ACT1) in the third direction (DR3). Although the first gate electrode (G1) and the first capacitor electrode (CAE1) are shown as being separated from each other in FIG. 6, the first gate electrode (G1) and the first capacitor electrode (CAE1) may be connected to each other.

[0135] A second gate insulating film (132) may be disposed on the first gate electrode (G1), the first capacitor electrode (CAE1), and the first gate insulating film (131) of the thin-film transistor (TFT1).

[0136] A second gate metal layer may be disposed on the second gate insulating film (132). The second gate metal layer may include a second capacitor electrode (CAE2). The second capacitor electrode (CAE2) may overlap with the first capacitor electrode (CAE1) of the thin film transistor (TFT1) in the third direction (DR3). Since the second gate insulating film (132) has a predetermined dielectric constant, a capacitor (C1 in FIG. 4) may be formed by the first capacitor electrode (CAE1), the second capacitor electrode (CAE2), and the second gate insulating film (132) disposed between them.

[0137] A first interlayer insulating film (141) may be disposed on the second capacitor electrode (CAE2) and the second gate insulating film (132).

[0138] A first data metal layer may be disposed on the interlayer insulating film (141). The first data metal layer may include a first source connection electrode (PCE1). The first source connection electrode (PCE1) may be connected to a first drain region (D1) of a first active layer (ACT1) through a first source contact hole (PCT1) penetrating the first gate insulating film (131), the second gate insulating film (132), and the interlayer insulating film (141).

[0139] A first flattening organic film (160) for flattening the step difference caused by the thin film transistor (TFT1) may be disposed on the first source connection electrode (PCE1) and the first interlayer insulating film (141).

[0140] A second data metal layer may be disposed on the first planarization organic film (160). The second data metal layer may include a second source connection electrode (PCE2). The second source connection electrode (PCE2) may be connected to the first source connection electrode (PCE1) through a second pixel contact hole (PCT2) that penetrates the first planarization organic film (160).

[0141] A second flattening organic film (180) may be disposed on the second source connection electrode (PCE2) and the first flattening organic film (160).

[0142] The barrier film (BR), the first gate insulating film (131), the second gate insulating film (132), and the interlayer insulating film (141) are inorganic films, for example, silicon nitride (SiN x ), silicon nitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), or aluminum oxide (AlO x It can be formed as ).

[0143] The first gate metal layer, the second gate metal layer, the first data metal layer, and the second data metal layer may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0144] The first flattening organic film (160) and the second flattening organic film (180) can be formed from organic films such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0145] A light-emitting element layer may be disposed on the second planarized organic film (180). The light-emitting element layer may include pixel electrodes (PXE1, PXE2, PXE3), a first conductive adhesive pattern (CBP), light-emitting elements (LE), a common electrode (CE), and an organic barrier (BWL).

[0146] A pixel electrode layer and a first organic layer (190) may be disposed on the second planarizing organic film (180). The pixel electrode layer may include a first pixel electrode (PXE1), a second pixel electrode (PXE2), and a third pixel electrode (PXE3). Each of the pixel electrodes (PXE1, PXE2, PXE3) may be connected to a second source connection electrode (PCE2) through a connection hole (CT1 / CT2 / CT3 in FIG. 6) penetrating the second planarizing organic film (180). Each of the pixel electrodes (PXE1, PXE2, PXE3) may be connected to a first source region (S1) or a first drain region (D1) of a thin film transistor (TFT1) through the first source connection electrode (PCE1) and the second source connection electrode (PCE2). Therefore, a voltage controlled by the thin-film transistor (TFT1) can be applied to each of the pixel electrodes (PXE1, PXE2, PXE3).

[0147] The pixel electrodes (PXE1, PXE2, PXE3) may be formed as a single layer or a multilayer composed of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. For example, to lower the resistance of each of the pixel electrodes (PXE1, PXE2, PXE3), the pixel electrode layer may be made of copper (Cu), which has low sheet resistance. In addition, the pixel electrodes (PXE1, PXE2, PXE3)

[0148] When pixel electrodes (PXE1, PXE2, PXE3) are formed in multiple layers, they may include a first layer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof, and a second layer made of a highly reflective metallic material such as aluminum (Al) on the first layer.

[0149] The second conductive adhesive pattern (CBP2) may be disposed on one surface of each of the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3). In one embodiment, the second conductive adhesive pattern (CBP2) may completely overlap one surface of each of the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3). Additionally, the second conductive adhesive pattern (CBP2) may have the same area as the corresponding pixel electrodes (PXE1, PXE2, PXE3). For example, the second conductive adhesive pattern (CBP2) may have a rectangular planar shape having a short side equal to the length of the short side of the corresponding pixel electrodes (PXE1, PXE2, PXE3) and a long side equal to the length of the long side of the corresponding pixel electrodes (PXE1, PXE2, PXE3).

[0150] The thickness (height) of the second conductive adhesive pattern (CBP2), that is, the distance (h-CBP2) between the second conductive adhesive pattern (CBP2) and the contact electrode (CTE) of the light-emitting element (LE) corresponding to the second conductive adhesive pattern (CBP2) at the interface between the second conductive adhesive pattern (CBP2) and the corresponding pixel electrode (PXE1, PXE2, PXE3) is about 1 μm or less.

[0151] Light-emitting elements (LEs) can be bonded and electrically connected to corresponding pixel electrodes (PXE1, PXE2, PXE3) by a second conductive adhesive pattern (CBP2).

[0152] The second conductive adhesive pattern (CBP2) may be a conductive adhesive pattern comprising conductive nanoparticles (CP). The second conductive adhesive pattern (CBP2) may include a polymer resin and conductive nanoparticles (CP) dispersed in the polymer resin. The conductive nanoparticles (CP) are conductive particles with a particle size of 100 nm or less. The resistance of the conductive nanoparticles (CP) is 1 ohm or less.

[0153] The conductive nanoparticles (CP) may be conductive carbon black, but are not limited thereto. In addition to carbon black, the conductive nanoparticles (CP) may include one or more of the first materials selected from the group consisting of acetylene black, artificial graphite, natural graphite, copper powder, nickel powder, aluminum powder, indium powder, silver powder, and polyphenylene.

[0154] The second conductive adhesive pattern (CBP2) can be melted at less than 200°C, for example, 140°C, to adhere light-emitting elements (LE) onto corresponding pixel electrodes (PXE1, PXE2, PXE3).

[0155] The second conductive adhesive pattern (CBP2) may be the same material as the first conductive adhesive pattern (CBP1 in FIG. 3).

[0156] The second conductive adhesive pattern (CBP2) may further include a photosensitive resin. As the photosensitive resin, it may be an acrylic resin or a polyimide resin. The second conductive adhesive pattern (CBP2) can be patterned by a photolithography process. Therefore, the second conductive adhesive pattern (CBP2) can be finely patterned and is applicable to high-brightness display panels.

[0157] The organic barrier (BWL) can be formed on the second flattened organic film (180) with a first inclination angle (θ1) and a first height (h1). The bottom of the organic barrier (BWL) can be positioned lower than the bottom of the light-emitting element (LE).

[0158] When the top of the organic barrier (BWL) is formed lower than the light-emitting element (LE), there is an advantage that the light-emitting element (LE) can be easily transferred during the light-emitting element (LE) transfer process.

[0159] The first inclination angle (θ1) may be approximately 120 to 135 degrees. The first height (h1) may be approximately 5 μm to 8 μm, but is not limited thereto.

[0160] An organic barrier (BWL) may define a first aperture region (OP-A). The first aperture region (OP-A) may expose the second planarized organic film (180), which is the lower layer, and pixel electrodes (PXE1, PXE2, PXE3). The area exposed by the first aperture region (OP-A) may be larger than the area of ​​the light-emitting element (LE).

[0161] The organic barrier (BWL) may include a first organic layer (190) defining the shape of the barrier, a first protective film (INS1) covering the first organic layer (190), a reflective film (RF), and a second protective film (INS2).

[0162] The top of the first organic layer (190) may be higher than the active layer (MQW) of the light-emitting element (LE) and lower than the top of the light-emitting element (LE).

[0163] The first organic layer (190) can be formed from organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0164] A first protective film (INS1) is placed outside the first organic layer (190). The first protective film (INS1) can cover the entire first organic layer (190).

[0165] A reflective film (RF) is positioned on the outer side of the first protective film (INS1).

[0166] A second protective layer (INS2) is placed on top of the reflective film (RF). The reflective film (RF) is surrounded by the first protective layer (INS1) and the second protective layer (INS2). For example, the reflective film (RF) can be inserted between the first protective layer (INS1) and the second protective layer (INS2).

[0167] The reflective film (RF) may be in a closed-loop shape that surrounds the side of the light-emitting element (LE) while being spaced apart from the light-emitting element (LE) in a planar plane. The top of the reflective film (RF) may be positioned higher than the active layer (MQW) of the light-emitting element (LE). The bottom of the reflective film (RF) may be positioned lower than the light-emitting element (LE). The reflective film (RF) may include a highly reflective metallic material such as aluminum (Al).

[0168] The reflective film (RF) can reflect light traveling laterally from the light-emitting element (LE) and emit it onto the upper surface of the light-emitting element (LE). Therefore, since the loss of light from the light-emitting element (LE) can be reduced, the light efficiency of the light-emitting element (LE) can be increased.

[0169] The greater the slope (θ1) of the reflective film (RF), the greater the frontal light emission efficiency may be, but the greater the slope (θ1) of the reflective film (RF), the wider the width of the first organic layer (190). Therefore, it may be preferable that the slope (θ1) of the reflective film (RF) be about 120° to 130°.

[0170] The first protective layer (INS1) and the second protective layer (INS2) are inorganic films, for example, silicon nitride (SiN x ), silicon nitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), or aluminum oxide (AlO x It can be formed as ).

[0171] Multiple light-emitting elements (LEs) can be placed on pixel electrodes (PXE1, PXE2, PXE3). FIGS. 7 and 8 illustrate that each of the multiple light-emitting elements (LEs) is a vertical type micro LED extended in a third direction (DR3). A vertical type micro LED refers to an LED having a structure in which a first semiconductor layer (SEM1), an active layer (MQW), and a second semiconductor layer (SEM2) are sequentially arranged in a third direction (DR3) which is a vertical direction.

[0172] The light-emitting element (LE) may include substantially vertical sides as illustrated in FIG. 8. For example, the light-emitting element (LE) may be patterned through vertical etching and may have a rectangular or square cross-sectional shape in which the width of the top surface and the width of the bottom surface are substantially the same. The shape of the light-emitting element (LE) may vary depending on the embodiments. For example, the light-emitting element (LE) may have an inverted taper cross-sectional shape. For example, the light-emitting element (LE) may have an inverted trapezoidal cross-sectional shape in which the width of the top surface is wider than the width of the bottom surface.

[0173] Each of the plurality of light-emitting elements (LE) may be formed of an inorganic material such as gallium nitride (GaN). Each of the plurality of light-emitting elements (LE) may have a length in a first direction (DR1), a length in a second direction (DR2), and a length in a third direction (DR3), each ranging from several to several hundred μm. For example, each of the plurality of light-emitting elements (LE) may have a length in a first direction (DR1), a length in a second direction (DR2), and a length in a third direction (DR3), each ranging from approximately 6 μm to 10 μm or less.

[0174] Each of the plurality of light-emitting elements (LE) can be formed by growing on a semiconductor substrate such as a silicon substrate or a sapphire substrate. The plurality of light-emitting elements (LE) can be transferred directly from the semiconductor substrate onto the pixel electrodes (PXE1, PXE2, PXE3) of the display panel (100). Alternatively, the plurality of light-emitting elements (LE) can be transferred onto the pixel electrodes (PXE1, PXE2, PXE3) of the display panel (100) via an electrostatic method using an electrostatic head or a stamp method using an elastic polymer material such as PDMS or silicon as a transfer substrate.

[0175] The light-emitting element (LE) may include a conductive layer (E1), a first semiconductor layer (SEM1), an active layer (MQW), a second semiconductor layer (SEM2), a contact electrode (CTE), and a protective film (INS).

[0176] A conductive layer (E1) may be disposed on the lower surface of a first semiconductor layer (SEM1). Although FIG. 7 illustrates a case where the conductive layer (E1) covers the entire lower surface of the first semiconductor layer (SEM1), the embodiments of this specification are not limited thereto. As an example, the conductive layer (E1) may be disposed on a part of the lower surface of the first semiconductor layer (SEM1). The conductive layer (E1) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu).

[0177] The first semiconductor layer (SEM1) can be placed on the conductive layer (E1). The first semiconductor layer (SEM1) may be made of a semiconductor material layer doped with a first conductive type dopant such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), etc., for example, gallium nitride (GaN).

[0178] The active layer (MQW) can be placed on the first semiconductor layer (SEM1). The active layer (MQW) can emit light through the coupling of electron-hole pairs according to an electric signal applied through the first semiconductor layer (SEM1) and the second semiconductor layer (SEM2).

[0179] The active layer (MQW) may include a material having a single or multiple quantum well structure. When the active layer (MQW) includes a material having a multiple quantum well structure, it may have a structure in which multiple well layers and barrier layers are alternately stacked. In this case, the well layers may be formed of indium gallium nitride (InGaN), and the barrier layers may be formed of gallium nitride (GaN) or aluminum gallium nitride (AlGaN), but the embodiments of this specification are not limited thereto.

[0180] Alternatively, the active layer (MQW) may have a structure in which semiconductor materials with large band gap energy and semiconductor materials with small band gap energy are alternately stacked, or it may include different group 3 to group 5 semiconductor materials depending on the wavelength of the emitted light.

[0181] For example, when the active layer (MQW) contains indium gallium nitride (InGaN), the color of the emitted light may vary depending on the content of indium (In). For example, as the content of indium (In) increases, the wavelength band of the light emitted by the active layer shifts to a red wavelength band, and as the content of indium (In) decreases, the wavelength band of the light emitted by the active layer shifts to a blue wavelength band. For example, the content of indium (In) in the active layer (MQW) of a light-emitting device (LE) that emits a third light (light in the blue wavelength band) may be approximately 10 wt% to 20 wt%.

[0182] The second semiconductor layer (SEM2) can be disposed on the active layer (MQW). The second semiconductor layer (SEM2) may be a semiconductor material layer doped with a second conductivity type dopant, such as silicon (Si), germanium (Ge), tin (Sn), etc., for example, gallium nitride (GaN).

[0183] An electron blocking layer may be placed between the first semiconductor layer (SEM1) and the active layer (MQW). The electron blocking layer may be a layer for suppressing or preventing too many electrons from flowing into the active layer (MQW). For example, the electron blocking layer may be aluminum gallium nitride (AlGaN) or p-type aluminum gallium nitride (AlGaN) doped with p-type magnesium (Mg). The electron blocking layer may be omitted.

[0184] A superlattice layer may be disposed between the active layer (MQW) and the second semiconductor layer (SEM2). The superlattice layer may be a layer for relieving stress between the second semiconductor layer (SEM2) and the active layer (MQW). For example, the superlattice layer may be formed of indium gallium nitride (InGaN) or gallium nitride (GaN). The superlattice layer may be omitted.

[0185] Light extraction patterns (LEPs) can be formed on the upper surface of a semiconductor stack (STC) (SEM1, MQW, SEM2). For example, light extraction patterns (LEPs) can be formed on the upper surface of a second semiconductor layer (SEM2).

[0186] Light extraction patterns (LEPs) may be patterns designed to increase the efficiency of light emitted from the upper surface of a light-emitting element (LE). Light extraction patterns (LEPs) may be concave patterns formed as hemispheres or semi-ellipses. Light extraction patterns (LEPs) may be concave patterns having a semicircular or semi-elliptical cross-sectional shape.

[0187] The protective film (INS) may be a film for protecting the bottom surface and side surface of the light-emitting element (LE). The protective film (INS) may be disposed on the bottom surface and side surface of the conductive layer (E1) and on the side surface of the semiconductor stack (STC). Specifically, the protective film (INS) may be disposed on the bottom surface and side surface of the conductive layer (E1), on the side surface of the first semiconductor layer (SEM1), on the side surface of the active layer (MQW), and on the side surface of the second semiconductor layer (SEM2). The protective film (INS) may be an inorganic film, for example, silicon nitride (SiN x ), silicon nitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), or aluminum oxide (AlO x It can be formed as ).

[0188] The contact electrode (CTE) may be placed on the protective film (INS). The contact electrode (CTE) may be placed between the pixel electrodes (PXE1, PXE2, PXE3) and the protective film (INS). The contact electrode (CTE) may be in contact with the pixel electrodes (PXE1, PXE2, PXE3).

[0189] The contact electrode (CTE) can be connected to the exposed conductive layer (E1) without being covered by the protective film (INS).

[0190] The contact electrode (CTE) may include any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). Specifically, to increase reflectivity, the plurality of contact electrodes (CTE) may be formed into a two-layer structure of chromium (Cr) and gold (Au), a three-layer structure of titanium (Ti), aluminum (Al), and titanium (Ti), or a three-layer structure of ITO (Indium Tin Oxide), silver (Ag), and ITO (Indium Tin Oxide).

[0191] The distance (Ds) between the light-emitting element (LE) and the organic barrier (BWL) can be smaller than the width (W1) of the light-emitting element (LE).

[0192] The second organic layer (211) can be arranged to cover the sides of a plurality of light-emitting elements (LE).

[0193] The second organic layer (211) is a layer for flattening the step difference caused by the plurality of light-emitting elements (LE). The height of the second organic layer (211) may be arranged to cover most of the side of each of the plurality of light-emitting elements (LE), but in other embodiments, it may be arranged to cover the side of each of the light-emitting elements (LE) by a plurality of organic films.

[0194] The second organic layer (211) can be formed from an organic film such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0195] A common electrode (CE) can be disposed on the upper surface of each of the plurality of light-emitting elements (LE) and on the upper surface of the second organic layer (211).

[0196] The common electrode (CE) may be a common layer formed in common on the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3). The common electrode (CE) may be made of a transparent conductive material (TCO) such as Indium Tin Oxide (ITO) and Indium Zinc Oxide (IZO) that can transmit light.

[0197] The pixel electrodes (PXE1, PXE2, PXE3) are referred to as the anode electrode or the first electrode, and the common electrode (CE) may be referred to as the cathode electrode or the second electrode.

[0198] The first capping layer (CAP1) can be placed on the common electrode (CE). The first capping layer (CAP1) can serve to encapsulate the lower component.

[0199] The first capping layer (CAP1) is an inorganic film, for example, silicon nitride (SiN x ), silicon nitride (SiON), silicon oxide (SiO x ), titanium oxide (TiO x ), or aluminum oxide (AlO x It can be formed as ).

[0200] A third organic layer (213) may be disposed on the first capping layer (CAP1). A plurality of color filters (CF1, CF2, CF3) may be disposed on the third organic layer (213). The plurality of color filters (CF1, CF2, CF3) may include first color filters (CF1), second color filters (CF2), and third color filters (CF3).

[0201] A first color filter (CF1) placed in a first subpixel (SPX1) can transmit a first light (light in the red wavelength band). Accordingly, the first subpixel (SPX1) can emit the first light (light in the red wavelength band).

[0202] The second color filter (CF2) placed in the second subpixel (SPX2) can transmit the second light (light in the green wavelength band). Therefore, the second subpixel (SPX2) can emit the second light (light in the green wavelength band).

[0203] The third color filter (CF3) placed in the third subpixel (SPX3) can transmit third light (light in the blue wavelength band). Therefore, the third subpixel (SPX3) can emit third light (light in the blue wavelength band).

[0204] The first color filter (CF1), the second color filter (CF2), and the third color filter (CF3) overlapping in the third direction (DR3) can overlap with the organic barrier (BWL) in the third direction (DR3).

[0205] A fourth organic layer (214) for flattening can be disposed on a plurality of color filters (CF1, CF2, CF3).

[0206] The third organic layer (213) and the fourth organic layer (214) can be formed from acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0207] FIG. 9 is a layout diagram showing pixels of a display area according to one embodiment.

[0208] The embodiment of FIG. 9 differs from the embodiment of FIG. 6 in that the light-emitting element (LE) in each of the first sub-pixel (SPX1), the second sub-pixel (SPX2), and the third sub-pixel (SPX3) is disposed on the pixel electrode (PXE1 / PXE2 / PXE3) and the common electrode (CE). In FIG. 9, descriptions that overlap with the embodiment of FIG. 6 are omitted, and the explanation focuses on the differences from the embodiment of FIG. 6.

[0209] Referring to FIG. 9, pixel electrodes (PXE1 / PXE2 / PXE3) and a common electrode (CE) may be arranged in a second direction (DR2) at each of the first subpixel (SPX1), the second subpixel (SPX2), and the third subpixel (SPX3). Each of the pixel electrodes (PXE1, PXE2, PXE3) and the common electrodes (CE) may have a rectangular planar shape, but the embodiments of the present specification are not limited thereto.

[0210] The common electrode (CE) can be connected to a second power line (VSL) to which a second driving voltage (VSS) is applied. Therefore, the second driving voltage (VSS) can be applied to each of the common electrodes (CE).

[0211] In each of the first subpixel (SPX1), second subpixel (SPX2), and third subpixel (SPX3), the pixel electrode (PXE1 / PXE2 / PXE3) and the common electrode (CE) are positioned such that the light-emitting element (LE) is placed on the pixel electrode (PXE1 / PXE2 / PXE3) and the common electrode (CE), so the length of the second direction (DR2) of the light-emitting element (LE) may be longer than the length of the first direction (DR1).

[0212] The second conductive adhesive pattern (CBP2) may include a second-1 conductive adhesive pattern (CBP2-1) and a second-2 conductive adhesive pattern (CBP2-2).

[0213] The 2-1 conductive adhesive pattern (CBP2-1) is placed on the pixel electrodes (PXE1, PXE2, PXE3) of each sub-pixel (SPX1, SPX2, SPX3) and may have an area smaller than one side of the pixel electrodes (PXE1, PXE2, PXE3). The 2-1 conductive adhesive pattern (CBP2-1) may have a rectangular planar shape having a short side equal to the length of the short side of the corresponding pixel electrodes (PXE1, PXE2, PXE3) and a long side equal to the length of the corresponding pixel electrodes (PXE1, PXE2, PXE3).

[0214] The second-2 conductive adhesive pattern (CBP2-2) is placed on the common electrode (CE) of each subpixel (SPX1, SPX2, SPX3) and may have an area smaller than one side of the common electrode (CE). Similar to the second-1 conductive adhesive pattern (CBP2-1), the second-2 conductive adhesive pattern (CBP2-2) may have a rectangular planar shape having a long side in the first direction (DR1) and a short side in the second direction (DR2), or may have a long side in the second direction (DR2) and a short side in the first direction (DR1).

[0215] The 2-1 conductive adhesive pattern (CBP2-1) and the 2-2 conductive adhesive pattern (CBP2-2) of each subpixel (SPX1, SPX2, SPX3) can be formed with the same area as each other.

[0216] FIG. 10 is a cross-sectional view showing an example of a cross-section of a display panel corresponding to the line I2-I2' of FIG. 9. FIG. 11 is a cross-sectional view showing in detail an example of area B of FIG. 10.

[0217] The embodiments of FIGS. 10 and 11 differ from the embodiments of FIGS. 7 and 8 in that the light-emitting element (LE) is a flip-type micro LED. In FIGS. 10 and 11, descriptions that overlap with the embodiments of FIGS. 7 and 8 are omitted, and the explanation focuses on the differences from the embodiments of FIGS. 7 and 8.

[0218] Referring to FIGS. 10 and 11, a pixel electrode layer including pixel electrodes (PXE1, PXE2, PXE3) and a common electrode (CE) can be disposed on a second planarization organic film (180).

[0219] The light-emitting element (LE) may be a flip-type micro LED. A flip-type micro LED refers to an LED in which contact electrodes (CTE1, CTE2) are formed on one side (e.g., the bottom side) of the light-emitting element (LE).

[0220] FIG. 11 illustrates that a protective film (INS) is disposed on the lower surface of the conductive layer (E1) and on the sides of the first semiconductor layer (SEM1), the sides of the active layer (MQW), and the sides of the second semiconductor layer (SEM2), but embodiments of the present specification are not limited thereto. As an example, the protective film (INS) may be disposed on the sides of the first semiconductor layer (SEM1), the sides of the active layer (MQW), and the sides of the second semiconductor layer (SEM2) of the semiconductor stack (STC).

[0221] A plurality of light-emitting elements (LEs) can be placed on pixel electrodes (PXE1, PXE2, PXE3) and a common electrode (CE).

[0222] A first contact electrode (CTE1) may be disposed on pixel electrodes (PXE1, PXE2, PXE3) and a second contact electrode (CTE2) may be disposed on a common electrode (CE).

[0223] A hole (LEH) may be formed that penetrates the conductive layer (E1), the first semiconductor layer (SEM1), and the active layer (MQW) of the light-emitting element (LE) to expose the second semiconductor layer (SEM2). The hole (LEH) may have a circular planar shape, but the embodiments of this specification are not limited thereto. As an example, the hole (LEH) may have a polygonal planar shape such as an ellipse or a square.

[0224] Additionally, the protective film (INS) may be disposed on the sidewall of the conductive layer (E1) exposed in the hole (LEH), the sidewall of the first semiconductor layer (SEM1), the active layer (MQW), and the sidewall of the second semiconductor layer (SEM2). The protective film (INS) may not cover the second semiconductor layer (SEM2) in the hole (LEH).

[0225] The first contact electrode (CTE1) can be placed on one side of the conductive layer (E1). Therefore, the first contact electrode (CTE1) can be electrically connected to the conductive layer (E1). For example, the first contact electrode (CTE1) can be placed on the protective film (INS). The first contact electrode (CTE1) can be placed between the pixel electrodes (PXE1, PXE2 and PXE3) and the protective film (INS). The first contact electrode (CTE1) can be connected to the exposed conductive layer (E1) that is not covered by the protective film (INS).

[0226] The second contact electrode (CTE2) may be disposed on one side of the conductive layer (E1) spaced apart from the first contact electrode (CTE1). The second contact electrode (CTE2) may be disposed on a protective film (INS) disposed in the hole (LEH) and on a second semiconductor layer (SEM2) exposed in the hole (LEH) without being covered by the protective film (INS). Therefore, the second contact electrode (CTE2) may be electrically connected to the second semiconductor layer (SEM2) in the hole (LEH).

[0227] The 2-1 conductive adhesive pattern (CBP2-1) may be disposed on one side of each of the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3). In one embodiment, the 2-1 conductive adhesive pattern (CBP2-1) may be completely superimposed on one side of each of the first pixel electrode (PXE1), the second pixel electrode (PXE2), and the third pixel electrode (PXE3). Additionally, the first contact electrode (CTE1) of the light-emitting element (LE) may be disposed on the 2-1 conductive adhesive pattern (CBP2-1). The 2-1 conductive adhesive pattern (CBP2-1) may be electrically connected to the first contact electrode (CTE1) of the light-emitting element (LE).

[0228] The second-2 conductive adhesive pattern (CBP2-2) may be disposed on a portion of one side of the common electrode (CE). Additionally, the second contact electrode (CTE2) of the light-emitting element (LE) may be disposed on the second-2 conductive adhesive pattern (CBP2-2). The second-2 conductive adhesive pattern (CBP2-2) may be electrically connected to the second contact electrode (CTE2) of the light-emitting element (LE).

[0229] The thickness (height) of the second conductive adhesive pattern (CBP2), that is, the distance (h-CBP2) between the second conductive adhesive pattern (CBP2) and the contact electrodes (CTE1, CTE2) of the light-emitting element (LE) corresponding to the second conductive adhesive pattern (CBP2) at the interface between the second conductive adhesive pattern (CBP2) and the corresponding pixel electrodes (PXE1, PXE2, PXE3) (or common electrode (CE)), is about 1 μm or less.

[0230] The first contact electrode (CTE1) of the light-emitting elements (LE) can be bonded to and electrically connected to the corresponding pixel electrodes (PXE1, PXE2, PXE3) by the second-1 conductive adhesive pattern (CBP2-1). The second contact electrode (CTE2) of the light-emitting elements (LE) can be bonded to and electrically connected to the corresponding common electrode (CE) by the second-2 conductive adhesive pattern (CBP2-2).

[0231] The organic partition (BWL) can be formed on the second flattened organic film (180) with a first inclination angle (θ1) and a first height (h1).

[0232] The first inclination angle (θ1) may be 120 degrees or more. Preferably, the first inclination angle (θ1) may be about 120 degrees to 135 degrees. The first height (h1) may be about 5 µm to 6 µm.

[0233] An organic barrier (BWL) may define a first aperture region (OP-A). The first aperture region (OP-A) may expose a second planarizing organic film (180) which is a lower layer, pixel electrodes (PXE1, PXE2, PXE3), and a common electrode (CE). The area exposed by the first aperture region (OP-A) may be larger than the area of ​​the light-emitting element (LE).

[0234] The organic barrier (BWL) may include a first organic layer (190) defining the shape of the barrier, a first protective film (INS1) covering the first organic layer (190), a reflective film (RF), and a second protective film (INS2).

[0235] A reflective film (RF) is positioned outside the first protective film (INS1). A second protective film (INS2) is positioned on top of the reflective film (RF). The reflective film (RF) is surrounded by the first protective film (INS1) and the second protective film (INS2).

[0236] The reflective film (RF) may be in a closed-loop shape that surrounds the side of the light-emitting element (LE) while being spaced apart from the light-emitting element (LE) in a planar plane. The top of the reflective film (RF) may be positioned higher than the active layer (MQW) of the light-emitting element (LE). The bottom of the reflective film (RF) may be positioned lower than the light-emitting element (LE). The reflective film (RF) may include a highly reflective metallic material such as aluminum (Al).

[0237] The vertical distance (height) from the shortest part to the bottom part of the reflective film (RF) is 80% to 120% of the height of the light-emitting element (LE). When the reflective film (RF) is formed higher than the height of the light-emitting element (LE), there is an advantage in terms of light emission efficiency, and when the reflective film (RF) is formed lower than the height of the light-emitting element (LE), there is an advantage in that the light-emitting element (LE) can be easily transferred.

[0238] FIG. 12 is a diagram schematically illustrating the configuration of a laser bonding device according to one embodiment. FIG. 13 is a plan view schematically illustrating a mask according to one embodiment.

[0239] A laser bonding device (BD) can bond two or more bonding targets together using a laser beam. The bonding targets may be semiconductor devices such as substrates, films, display panels, touch panels, printed circuit boards (PCBs), flexible circuit boards, or light-emitting elements. For example, according to one embodiment, as shown in FIG. 12, the first bonding target may be a backplane substrate (110) and the second bonding target may be a light-emitting element (LE), but is not limited thereto. For example, as described with reference to FIG. 3, the second bonding target may be an integrated circuit (IC of FIG. 2) or a display driving circuit (250 of FIG. 3) instead of a light-emitting element (LE).

[0240] Referring to FIG. 12, a laser bonding device (BD) can bond a light-emitting element (LE) to a backplane substrate (110) by irradiating a laser beam.

[0241] A laser bonding device (BD) may include a stage (STG), a pressurizing member (PM) that applies downward pressure, a mask (M), and a laser irradiator (LS) capable of irradiating a laser beam.

[0242] The stage (STG) has an upper surface parallel to a plane defined by a first direction (DR1) and a second direction (DR2) that are perpendicular to each other. A bonding target, for example, a backplane substrate (110), is placed on the upper surface of the stage (STG).

[0243] The stage (STG) and the laser bonding device (BD) can be arranged in a straight line in the third direction (DR3) so as to overlap on the plane. That is, the laser beam generated from the laser irradiator (LS) is irradiated in a direction toward the stage (STG).

[0244] In one embodiment, the stage (STG) may be moved to a working position or a waiting position by means of a separate rail or the like. For example, the stage (STG) may move in a second direction (DR2), i.e., forward and backward, but is not limited thereto.

[0245] The pressure member (PM) is positioned above the backplane substrate (110) and the light-emitting element (LE), is formed of a material that transmits light, and can move in the up and down direction.

[0246] The pressurizing member (PM) may further include a beam transmission plate and a head transfer unit.

[0247] The beam transmission plate may be formed as a rectangular plane having a long side in the first direction (DR1) and a short side in the second direction (DR2) that intersects the first direction (DR1). The corner where the long side in the first direction (DR1) and the short side in the second direction (DR2) meet may be formed at a right angle. The planar shape of the beam transmission plate is not limited to a rectangle and may be formed as other polygons, circles, or ellipses.

[0248] The beam transmission plate can be formed from a rigid, transparent material and implemented as a base material that transmits a laser beam.

[0249] The base material of the beam-transmitting plate can be implemented with any beam-transmitting material. The base material of the beam-transmitting plate may be made of materials such as, for example, tempered glass, quartz, acrylic, metal oxides or metalloid oxides, for example, silicon oxide, aluminum oxide, etc. However, it is not limited thereto. In particular, in the case of quartz, it may be desirable as the laser transmittance is 85% to 99%.

[0250] The beam transmission plate may include a chuck having an adsorption function on one side. Due to this adsorption function, the beam transmission plate can adsorb and transport a second bonding target (e.g., a light-emitting element (LE)).

[0251] The head transfer unit moves the beam transmission plate to a working position or a standby position. For example, the head transfer unit can lower or raise the beam transmission plate, or move it left or right and then lower or raise it.

[0252] Referring to FIG. 13, the mask (M) can serve to expose the conductive adhesive pattern (CBP) and the light-emitting element (LE) and to cover the area of ​​the backplane substrate (110) other than the conductive adhesive pattern (CBP) and the light-emitting element (LE). The mask (M) may be a material that does not transmit a laser beam. For example, the mask (M) may be a pattern having light-blocking or reflective properties. The thickness of the mask (M) is not particularly limited, but may have a film thickness within the range of 80 nm to 180 nm. This is because if it is too thin, it becomes difficult to obtain the desired light-blocking or reflective properties, and if it is too thick, it becomes difficult to process the light-blocking pattern with high precision.

[0253] The mask (M) is not particularly limited as long as it is a material having light-blocking or reflective properties, but examples include chromium (Cr), chromium nitride (CrON), chromium nitride (CrN), molybdenum silicide oxide (MoSiO), molybdenum silicide oxide (MoSiON), tantalum oxide (TaO), tantalum silicide oxide (TaSiO), etc.

[0254] The mask (M) includes a plurality of openings (M-OS) that overlap with the conductive adhesive pattern (CBP) and the light-emitting element (LE).

[0255] The laser beam can pass through the openings (M-OS). Thus, the openings (M-OS) can define the transmission area of ​​the laser beam. Therefore, light irradiated from the laser irradiator (LS) passes through the openings (M-OS) of the mask (M) and is irradiated onto the conductive adhesive pattern (CBP). While the conductive adhesive pattern (CBP) is irradiated by the laser beam, the mask (M) can prevent the entire area of ​​the backplane substrate (110) from being exposed to the laser beam and suffering thermal damage.

[0256] The laser irradiator (LS) can irradiate a laser in a desired direction. The laser irradiator (LS) can provide not only a point light source but also a surface light source. The laser irradiator (LS) is positioned above the pressure member (PM) and irradiates a laser beam (LSB) toward the conductive adhesive pattern (CBP).

[0257] For example, the laser irradiator (LS) may include a laser light source and an optical system.

[0258] A laser light source is a device capable of generating laser light by means of energy supplied from an external source, and can be configured to generate laser light such as solid-state lasers such as YAG lasers, ruby ​​lasers, glass lasers, YVO4 lasers, LD lasers, and fiber lasers, liquid lasers such as dye lasers, CO2 lasers, excimer lasers (ArF lasers, KrF lasers, XeCl lasers, XeF lasers, etc.), gas lasers such as Ar lasers and He-Ne lasers, semiconductor lasers, and free electron lasers.

[0259] The optical system can receive a beam-shaped laser light from a laser light source and perform optical dispersion to enable area heating over a predetermined area (e.g., heating is possible over an appropriate area of ​​the backplane substrate (110)).

[0260] For example, the optical system may include a beam shaper that converts a spot-shaped laser into a surface light source. Additionally, the optical system may further include a plurality of lens modules positioned below the beam shaper and spaced apart from each other at appropriate intervals inside the lens barrel. The surface light source emitted from the beam shaper can be controlled by the plurality of lens modules to be irradiated onto the irradiation area of ​​the bonding targets (WP1, WP2).

[0261] The optical system can be raised or lowered along the third direction (DR3), moved left or right along the first direction (DR1), or moved along the second direction (DR2) to adjust flatness and height with respect to the bonding targets.

[0262] A laser beam (LSB) emitted from a laser irradiator (LS) passes through a pressure member (PM) and is irradiated onto a conductive adhesive pattern (CBP), and can heat a predetermined area. The laser light emitted from the optical system may have a wavelength range of about 250 nm to 5 μm. However, the present invention is not limited thereto.

[0263] In some embodiments, the temperature at which the conductive adhesive pattern (CBP) is reflowed may be about 140°C and the temperature at which it is cured may be about 240°C to 280°C. Accordingly, the output of the laser light source, etc., may be adjusted in consideration of these points.

[0264] Thus, the state of the conductive adhesive pattern (CBP) is changed so that the light-emitting element (LE) can be bonded to the backplane substrate (110). Although the light-emitting element (LE) has been described as an example in the embodiments of FIGS. 8 and 11, it is not limited thereto and can be applied to an integrated circuit (IC) or display driving circuit (250) described with reference to FIGS. 2 and 3.

[0265] The laser bonding device (BD) may further include a control unit (CU).

[0266] The control unit (CU) controls the overall operation of the laser bonding device (BD) and each component. For example, the control unit (CU) controls the laser power and laser irradiation time of the laser generator of the laser irradiator (LS).

[0267] In addition, in one embodiment, the control unit (CU) can control the pressure applied to the pressure module (PM) according to the state.

[0268] The operations performed by the control unit (CU) can be distributed and processed by multiple physically separated computing devices. It is also possible for a first server to perform some of the operations performed by the control unit (CU) and a second server to perform others. In this case, the control unit (CU) can be implemented as the sum of the physically separated computing devices.

[0269] A control unit (CU) according to an exemplary embodiment of the present invention may be implemented through a non-volatile memory (not shown) configured to store data relating to an algorithm configured to control the operation of various components of a laser bonding device (BD) or software instructions for reproducing said algorithm, and a processor (not shown) configured to perform the operation described below using the data stored in said memory. Here, the memory and the processor may be implemented as separate chips. Alternatively, the memory and the processor may be implemented as a single chip integrated with each other. The processor may take the form of one or more processors.

[0270] A laser bonding device (BD) according to one embodiment can control the temperature and pressure (kilogram-force (kgf) or kilogram-force per square centimeter (kgf / cm)) of heat applied according to the condition of the bonding member by varying the laser power (W) and irradiation time (s) during the laser bonding process (e.g., as in FIG. 19).

[0271] For example, the control unit (CU) of the laser bonding device (BD) may irradiate a laser of a first power for a first time period, and then irradiate a laser of a second power higher than the first power for a second time period. The first irradiation and the second irradiation may be performed continuously. The temperature of the first irradiation may be the melting temperature of the polymer resin and may be about 140°C. As the polymer resin of the conductive adhesive pattern (CBP) melts, the light-emitting element (LE) can be bonded to the backplane substrate (110). The temperature of the second irradiation may be a temperature for forming an electrical network of nanoconductive particles such as carbon black and stabilizing the components inside the polymer resin and may be about 240 to 280°C.

[0272] Here, the first time may be 4 seconds and the first power may be 600W, and the second time may be 2 seconds and the second power may be 1400W, but this may change depending on the performance of the laser irradiator (LS).

[0273] FIG. 14 is a method for explaining a method for manufacturing a display device using a conductive adhesive pattern.

[0274] FIGS. 15 to 18 and FIG. 20 are step-by-step cross-sectional views for explaining a method of manufacturing a display device according to one embodiment. For example, FIGS. 15 to 18 and FIG. 20 illustrate specific steps in the form of cross-sectional views for explaining a method of manufacturing a display device according to one embodiment. FIG. 19 is a graph showing the laser power and laser temperature over time of a laser bonding device according to one embodiment.

[0275] Hereinafter, a method for manufacturing a display device will be described with reference to FIG. 15 to FIG. 20, taking into account FIG. 14.

[0276] The method for manufacturing a display device described with reference to FIGS. 14 to 20 can be applied to a display device including a light-emitting element and a display panel described with reference to FIGS. 9 to 11. Additionally, the method for manufacturing a display device described with reference to FIGS. 15 to 18 can be performed by a laser bonding device (BD) described with reference to FIG. 12.

[0277] Referring to FIG. 15, a plurality of pixel electrodes (PXE) and a common electrode (CE) can be formed on a backplane substrate (110). (S110 of FIG. 14)

[0278] For example, a conductive electrode material is first deposited on a backplane substrate (110), and then a plurality of pixel electrodes (PXE) and a common electrode (CE) are formed through a patterning process.

[0279] The conductive electrode material can be deposited using any method capable of forming a metal layer, such as screen printing, electron beam (E-Beam) deposition, or sputtering.

[0280] In a patterning process, a photoresist is applied onto a conductive electrode material, a photolithography process is performed to transfer a pattern onto the photoresist, and a development process is performed to remove parts other than the pattern, thereby forming a plurality of pixel electrodes (PXE) and a common electrode (CE).

[0281] The backplane substrate (110) may include the substrate (SUB) described in FIG. 7 and the thin-film transistor layer (TFTL).

[0282] Referring to FIGS. 16 and 17, a conductive adhesive pattern (CBP) is formed on each electrode of a plurality of pixel electrode (PXE) and common electrode (CE) pairs. (S120 of FIG. 14)

[0283] To this end, a conductive adhesive material (CBPL) containing a polymer resin and conductive nanoparticles is applied to the front surface of a backplane substrate (110), and then, through a patterning process, only the conductive adhesive material (CBPL) in the area that completely overlaps with a plurality of pixel electrodes (PXE) and a common electrode (CE) is left, while the rest is removed. Accordingly, a conductive adhesive pattern (CBP) can be formed in the area that overlaps with a plurality of pixel electrodes (PXE) and a common electrode (CE).

[0284] Next, referring to FIG. 18, a laser bonding device (BD) applies heat to a conductive adhesive pattern (CBP) to bond a light-emitting element (LE) (S130 in FIG. 14).

[0285] In FIG. 18, a light-emitting element (LE) is exemplified, but in addition to the light-emitting element (LE), any of the integrated circuit (IC), sensor, and display driving circuit (250) described with reference to FIG. 2 and FIG. 3 may be used, and any of the light-emitting element (LE) described with reference to FIG. 7 or FIG. 11 may be used.

[0286] For example, a backplane substrate (110) is placed on a stage (STG).

[0287] A light-emitting element (LE) is positioned to face the conductive adhesive pattern (CBP) of the backplane substrate (110).

[0288] The light-emitting element (LE) may be disposed on the second substrate (SSB). The second substrate (SSB) may be a relay substrate.

[0289] Multiple light-emitting elements (LEs) can be transferred onto a relay substrate using an electrostatic method using an electrostatic head or a stamping method using an elastic polymer material such as PDMS or silicon as a transfer substrate.

[0290] The intermediate substrate may consist of a support layer and an adhesive layer disposed on the support layer. The support layer may be made of a material that is transparent and mechanically stable so that light can pass through. For example, the support layer may include transparent polymers such as polyester, polyacrylic, polyepoxy, polyethylene, polystyrene, polyethylene terephthalate, etc. The adhesive layer may include an adhesive material for bonding a light-emitting element (LE). For example, the adhesive material may include urethane acrylate, epoxy acrylate, polyester acrylate, etc. The adhesive material may be a material whose adhesive strength changes when ultraviolet (UV) light or heat is applied, thereby allowing the adhesive layer to be easily separated from the light-emitting element (LE).

[0291] The contact electrode (CTE) of the light-emitting element (LE) is positioned to contact the conductive adhesive pattern (CBP), and a pressure member (PM) is placed on the second substrate (SSB).

[0292] A mask (M) may be disposed between the second substrate (SSB) and the pressurizing member (PM). The mask (M) may be the mask described with reference to FIGS. 12 and FIGS. 13. The openings (M_OS) of the mask (M) may be disposed to overlap with the light-emitting element (LE).

[0293] A laser irradiator (LS) can be placed on top of a pressure member (PM). First, the laser irradiator (LS) can irradiate a laser of a first power for a first time period, and then irradiate a laser of a second power higher than the first power for a second time period. If a mask (M) is placed between the second substrate (SSB) and the pressure member (PM) prior to laser irradiation, the first irradiation and the second irradiation can be performed continuously.

[0294] During laser irradiation, the pressurizing module (PM) pressurizes the light-emitting element (LE) to make the height of the conductive adhesive pad (CBP) 1 μm or less. The pressurizing module (PM) can pressurize with a pressure of about 5 MPa.

[0295] Referring to FIG. 19, the solid line of the graph represents laser power and the dotted line of the graph represents temperature. The left vertical axis of the graph represents laser power (W), and the right vertical axis represents temperature (°C). The horizontal axis of the graph represents laser irradiation time (seconds, S).

[0296] A laser irradiator (LS) irradiates a laser beam with a laser power of 400W for 4 seconds to raise the temperature to 140℃. Then, a laser beam with a laser power of 1500W is irradiated continuously for 2 seconds to raise the temperature to 260℃.

[0297] In another embodiment, the first laser irradiation can be performed without placing the mask (M) between the second substrate (SSB) and the pressure member (PM) prior to the laser irradiation. As described above, the first laser irradiation is performed at a relatively low temperature, so there is less risk of causing thermal damage to the backplane substrate (110), and thus it can be performed without placing the mask (M). After the first laser irradiation, the mask (M) can be placed between the second substrate (SSB) and the pressure member (PM), and the laser power can be increased to perform the second laser irradiation. Since the second irradiation is performed at a relatively high temperature, the mask (M) can be used to prevent the entire area of ​​the backplane substrate (110) from being exposed to the laser beam.

[0298] When the second laser irradiation is completed, the pressurizing module (PM) is raised, and the second substrate (SSB) is separated from the light-emitting element (LE) and removed as shown in FIG. 20.

[0299] As described above, the method of bonding devices by irradiating conductive nanoparticles with a laser can be completed within a short time (e.g., 6 seconds) from bonding to post-curing in a single process by controlling the laser power. In addition, since a mask is used, the exposure of the backplane substrate to the laser beam is minimized, thereby minimizing thermal damage.

[0300] FIG. 21 is a diagram illustrating the bonding state according to the bonding temperature and bonding pressure in a bonding process by a laser bonding device according to one embodiment.

[0301] First, in the laser bonding method described with reference to FIGS. 15 to 21 according to one embodiment, the most preferred bonding temperature is 140°C and the bonding pressure is 5 MPa.

[0302] When the bonding temperature is 100°C to 120°C and the bonding pressure is 1 MPa, the light-emitting element may be tilted or shifted. When the bonding temperature is 140°C and the bonding pressure is 1 MPa, the light-emitting element may be bonded while tilted or shifted and short-circuited.

[0303] When the bonding temperature is 100℃ and the bonding pressure is 2 MPa, the electrical network between the nanoparticles in the conductive nanoparticles is not formed smoothly, so the conductivity may be poor.

[0304] When the bonding temperature is 100℃ and the bonding pressure is 4 MPa, the polymer resin within the light-emitting element and the conductive nanoparticles is not sufficiently melted, so there is a possibility that the light-emitting element may detach.

[0305] Next, when the bonding temperature is 140℃ and the bonding pressure is 3~4 MPa, there is a possibility that the conductive nanoparticles will be destroyed.

[0306] FIGS. 22 and FIGS. 23 are exemplary drawings showing a smart watch including a display device according to one embodiment.

[0307] Referring to FIGS. 22 and 23, a display device (10_1) according to one embodiment can be applied to a smart watch (1000_1), which is one of the smart devices.

[0308] The planar shape of the display device (10_1) may be square or circular, but is not limited thereto and can be varied in various ways, such as elliptical.

[0309] FIG. 24 is an exploded perspective view of a smart watch including a display device according to one embodiment.

[0310] Referring to FIG. 24, the smart watch (1000_1) may include a main body unit (BP) and a wearable part (BD).

[0311] The main body unit (BP) may include a display panel (100) on which an image is displayed, a cover window (CW) placed on the display panel (100), a lower cover (BC) placed below the display panel (100), a middle frame (MF) placed between the cover window (CW) and the lower cover (BC), and a battery (BR) placed between the middle frame (MF) and the lower cover (BC). In addition, in addition to the battery (BR), a circuit board on which a main processor controlling the smart watch (1000_1), a communication chipset communicating with the outside via wired or wireless communication, and memory are mounted may be additionally placed between the middle frame (MF) and the lower cover (BC).

[0312] The main body unit (BP) may have a lower cover (BC), a battery (BR), a middle frame (MF), a display panel (100), and a cover window (CW) arranged sequentially.

[0313] A cover window (CW) is positioned on the upper part of a display panel (100) to protect the display panel (100) and to transmit light emitted from the display panel (100). As described above, the cover window (CW) may include a light-blocking portion to block a portion of the light emitted from the display panel (100). The cover window (CW) may be made of a transparent plastic material, a glass material, or a reinforced glass material.

[0314] A cover window (CW) may be positioned to overlap the display panel (100) and cover the front of the display panel (100). The cover window (CW) generally has a shape similar to the display panel (100) in planar form, but its size may be larger than that of the display panel (100). For example, the cover window (CW) may protrude outward from the display panel (100). The planar shape of the cover window (CW) may be the same as the planar shape of the main body unit (BP). For example, the planar shape of the cover window (CW) may generally be circular, but is not limited thereto and may have various shapes, such as a polygon (e.g., square) or an ellipse.

[0315] The middle frame (MF) is positioned between the cover window (CW) and the lower cover (BC) as a connecting member for joining the cover window (CW) and the lower cover (BC). For example, the middle frame (MF) may include a bracket.

[0316] The lower cover (BC) is a housing placed at the bottom of the display panel (10).

[0317] The lower cover (BC) may include a central cover portion (BCP) and a peripheral portion (BS) positioned around the central cover portion (BCP).

[0318] The central cover portion (BCP) is located in the center of the lower cover (BC) and can be generally flat.

[0319] The periphery (BS) may be positioned to surround the central cover portion (BCP). The periphery (BS) may be a bent portion that is folded away from the central cover portion (BCP). The periphery (BS) may be folded away from the edge of the central cover portion (BCP). In some embodiments, the periphery (BS) may include a curved surface having a certain curvature in part, and a flat part in other parts. The degree (or angle) at which the periphery (BS) is folded away from the central cover portion (BCP) may be obtuse, but is not limited thereto, and may be right or acute.

[0320] A storage space (BC-S) can be formed by the central cover portion (BCP) and the peripheral portion (BS). A battery (BR) can be placed in the storage space (BC-S).

[0321] The battery (BR) can be connected to a circuit board on which the main processor, etc. is mounted. The display device (10_1) is electrically connected to the circuit board and can receive digital video signals, timing signals, power, etc.

[0322] The lower cover (BC) is positioned on the outermost rear surface of the electronic device and comprises at least one material among plastic, metal, and glass, and may include a color coating layer. For example, the lower cover (BC) according to one example may be a flat glass having a transparent, translucent, or opaque color coating layer.

[0323] According to another example, the lower cover (BC) may include a glass material having a color coating layer and having the same shape as the cover window (CW). For example, according to another example, the lower cover (BC) may have a structure symmetrical to the cover window (CW) with the middle frame (MF) in between, and may include a transparent, translucent, or opaque color coating layer.

[0324] The wearing part (BD) is a part for securing the main body unit (BP) to the user's wrist, etc., and may be, for example, any one of a strap, a chain, and a bracelet.

[0325] FIG. 25 is an exemplary drawing showing a virtual reality device including a display device according to one embodiment.

[0326] Referring to FIG. 25, a head-mounted display device (1000_2) according to one embodiment includes a display device storage unit (1100), a storage unit cover (1200), a first eyepiece (1210), a second eyepiece (1220), and a head-mounted band (1300).

[0327] A display device may be housed within the display device housing (1100). Additionally, the head-mounted display device (1000_2) may further include optical members between the display device and the first eyepiece (1210) and between the second eyepiece (1220). Each may include at least one convex lens.

[0328] The storage cover (1200) is positioned to cover an open side of the display device storage unit (1100). The storage cover (1200) may include a first eyepiece (1210) in which the user's left eye is positioned and a second eyepiece (1220) in which the user's right eye is positioned. Although FIG. 30 illustrates the first eyepiece (1210) and the second eyepiece (1220) being positioned separately, the embodiments of this specification are not limited thereto. The first eyepiece (1210) and the second eyepiece (1220) may be combined into one.

[0329] The head mounting band (1300) serves to secure the display device storage unit (1100) to the user's head so that the first eyepiece (1210) and the second eyepiece (1220) of the storage unit cover (1200) can be maintained in a state where they are positioned on the user's left and right eyes, respectively.

[0330] In addition, the head-mounted display device (1000_2) may further be equipped with a battery for supplying power, an external memory slot for storing external memory, an external connection port for receiving video sources, and a wireless communication module. The external connection port may be a USB (universe serial bus) terminal, a display port, or an HDMI (high-definition multimedia interface) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0331] FIG. 26 is an exemplary drawing showing a virtual reality device including a display device according to another embodiment. FIG. 26 shows a virtual reality device (1000_3) to which a display device (10_4) according to one embodiment is applied.

[0332] Referring to FIG. 26, a virtual reality device (1000_3) according to one embodiment may be a device in the form of glasses. A virtual reality device (1000_3) according to one embodiment may have a display device (10_4), a left eye lens (10a), a right eye lens (10b), a support frame (20), eyeglass frame legs (30a, 30b), a reflective member (40), and a display device housing (50).

[0333] FIG. 26 illustrates a virtual reality device (1000_3) that is an eyeglass-type display device including eyeglass frame temples (30a, 30b). That is, the virtual reality device (1000_3) according to one embodiment is not limited to that shown in FIG. 26 and can be applied in various forms in various other electronic devices.

[0334] The display device housing (50) may include a display device (10_4) and a reflective member (40). An image displayed on the display device (10_4) may be reflected from the reflective member (40) and provided to the user's right eye through the right eye lens (10b). As a result, the user can view the virtual reality image displayed on the display device (10_4) through their right eye.

[0335] FIG. 26 illustrates that the display device housing (50) is positioned at the right end of the support frame (20), but the embodiments of this specification are not limited thereto. For example, the display device housing (50) may be positioned at the left end of the support frame (20), in which case the image displayed on the display device (10_4) may be reflected from the reflective member (40) and provided to the user's left eye through the left eye lens (10a). As a result, the user can view the virtual reality image displayed on the display device (10_4) through the left eye. Alternatively, the display device housing (50) may be positioned at both the left end and the right end of the support frame (20), in which case the user can view the virtual reality image displayed on the display device (10_4) through both the left eye and the right eye.

[0336] FIG. 27 is an exemplary drawing showing an automobile instrument panel and a center fascia including display devices according to one embodiment. FIG. 27 shows an automobile with display devices (10_a, 10_b, 10_c, 10_d, 10_e) according to one embodiment applied.

[0337] Referring to FIG. 27, display devices (10_a, 10_b, 10_c) according to one embodiment may be applied to an instrument panel of a vehicle, to a center fascia of a vehicle, or to a Center Information Display (CID) placed on the dashboard of a vehicle. Additionally, display devices (10_d, 10_e) according to one embodiment may be applied to a room mirror display that replaces a side mirror of a vehicle.

[0338] FIG. 28 is an exemplary drawing showing a transparent display device including a display device according to one embodiment.

[0339] Referring to FIG. 28, a display device (10_5) according to one embodiment can be applied to a transparent display device. The transparent display device can display an image (IM) and transmit light simultaneously. Therefore, a user located in front of the transparent display device can not only view the image (IM) displayed on the display device (10_5) but also see an object (RS) or background located on the back of the transparent display device. When the display device (10_5) is applied to a transparent display device, the substrate of the display device (10_5) may include a light-transmitting portion capable of transmitting light or be formed of a material capable of transmitting light.

[0340] Although embodiments of the present invention have been described above with reference to the attached drawings, those skilled in the art will understand that the present invention may be implemented in other specific forms without changing the technical concept or essential features thereof. Therefore, the embodiments described above should be understood as illustrative in all respects and not restrictive.

Claims

1. A stage supporting the first substrate; A pressure module for fixing a plurality of elements disposed on the first substrate; A laser irradiator for irradiating a laser beam onto a conductive adhesive pattern disposed between the first substrate and the plurality of elements; and It includes a mask having openings disposed on the upper part of the first substrate and overlapping with the plurality of elements, and The above plurality of elements include one or more of a light-emitting element, an integrated circuit, and a driving circuit, and The above laser irradiator is a laser bonding device that irradiates a laser beam of first power for a first time and irradiates a laser beam of second power higher than the first power for a second time.

2. A laser bonding device according to claim 1, wherein the conductive adhesive pattern comprises a polymer resin and conductive nanoparticles dispersed in the polymer resin.

3. In Paragraph 2, The above conductive nanoparticles are conductive carbon black, a laser bonding device.

4. A laser bonding device according to claim 1, wherein the height of the conductive adhesive pattern is 1 μm or less.

5. A laser bonding device according to claim 1, wherein the mask comprises a light-blocking or reflective material in an area other than the opening.

6. In Paragraph 1, The above laser irradiator is a laser bonding device configured to enable area heating over a predetermined area.

7. In Paragraph 1, The laser bonding device described above irradiates a laser beam with a first power for a first time period to heat the process temperature to 140°C, and irradiates a laser beam with a second power for a second time period to heat the process temperature to 260°C.

8. In Paragraph 1, A first electrode is disposed on the first substrate, and a conductive adhesive pattern is disposed on the first electrode. A laser bonding device in which the openings of the above mask overlap with the above conductive adhesive pattern.

9. In Paragraph 1, The light-emitting element comprises a contact electrode disposed on one surface and a plurality of semiconductor layers disposed on the contact electrode, and A laser bonding device in which the contact electrode is disposed on the conductive adhesive pattern and electrically connected to the conductive adhesive pattern.

10. A step of forming a first electrode on a first substrate; A step of forming a conductive adhesive pattern on the first electrode; A step of disposing of one of a plurality of elements on the conductive adhesive pattern, wherein the plurality of elements includes one or more of a light-emitting element, an integrated circuit, and a driving circuit; and The laser irradiator includes the step of irradiating the conductive adhesive pattern with a laser beam of a first power for a first time period and irradiating it with a laser beam of a second power higher than the first power for a second time period. A laser bonding method comprising placing a mask having openings overlapping with a plurality of elements on the first substrate prior to the step of irradiating a laser beam of second power higher than the first power for a second time.

11. A laser bonding method according to claim 10, wherein the conductive adhesive pattern comprises a polymer resin and conductive nanoparticles dispersed in the polymer resin.

12. In Paragraph 11, The above conductive nanoparticles are conductive carbon black, laser bonding method.

13. In Paragraph 10, In the step of forming the conductive adhesive pattern above, A laser bonding method for forming a conductive adhesive pattern by applying a conductive adhesive material to the front surface of the substrate to cover the first electrode and patterning it using a mask in a photolithography process.

14. In Paragraph 11, A laser bonding method in which a pressure member is placed between a laser irradiator and the light-emitting element, and the light-emitting element is pressured to 5 MPa while the laser beam is irradiated.

15. In Paragraph 14, A laser bonding method in which the above-described pressure member presses the conductive adhesive pattern until the height of each conductive adhesive pattern becomes 1 μm or less.

16. A laser bonding method according to claim 10, wherein the mask comprises a light-blocking or reflective material in an area other than the opening.

17. In claim 10, the laser irradiator is a laser bonding method that performs area heating on a predetermined area of ​​the first substrate.

18. In Paragraph 10, A laser bonding method in which the above laser irradiator irradiates a laser beam with a first power for a first time to heat the process temperature to 140°C, and irradiates a laser beam with a second power for a second time to heat the process temperature to 260°C.

19. In the step of placing an element on the conductive adhesive pattern according to claim 10, The light-emitting element is disposed on a second substrate, and the contact electrode of the light-emitting element is disposed to face the conductive adhesive pattern, and A laser bonding method in which, after the laser irradiation is completed, the second substrate is separated from the light-emitting element and removed.

20. An electronic device including a laser bonding device, The laser bonding device is A stage supporting a first substrate; A pressure module for fixing a plurality of elements disposed on the first substrate; A laser irradiator for irradiating a laser beam onto a conductive adhesive pattern disposed between the first substrate and the plurality of elements; and It includes a mask having openings disposed on the upper part of the first substrate and overlapping with the plurality of elements, and The above plurality of elements include one or more of a light-emitting element, an integrated circuit, and a driving circuit, and The above laser irradiator is an electronic device that irradiates a laser beam of first power for a first time and irradiates a laser beam of second power higher than the first power for a second time.

Images