Capping for selective sam deposition and removal

Abstract

A method of forming a microelectronic device includes depositing a metal cap layer on a metal surface of a feature formed in a substrate, depositing a self-assembled monolayer (SAM) selectively on the metal cap layer on the metal surface of the feature over a dielectric surface of the feature, depositing a barrier layer selectively on the dielectric surface, and removing the SAM.

Description

PATENTAttorney Docket No.: 44025963WO01CAPPING FOR SELECTIVE SAM DEPOSITION AND REMOVAL BACKGROUNDField

[0001] Embodiments of the present invention generally relate to methods of forming interconnect structures in microelectronic devices. More particularly, embodiments of the disclosure are directed to methods of enhancing selectivity in depositing self-assembled monolayers on metal surfaces over dielectric surfaces and reducing carbon residue after removal of self-assembled monolayers during formation of interconnect structures in microelectronic devices.Description of the Related Art

[0002] The semiconductor industry faces many challenges in the pursuit of device miniaturization which involves rapid scaling of nanoscale features. Such issues include the introduction of complex fabrication steps such as multiple lithography steps and integration of high-performance materials. Selective deposition has shown promise in device miniaturization as it has the potential to remove costly lithographic steps by simplifying integration schemes.

[0003] Selective deposition of materials can be accomplished in a variety of ways. A chemical precursor may react selectively with one surface relative to another surface (metallic or dielectric). Process parameters such as pressure, substrate temperature, precursor partial pressures, and / or gas flows might be modulated to modulate the chemical kinetics of a particular surface reaction. Another possible scheme involves surface pretreatments that can be used to activate or deactivate a surface of interest to an incoming film deposition precursor. For example, a selfassembled monolayer (SAM) can be formed on a surface to prevent subsequent deposition on that surface.

[0004] The issues with current state of the SAM include insufficient selectivity in SAM deposition on a metal surface (e.g., molybdenum (Mo)) and some carbon residue after SAM removal. The insufficient selectivity causes inability to cover a large area with SAM, leading to unwanted deposition of a barrier layer (e.g., tantalum nitride (TaN)) on the metal surface (e.g., molybdenum (Mo)) and formation of metal nitride (e.g., molybdenum nitride (MoN)). The carbon residue is more critical now to be 8899576 1PATENTAttorney Docket No.: 44025963WO01resolved, as it may cause a higher overall effective resistance Re of an electrical circuit with carbon impurity and Re drift issue. Carbon residue on metals and other surface may also cause time dependent dielectric breakdown (TDDB) failures.

[0005] Accordingly, there is an ongoing need in the art for methods of enhancing selectivity in depositing self-assembled monolayers on metal surfaces and reducing carbon residue after removing the self-assembled monolayers during formation of interconnect structures in microelectronic devices.SUMMARY

[0006] Embodiments of the disclosure include a method of forming a microelectronic device. The method includes depositing a metal cap layer on a metal surface of a feature formed in a substrate, depositing a self-assembled monolayer (SAM) selectively on the metal cap layer on the metal surface of the feature over a dielectric surface of the feature, depositing a barrier layer selectively on the dielectric surface, and removing the SAM.

[0007] Embodiments of the disclosure also include a method of forming a microelectronic device. The method includes depositing a metal cap layer on a top surface of a first metal layer exposed within a feature opening extending through a dielectric layer that is formed on the first metal layer, depositing a blocking layer selectively on the metal cap layer on the top surface of the first metal layer exposed within the feature opening over sidewalls of the feature opening, depositing a barrier layer selectively on the sidewalls of the feature opening over the blocking layer, removing the blocking layer, and filling the feature opening with a second metal layer.

[0008] Embodiments of the disclosure further include a method of removal of selfassembled monolayer (SAM) from a metal surface. The method includes exposing the metal surface to a ruthenium (Ru)-containing precursor, forming a metal cap layer, depositing a self-assembled monolayer (SAM) on the metal cap layer, and removing the SAM from the metal surface, wherein carbon (C) residue on the metal surface after the removing the SAM is reduced as compared to a SAM removal without exposing the metal surface to the ruthenium (Ru)-containing precursor.8899576 2PATENTAttorney Docket No.: 44025963WO01BRIEF DESCRIPTION OF THE DRAWINGS

[0009] So that the manner in which the above recited features of the present disclosure can be understood in detail, a more particular description of the disclosure, briefly summarized above, may be had by reference to embodiments, some of which are illustrated in the appended drawings. It is to be noted, however, that the appended drawings illustrate only typical embodiments of this disclosure and are therefore not to be considered limiting of its scope, for the disclosure may admit to other equally effective embodiments.

[0010] Figure 1 illustrates a process flow diagram of a method of forming a microelectronic device in accordance with one or more embodiments of the disclosure.

[0011] Figure 2 illustrates a cross-sectional schematic view of a microelectronic device prior to a selective deposition process in accordance with one or more embodiments of the disclosure.

[0012] Figure 3 illustrates a cross-sectional schematic view of the microelectronic device of Figure 2 after selective deposition of a cap layer in accordance with one or more embodiments of the disclosure.

[0013] Figure 4 illustrates a cross-sectional schematic view of the microelectronic device of Figure 3 after formation of a blocking layer in accordance with one or more embodiments of the disclosure.

[0014] Figure 5 illustrates a cross-sectional schematic view of the microelectronic device of Figure 4 after formation of a barrier layer in accordance with one or more embodiments of the disclosure.

[0015] Figure 6 illustrates a cross-sectional schematic view of the microelectronic device of Figure 5 after removal of the blocking layer in accordance with one or more embodiments of the disclosure.

[0016] Figure 7 illustrates a cross-sectional schematic view of the microelectronic device of Figure 6 after formation of a metal liner in accordance with one or more embodiments of the disclosure.8899576PATENTAttorney Docket No.: 44025963WO01

[0017] Figure 8 illustrates a cross-sectional schematic view of the microelectronic device of Figure 7 after a gapfill process in accordance with one or more embodiments of the disclosure.

[0018] To facilitate understanding, identical reference numerals have been used, where possible, to designate identical elements that are common to the figures. It is contemplated that elements and features of one embodiment may be beneficially incorporated in other embodiments without further recitation.DETAILED DESCRIPTION

[0019] Embodiments described herein are directed to methods of enhancing selectivity in depositing self-assembled monolayers on metal surfaces over dielectric surfaces and reducing carbon residue after removing self-assembled monolayers during formation of interconnect structures in microelectronic devices. The methods described herein include depositing a metal cap layer (e.g., ruthenium (Ru)) prior to a self-assembled monolayer (SAM) soak process, to enhance selectivity in SAM deposition on metal surfaces (e.g., molybdenum (Mo)) and mitigate and weaken the bonding between a SAM and the metal surfaces. The use of a thin selective ruthenium (Ru) cap layer on molybdenum (Mo) metal surfaces results in selective deposition of SAM on the metal surfaces in an extended area, and an improved ability to remove a SAM layer. Unwanted deposition of a barrier layer (e.g., tantalum nitride (TaN)) on the metal surface (e.g., molybdenum (Mo)) can be avoided and thus formation of metal nitride (e.g., molybdenum nitride (MoN)) can be mitigated.

[0020] The inventors have shown that selectivity of a SAM deposition on a ruthenium (Ru) capped molybdenum (Mo) surface is enhanced by between about 18 and about 36 times, as compared to a molybdenum (Mo) surface.

[0021] A process flow of a method 10 of forming a microelectronic device according to one or more embodiments of the disclosure is described with respect to Figures 1 to 7. The method 10 described herein can be used to form semiconductor devices or interconnects for semiconductor devices.

[0022] The method 10 in Figure 1 includes depositing a metal cap layer selectively on a metal surface of a feature extending into a semiconductor substrate (operation 12); exposing the feature to blocking molecule, to form a blocking layer on the cap8899576 4PATENTAttorney Docket No.: 44025963WO01layer, the feature defining a gap including the metal surface, a dielectric surface, and an aluminum oxide surface or an aluminum nitride surface, the blocking layer forming selectively on the metal cap layer over the dielectric surface and one of an aluminum oxide surface or an aluminum nitride surface (operation 14); selectively depositing a barrier layer on the dielectric surface and one of the aluminum oxide surface or the aluminum nitride surface over the blocking layer (operation 16); removing the blocking layer (operation 18); optionally, selectively depositing a metal liner on the barrier layer (operation 20); and performing a gapfill process (operation 22).

[0023] Figure 2 illustrates an exemplary embodiment of an electronic device 100. The electronic device 100 includes a substrate 105 with a first layer 110 formed thereon. The substrate 105 can be any suitable substrate material for use with an electronic device. In some embodiments, the substrate 105 is a semiconductor substrate. In some embodiments, the substrate 105 can include additional layers of dielectrics, metals, etch stop layers and semiconductor layers including underlying circuits (e.g., transistors, capacitors) that have been formed in prior processes.

[0024] The first layer 110 is an optional layer. In some embodiments, the first layer 110 is omitted. In some embodiments, the first layer 110 is formed of a lamination of more than one layer. The first layer 110 can have any suitable function including, but not limited to, acting as an etch stop layer for previous or future microelectronic device manufacturing operations.

[0025] A first dielectric layer 140 is formed on a portion of the first layer 110. The first dielectric layer 140 has an inner sidewall 142 which defines a boundary of the first dielectric layer 140, leaving an opening. The opening can be, for example, a trench for a first metallization layer of the electronic device 100.

[0026] The first dielectric layer 140 can be any suitable material formed by any suitable technique. In some embodiments, the first dielectric layer 140 is formed of an oxide, a nitride, or any combination thereof. In some embodiments, the first dielectric layer 140 is formed of silicon oxide (SiC ). The first dielectric layer 140 may be deposited by one or more of chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced atomic layer deposition (PEALD), physical vapor deposition (PVD), or spin-on techniques.8899576PATENTAttorney Docket No.: 44025963WO01

[0027] The dielectric surface of the first dielectric layer 140 on the substrate 105 may be formed of any suitable dielectric materials. Suitable dielectric materials include, but are not limited to, oxides (e.g., silicon oxides (SiC )), IOW-K dielectric materials, and high-k dielectric materials. In some embodiments, the first dielectric layer 140 is formed of silicon oxide (SiC ), silicon nitride (SislS ), silicon carbooxynitride (SiCON), silicon oxycarbide (SiOC), aluminum oxide (AIOx), aluminum nitride (AINX), or any combination thereof.

[0028] In some embodiments, a liner 120 is formed on the top surface of the first layer 110 and abutting the inner sidewall 142 of the first dielectric layer 140. The liner 120 acts as one or more of an adhesion layer, barrier layer, or liner. The liner 120 can be any suitable material, including, but not limited to, oxides and nitrides. The liner 120 can be formed by any suitable technique. In some embodiments, the liner 120 is formed as a conformal film by atomic layer deposition (ALD).

[0029] In some embodiments, a first metal layer 130 is formed on the liner 120 and forms a first metallization layer. The first metal layer 130 can be any suitable material deposited by any suitable technique. Suitable metal materials include, but are not limited to, metals, metal nitrides, metal alloys, and other conductive materials. In some embodiments, the first metal layer 130 is formed of molybdenum (Mo), copper (Cu), cobalt (Co), tungsten (W), titanium nitride (TiN), or any combination thereof.

[0030] In some embodiments, an etch stop layer 150 is formed on the first metal layer 130. The etch stop layer 150 can be any suitable material formed by any suitable technique.

[0031] In some embodiments, the etch stop layer 150 is formed of aluminum oxide (AIOx), such as AI2O3, aluminum nitride (AINx), or combination thereof.

[0032] In some embodiments, a second dielectric layer 160 is formed on the etch stop layer 150. The second dielectric layer 160 can be any suitable material formed by any suitable technique. In some embodiments, the second dielectric layer 160 is formed of an oxide, a nitride, or combination thereof. In some embodiments, the second dielectric layer 160 is formed of a IOW-K dielectric material. In some embodiments, the second dielectric layer 160 is formed of silicon oxide. The second dielectric layer 160 may be deposited by one or more of chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition 8899576PATENTAttorney Docket No.: 44025963WO01(PECVD), plasma-enhanced atomic layer deposition (PEALD), physical vapor deposition (PVD), or spin-on techniques.

[0033] The dielectric surface of the second dielectric layer 160 may be formed of any suitable dielectric materials. Suitable dielectric materials include, but are not limited to, oxides (e.g., silicon oxides), IOW-K dielectric materials, and high-k dielectrics. In some embodiments, the second dielectric layer 160 is formed of silicon oxide (SiO2), silicon nitride (SislS ), silicon carbooxynitride (SiCON), silicon oxycarbide (SiOC), aluminum oxide (AIO%), aluminum nitride (AINX), or any combination thereof. In some embodiments, the second dielectric layer 160 is formed of the same material as the first dielectric layer 140. In some embodiments, the second dielectric layer 160 is formed of a different material than the first dielectric layer 140.

[0034] The substrate 105 including the second dielectric layer 160, the etch stop layer 150 and the first metal layer 130 has a feature 170 formed therein. The feature 170 is formed in the second dielectric layer 160 and the etch stop layer 150 exposing a top surface 132 of the first metal layer 130. The feature 170 illustrated has a via portion 172 and a trench portion 174.

[0035] The via portion 172 extends through the second dielectric layer 160 and the etch stop layer 150 to the first metal layer 130. The via portion 172 exposes the top surface 132 of the first metal layer 130. The top surface 132 of the first metal layer 130 forms a bottom surface 164 of the via portion 172. The via portion 172 is bounded on one side by a sidewall 162 of the second dielectric layer 160 and a sidewall 163 of the etch stop layer 150. The via portion 172 is bounded on another side by a lower sidewall 167 of the second dielectric layer 160 and the sidewall 163 of the etch stop layer 150. It should be noted that the via portion 172 may have a circular cross-section and that the use of a first side and a second side (e.g., one side and another side) to describe the via portion 172 is for descriptive purposes based on the cross-sectional views in the Figures. When the via portion 172 is a cylindrical hole, the sidewalls of the dielectric layer and the etch stop layer are continuous so that there is effectively a single sidewall, rather than a first side and second side (e.g., one side and another side) that appears in the cross-section.

[0036] The trench portion 174 has a bottom surface 168 formed from the second dielectric layer 160 and is bounded on one side by an upper sidewall 169 which is8899576 7PATENTAttorney Docket No.: 44025963WO01formed of the second dielectric layer 160. The trench portion 174 has an open side where the via portion 172 passes through the second dielectric layer 160 and etch stop layer 150.

[0037] The portion of the feature 170 not bounded by the via portion 172 and the trench portion 174 can be collectively referred to as a gap.

[0038] The substrate 105 includes a metal surface (the bottom surface 164 of the via portion 172), a dielectric surface (the sidewall 162, the lower sidewall 167, the bottom surface 168, the upper sidewall 169, and a top surface 161) and one or more of an aluminum oxide surface or an aluminum nitride surface (the sidewall 163 of etch stop layer 150).

[0039] Figure 3 illustrates the electronic device 100 of Figure 2 after selectively depositing a metal cap layer 179 on the metal surface of the substrate 105 (operation 12). The metal cap layer 179 may be formed of ruthenium (Ru), having a thickness of between about 1 A and about 30 A. During operation 12, the substrate 105 including the metal surface (the bottom surface 164 of the via portion 172), the dielectric surface (the sidewall 162, the lower sidewall 167, the bottom surface 168, the upper sidewall 169, and the top surface 161), and one or more of the aluminum oxide surface or the aluminum nitride surface (the sidewall 163 of the etch stop layer 150) is exposed to a ruthenium (Ru)-containing precursor, such as Ru(CO)s(1 -methyl-1 ,4-cyclohexadiene), Ru(CO)3(1-ethyl-1 ,4-cyclohexadiene), or Ru(CO)3(1-propyl-1 ,4-cyclohexadiene).

[0040] Figure 4 illustrates the electronic device 100 of Figure 3 after selectively depositing a blocking layer 180 on the metal cap layer 179 (operation 14). The substrate 105 including the metal surface (the metal cap layer 179 on the bottom surface 164 of the via portion 172), the dielectric surface (the sidewall 162, the lower sidewall 167, the bottom surface 168, the upper sidewall 169, and the top surface 161 ), and one or more of the aluminum oxide surface or the aluminum nitride surface (the sidewall 163 of the etch stop layer 150) is exposed to a blocking molecule, to form the blocking layer 180. The blocking layer 180 is selectively formed on the metal cap layer 179 (on the bottom surface 164 of the via portion 172) over the dielectric surface (the sidewall 162, the lower sidewall 167, the bottom surface 168, the upper8899576PATENTAttorney Docket No.: 44025963WO01sidewall 169, and the top surface 161) and the aluminum oxide surface or the aluminum nitride surface (the sidewall 163 of the etch stop layer 150).

[0041] In some embodiments, the blocking molecule used to deposit the blocking layer 180 is formed of alkyne molecules. In some embodiments, the blocking molecule is reacted with a metal surface of the metal cap layer 179 (e.g. ruthenium (Ru)) in solution or vapor phase. In some embodiments, the metal surface is cleaned prior to reaction with the blocking molecule.

[0042] The dielectric surface of the substrate 105 may be formed of any suitable dielectric materials. Suitable dielectric materials include, but are not limited to, oxides (e.g., silicon oxides), low-k dielectric materials, and high-k dielectrics.

[0043] In some embodiments, forming the blocking layer 180 in operation 14 includes soaking the substrate 105 in the blocking molecule. In some embodiments, forming the blocking layer 180 includes exposing the substrate 105 to pulses of the blocking chemistry. The pulses of blocking chemistry can be any suitable duration and occur any suitable number of times. In some embodiments, during formation of the blocking layer 180 occurs with greater than 1 , 10, 100, 250, 500 or 1000 pulses of blocking layer chemistry. In some embodiments, the total time for exposure to the blocking chemistry is greater than 1 second, 10 seconds, 100 seconds, 500 seconds or 1000 seconds.

[0044] In some embodiments, the alkyne groups cross-link with each other after deposition. In some embodiments, the blocking layer contains substantially no crosslinking between the alkyne groups.

[0045] In some embodiments, the substrate 105 is cleaned prior to depositing the metal cap layer 179 on the metal surface of the substrate 105 (operation 12). In some embodiments, only the metal surface of the substrate 105 is cleaned prior to depositing the metal cap layer 179 on the metal surface of the substrate 105. In some embodiments, the substrate 105 or the metal surface of the substrate 105 is cleaned with a hydrogen plasma. In some embodiments, the hydrogen plasma is a conductively coupled plasma (CCP). In some embodiments, the hydrogen plasma is an inductively coupled plasma (ICP). In some embodiments, the hydrogen plasma is formed of plasma of H2.8899576PATENTAttorney Docket No.: 44025963WO01

[0046] The blocking layer 180 is formed at a temperature that is favorable to close packing of the self-assembled monolayer of blocking chemistry species. In some embodiments, the substrate 105 is maintained at a temperature in the range of 100QC to 500QC, or in the range of 150QC to 450QC, or in the range of 200QC to 400QC, or in the range of 225QC to 350QC, or in the range of 250QC to 350QC, or in the range of 250QC to 300QC.

[0047] Pre-cleaning of the substrate can occur at any suitable temperature depending on, for example, the cleaning technique. In some embodiments, precleaning of the substrate occurs at a temperature in the range of 200QC to 500QC, or in the range of 300QC to 400QC.

[0048] Figure 5 illustrates the electronic device 100 of Figure 4 after formation of a barrier layer 190 on the surfaces of the second dielectric layer 160 and the etch stop layer 150 (operation 16).

[0049] In some embodiments, the barrier layer 190 is a dielectric layer that is selectively deposited on the dielectric surface after deposition of the blocking layer 180. In some embodiments, the barrier layer 190 is formed of silicon nitride. Deposition of silicon nitride can be performed through any suitable process. In one or more embodiments, the barrier layer 190 is formed by an atomic layer deposition (ALD) process. Suitable processes may include exposure of the substrate to a silicon halide and ammonia. Suitable silicon halides include, but are not limited to dichlorosilane (DCS), trichlorosilane (TCS), tetrachlorosilane (SiCk), tetrabromosilane (SiBr4), tetraiodosilane (Sik), and hexachlorodisilane (HCDS).

[0050] In some embodiments, the barrier layer 190 is formed of tantalum nitride (TaN). In some embodiments, the tantalum nitride (TaN) is deposited by a thermal atomic layer deposition (ALD) process. As used in this manner, a thermal process does not include a plasma. In some embodiments, the tantalum nitride is deposited using pentakis(dimethylamino)tantalum (PDMAT) and ammonia in a thermal ALD process.

[0051] In some embodiments, exposing the substrate to the blocking molecule (operation 14) is repeated after deposition of the barrier layer 190 (operation 16) to regenerate the blocking layer 180. In some embodiments, the barrier layer 190 is deposited again after the blocking layer 180 is regenerated. In some embodiments, 8899576PATENTAttorney Docket No.: 44025963WO01exposure of the substrate 105 to a blocking molecule and depositing the barrier layer 190 is repeated until the barrier layer 190 has reached a predetermined thickness.

[0052] The exposure to the surface blocking chemistry, or the regeneration of the blocking layer 109, can be performed once or repeated after a number of deposition cycles or after a predetermined film thickness is formed. In some embodiments, the barrier layer 190 is deposited with a thickness in the range of about 5 A to about 50 A, or in the range of about 10 A to about 40 A, or in the range of about 15 A to about 35 A before the blocking layer 180 is regenerated.

[0053] In some embodiments, the first metal layer 130 is formed of molybdenum (Mo), the etch stop layer 150 is formed of aluminum oxide, aluminum nitride, or combination thereof, the second dielectric layer 160 is formed of silicon oxide (SiC ), and the barrier layer 190 is formed of tantalum nitride (TaN).

[0054] In some embodiments, the barrier layer 190 is selectively deposited on the top surface 161 , the sidewall 162, the lower sidewall 167, the bottom surface 168, the upper sidewall 169 of the second dielectric layer 160 in the feature 170 and the surface (the sidewall 163) of the etch stop layer 150 after formation of the blocking layer 180 on the underlying metal surface (the bottom surface 164 of the via portion 172). Stated differently, the barrier layer 190 is deposited on the sidewall 162, the sidewall 163 of the via portion 172 and the bottom surface 168 and the upper sidewall 169 of the trench portion 174 of the feature 170. In some embodiments, the barrier layer 190 is formed on the sidewalls to the blocking layer 180 on the metal cap layer 179 on the metal surface. In some embodiments, a small gap is formed between the bottom surface 164 of the via portion 172 and the bottom edge of the barrier layer 190 due to the presence of the blocking layer 180.

[0055] Deposition of tantalum nitride (TaN) can be performed by any suitable process. In some embodiments, the barrier layer 190 is formed of one or more of tantalum nitride (TaN), titanium nitride (TiN), silicon nitride (SisN4), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN) or silicon oxynitride (SiON).

[0056] In the embodiment illustrated in the Figures, the barrier layer 190 is formed on the sidewall 162 of the via portion 172, the lower sidewall 167, the bottom surface 168 and the upper sidewall 169 of the trench portion 174 of the feature 170. The Figures do not show the barrier layer 190 material on the top surface 161 of the 8899576 11PATENTAttorney Docket No.: 44025963WO01second dielectric layer 160. In some embodiments, deposition of the barrier layer 190 results in formation of the barrier layer 190 on the top surface 161 of the second dielectric layer 160. The substrate 105 is then subjected to a process to remove the barrier layer 190 from the top surface 161 of the second dielectric layer 160, for example, by chemical mechanical planarization (CMP).

[0057] Figure 6 illustrates the electronic device 100 of Figure 5 after removal of the blocking layer 180 to expose the metal cap layer 179 on the bottom surface 164 of the via portion 172 (operation 18).

[0058] The blocking layer 180 can be removed by any suitable technique (operation 18). In some embodiments, removing the blocking layer 180 includes exposing the blocking layer 180 to hydrogen (H2) plasma. In some embodiments, the plasma is a capacitively coupled plasma (CCP). In some embodiments, the plasma is an inductively coupled plasma (ICP).

[0059] Figure 7 illustrates the electronic device of Figure 6 after deposition of a metal liner 192 on the barrier layer 190 (optional operation 20). In some embodiments, the metal liner 192 is selectively deposited on the barrier layer 190 by any suitable deposition process described herein. In some embodiments, the metal liner 192 is formed of ruthenium (Ru), cobalt (Co), molybdenum (Mo), tantalum (Ta), or any combination thereof. In some embodiments, the metal liner 192 is formed to a thickness in the range of 5 A to 25 A.

[0060] In some embodiments, the metal liner 192 is formed of cobalt (Co), the barrier layer 190 is formed of tantalum nitride (TaN), the etch stop layer 150 is formed of aluminum oxide aluminum oxide, the second dielectric layer 160 is formed of silicon oxide, and the first metal layer 130 is formed of tungsten.

[0061] Figure 8 illustrates the electronic device of Figure 7 after the gapfill process (operation 22) to deposit a second metal layer 195 in the feature 170. In some embodiments, the second metal layer 195 is deposited to fill the gap, i.e., the portion of the feature 170 not bounded by the via portion 172 and the trench portion 174. The second metal layer 195 is formed on the top surface of the first metal layer 130 (the bottom surface 164 of the via portion 172). In some embodiments, the second metal layer 195 is formed on the top surface of the metal liner 192. In some embodiments, the second metal layer 195 is formed of copper (Cu) or cobalt (Co). In some 8899576 12PATENTAttorney Docket No.: 44025963WO01embodiments, the second metal layer 195 is formed of copper (Cu). In some embodiments, the second metal layer 195 is formed of cobalt (Co).

[0062] In some embodiments, the second metal layer 195 is formed of copper (Cu), the metal liner 192 is formed of cobalt (Co), the barrier layer 190 is formed of tantalum nitride (TaN), the etch stop layer 150 is formed of aluminum oxide (AI2O3), the second dielectric layer 160 is formed of silicon oxide, the first metal layer 130 is formed of tungsten (W), and the second metal layer 195 is formed on the top surface of the first metal layer 130 that is exposed through the via portion 172 of the feature 170 and on the metal liner 192.

[0063] In embodiments where the metal liner 192 is not present, the second metal layer 195 is formed on the top surface of the first metal layer 130 that is exposed through the via portion 172 of the feature 170, the barrier layer 190 on the sidewall 162 of the via portion 172, and on the barrier layer 190 of the lower sidewall 167, the bottom surface 168 and the upper sidewall 169 of the trench portion 174.

[0064] In some embodiments, a blanket deposition process deposits the second metal layer 195 into the feature 170 and on the top surface 161 of the second dielectric layer 160. The second metal layer 195 is formed on the top surface 161 of the second dielectric layer 160 can be removed by any suitable technique including, but not limited to, etching and chemical mechanical planarization.

[0065] One or more embodiments of the disclosure are directed to a non-transitory computer readable medium including instructions, that, when executed by a controller of a processing chamber, cause the processing chamber to perform the operations of the method 10. In some embodiments, the non-transitory computer readable medium includes instructions, that, when executed by a controller of a processing chamber, cause the processing chamber to: deposit a cap layer selectively on a metal surface of a feature extending into a semiconductor substrate (operation 12); expose the feature to blocking molecule to form a blocking layer, the feature defining a gap including the metal surface, a dielectric surface, and an aluminum oxide surface or an aluminum nitride surface, the blocking layer forming selectively on the metal cap layer 179 over the dielectric surface and one of the aluminum oxide surface or the aluminum nitride surface (operation 14); selectively deposit a barrier layer on the dielectric surface and one of the aluminum oxide surface or the aluminum nitride surface over8899576 13PATENTAttorney Docket No.: 44025963WO01the blocking layer (operation 16); remove the blocking layer (operation 18); optionally, selectively deposit a metal liner on the barrier layer (operation 20); and performing a gapfill process (operation 22).

[0066] In the embodiments described herein, methods of enhancing selectivity in depositing self-assembled monolayers on metal surfaces over dielectric surfaces and reducing carbon residue after removing self-assembled monolayers during formation of interconnect structures in microelectronic devices. The methods described herein include depositing a metal cap layer (e.g., ruthenium (Ru)) prior to a self-assembled monolayer (SAM) soak process. The use of a thin selective ruthenium (Ru) cap layer on molybdenum (Mo) metal surfaces results in selective deposition of SAM on the metal surfaces in an extended area, and an improved ability to remove a SAM layer. Unwanted deposition of a barrier layer (e.g., tantalum nitride (TaN)) on the metal surface (e.g., molybdenum (Mo)) can be avoided and thus formation of metal nitride (e.g., molybdenum nitride (MoN)) can be mitigated.

[0067] Advantages of the method described herein are summarized in the Appendix.

[0068] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.8899576 14

Claims

PATENTAttorney Docket No.: 44025963WO01What is claimed is:

1. A method of forming a microelectronic device, the method comprising:depositing a metal cap layer on a metal surface of a feature formed in a substrate;depositing a self-assembled monolayer (SAM) selectively on the metal cap layer on the metal surface of the feature over a dielectric surface of the feature;depositing a barrier layer selectively on the dielectric surface; and removing the SAM.

2. The method of claim 1 , wherein the metal surface comprises molybdenum (Mo) and the metal cap layer comprises ruthenium (Ru).

3. The method of claim 1 , further comprising:selectively depositing a metal liner on the barrier layer.

4. The method of claim 3, wherein the metal liner comprises ruthenium (Ru), cobalt (Co), molybdenum (Mo), tantalum (Ta), or any combination thereof.

5. The method of claim 1 , further comprising:performing a gapfill process.

6. The method of claim 1, wherein depositing the SAM comprises soaking the substrate in blocking molecules.

7. The method of claim 6, wherein the blocking molecules comprise alkyne molecules.

8. The method of claim 1, wherein the barrier layer comprises one or more of tantalum nitride (TaN), titanium nitride (TiN), silicon nitride (SislSk), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), or silicon oxynitride (SiON).

9. A method of forming a microelectronic device, the method comprising:8899576 15PATENTAttorney Docket No.: 44025963WO01depositing a metal cap layer on a top surface of a first metal layer exposed within a feature opening extending through a dielectric layer that is formed on the first metal layer;depositing a blocking layer selectively on the metal cap layer on the top surface of the first metal layer exposed within the feature opening over sidewalls of the feature opening;depositing a barrier layer selectively on the sidewalls of the feature opening over the blocking layer;removing the blocking layer; andfilling the feature opening with a second metal layer.

10. The method of claim 9, wherein the first metal layer comprises molybdenum (Mo) and the metal cap layer comprises ruthenium (Ru).

11. The method of claim 9, further comprising:prior to filling the feature opening, selectively depositing a metal liner on the barrier layer.

12. The method of claim 11 , wherein the metal liner comprises ruthenium (Ru), cobalt (Co), molybdenum (Mo), tantalum (Ta), or any combination thereof.

13. The method of claim 9, wherein depositing the blocking layer comprises soaking the top surface of the first metal layer in blocking molecules.

14. The method of claim 13, wherein the blocking molecules comprise alkyne molecules.

15. The method of claim 9, wherein the barrier layer comprises one or more of tantalum nitride (TaN), titanium nitride (TiN), silicon nitride (SislS ), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), or silicon oxynitride (SiON).

16. The method of claim 9, wherein the second metal layer comprises copper (Cu) or cobalt (Co).8899576PATENTAttorney Docket No.: 44025963WO0117. A method of removal of self-assembled monolayer (SAM) from a metal surface, the method comprising:exposing the metal surface to a ruthenium (Ru)-containing precursor, forming a metal cap layer;depositing a self-assembled monolayer (SAM) on the metal cap layer; and removing the SAM from the metal surface, wherein carbon (C) residue on the metal surface after the removing the SAM is reduced as compared to a SAM removal without exposing the metal surface to the ruthenium (Ru)-containing precursor.

18. The method of claim 17, wherein the metal surface comprises molybdenum (Mo).

19. The method of claim 17, wherein depositing the SAM comprises soaking the metal surface in blocking molecules comprising alkyne molecules.

20. The method of claim 17, further comprising:prior to exposing the metal surface, pre-cleaning the metal surface.8899576 17

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