Hardware architecture for machine learning-based computation

Abstract

The disclosed subject matter includes a signal-processing system comprising an implantable system-on-chip (SoC) coupled to neural tissue and configured to acquire neural signals from a plurality of sensory channels. The implantable SoC includes one or more processors configured to execute a machine learning model using multiply-and-accumulate operations to process the neural signals prior to wireless transmission. By performing machine learning inference on the implantable SoC, the system reduces wireless communication bandwidth and supports scalable operation with increasing sensory channel counts while maintaining power and thermal constraints suitable for implantation.

Description

[0001] 070050.6988

[0002] CU25171 HARDWARE ARCHITECTURE FOR MACHINE LEARNING-BASED COMPUTATION

[0003] CROSS REFERENCE TO RELATED APLICATIONS

[0004] This PCT Application claims priority to the United States Provisional Application Serial No. 63 / 759,994 filed on February 18, 2025, the contents of which are hereby incorporated by reference in its entirety.

[0005] BACKGROUND

[0006] The disclosed subject matter relates to signal-processing systems and, more particularly, to signal-processing systems that incorporate on-implant machine learning computation architectures for processing neural signals.

[0007] The signal-processing systems enable communication between neural tissue and external devices by acquiring neural signals and decoding such signals into control outputs, including motion, speech, or other representations of user intent. Certain applications rely on implantable or wearable neural interfaces that record signals from large numbers of sensory channels at high sampling rates, resulting in a substantial volume of data to be processed and transmitted. In addition, certain systems transmit raw or lightly processed neural data to external computing platforms for decoding and interpretation. Such wireless transmission of high-bandwidth neural data can significantly increase power consumption and heat dissipation, constraining battery lifetime and limiting safe chronic operation of a signal-processing device. These constraints can be exacerbated as sensory channel counts and sampling rates increase.

[0008] While certain machine learning models, including deep neural networks (DNN), can improve decoding performance, executing such DNN models can require substantial computational resources and energy. General-purpose processors and computing architectures can be inefficient for implantable environments.070050.6988

[0009] CU25171 Accordingly, there remains a need for a signal-processing architecture that supports efficient on-implant machine learning inference while operating within power, thermal, and bandwidth constraints suitable for chronic implantation.

[0010] SUMMARY

[0011] The disclosed subject matter provides signal-processing systems including an implantable system-on-chip (SoC) configured to generate inference output from acquired sensory signals. An example system can include an interface having a plurality of sensory channels coupled to the implantable SoC and configured to acquire sensory signals, and a wireless communication interface configured to transmit processed output data to an external device. The implantable SoC includes one or more memories coupled to one or more processors configured to execute a machine-learning model using multiply-and-accumulate (MAC) operations to generate the processed output data.

[0012] In certain embodiments, the one or more processors comprise a plurality of processing elements (PEs), each including at least one MAC unit. The processors can execute the machine-learning model according to different architectural paradigms. For example, execution can occur according to a communication-centric architecture that prioritizes wireless transmission of processed output data, or according to a computation-centric architecture that prioritizes on-implant computation to reduce transmission data volume.

[0013] In certain embodiments, in the communication-centric architecture, sensory data are transmitted with minimal processing, such that wireless bandwidth scales with sensory channel count. In contrast, in the computation-centric architecture, sensory data are processed on the implantable SoC prior to transmission, thereby reducing transmitted data volume and associated communication bandwidth requirements.

[0014] In certain embodiments, the implantable SoC is architected according to a computation-centric framework in which computation resources are dimensioned based on070050.6988

[0015] CU25171 acquired sensory data throughput, latency constraints, and power density constraints associated with chronic implantation. The interface can comprise a neural interface, and the implantable SoC can be configured to be coupled to sensory tissue of a subject, including brain tissue in a brain-computer interface (BCI) system.

[0016] In certain embodiments, the processors are configured to execute the machinelearning model within a fixed time window corresponding to a sensory signal sampling interval, thereby supporting real-time inference under implant power and thermal constraints.

[0017] The disclosed subject matter provides methods for architecting an implantable system-on-chip (SoC) for an implantable signal-processing system. An example method includes acquiring sensory signals from a plurality of sensory channels using an implantable system-on-chip (SoC); executing, by the implantable SoC, a machine learning model on acquired sensory signals, wherein executing the machine learning model comprises performing a plurality of multiply-and-accumulate (MAC) operations; dimensioning computation processing elements of the implantable SoC based on computation workload requirements and implant power constraints; allocating resources among processing elements, the computation processing elements, and wireless communication processing elements to satisfy real-time processing and thermal safety constraints; generating processed output data based on execution of the machine learning model; and transmitting the processed output data from the implantable SoC to an external device via a wireless communication interface. In certain embodiments, dimensioning the computation processing elements includes determining a number of MAC units required to execute the machine learning model within a predefined latency interval corresponding to sensory signal acquisition.

[0018] In certain embodiments, the machine learning model comprises a deep neural network (DNN) including a plurality of layers. Determining the number of MAC units can include determining a number of independent MAC operations and a sequence length for each070050.6988

[0019] CU25171 neural network layer. Runtime for each neural network layer can be determined based on at least one of a sequence length, execution time of a MAC step, and available MAC units. Executing the machine learning model can further comprise dynamically selecting one or more active MAC operations based on at least one of a power constraint, a latency constraint, and a model complexity.

[0020] The disclosed subject matter further provides non-transitory computer-readable media storing instructions that, when executed by an implantable system-on-chip (SoC) of an implantable signal-processing system, cause the implantable SoC to acquire sensory signal data from a plurality of sensory channels; execute a machine learning model on acquired sensory signal data using one or more processors via multiply-and-accumulate (MAC) operations; dimension computation processing elements of the implantable SoC based on computation workload requirements and implant power constraints; allocate resources among processing elements, the computation processing elements, and wireless communication processing elements to satisfy real-time processing and thermal safety constraints; generate processed output data based on execution of the machine learning model; and transmit the processed output data to an external device via a wireless communication interface.

[0021] In certain embodiments, dimensioning the computation processing elements includes determining a number of MAC units required to execute the machine learning model within a predefined latency interval corresponding to sensory signal acquisition. In certain embodiments, the machine learning model comprises a deep neural network (DNN) including a plurality of layers. The instructions can cause the implantable SoC to schedule MAC operations to satisfy real-time latency constraints, determine a number of independent MAC operations and a sequence length for each neural network layer, and dynamically select one or more active MAC operations based on at least one of a power constraint, a latency constraint, and a model complexity.070050.6988

[0022] CU25171 BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings, which are incorporated and constitute part of this disclosure, illustrate preferred embodiments of the disclosed subject matter and serve to explain the principles of the disclosed subject matter.

[0024] FIG. 1 illustrates an example signal-processing system in which an implantable system-on-chip (SoC) is positioned relative to neural tissue and is configured to communicate wirelessly with an external device, according to one or more embodiments.

[0025] FIG. 2 illustrates a schematic dataflow for the implantable SoC, including both a communication-centric architecture and a computation-centric architecture, according to one or more embodiments.

[0026] FIG. 3 illustrates an example computation-centric dataflow in which neural signals are processed on the implantable SoC prior to wireless transmission using a machinelearning model, according to one or more embodiments.

[0027] FIG. 4A illustrates an example dataflow architecture for executing a deep neural network (DNN) layer on an implantable system-on-chip (SoC), including input registers, a dataflow finite state machine, processing elements, and output registers, according to one or more embodiments.

[0028] FIG. 4B illustrates example design configurations for processing elements used in executing DNN layers, including different arrangements of multiply-and-accumulate operations and hardware resources, according to one or more embodiments.

[0029] FIG. 4C illustrates example power consumption associated with execution of DNN layers and corresponding processing elements across multiple design configurations, according to one or more embodiments.070050.6988

[0030] CU25171 FIG. 4D illustrates example ratios of processing-element power consumption relative to total layer power consumption for different design configurations, according to one or more embodiments.

[0031] FIG. 5 illustrates example normalized power consumption of machine learning inference executed on an implantable SoC as a function of a number of neural interface channels for different neural network architectures, according to one or more embodiments.

[0032] Throughout the drawings, the same reference numerals and characters, unless otherwise stated, are used to denote like features, elements, components or portions of the illustrated embodiments. Moreover, while the disclosed subject matter will now be described in detail with reference to the FIGs., it is done so in connection with the illustrative embodiments.

[0033] DETAILED DESCRIPTION

[0034] The disclosed subject matter provides a computer chip device that can be safely coupled in the tissue to help interpret neural signals in real time. Instead of sending large amounts of raw tissue data wirelessly out of the body, the disclosed system analyzes the signals directly inside the tissue using machine learning techniques and only sends a smaller, processed result. This reduces wireless data transmission, lowers power consumption, and makes the system safer and more reliable for long-term use. The design can scale to work with many tissue sensors and can share processing tasks with an external wearable device when needed, enabling faster, more efficient tissue-computer interfaces for applications such as movement control or speech assistance.

[0035] The terms used in this specification generally have their ordinary meanings in the art, within the context of this disclosure, and in the specific context where each term is used. Certain terms are discussed below, or elsewhere in the specification, to provide070050.6988

[0036] CU25171 additional guidance to the practitioner in describing the compositions and methods of the disclosure and how to make and use them.

[0037] The terms “about” or “approximately” mean within an acceptable error range for the particular value as determined by one of ordinary skill in the art, which will depend in part on how the value is measured or determined, i.e., the limitations of the measurement system. For example, “about” can mean within 3 or more than 3 standard deviations, per the practice in the art. Alternatively, “about” can mean a range of up to 20%, up to 10%, up to 5%, and up to 1% of a given value.

[0038] The term “processing element (PE)” means a basic hardware compute unit within the SoC that performs arithmetic operations, typically including multiply-and-accumulate (MAC) operations.

[0039] The term “on-off keying (OOK)” means a simple digital modulation scheme used in wireless communication. In certain embodiments, a “1” is sent by turning the carrier signal ON; a “0” is sent by turning the carrier signal OFF.

[0040] FIG. 1 shows an example environment for a signal-processing system . An implantable SoC 101 is positioned adjacent to tissue 103, such as on or near a cortical surface. The implantable SoC 101 is configured to acquire neural signals from the tissue 103 , for example, through coupling with a neural interface including one or more sensing electrodes or sensor elements, and to perform on-implant processing of the acquired neural signals. In certain embodiments, the signal-processing system can be a brain-computer interface (BCI) system.

[0041] In the illustrated embodiments, the implantable SoC 101 is located beneath a dura mater layer 104 and a skull of a subject 105 and is configured to communicate wirelessly with an external device, such as a wearable SoC 102, located outside the skull. Wireless communication between the implantable SoC 101 and the wearable SoC 102 enables070050.6988

[0042] CU25171 transmission of processed output data generated by the implantable SoC 101 while avoiding transcutaneous wiring.

[0043] The arrangement shown in FIG. 1 is provided as a non-limiting example. In certain embodiments, the implantable SoC 101 can be positioned at different locations relative to the tissue 103, and the external device 102 can take various forms, including wearable, portable, or fixed computing devices. The illustrated configuration supports chronic implantation while enabling low-power operation and scalable neural signal processing. In certain embodiments, functionality of the implantable SoC 101 and the external device 102 can be partially integrated or co-designed within a unified wearable platform.

[0044] The implantable SoC is located within a subdural space between the dura mater and the tissue. Such placement provides a balance between invasiveness and signal quality, enabling the implantable SoC to acquire neural signals with high fidelity while remaining suitable for chronic implantation. The form factor of the implantable SoC allows conformal placement along the cortical surface and supports integration with a neural interface comprising a plurality of neural recording channels.

[0045] As shown in FIG. 1, the implantable SoC 101 is configured to wirelessly communicate with the external device 102 positioned outside the skull, such as a wearable system-on-chip (wearable SoC). Neural activity sensed by the implantable SoC 101 can be processed locally and transmitted, e.g., via a radio-frequency (RF) communication link, to the external device. In certain embodiments, the extent and type of processing performed on the implantable SoC 101 are selected based on constraints imposed by the biological environment, including power consumption, thermal limits, and characteristics of analog front-end components associated with neural signal acquisition.

[0046] FIG. 2 shows a schematic dataflow including two architectures for processing neural signals in an implantable interface signal-processing system. As shown, neural signal070050.6988

[0047] CU25171 data is generated by a neural interface 203, which can include a plurality of neural sensing channels coupled to neural tissue, thereby recording neural activity from neural tissue. The acquired neural data can be digitized and formatted for subsequent processing and / or transmission.

[0048] In a communication-centric architecture 201, communication functions can have a higher priority within the implantable device. Neural signal data acquired by the neural interface 203 is lightly or minimally processed and provided primarily to a wireless communication interface 205 for transmission to an external device. In this configuration, more than one data processing is performed outside the implant, and wireless bandwidth requirements can increase as the number of neural channels increases.

[0049] In a computation-centric architecture 202, computation functions are prioritized within the implantable device. Neural signal data from the neural interface 203 is provided to on-implant computation circuitry 204 prior to wireless transmission. The computation circuitry 204 is configured to execute machine-learning or other signal-processing operations, thereby generating processed or inference output data. The processed output data is then transmitted via the wireless communication interface 205. By performing computation on the implant, the computation-centric architecture can reduce the volume of data transmitted wirelessly relative to the communication-centric architecture. As used herein, computation circuitry in the disclosed subject matter can refer to, not limiting into, hardware circuitry of the implantable SoC configured to perform data processing operations, and can include one or more processors, processing cores, or processing elements, together with associated logic, registers, and memory. In certain embodiments, the computation circuitry executes machine-learning operations, including multiply-and-accumulate (MAC) operations, under control of stored instructions or configuration data. The computation circuitry can be implemented using070050.6988

[0050] CU25171 dedicated hardware, programmable logic, general-purpose processing units, or any combination thereof.

[0051] In the communication-centric architecture 201, the implantable SoC is configured to prioritize wireless transmission of neural data substantially as acquired from neural sensing channels. Processing performed on the implant is limited to front-end and transmission-enabling operations, such as signal conditioning, digitization, compression, and packetization, such that wireless transmission bandwidth scales with the number of neural interface channels. Alternatively, the computation-centric architecture 202 can prioritize execution of computational kernels directly on the implantable SoC. Such kernels can correspond to application-level functions, including but not limited to motion decoding, speech synthesis, vision decoding, neural state classification, or other machine-learning inference tasks, executed to transform raw neural signals into higher-level output representations prior to transmission.

[0052] In certain embodiments, the computation-centric architecture 202 is configured to minimize wireless communication requirements by generating inference output data that is substantially reduced in volume relative to raw neural data aggregated across the neural interface channels. Because inference outputs typically encode decoded intent, classification states, or other compressed representations, the required wireless data rate can be significantly lower than that required for transmission of unprocessed neural signals within such embodiments. Conversely, the communication-centric architecture 201, where feasible given wireless bandwidth and channel scaling constraints, can avoid implementation of computational kernels on the implantable device altogether, thereby reducing on-implant power consumption and design complexity. In such configurations, computational processing is performed primarily on an external wearable or companion device, which receives the070050.6988

[0053] CU25171 transmitted neural data and executes application-level decoding or machine-learning workloads.

[0054] FIG. 2 demonstrates different architectures implemented on an implantable SoC of a signal-processing system. In certain embodiments, the dataflow begins with acquisition of neural signals by a neural interface and terminates with wireless transmission via a transceiver.

[0055] For signal -processing applications that control external devices, the implantable SoC primarily transmits neural data or computation results to an external device, such as a wearable SoC. Reception of data from the external device can be performed intermittently for tasks such as configuration, calibration, or protocol establishment. In certain embodiments, the impact of the receiving direction on overall system architecture can be small relative to the transmitting direction.

[0056] In certain embodiments, the implantable signal-processing system includes an implantable SoC configured to acquire neural signals from a neural interface and to transmit data wirelessly to an external device. The implantable SoC can be positioned on a cortical surface of the tissue, for example, within a subdural space between the dura mater and tissue and can be configured with a substantially flat form factor suitable for chronic implantation, where the SoC has a low-profile geometry with a thickness that is small relative to its lateral dimensions, such that the SoC conforms to or lies adjacent to the cortical surface and reduces or minimizes localized protrusion into surrounding tissue. The implantable SoC senses neural activity and performs at least a portion of signal processing prior to wireless transmission.

[0057] In operation, the implantable SoC can implement a predefined data pipeline that begins with sensing neural data at the neural interface and ends with wireless transmission. In certain embodiments, the implantable SoC operates in a communication-centric mode in which reduced or minimal computation is performed locally and neural data are transmitted with070050.6988

[0058] CU25171 limited processing. In other embodiments, the implantable SoC operates in a computationcentric mode in which application-specific processing, including machine learning inference, is performed locally on the neural data prior to transmission. The computation-centric mode reduces the volume of data transmitted wirelessly while accommodating neural interface throughput requirements.

[0059] In certain embodiments, the implantable SoC is configured to operate within power and thermal constraints suitable for chronic implantation in neural tissue. Power consumption and silicon area can be selected to maintain a power density below a predetermined threshold associated with safe operation. In certain embodiments, safe operation can correspond to a thermal condition in which operation of the implantable SoC does not increase surrounding tissue temperature beyond a limited rise, for example on the order of certain range of temperature, e.g., approximately 1-2 °C. The implantable SoC can allocate resources among neural interface circuitry, computation circuitry, and wireless communication circuitry in accordance with the selected operating mode. Accordingly, implant operation can be constrained within a corresponding power density limit, for example on the order of approximately 40 mW / cm2, to maintain thermal safety.

[0060] In certain embodiments, total implant power consumption can be allocated among neural sensing circuitry, computation hardware, and wireless communication circuitry under a defined system power budget. Thermal modeling can assume substantially uniform heat dissipation across the implant surface, recognizing that localized activity variations can occur but are mitigated by heat spreading through surrounding tissue. Resource allocation within the implantable SoC is therefore selected to satisfy sensing, computation, and communication requirements while remaining within allowable thermal and power constraints.

[0061] In certain embodiments, implant physical architecture is configured to support high-density neural sensing while maintaining implantation compatibility. Flexible or070050.6988

[0062] CU25171 conformable substrates can be used to accommodate non-planar cortical surfaces and maintain contact between sensing elements and neural tissue. As neural channel counts increase, implant design can balance sensing area and supporting circuitry area to improve volumetric efficiency. This approach enables scaling of neural interfaces while maintaining safe thermal operation and manageable implant form factor.

[0063] In certain computation-centric embodiments, increased on-chip computation can be performed to reduce wireless communication bandwidth and associated transceiver power consumption. The resulting tradeoff between computation power and communication power enables the implantable SoC to remain within an overall power budget while supporting real-time neural decoding. In certain embodiments, machine learning computation is implemented using architectures that emphasize local data reuse and efficient execution of multiply-and-accumulate operations to improve energy efficiency.

[0064] The disclosed architectures enable scalability with increasing neural channel counts while maintaining power consumption and chip area within ranges suitable for implantable operation. By balancing computation, communication, and neural interface resources, the implantable SoC supports on-implant processing of neural signals while satisfying constraints imposed by the biological environment.

[0065] Scaling of Implantable SoC Architectures to Increased Channel Counts In certain embodiments, an implantable signal-processing system, e.g., BCI system, is configured to support a neural interface having a plurality of neural channels, for example, including channel counts on the order of approximately 1024 channels. Design considerations for scaling implantable SoC architectures to increased channel counts include silicon area, power consumption, power density, and signal quality constraints associated with chronic implantation.070050.6988

[0066] CU25171 In certain embodiments, the implantable SoC can support a maximum number of active channels determined by the architecture of the neural interface and associated analog front-end circuitry. The implantable SoC can be configured to acquire neural signals from the neural interface in parallel. For purposes of system design and comparison, the implantable SoC can be evaluated under a standardized channel configuration, such as a 1024-channel configuration, to assess scalability and compliance with power and thermal constraints.

[0067] In certain embodiments, scaling of implantable SoC designs to higher channel counts can be performed by extrapolating reported area and power characteristics associated with a lower channel count. Such extrapolation can account for both linear scaling effects and non-linear effects associated with increased routing complexity, inter-channel spacing, and analog-to-digital conversion overhead. In certain embodiments, silicon area can scale proportionally to a square root of a number of channels, while total power consumption can scale proportionally to the number of channels, based on reported per-channel area and power characteristics.

[0068] In certain embodiments, implantable SoC designs that do not meet power density constraints when scaled directly to increased channel counts can be modified to reduce power consumption, reduce silicon area, or both. Such modifications can include redesign of computation circuitry, reduction of per-channel power consumption, or improved spatial efficiency. In certain embodiments, power reduction techniques can be applied to maintain total power consumption below a predetermined threshold suitable for implantation, such as a threshold associated with limiting tissue heating.

[0069] In certain embodiments, special-purpose implantable SoC designs can employ alternative scaling approaches. For example, implantable SoCs configured to interface with penetrating neural probes or grouped electrode structures can scale area and power based on probe count rather than channel count. In such embodiments, scaling of area and power can be070050.6988

[0070] CU25171 performed linearly with respect to probe count to account for physical spacing constraints and implant geometry.

[0071] The disclosed scaling approaches enable evaluation and selection of implantable SoC architectures that support increased neural channel counts while maintaining power density, area, and thermal characteristics compatible with chronic implantation. These approaches can facilitate design of implantable systems that scale to high-channel-count neural interfaces without exceeding biological or operational constraints.

[0072] Scaling Beyond Multiple Neural Channels

[0073] In certain embodiments, an implantable signal-processing system, e.g., a BCI system is configured to support neural interfaces having channel counts greater than a range, for example 1024 channels. As channel counts increase, scaling considerations can extend beyond per-channel sensing circuitry to include computation and communication resources integrated on an implantable SoC. In certain embodiments, the implantable SoC partitions resources associated with sensing, computation, and wireless communication to support increased channel counts without exceeding power or thermal constraints.

[0074] In certain embodiments, scaling beyond a baseline channel count involves allocating a greater proportion of silicon area and power budget to neural sensing functions while maintaining sufficient resources for computation and communication. The implantable SoC can be configured such that sensing circuitry, computation circuitry, and communication circuitry scale differently as channel count increases. For example, sensing-related circuitry can scale approximately with channel count, while computation and communication resources can scale sub-linearly through reuse, multiplexing, or aggregation of neural data.

[0075] In certain embodiments, the implantable SoC can be designed to maintain operation within a predetermined power density limit as channel count increases. To achieve this, architectural modifications can be applied, including reduction of per-channel power070050.6988

[0076] CU25171 consumption, increased spatial efficiency, or redistribution of resources between sensing and computation. Such approaches enable scaling of implantable systems to higher channel counts while maintaining compatibility with chronic implantation constraints.

[0077] Real-Time Throughput and Dataflow Constraints

[0078] In certain embodiments, an implantable signal-processing system, e.g., a BCI system, operates under real-time throughput constraints imposed by neural signal acquisition. Neural signals acquired from a plurality of neural channels can be sampled at a predetermined sampling rate, such as on the order of kilohertz frequencies. The resulting data throughput establishes a real-time requirement for processing and transmission of neural data by the implantable SoC.

[0079] In certain embodiments, the implantable SoC processes neural signals using a computation-centric dataflow in which computation can be performed on the neural data at a rate substantially matching the rate at which the data are acquired. The computation can include machine learning inference operations executed by a machine learning computation subsystem, including execution of one or more layers of a neural network implemented using multiply-and-accumulate operations. Output data generated by the computation subsystem can represent decoded neural information and can have a lower data rate than the input neural signals.

[0080] In certain embodiments, the implantable SoC operates in a communicationcentric dataflow in which computation is limited and neural data are transmitted with minimal processing. In such embodiments, the required wireless communication throughput can scale approximately with the number of neural channels. In contrast, computation-centric architectures can reduce required communication throughput by performing local processing, thereby transmitting only processed or compressed data. Selection between computationcentric and communication-centric dataflows enables the implantable SoC to balance real-time throughput requirements, power consumption, and wireless bandwidth constraints.070050.6988

[0081] CU25171 Communication-Centric Architectures with Energy-Efficient Modulation In certain embodiments, a signal-processing system implements a communication-centric architecture in which an implantable SoC transmits neural data after digitization and packetization, with minimal local computation. In such embodiments, computation performed on the implantable SoC is limited primarily to preparing neural data for transmission, and substantially all digitized neural samples are communicated to an external device. As a result, a required wireless communication throughput of the implantable SoC is substantially determined by a sensing throughput associated with the neural interface.

[0082] In certain embodiments, the implantable SoC includes a wireless transceiver and an antenna configured to support a transmission bandwidth sufficient to accommodate the required communication throughput. The transceiver can implement one or more energyefficient modulation techniques selected to reduce energy consumption per transmitted bit while maintaining reliable communication. In certain embodiments, the modulation technique encodes a limited number of bits per symbol and is optimized to operate within a bandwidth supported by the antenna of the implantable SoC.

[0083] In certain embodiments, the implantable SoC employs on-off keying (OOK) or a similar energy-efficient modulation scheme. In such embodiments, each transmitted symbol encodes a single bit of information, and transmission parameters are selected to maintain a substantially constant energy per bit across a range of data rates. Practical design considerations, including antenna characteristics and noise tolerance, can limit the maximum achievable data rate below an ideal bandwidth limit. Nevertheless, such modulation can provide for efficient use of available bandwidth while maintaining energy efficiency suitable for implantable operation.

[0084] In certain embodiments, scaling a communication-centric architecture to increased neural channel counts increases the required communication throughput. The070050.6988

[0085] CU25171 implantable SoC can be configured such that additional neural channels contribute incrementally to both sensing power consumption and communication power consumption. In certain embodiments, the wireless transceiver is designed with sufficient performance margin to accommodate increased data rates associated with higher channel counts without requiring proportional increases in power consumption.

[0086] In certain embodiments, alternative design strategies are employed to improve scalability of communication-centric architectures. For example, the implantable SoC can be configured with a transceiver capable of operating beyond a baseline data rate, allowing increased channel counts to be supported within an existing power budget. In such embodiments, the proportion of total silicon area and power allocated to sensing circuitry can increase with channel count, while communication circuitry maintains substantially constant power characteristics.

[0087] In certain embodiments, selection of modulation schemes, transmission bandwidth, and transceiver operating parameters is configurable. The implantable SoC can adjust communication behavior based on channel count, sampling rate, available power budget, or thermal conditions. These communication-centric embodiments provide a flexible approach for supporting high-channel-count signal-processing systems while maintaining energy efficiency and compliance with implantation constraints.

[0088] Communication-Centric Architectures with Advanced Modulation

[0089] In certain embodiments, a signal-processing system, e.g. a BCI system implements a communication-centric architecture in which an implantable SoC supports increased wireless transmission throughput by employing advanced modulation techniques that encode multiple bits per symbol. Such modulation techniques enable higher data rates without requiring proportional increases in antenna size or transmission bandwidth, which is advantageous for implantable devices subject to size and bandwidth constraints.070050.6988

[0090] CU25171 In certain embodiments, the implantable SoC employs quadrature amplitude modulation (QAM) or other multi-level modulation schemes in which each transmitted symbol represents multiple bits of information. By increasing the number of bits per symbol, the implantable SoC can support higher effective data rates while maintaining a substantially constant symbol rate. In such embodiments, antenna dimensions and bandwidth can remain substantially unchanged as channel count increases.

[0091] In certain embodiments, use of advanced modulation techniques introduces increased transceiver complexity and variable energy consumption per transmitted bit. The implantable SoC can be configured to adjust modulation parameters, including constellation size or symbol mapping, to balance energy efficiency, signal integrity, and achievable throughput. In certain embodiments, energy per bit can increase as additional bits are encoded per symbol, reflecting tradeoffs between modulation efficiency and power consumption.

[0092] In certain embodiments, scaling a communication-centric architecture beyond a baseline neural channel count is achieved by increasing the number of bits per symbol rather than increasing the symbol rate. The implantable SoC can be configured such that non-sensing circuitry, including communication and computation circuitry, does not scale proportionally with channel count, thereby mitigating increases in silicon area and power consumption associated with higher channel counts.

[0093] In certain embodiments, advanced modulation techniques enable the implantable SoC to support increased neural channel counts while maintaining a power density suitable for chronic implantation. However, practical limitations associated with noise, interference, biological attenuation, and transceiver non-idealities can constrain achievable modulation efficiency. Accordingly, the implantable SoC can operate at modulation efficiencies below an ideal theoretical limit to ensure reliable communication and compliance with implantation constraints.070050.6988

[0094] CU25171 In certain embodiments, the selection of advanced modulation techniques is configurable. The implantable SoC can dynamically select between energy-efficient single-bit modulation and multi-bit modulation based on channel count, required data rate, available power budget, thermal conditions, or operating environment. Such configurability enables the signal-processing system to adapt communication behavior across a range of deployment scenarios while preserving energy efficiency and real-time performance.

[0095] Computation-Centric Architectures with On-Implant Deep Neural Networks (DNN)

[0096] In certain embodiments, a signal-processing system implements a computationcentric architecture in which an implantable SoC performs deep neural network (DNN) inference on acquired neural signals prior to wireless transmission. In such embodiments, increased on-implant computation is used to reduce wireless communication throughput requirements, enabling scaling to large neural channel counts while maintaining power and thermal constraints suitable for chronic implantation.

[0097] In certain embodiments, the computation-centric architecture is designed in accordance with a unified architectural methodology that defines how computational workloads are mapped onto implantable hardware subject to power density, throughput, and latency constraints associated with neural data acquisition. Such methodology provides rules for dimensioning computation resources of the implantable SoC based on neural interface characteristics and machine-learning workload requirements.

[0098] In certain embodiments, the implantable SoC is configured to execute one or more DNN layers, including fully connected layers or convolutional layers, using a plurality of processing elements that perform multiply-and-accumulate (MAC) operations. DNN inference workloads are well suited for execution on the implantable SoC because they are dominated by MAC operations and can be structured to exploit parallelism and local data reuse.070050.6988

[0099] CU25171 The implantable SoC can be optimized for inference rather than training, thereby reducing architectural complexity and power consumption. In certain embodiments, the computationcentric architecture of the implantable SoC is designed using a computational dimensioning methodology that characterizes machine-learning inference workloads relative to implant resource constraints. While prior accelerator designs often optimize data flow between processing units and external memory, implantable signal-processing systems instead employ a computation-centric, one-way pipeline in which neural data flows from the neural interface to computation circuitry and then to wireless transmission circuitry. Such architecture enables a non-Von Neumann execution model that minimizes reliance on centralized memory resources and supports application-specific neural signal processing within the implant.

[0100] The DNN inference workloads executed on the implantable SoC are dominated by matrix multiplications and convolution operations, both of which can be decomposed into sequences of MAC operations. To establish a lower-bound computation requirement for implantable inference acceleration, the architecture models computation in terms of MAC operation sequences executed by dedicated hardware units. In frameworks of certain embodiments, each MAC operation represents a sequence of steps in which two input values are multiplied and accumulated with a prior result. To dimension computation resources, the following variables are defined:

[0101] MACoPA sequence of operations in which each step includes multiplying two values and accumulating the result.

[0102] #MACop. Number of independent MAC operations required within a DNN layer. MACseq. Number of sequential accumulation steps within a MAC operation. MACim> Hardware cost of supporting one MAC operation, including compute logic and associated encapsulation resources within a processing element (PE).070050.6988

[0103] CU25171 These parameters characterize both computational workload and hardware provisioning requirements.

[0104] In certain embodiments, as illustrated in FIG. 3, the implantable SoC includes processing elements that each implement one or more MAC units. A MAC unit performs a sequence of operations including multiplication of input values and accumulation of results over multiple cycles. DNN layers can be decomposed into a series of MAC operations distributed across multiple processing elements. In certain embodiments, MAC operations are scheduled such that intermediate results are accumulated locally within a processing element, reducing data movement and improving energy efficiency. As illustrated in FIG.3, example relationships between MACop an MACseq parameters are presented. In one example, a matrixmatrix multiplication between a first matrix and a second matrix results in multiple independent MAC operations, with each MAC operation having a defined sequence length corresponding to the shared matrix dimension. In another example, a convolutional neural network layer having a defined kernel size and output size results in a corresponding number of MAC operations, each executed across a sequence of accumulation steps associated with kernel and channel dimensionality.

[0105] By definition, MAC operations within an individual neural network layer are independent and can be executed in parallel. Furthermore, the sequence length of MAC operations remains consistent across MAC operations of a given layer. For modeling simplicity, a complete MAC operation is assumed to be executed by a single MAC unit. Additionally, each MAC unit can execute multiple MAC operations through time-multiplexed scheduling. This modeling framework can allow minimization of required MAC hardware resources while establishing lower bounds on resource utilization and power consumption for implantable DNN execution.070050.6988

[0106] CU25171 To demonstrate implementation feasibility of the above embodiments of the disclosed subject matter, a DNN accelerator architecture can be constructed to execute neural network layers. In certain embodiments, such accelerator architecture includes a finite state machine (FSM) configured to control data movement and sequencing of MAC execution. Processing elements can include MAC units, activation function circuitry or processor such as rectified linear units (ReLU), local storage elements including registers or small memory blocks, and read-only memory configured to store neural network weights. The accelerator architecture can be configured at design time to support different neural network layer dimensions associated with multilayer perceptron (MLP) or convolutional neural network (CNN) workloads.

[0107] In certain embodiments, accelerator implementations are synthesized across varying values of MACop, MACseq, and MAChw parameters using semiconductor process technologies. Power consumption and execution characteristics can be evaluated using hardware synthesis and simulation tools to assess feasibility of executing DNN workloads within implantable system constraints.

[0108] FIG. 4A illustrates an example architecture for executing a DNN layer on an implantable SoC. Input data is received and stored in input registers 401, and execution is coordinated by a dataflow finite state machine (FSM) 402. The dataflow FSM 402 controls movement of data through a plurality of processing elements (PEs) 403, each configured to perform arithmetic operations associated with DNN inference. Intermediate results generated by the PEs 403 are stored in output registers 404. In the illustrated embodiment, each PE includes access to stored weights 405, one or more multiply-and-accumulate (MAC) units 407, and an activation function unit, such as a rectified linear unit (ReLU) 406. Control information can be stored in read-only memory 409, while registers 410 store intermediate or configuration070050.6988

[0109] CU25171 data. The architecture shown supports pipelined and parallel execution of DNN layers under control of the dataflow FSM 402.

[0110] FIG. 4B illustrates example design configurations for processing elements used to execute DNN layers. Each configuration can differ in parameters such as a number of MAC operations executed sequentially, a number of hardware MAC units operating in parallel, and a total number of MAC operations assigned to a layer. These configurations represent different tradeoffs between parallelism, latency, and hardware resource utilization. The illustrated configurations are provided as examples to demonstrate flexibility of the processing-element architecture. Alternative configurations can be used depending on application requirements, neural channel count, or power constraints.

[0111] In smaller accelerator configurations of certain embodiments, such as design variants 1-5, scaling is achieved primarily by increasing the number of independent MAC operations (#MACop), while MAC hardware resources (MAChw) remain limited. Under such conditions, relative PE power consumption remains comparatively low, for example at approximately twenty-five percent of total layer power. As MAC hardware resources are increased to match the number of independent MAC operations, as illustrated in design variants 6-9, total power consumption increases. In these configurations, PE power consumption can reach approximately eighty percent of total power. Further scaling of #MACop, MAChw, and MACseq, as illustrated in design variants 10-12, increases relative PE power contribution to approximately ninety-six percent, demonstrating that PE computation hardware represents a primary driver of overall power consumption and supporting lower-bound power modeling proportional to MAChw.

[0112] FIG. 4C illustrates example power consumption associated with execution of DNN layers across different design configurations. As shown, both total layer power consumption and power attributable to individual processing elements can vary based on070050.6988

[0113] CU25171 configuration parameters such as degree of parallelism and sequencing of MAC operations. The illustrated trends demonstrate how increasing computational capacity, or parallelism can increase power consumption, and how design choices affect overall system power behavior. These examples are provided to illustrate relative scaling behavior rather than to impose specific power requirements.

[0114] FIG. 4D illustrates example ratios of processing-element power consumption relative to total layer power consumption for different design configurations. The ratio indicates a proportion of power consumed by computation circuitry relative to other components involved in executing a DNN layer. As shown, in certain configurations the processing elements account for a larger fraction of total layer power, while in other configurations non-compute components contribute more significantly. This illustrates tradeoffs in architecture design and supports selection of configurations that balance computation efficiency with overall system power constraints.

[0115] Optimization Methodology

[0116] Under real-time operating constraints, the maximum allowable execution time for DNN inference is determined by neural interface sampling frequency, such that:

[0117] y = i / t

[0118] To implement a hardware-based DNN capable of executing NNN layers within time t, computation workload parameters can first be determined for each layer.

[0119] A function f AC is defined to characterize MAC execution requirements for each DNN layer:

[0120] JV]

[0121] ely, the number of

[0122]

[0123] J’

[0124] independent MAC operations and the sequence length for the z-th DNN layer.070050.6988

[0125] CU25171 The runtime for execution of the z-th layer, denoted ti , is defined as:

[0126]

[0127] subject to:

[0128] N

[0129] 2 / - < t

[0130] i=l

[0131] where tMACrepresents the execution time of a single MAC step using one MAC unit.

[0132] In certain embodiments, hardware provisioning constraints require that the number of MAC units satisfies:

[0133] #MAChw> 0,#MAChw< max(#MACQlp),

[0134] ensuring that MAC hardware allocation remains feasible relative to computation workload requirements of individual layers.

[0135] Based on MAC hardware provisioning, a lower bound on computation power consumption Pcompcan be expressed as:

[0136] Pcomp #MAChw.PMAC

[0137] PMACrepresents power consumption associated with operation of a single MAC unit.

[0138] If pipelined execution across DNN layers is implemented, runtime constraints can be reformulated as:

[0139] <

[0140]

[0141] 070050.6988

[0142] CU25171 and MAC hardware provisioning across layers satisfies:

[0143] N N

[0144] #MAChw> 0,#MAChw= Y #MAC.1< Y #MAC1

[0145] Z—i hw -j op

[0146] i=l i=l

[0147] where#MAC^ represents MAC units allocated to the z-th layer.

[0148] Following DNN inference execution on the implantable SoC, the volume of data transmitted wirelessly is reduced relative to transmission of raw neural data. As neural channel count increases, communication power consumption Pcompis correspondingly reduced,

[0149] offsetting increases in computation power consumption. This relationship enables evaluation of conditions under which investment in on-implant computation yields greater system efficiency than investment in higher-throughput wireless communication architectures.

[0150] The computation modeling methodology establishes an architectureindependent lower bound on DNN power consumption based on the minimum number of MAC units required for correct inference execution. This lower bound provides a conservative estimate for evaluating whether a given DNN workload can operate within implant power and performance constraints. Where margin exists between the lower bound and the total system power budget, additional microarchitectural optimizations can be incorporated.

[0151] In certain embodiments, MAC units are synthesized using semiconductor process technologies. For example, a MAC unit synthesized using a forty-five nanometer technology library and operating at a target clock frequency of one hundred megahertz results in execution timing and power characteristics suitable for implant modeling.

[0152] DNN workloads, including DenseNet convolutional neural networks and multilayer perceptron (MLP) networks trained for speech synthesis using neural data, can be evaluated using the computation modeling framework. Example baseline models can be070050.6988

[0153] CU25171 configured for neural interfaces comprising one hundred twenty-eight channels sampled at approximately two kilohertz, with inference outputs corresponding to speech feature decoding.

[0154] For each modeled DNN, performance can be evaluated under pipelined and non-pipelined execution architectures to determine feasible operating configurations under implant constraints.

[0155] FIG. 5 illustrates example scaling behavior of power consumption for computation-centric architectures implemented on an implantable SoC. The horizontal axis represents a number of neural interface (NI) channels, and the vertical axis represents normalized power consumption relative to a predetermined power budget. Separate plots are shown for different machine learning architectures, including, by way of example, convolutional neural network (CNN)-based models and multi-layer perceptron (MLP)-based models. The data presents lower-bound power estimates for implantable SoCs scaled across different neural interface channel counts.

[0156] As shown, the lower bound of SoC power consumption Psoc relative to an allowable power budget P budget is evaluated for multiple implantable SoC design configurations. Each design is scaled to accommodate increasing numbers of neural interface channels. The analysis demonstrates that, even at a current standard channel count, e.g., approximately 1024 channels, certain SoC implementations do not possess sufficient power budget to integrate the lower bound of DNN computation power.

[0157] In certain embodiments, only a subset of SoC designs are capable of integrating dense neural network computation within the available power budget. For example, selected SoC designs can accommodate DenseNet convolutional neural network (DN-CNN) workloads with certain chancel counts, e.g., approximately 1024 neural channels, while other designs exceed the allowable power budget by multiple factors when evaluated under equivalent scaling conditions.070050.6988

[0158] CU25171 For multilayer perceptron (MLP) neural network models, scaling feasibility can be further constrained. In certain embodiments, only a limited subset of SoC designs can integrate MLP workloads within the available power budget at 1024 neural channels. Other designs exceed the allowable power budget at this channel scale.

[0159] Among implantable SoCs capable of accommodating DNN workloads, an average maximum neural channel capacity can be estimated. For example, certain SoC designs exhibit maximum feasible integration at approximately: 1800 neural channels for MLP workloads, and 1400 neural channels for DN-CNN workloads. These values represent approximate upper bounds under lower-bound power estimation conditions.

[0160] In comparison, when implant resources are instead allocated to advanced wireless communication architectures, higher neural channel scaling can be achievable under equivalent power constraints. For example, approximately 1800 neural channels can be supported using communication-centric modulation approaches operating at reduced modulation efficiency levels. This comparison demonstrates that, when scaling to approximately twice the current neural channel standard, communication-centric implant architectures can provide greater feasibility than computation-centric architectures executing full DNN inference on-implant.

[0161] Accordingly, in certain embodiment, a first-order lower-bound power analysis of modern DNN workloads can be used to indicate that neural network accelerators relying solely on MAC computation scaling may not achieve channel scaling beyond approximately twice current implant standards without exceeding allowable power budgets. This observation highlights system-level constraints associated with integrating full DNN accelerators into implantable signal-processing system SoCs using current semiconductor and architectural design approaches.070050.6988

[0162] CU25171 In certain embodiments, computation-centric architectures enable more favorable scaling behavior compared to communication-centric architectures as neural channel count increases. By reducing the volume of data transmitted wirelessly, the implantable SoC shifts energy consumption from communication to computation, which can scale more efficiently with channel count. This approach can be advantageous for signal-processing systems with large numbers of neural channels and stringent real-time throughput requirements.

[0163] In certain embodiments, the implantable SoC supports configurable execution of a DNN inference. Parameters such as number of layers executed on-implant, degree of parallelism, MAC utilization, and execution frequency can be adjusted based on channel count, available power budget, and application requirements. In certain embodiments, the implantable SoC cooperates with an external device to execute remaining portions of a DNN, providing enabling split inference configurations.

[0164] In certain embodiments, while advanced communication techniques can be used to support increased channel counts, computation-centric architectures provide improved scalability for large-scale signal-processing systems. By integrating DNN inference directly on the implantable SoC, the signal-processing system reduces dependence on high-throughput wireless communication and provides operation within biological and technological constraints associated with chronic implantation.

[0165] In certain embodiments, a signal-processing system employs a computationcentric architecture in which an implantable SoC executes machine learning inference using a combination of architectural and model-level optimizations. By performing inference on the implantable SoC, wireless communication requirements are reduced, providing for the system to scale to increased neural channel counts while operating within power, thermal, and area constraints suitable for chronic implantation.070050.6988

[0166] CU25171 In certain embodiments, DNN execution can partitioned between the implantable SoC and an external device. The implantable SoC can execute one or more initial layers of a DNN, while remaining layers are executed externally. In certain implementations, one or more initial layers of the DNN are executed on-implant, while subsequent layers are executed off-implant. Partition selection can be performed based on communication bandwidth, computational workload, and latency constraints. This approach, sometimes referred to as layer reduction, reduces on-implant computation power consumption while trading off increased wireless transmission of intermediate feature data. The partition point may be selected such that required communication throughput does not exceed that of a communication-centric architecture designed for a comparable neural channel count. Partitioning reduces computational workload and power consumption on the implantable SoC while limiting the volume of data transmitted wirelessly. The partition point can be selected based on channel count, model architecture, power budget, or latency requirements.

[0167] In certain embodiments, additional complementary optimization strategies are applied individually or in combination with DNN partitioning to further improve scalability. These include channel dropout, in which neural data from a subset of sensing channels is selectively omitted to reduce computational workload; technology scaling, in which computation circuitry is implemented in a more advanced semiconductor process node to reduce per-operation energy; and channel density optimization, in which physical sensing area and inter-channel spacing are adjusted to improve volumetric efficiency while respecting thermal limits. Evaluation of these optimizations can be performed using the same MAC -based workload and power modeling framework described herein, thereby enabling unified assessment of computation, communication, and sensing tradeoffs. Collectively, these techniques facilitate design of computation-capable implantable signal-processing systems that achieve safe operation and scalable neural interfacing at increased channel counts.070050.6988

[0168] CU25171 While the disclosed subject matter is described herein in certain embodiments of BCI systems, the architectural methodologies, design rules, and computational scaling approaches disclosed herein are not limited to neural applications. In certain embodiments, the disclosed SoC architectures and associated computation-communication partitioning techniques can be applied to any implantable and / or edge-based sensory interface system in which a device operates under power and thermal constraints, acquires high-volume sensory data from a plurality of sensory channels, and performs machine-learning or signal-processing operations subject to real-time throughput or latency requirements. By way of example, such systems can include implantable or wearable physiological monitoring platforms, neuromodulation devices, prosthetic control systems, or other bioelectronic sensing platforms. More generally, the disclosed methodologies can extend to non-biological edge devices that process multi-channel sensor data under constrained energy and communication budgets, where computation workloads are characterizable using MAC -based analysis consistent with the design framework described herein.

[0169] The foregoing merely illustrates the principles of the disclosed subject matter. Various modifications and alterations to the described embodiments will be apparent to those skilled in the art in view of the teachings herein. It will thus be appreciated that those skilled in the art will be able to devise numerous techniques which, although not explicitly described herein, embody the principles of the disclosed subject matter and are thus within the spirit and scope of the disclosed subject matter.

Claims

070050.6988CU25171 WHAT IS CLAIMED IS:

1. A signal-processing system, comprising:an implantable system-on-chip (SoC) configured to generate inference output;an interface comprising a plurality of sensory channels and coupled to the implantable SoC and configured to acquire sensory signals from the plurality of sensory channels; and a wireless communication interface coupled to the implantable SoC and configured to transmit processed output data to an external device,wherein the implantable SoC includes one or more memories coupled to one or more processors configured to execute a machine learning model to generate the processed output data using multiply-and-accumulate (MAC) operations.

2. The system of claim 1, wherein the one or more processors comprise a plurality of processing elements (PEs), each including at least one MAC unit.

3. The system of claim 2, wherein the one or more processors are configured to execute the machine learning model selectively using(a) a communication-centric architecture prioritizing wireless transmission of the processed output data; or(b) a computation-centric architecture prioritizing on-implant computation.

4. The system of claim 3, wherein in the communication-centric architecture, the processed output data are transmitted with minimal processing and wireless bandwidth scales with sensory channel count.

5. The system of claim 3, wherein in the computation-centric architecture, the processed output data are processed on-implant to reduce transmission data volume.

6. The system of claim 1, wherein the implantable SoC is architected according to a computation-centric architecture that dimensionally allocates computation resources based on070050.6988CU25171 acquired sensory signal data throughput, latency constraints, and power density constraints associated with chronic implantation.

7. The system of claim 1, wherein the interface comprises a neural interface.

8. The system of claim 1, wherein the implantable system-on-chip (SoC) is configured to be coupled to sensory tissue of a subject.

9. The system of claim 8, wherein the signal-processing system comprises a braincomputer interface (BCI) system.

10. The system of claim 1, wherein the one or more processors are configured to execute the machine learning model within a fixed time window corresponding to a sensory signal sampling interval.

11. A method for architecting an implantable system-on-chip (SoC) for an implantable signal-processing system, comprising:acquiring sensory signals from a plurality of sensory channels using an implantable system-on-chip (SoC);executing, by the implantable SoC, a machine learning model on acquired sensory signals, wherein the executing the machine learning model comprises performing a plurality of multiply-and-accumulate (MAC) operations;dimensioning computation processing elements of the implantable SoC based on computation workload requirements and implant power constraints;allocating resources among processing elements, the computation processing elements, and wireless communication processing elements to satisfy real-time processing and thermal safety constraints;generating processed output data based on execution of the machine learning model; and070050.6988CU25171 transmitting the processed output data from the implantable SoC to an external device via a wireless communication interface,wherein dimensioning the computation processing elements includes determining a number of MAC units required to execute the machine learning model within a predefined latency interval corresponding to sensory signal acquisition.

12. The method of claim 11, wherein the machine learning model comprises a deep neural network (DNN) including a plurality of layers.

13. The method of claim 12, wherein determining the number of MAC units includes: determining a number of independent MAC operations and a sequence length for each neural network layer.

14. The method of claim 12, wherein runtime for each neural network layer is determined based on at least one of a sequence length, execution time of a MAC step, and available MAC units.

15. The method of claim 11, wherein the executing the machine learning model comprises dynamically selecting one or more active MAC operations based on at least one of a power constraint, a latency constraint, and a model complexity.

16. A non-transitory computer-readable medium storing instructions that, when executed by an implantable system-on-chip (SoC) of an implantable signal-processing system , cause the implantable SoC to:acquire sensory signal data from a plurality of sensory channels;execute a machine learning model on acquired sensory signal data using one or more processors via multiply-and-accumulate (MAC) operations;dimension computation processing elements of the implantable SoC based on computation workload requirements and implant power constraints;070050.6988CU25171 allocate resources among processing elements, the computation processing elements, and wireless communication processing elements to satisfy real-time processing and thermal safety constraints; andgenerate processed output data based on execution of the machine learning model; and transmit the processed output data to an external device via a wireless communication interface,wherein dimensioning the computation processing elements includes determining a number of MAC units required to execute the machine learning model within a predefined latency interval corresponding to sensory signal acquisition.

17. The non-transitory computer-readable medium of claim 16, wherein the machine learning model comprises a deep neural network (DNN) including a plurality of layers.

18. The non-transitory computer-readable medium of claim 16, wherein the instructions cause the implantable SoC to schedule MAC operations to satisfy real-time latency constraints.

19. The non-transitory computer-readable medium of claim 16, wherein determining the number of MAC units includes:determining a number of independent MAC operations and a sequence length for each neural network layer.

20. The non-transitory computer-readable medium of claim 16, wherein executing the machine learning model comprises dynamically selecting one or more active MAC operations based on at least one of a power constraint, a latency constraint, and a model complexity.

Images