Techniques for execution memory indirection addressing for memory architectures

Abstract

This invention relates to techniques for performing memory indirect addressing for memory architectures. Various embodiments generally relate to apparatus, methods, and other techniques for receiving a request from a core associated with a memory operation to read or write data, the request including a first address and an offset, the first address identifying a memory location. Embodiments include: a first iteration of performing a memory indirect addressing operation, including reading memory at the memory location to determine a second address based on the first address, and determining a memory resource based on the second address and the offset, the memory resource to be used to perform a memory operation on a computing resource or a second iteration of performing the memory indirect addressing operation.

Description

Technical Field

[0001] The embodiments described herein generally include techniques for performing memory indirect addressing operations in memory systems. Background Technology

[0002] Computing data centers typically comprise several resources, such as computing resources, memory resources, accelerator resources, and so on. These resources can be stored in various computing architectures (e.g., servers or sleds) and can physically reside across multiple racks. A sled can include several resources interconnected via one or more computing architectures, buses, and interconnects. Computing resources, such as processing cores, can issue memory operation requests and prefetch instructions associated with memory resources coupled via interconnects. However, in some cases, these interconnected requests and instructions can become latency-constrained because one or more subsequent processing steps cannot proceed, unless the content of the proceeding steps is known at the requesting core. As a result, memory operations are slow, latency-constrained, and generate significant serialization in the request flow across the interconnect. Attached Figure Description

[0003] Figure 1A The first example of the system is shown.

[0004] Figure 1B A second example of the system is shown.

[0005] Figure 2 An example of the first logical flow is shown.

[0006] Figure 3 An example of the second logical flow is shown.

[0007] Figure 4A An example of the first processing flow is shown.

[0008] Figure 4B An example of the second processing flow is shown.

[0009] Figure 4C An example of a third processing stream is shown.

[0010] Figure 5 An example of a third logical flow is shown.

[0011] Figure 6 An example embodiment of a computing architecture is illustrated. Detailed Implementation

[0012] The embodiments discussed herein may involve performing memory indirect addressing operations to enable latency-constrained memory operations, such as reading data from memory and writing data to memory, that suffer from severe serialization in the memory request stream. As software tends to use more outward-extending architectures, providing memory semantics over the interconnect becomes important. Common software operations involve memory operations that need to be resolved at the core or processor. For example, databases often use list traversals or tree traversals involving “pointer solving.” However, in some cases, prefetching over the interconnect fails because one or more subsequent processing steps cannot proceed unless the content of the proceeding steps is known, for example, there is a strong dependency that the proceeding steps must be completed in that core. As a result, performing the aforementioned memory operations is slow, latency-constrained, and introduces severe serialization in the request stream over the interconnect.

[0013] In embodiments, one or more iterations of memory indirect addressing operations can be performed to address these dependencies and serialization issues. For example, an iteration of memory indirect addressing may include: a processing core issuing a request to perform a memory operation, and a memory resource with an interface receiving the request from the core. The request may include an address and offset pointing to a memory location of the memory resource. The address and offset may be used to determine another address of the memory location and to perform another iteration of the memory indirect addressing operation, or the memory location may include data to be returned to the core. In some cases, the request may include an indication of the number of iterations to be performed to perform memory indirect addressing operations such that processing read or write data is performed. These and other details will become more apparent in the following description.

[0014] Reference is now made to the accompanying drawings, wherein the same reference numerals are used throughout to refer to the same elements. In the following description, numerous specific details are set forth for purposes of explanation to provide a thorough understanding therefrom. However, it will be apparent, however, that novel embodiments can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form to facilitate description. The intention is to cover all modifications, equivalents, and alternatives consistent with the claimed subject matter.

[0015] Figure 1A Example embodiments of a system 100 in which various aspects of this disclosure can be employed to perform memory indirect addressing techniques are illustrated. System 100 may include several resources, such as computing resources 101-1 to 101- x ,in x It can be any positive integer, and the memory resources are 151-1 to 151- y ,in yIt can be any positive integer. In an embodiment, computing resource 101 and memory resource 151 may be part of a rack-configured data center. Each of computing resource 101 and memory resource 151 may reside in one of a plurality of racks. The rack configuration may include other resources, such as accelerator resources and storage resources. Furthermore, the resources may be implemented virtually, physically, or in a hybrid virtual and physical manner. The embodiment is not limited to this example.

[0016] In this embodiment, the resources including computing resource 101 and memory resource 151 are coupled via one or more interconnects 130, such as fabric networks (Omnipath® or InfiniBand®) or Ethernet networks. Other examples of the one or more interconnects 130 include QuickPath® interconnect (QPI), high-speed peripheral component interconnect (PCIe), UltraPath interconnect (UPI), and so on. Interconnect 130 may include one or more switches, bridging interconnects, routers, and network devices to support fabric or Ethernet communication. For example, interconnect 130 transmits information and data electrically and / or optically between computing resource 101 and memory resource 151.

[0017] Computing resource 101 includes circuitry for processing information and data. For example, each computing resource 101 includes one or more central processing units (CPUs) 110 having one or more cores 112. The CPU 110 can be one or more of any type of computing element, such as, but not limited to: microprocessors, processors, computing processing units, digital signal processing units, dual-core processors, mobile device processors, desktop processors, single-core processors, system-on-a-chip (SoC) devices, complex instruction set computing (CISC) microprocessors, reduced instruction set computing (RISC) microprocessors, very long instruction word (VLIW) microprocessors, or any other type of processor or processing circuitry on a single chip or integrated circuit.

[0018] Furthermore, each CPU 110 includes one or more cores 112, each core 112 being a unit for reading and executing program instructions. Instructions are CPU instructions, such as add, move, load, and branch. A single CPU 110 with multiple cores 112 can run multiple instructions simultaneously on separate cores, thereby improving overall speed. In embodiments, core 112 includes elements for reading and writing data in memory (such as memory 153 of memory resource 151) via interface 120. In one example, core 112 may issue a load instruction via interface 120 to read data from memory at a location and place it into one or more registers of core 112. The load instruction may be included in a request transmitted to memory resource 151 via interconnect 130. In some cases, remote direct memory access (RDMA) is used to perform reads and writes regarding memory 153 of memory resource 151.

[0019] In this embodiment, interface 120 can be any type of interface, such as a Host Configuration Interface (HFI) for communication via a network configuration, a Network Interconnect Card (NIC) interface for communication via an Ethernet network, a PCIe interface, a Memory Configuration Interface, a QPI interface, a UPI interface, and so on. Interface 120 can receive requests from core 112 to perform transactions concerning memory resource 151. Furthermore, interface 120 can receive responses from memory resource 151. For example, interface 120 can receive a response from memory resource 151 for a request for data, the response including the requested data.

[0020] Interface 120 enables indirect addressing memory operations by exposing instruction capabilities to perform indirect addressing memory operations with respect to memory resource 151. Indirect addressing memory operations may include processing requests, such as read or write requests issued to memory resource 151 coupled via interconnect 130. A request may include an address and an offset, with the address pointing to a memory location having another address. This other address is used with the offset to determine a third address, which may be the actual location to process the request (read / write). However, in some embodiments, the location identified by the third address may even include another address, which may be used with another offset to determine a fourth address and another location that can be used to process the request. Multiple address layers may exist, and processing of addresses pointing to locations with other addresses may be repeated any number of times until the actual location to process the request is determined and data can be returned to the request core.

[0021] In an embodiment, instruction capability may include a construct load instruction that can be used by the receiving interface to determine, based on the instruction itself, whether the request is an indirect addressing instruction, such as "FABRIC-LOAD-I". <addr> , <offset>In some cases, memory indirect addressing operations can be performed locally within the same computing resource 101 that issues the load instruction for the request. In this example, the instruction capability may include utilizing a load instruction with parameters for local memory indirect addressing (e.g., "LOAD"). <addr> , <offset>The local load instruction is used to perform memory indirect addressing operations on memory requests in non-de-aggregated memory. The local load instruction can be processed locally by interface and / or memory controller circuitry (e.g., interface 120 or memory controller circuitry of the computing resource 101 that issued the request). Note that the embodiments are not limited to specific instruction names such as "FABRIC-LOAD-I" and "LOAD". <addr> , <offset>Furthermore, different naming conventions can be envisioned, allowing the interface and memory controller circuitry to recognize instructions as indirect addressing instructions, including both the address and offset.

[0022] In some embodiments, the construct load and / or load instructions may include instructions for several indirection addresses. In some cases, instead of a single indirection address, several nested indirection addresses occur as the request is processed. Furthermore, indirection addresses can be local, such as within the same resource, or remote, such as via interconnect coupling. In one example, the construct instruction could be "FABRIC-LOAD-I, <number of indirection addresses>, <addr> , <offset>Furthermore, the load instruction can be "LOAD <number of indirect addresses>", <addr> , <offset>The embodiments are not limited to these examples.

[0023] Interface 120 enables existing write semantics with a payload targeting a de-aggregated memory (e.g., memory resource 151) coupled via interconnect 130 to indicate that the request is an indirect addressing instruction. One or more bits in the payload of the request can be used to indicate that the request is an indirect addressing instruction. For example, core 112 can issue a request with bits in the payload indicating that the request is an indirect addressing instruction. The receiving interface can process the request accordingly, for example, as an indirect addressing instruction, as will be discussed in more detail below.

[0024] The embodiments include a memory resource 151 having memory 153, an interface 160, and other components not shown to enable the implementation of the embodiments discussed herein. Memory 153 may include a plurality of memory devices 155 for reading and writing data therefrom. Memory 153 may be one or more of the following volatile memories: random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), double data rate synchronous dynamic RAM (DDR SDRAM), SDRAM, DDR1 SDRAM, DDR2 SDRAM, SSD3 SDRAM, single data rate SDRAM (SDR SDRAM), etc. The embodiments are not limited in this way, and other memory types may be conceived and consistent with the embodiments discussed herein. For example, memory 153 may be a three-dimensional cross-point memory device, or other byte-addressable, write-in-place, non-volatile memory devices. In embodiments, the memory device may be or may include a chalcogenide glass, multi-threshold NAND flash memory, NOR flash memory, single-level or multi-level phase-change memory (PCM), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), antiferroelectric memory, magnetoresistive random access memory (MRAM) incorporating memristor technology, resistive memory including metal oxide-based memory, oxygen vacancy-based and conductive bridge random access memory (CB-RAM), or spin-transfer torque (STT)-MRAM, a device based on spintronic magnetic junction memory, a device based on magnetic tunnel junction (MTJ), a device based on DW (domain wall) and SOT (spin-orbit transfer), a semiconductor thyristor-based memory device, or any combination of the above devices, or other memory.

[0025] In this embodiment, memory resource 151 includes an interface 160, such as an HFI for communication via a network construct, a NIC interface for communication via an Ethernet network, a PCIe interface, a memory construct interface, a QPI interface, a UPI interface, etc. Interface 160 processes read / write requests issued by resources such as computing resource 101. Interface 160 can receive the request and determine, based on the instruction itself, whether the request is an indirect addressing instruction; for example, an indirect addressing instruction could be a construct load instruction, such as "FABRIC-LOAD-I". <addr> , <offset>In some instances, memory indirect addressing operations can be performed locally within the same compute resource 101 or memory resource 151 that issues the load instruction for the request. This is achieved using a load instruction with parameters for local memory indirect addressing (e.g., "LOAD"). <addr> , <offset>") to perform memory indirect addressing operations on memory requests in non-de-aggregated memory.

[0026] Interface 160 can also determine that the request is an indirect addressing instruction based on bits within the request that indicate it is an indirect addressing instruction. As mentioned above, reserved bits in existing read or write requests can be used to identify an instruction as an indirect addressing instruction. Embodiments are not limited to these examples.

[0027] In an embodiment, interface 160 can process indirect addressing instructions and use the address in the request to determine a location in memory with another address. For example, interface 160 reads the memory at that location to determine the address stored therein. The address at that location can be combined with an offset to determine another address at another location, which can be the actual location for retrieving data for the request, or, if multiple layers of indirect addressing exist, this other address can include another address.

[0028] In one embodiment, interface 160 sends a request to another memory resource that can be coupled via an interconnect. Interface 160 can determine the memory resource 151 associated with the address based on the memory location in conjunction with an offset. For example, a system address decoder is used to determine the memory resource 151 associated with the address in conjunction with the offset. In some cases, interface 160 can determine that the memory associated with the memory resource is part of a local or remote memory resource, such as a memory resource coupled via an interconnect.

[0029] For example, memory resource 151-1, including interface 160-1, can receive a request and determine the address related to that request. Interface 160-1 can use that address to locate another address in memory 153-1. Interface 160-1 can use the address from memory 153-1 combined with an offset from the request to determine another address, such as a third address in this case. Interface 160-1 can use a system address decoder to determine the memory of memory resource 151, which can be local, within the current memory resource 151-1, or remote, within another memory resource 151-1. y If the memory associated with the determined address is local, interface 160-1 can cause memory resource 151-1 to process the request or perform another indirect addressing iteration. For example, interface 160-1 can send data to processing circuitry, processing components, controllers, etc., to prompt processing of the request or execution of another indirect addressing iteration. If the memory is remote, within remote memory resource 151- y In this case, interface 160-1 can send the request to remote storage resource 151- y Remote storage resource 151- y The request can be processed and the data returned to the request processing resource, or another indirect addressing iteration can be performed.

[0030] In some cases, interface 160 determines and reports when a failure has occurred. For example, a failure may occur when performing a lookup to determine the address at a memory location based on the address received in the request. There might be no address, the address might be incorrect, the memory read might fail, and so on. In another example, a failure may occur when the system address decoder is attempting to decode the address in the location plus an offset. Interface 160 returns a response indicating that a failure has occurred. More specifically, interface 160 may return a response that includes a failure indication, which may include the faulty address and a failure iteration of the memory indirect addressing operation.

[0031] Figure 1B A system 150 is illustrated, including computing resources 101 coupled to memory resources 151 via interconnect 130. The illustrated example includes further details of the interface 120 for computing resources 101 and the interface 160 for memory resources 151. However, embodiments are not intended to be limited in this manner, and resources may include additional circuitry, memory, logic, etc., to perform one or more other operations and processes.

[0032] Computing resource 101 includes interface 120, which further includes logic 122, processing circuitry 124, and media access control (MAC) and physical (PHY) layer circuitry / logic 126. Logic 122 includes one or more instructions stored in memory that can operate on processing circuitry 124 to perform one or more operations targeting interface 120. Operations include, for example, regarding... Figure 3 The operations discussed. For example, logic 122 can be stored in non-volatile memory. MAC / PHY layer circuitry 126 processes data to enable communication via interconnect 130, such as one or more constructs and Ethernet communication.

[0033] Memory resource 151 includes interface 160, which further includes logic 162, processing circuitry 164, and MAC / PHY layer circuitry / logic 166. Logic 162 includes one or more instructions stored in memory that can operate on processing circuitry 164 to perform one or more operations on interface 160, such as... Figure 2 The operations discussed. For example, logic 162 can be stored in non-volatile memory. MAC / PHY layer circuitry 166 processes data to enable communication via interconnect 130, such as construct or Ethernet communication.

[0034] Figure 2 Examples of logical flows 200 that may represent some or all of the operations performed by one or more embodiments described herein are illustrated. For example, logical flow 200 may exemplify operations performed by memory resource 151, and particularly by interface 160, as described herein. However, the embodiments are not intended to be limited in this way. For example, as per [the description of...] Figure 2 The memory indirect addressing operations discussed can be performed by requesting resources such as computing resource 101 and interface 120.

[0035] At block 202, logic flow 200 includes receiving a request from a computing resource via an interface; the request may be a read request to read data from memory or a write request to write data to memory. In one example, the request includes a load instruction to load data from memory into one or more registers of the CPU of the computing resource that sent the request. The interface may receive the request and determine, based on the instruction itself, whether the request is an indirect addressing instruction; for example, the instruction may be a construct load instruction or a load instruction that includes an address and an offset. In another example, the interface may determine that the request is an indirect addressing instruction based on bits within the request that indicate the request is an indirect addressing instruction.

[0036] At block 204, logic flow 200 includes determining an address based on the request, the address including an address and an offset, as previously discussed. This address identifies a location in memory containing the payload. For example, if the request is an indirect addressing instruction, the address points to a location in memory with a different address. At block 206, logic flow includes determining an address at that location in memory based on the received address. For example, embodiments include reading memory at that location to determine an address stored therein. The address at that location may be combined with the offset to determine another address at another location, which may be the actual location for the request, or may include another address containing the requested data.

[0037] In an embodiment, logic flow 200 includes determining, at block 206, the memory resource associated with the address in conjunction with an offset. More specifically, a system address decoder is used to determine the memory associated with the address. The memory resource can be determined based on the memory associated with the address. The memory can be in local memory resources or remote memory resources, as will be discussed in more detail. At block 208, logic flow 200 includes determining whether a fault has occurred. For example, a fault may occur when attempting to read a memory location or when determining the memory associated with the address via the system address decoder. If a fault occurs, logic flow 200 includes at block 214 sending a response indicating the fault to a requesting compute resource.

[0038] At block 210, logic flow 200 includes determining whether the memory is within a local memory resource or a remote memory resource coupled via an interconnect. If the memory resource is local, logic flow 200 may include, at block 216, prompting a processing request, such as prompting a read or write memory operation. For example, a LOAD instruction may be issued. If the memory resource is remote, logic flow 200 includes sending the request to the memory resource via an interconnect. The remote memory resource may receive and process the request. For example, a FABRIC-LOAD-I instruction may be issued. In some cases, the memory of either the local or remote memory resource may include another address at the location pointed to by the address in the request, and logic flow 200 may be repeated. In other words, multiple levels of indirect addressing may occur before the request is processed by the memory resource and returned to the compute resource.

[0039] Figure 3 Examples of logical flows 300 that may represent some or all of the operations performed by one or more embodiments described herein are illustrated. For example, logical flow 300 may exemplify operations performed by computing resource 101, and in particular by interface 120, as described herein.

[0040] At block 302, logic flow 300 includes receiving a request from the core to perform a memory operation. This request may be to perform a memory operation on a de-aggregated memory resource (e.g., a memory resource coupled via an interconnect (structure or network)) or a local memory resource (e.g., in the same resource as the core that generated the request). The request includes an address and offset to enable the memory operation to be performed. The core can determine the address and offset by reading data in one or more data structures associated with a memory allocation specifying the location of the stored data. In embodiments, the core may also indicate that the request is an instruction using indirect addressing, such as an indirect addressing instruction. For example, the request may include an indirect addressing instruction such as "FABRIC-LOAD-I". <addr> , <offset>In another example, the request includes a bit set indicating that the request includes indirect addressing instructions. In some cases, multi-level indirect addressing is used, and the construction load or load instructions may include the number of indirect addressing iterations utilized.

[0041] At block 304, logic flow 300 includes determining the memory resource to which the request will be sent. As previously described, the memory resource may be coupled to computing resources having the core that generated the request via interconnects such as constructs or network interconnects. In one example, the interface uses a system address decoder to determine the memory resource based on the address of the request associated with memory located within the memory resource. In other cases, the memory resource may be local to the core that generated the request. At block 306, the interface sends the request to the determined memory resource or processes the request locally. The interface may continue to transmit data and receive responses to the request.

[0042] At block 308, the interface can receive a response to the request. The response may include the data requested in the request, an indication of successful completion of the memory operation, and / or a memory operation failure. At block 310, the interface may send the response to the requesting core. The embodiment is not limited to the operation indicating logic flow 300, and one or more operations may occur before or after other operations.

[0043] Figure 4A An example of a first processing flow 400 for understanding the processing requests of aggregated memory resources is illustrated. The example shown includes multiple memory resources 151 coupled via one or more interconnects 130. y The computing resources are 101, of which y It can be any positive integer. One or more interconnects 130 can be structural interconnects or network interconnects, as previously discussed. Furthermore, Figure 4A A system including a single computing resource 101 is illustrated; however, the embodiments are not limited in this way. Embodiments may include more than one computing resource 101; each computing resource is capable of transmitting requests and receiving responses.

[0044] In the illustrated processing flow 400, computing resource 101, including interface 120, publishes a request at line 401 to perform a memory operation such as a read or write. This request includes an address and offset pointing to a location in memory 153. In this example, the request is sent to memory resource 151-2 associated with the address in the request. Furthermore, interface 120 determines whether to send the request to memory resource 151-2 based on operations performed by the system address decoder to identify memory resources 151-2 and memory 153-2.

[0045] Memory resource 151-2, including interface 160-2, can receive the request and determine that the request is an indirect addressing instruction based on the request itself (e.g., the request includes an indirect addressing instruction) or based on a bit group in the request indicating that the request includes an indirect addressing instruction. The circuitry of interface 160-2 and / or memory resource 151-2 can determine the contents of the location in memory 153-2 pointed to by the address in the request. If the request includes an indirect addressing instruction, the location includes a second address, which can be used to determine another address to send the request. More specifically, the offset in the request is applied to the address at the location to determine another address. Interface 160-2 uses this address to determine the memory resource to which the request is to be sent. For example, interface 160-2 can use a system address decoder to determine the memory resource associated with that address. In this example, the address is located in and associated with memory resource 151-1.

[0046] At line 403, memory resource 151-2, including interface 160-2, can send a request to memory resource 151-1, which is associated with the address based on the address located within memory 153-2 and the offset. Memory resource 151-1 can receive and process the request. In the illustrated example, memory resource 151-1 can perform a memory operation (read / write) associated with the request and return a response to computing resource 101 at line 405. However, the embodiments are not limited in this way, and in some cases, the request transmitted at 403 may include indirect addressing instructions to determine another memory resource to perform the memory request. As previously described, multiple levels of indirect addressing can be performed before performing the memory operation and the result returned to computing resource 101.

[0047] Figure 4B An example of a second processing flow 450 for processing requests to aggregated memory resources is illustrated. The example includes multiple memory resources 151 coupled via one or more interconnects 130. y The computing resources are 101, of which y It can be any positive integer. One or more interconnects 130 can be structural interconnects or network interconnects, as previously discussed. Furthermore, Figure 4B A system including a single computing resource 101 is illustrated; however, the embodiments are not limited in this way. Embodiments may include more than one computing resource 101; each computing resource is capable of transmitting requests and receiving responses.

[0048] In the illustrated processing flow 450, computing resource 101, including interface 120, publishes a request at line 451 to perform a memory operation such as a read or write. This request includes an address and offset pointing to a location in memory. In this example, the request is sent to memory resource 151-2 associated with the address in the request. Furthermore, interface 120 determines whether to send the request to memory resource 151-2 based on operations performed by the system address decoder to identify memory resources 151-2 and memory 153-2.

[0049] Memory resource 151-2, including interface 160-2, can receive the request and determine that the request is an indirect addressing instruction based on the request itself (e.g., the request includes an indirect addressing instruction) or based on a bit group in the request indicating that the request includes an indirect addressing instruction. Circuitry of interface 160-2 and / or memory resource 151-2 can determine the contents of the location in memory 153-2 pointed to by the address in the request. If the request includes an indirect addressing instruction, the location includes an address that can be used with an offset to determine another address to which the request should be sent. More specifically, the offset in the request is applied to the address in the location of memory 153-2 to determine the other address. Interface 160-2 uses this other address to determine the memory resource to which the request should be sent. For example, interface 160-2 can use a system address decoder to determine the memory resource associated with that address. In this example, the address is located in and associated with memory resource 151-2 (e.g., a local memory resource).

[0050] At line 453, memory resource 151-2 can process the request. In the illustrated example, memory resource 151-2 can perform the memory operation (read / write) associated with the request and return a response to computing resource 101 at line 455. However, the embodiment is not limited in this way, and in some cases, the address can point to a location in memory 153-2 with another address, which can be used to determine whether to process the request or a memory resource with another address. As previously mentioned, multiple levels of indirect addressing can be performed before the memory operation is executed, and the result is returned to computing resource 101.

[0051] Figure 4C An example is illustrated where a third processing stream 475 utilizes multi-level indirect addressing to handle requests from aggregated memory resources. The illustrated example includes multiple memory resources 151 coupled via one or more interconnects 130. y The computing resources are 101, of which y It can be any positive integer. One or more interconnects 130 can be structural interconnects or network interconnects, as previously discussed. Furthermore, Figure 4C A system including a single computing resource 101 is illustrated; however, the embodiments are not limited in this way. Embodiments may include more than one computing resource 101; each computing resource is capable of transmitting requests and receiving responses.

[0052] In the illustrated processing flow 475, computing resource 101, including interface 120, publishes a request at line 476 to perform a memory operation such as a read or write. This request includes an address and offset pointing to a location in memory 153, and in this example, may also include a number indicating the number of indirect addressing steps to be performed to process the request. In this example, the request is sent to memory resource 151-2 associated with the address in the request. Interface 120 determines whether to send the request to memory resource 151-2 based on operations performed by the system address decoder to identify memory resources 151-2 and memory 153-2.

[0053] Memory resource 151-2, including interface 160-2, can receive the request and determine that the request is an indirect addressing instruction based on the request itself (e.g., the request includes an indirect addressing instruction) or based on a bit group in the request indicating that the request includes an indirect addressing instruction. The circuitry of interface 160-2 and / or memory resource 151-2 can determine the contents of the location in memory 153-2 pointed to by the address in the request. The request includes an indirect addressing instruction and an indication of the number of indirect addressing iterations. The memory location pointed to by the location in the request includes a second address, which can be used to determine another address to send the request. More specifically, the offset in the request is applied to the address at the location to determine another address. Interface 160-2 uses this address to determine the memory resource to which the request is to be sent. For example, interface 160-2 can use a system address decoder to determine the memory resource associated with that address. In this example, the address is located in and associated with memory resource 151-1.

[0054] At line 478, memory resource 151-2, including interface 160-2, can send a request to memory resource 151-1, which is associated with the address based on the address located within memory 153-2 and the offset. Memory resource 151-1 can receive and process the request. In the illustrated example, memory resource 151-1 can determine that the request includes an indirect addressing instruction. The circuitry of interface 160-1 and / or memory resource 151-1 can determine the contents of the location in memory 153-1 pointed to by the address in the request. The memory location pointed to by the location in the request includes a second address that can be used to determine another address to which the request should be sent. More specifically, the offset in the request is applied to the address at the location to determine another address. Interface 160-1 uses this address to determine the memory resource to which the request should be sent. For example, interface 160-1 can use a system address decoder to determine the memory resource associated with that address. In this example, the address is located in and associated with memory resource 151-2.

[0055] At line 480, memory resource 151-1, including interface 160-1, can send a request to memory resource 151-2, which is associated with the address based on the address located within memory 153-1 and the offset. Memory resource 151-2 can receive and process the request. In the illustrated example, memory resource 151-2 can perform a memory operation (read / write) associated with the request and return a response to computing resource 101 at line 482. The embodiment is not limited to the manner discussed in this example. In this example, two levels of indirect addressing are utilized and indicated in the request. However, embodiments may include any number of indirect addressing levels.

[0056] Figure 5 Examples of third logic flows 500 that may represent some or all of the operations performed by one or more embodiments described herein are illustrated. For example, as described herein, logic flow 500 may represent operations performed by a node.

[0057] At block 505, logic flow 500 may include receiving a request from the core associated with a memory operation to read or write data, and the request includes a first address and an offset, the first address being used to identify a memory location. In some cases, the request may also indicate the number of iterations to be performed for a memory indirect addressing operation to process the read or write operation. In an embodiment, an interface to the memory resource may receive the request from the core. Alternatively, a core-local interface, for example, within the same computing resource, may receive and process the request.

[0058] At block 510, logic flow 500 includes a first iteration of performing a memory indirect addressing operation, including reading memory at the memory location to determine a second address based on a first address, and determining a memory resource based on the second address and an offset, which is to perform a memory operation for the core or to perform a second iteration of the memory indirect addressing operation. In embodiments, the determined memory resource may include memory having memory devices and may be a remote memory resource (e.g., coupled via an interconnect) or a local memory resource (e.g., the same memory resource). If the memory resource is a remote memory resource, the interface may forward the request to the remote memory resource for further processing, such as determining data to return to the core or performing another iteration of the memory indirect addressing operation. Similarly, if the memory resource is a local memory resource, the local memory resource may determine data for the core or perform another iteration of the memory indirect addressing operation.

[0059] Figure 6 Examples of exemplary computing architectures 600 suitable for implementing the various embodiments described above are illustrated. In some embodiments, for example, computing architecture 600 may include nodes or be implemented as part of nodes.

[0060] As used herein, the terms "system" and "component" are intended to refer to computer-related entities, hardware, combinations of hardware and software, software, or software in execution, examples of which are provided by exemplary computing architecture 600. For example, a component can be, but is not limited to, a process running on a processor, a processor, a hard disk drive, multiple storage drives (of optical and / or magnetic storage media), an object, an executable object, an execution thread, a program, and / or a computer. As an example, both an application running on a server and the server itself can be components. One or more components may reside within a process and an execution thread, and components may be located on a single computer or distributed across two or more computers. Additionally, components can communicatively couple with each other to coordinate operation via various types of communication media. Coordination can involve one-way or two-way exchange of information. For example, components may transmit information in the form of signals transmitted via a communication medium. Information can be implemented as signals assigned to various signal lines. In such assignments, each message is a signal. However, alternative embodiments may employ data messages. Such data messages can be sent across various connections. Exemplary connections include parallel interfaces, serial interfaces, and bus interfaces.

[0061] The computing architecture 600 includes a variety of common computing elements, such as one or more processors, multi-core processors, coprocessors, memory units, chipsets, controllers, peripherals, interfaces, oscillators, timing devices, video cards, audio cards, multimedia input / output (I / O) components, power supplies, and so on. However, embodiments are not limited to those implemented by the computing architecture 600.

[0062] like Figure 6 As shown, the computing architecture 600 includes a processing unit 604, a system memory 606, and a system bus 608. The processing unit 604 can be any of a variety of commercially available processors.

[0063] System bus 608 provides an interface for system components, including but not limited to system memory 606, to processing unit 604. System bus 608 can be any of several types of bus structures that can use any of a variety of commercially available bus architectures to further interconnect to memory buses (with or without memory controllers), peripheral buses, and local buses. Interface adapters can be connected to system bus 608 via slot architectures. Example slot architectures may include, but are not limited to, Accelerated Graphics Port (AGP), Card Bus, (Extended) Industry Standard Architecture ((E)ISA), Micro Channel Architecture (MCA), NuBus, Peripheral Component Interconnect (Extended) (PCI(X)), Fast PCI, PCMCIA, etc.

[0064] The computing architecture 600 may include or implement various articles of manufacture. Articles of manufacture may include computer-readable storage media for storing logic. Examples of computer-readable storage media may include any tangible medium capable of storing electronic data, including volatile or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory, and so on. Examples of logic may include executable computer program instructions implemented using any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, object-oriented code, visual code, etc. Embodiments may also be implemented, at least in part, as instructions contained in or on a non-transitory computer-readable medium, which may be read and executed by one or more processors to enable the performance of the operations described herein.

[0065] System memory 606 may include various types of computer-readable storage media in the form of one or more higher-speed memory cells, such as read-only memory (ROM), random access memory (RAM), dynamic RAM (DRAM), double data rate DRAM (DDRAM), synchronous DRAM (SDRAM), static RAM (SRAM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, polymer memory such as ferroelectric polymer memory, austenite memory, phase-change or ferroelectric memory, silicon oxynitride (SONOS) memory, magnetic or optical cards, device arrays such as redundant independent disk arrays (RAID) drives, solid-state memory devices (e.g., USB storage, solid-state drives (SSDs)), and any other type of storage media suitable for storing information. Figure 6 In the illustrated embodiment, system memory 606 may include non-volatile memory 610 and volatile memory 612. The basic input / output system (BIOS) may be stored in non-volatile memory 610.

[0066] Computer 602 may include various types of computer-readable storage media in the form of one or more low-speed memory cells, including internal (or external) hard disk drive (HDD) 614, magnetic floppy disk drive (FDD) 616 for reading from or writing to removable disk 618, and optical disc drive 620 for reading from or writing to removable optical disc 622 (e.g., CD-ROM or DVD). HDD 614, FDD 616, and optical disc drive 620 may be connected to system bus 608 via HDD interface 624, FDD interface 626, and optical drive interface 628, respectively. HDD interface 624 for external drive implementation may include at least one or both of Universal Serial Bus (USB) and IEEE 1394 interface technologies.

[0067] Drives and associated computer-readable media provide volatile and non-volatile storage for data, data structures, computer-executable instructions, etc. For example, numerous program modules may be stored in drive and memory units 610, 612, including an operating system 630, one or more application programs 632, other program modules 634, and program data 636. In one embodiment, one or more application programs 632, other program modules 634, and program data 636 may include, for example, various applications and components of system 100.

[0068] Users can input commands and information into computer 602 through one or more wired / wireless input devices (e.g., keyboard 638 and pointing devices such as mouse 640). Other input devices may include microphones, infrared (IR) remote controls, radio frequency (RF) remote controls, gamepads, styluses, card readers, dongles, fingerprint readers, gloves, graphics tablets, joysticks, keyboards, retinal readers, touchscreens (e.g., capacitive, resistive, etc.), trackballs, touchpads, sensors, styluses, etc. These and other input devices are typically connected to processing unit 604 via input device interface 642 coupled to system bus 608, but can be connected via other interfaces such as parallel ports, IEEE 1394 serial ports, game ports, USB ports, IR interfaces, etc.

[0069] Monitor 644 or other types of display devices are also connected to system bus 608 via an interface such as video adapter 646. Monitor 644 can be inside or outside computer 602. In addition to monitor 644, computer typically includes other peripheral output devices such as speakers, printers, etc.

[0070] Computer 602 can operate in a networked environment using logical connections to one or more remote computers (such as remote computer 648) via wired and wireless communications. Remote computer 648 can be a workstation, server computer, router, personal computer, portable computer, microprocessor-based entertainment device, peer-to-peer device, or other public network node, and typically includes many or all of the elements described with respect to computer 602; however, for brevity, only memory / storage device 650 is illustrated. The depicted logical connections include wired / wireless connections to a local area network (LAN) 652 and larger networks (e.g., a wide area network (WAN) 654). Such LAN and WAN networking environments are common in offices and companies and facilitate enterprise-wide computer networks, such as intranets, all of which can connect to global communication networks, such as the Internet.

[0071] When used in a LAN networking environment, computer 602 connects to LAN 652 via a wired and / or wireless communication network interface or adapter 656. Adapter 656 facilitates wired and / or wireless communication to LAN 652, which may also include a wireless access point disposed thereon for communicating with the wireless functionality of adapter 656.

[0072] When used in a WAN networking environment, computer 602 may include modem 658, or a communication server connected to WAN 654, or other components for establishing communication via WAN 654 (such as via the Internet). Modem 658, which may be internal or external and wired and / or wireless, is connected to system bus 608 via input device interface 642. In a networking environment, the program modules or portions thereof described with respect to computer 602 may be stored in remote memory / storage device 650. It will be appreciated that the network connections shown are exemplary and other means of establishing communication links between computers may be used.

[0073] Computer 602 is operable to communicate with wired and wireless devices or entities using the IEEE 802 family of standards, such as wireless devices operable in wireless communication (e.g., IEEE 802.16 air modulation technology). This includes at least Wi-Fi (or Wireless Fidelity), WiMax, and Bluetooth™ wireless technologies. Therefore, communication can be a predefined structure like a regular network or simply dedicated communication between at least two devices. Wi-Fi networks use radio technology known as IEEE 802.11x (a, b, g, n, etc.) to provide secure, reliable, and fast wireless connectivity. Wi-Fi networks can be used to connect computers to each other, connect to the Internet, and connect to wired networks (which use IEEE 802.3 related media and functions).

[0074] The various elements of the devices previously described with reference to Figures 1-6 may include a variety of hardware elements, software elements, or combinations of both. Examples of hardware elements may include devices, logic devices, components, processors, microprocessors, circuits, processors, circuit elements (e.g., transistors, resistors, capacitors, inductors, etc.), integrated circuits, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), digital signal processors (DSPs), field-programmable gate arrays (FPGAs), memory cells, logic gates, registers, semiconductor devices, chips, microchips, chipsets, and so on. Examples of software elements may include software components, programs, applications, computer programs, application programs, system programs, software development programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, processes, software interfaces, application programming interfaces (APIs), instruction sets, computational code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. However, the determination of whether to use hardware and / or software components to implement an embodiment can vary based on any number of factors such as desired computing speed, power level, thermal tolerance, processing cycle budget, input data rate, output data rate, memory resources, data bus speed, and other design or performance constraints, as is expected for a given implementation.

[0075] This detailed disclosure now turns to providing examples relating to other embodiments. Examples 1 through 29 provided below are intended to be exemplary and not restrictive.

[0076] In a first example, a system, device, apparatus, etc., may include processing circuitry that: receives a request from a core, the request being associated with a memory operation to read or write data, and the request including a first address and an offset, the first address being used to identify a memory location; and performs a first iteration of a memory indirect addressing operation, including reading memory at the memory location to determine a second address based on the first address, and determining a memory resource based on the second address and the offset, the memory resource being used to perform the memory operation on the core or to perform a second iteration of the memory indirect addressing operation.

[0077] In the second example, and to facilitate the first example, a system, device, apparatus, etc., shall include processing circuitry that determines a third address based on a second address and the offset, the third address being associated with the memory resource.

[0078] In the third example, and to facilitate any of the preceding examples, a system, device, apparatus, etc., may include processing circuitry that performs a lookup in a system address decoder using a third address to determine the memory resource from a plurality of memory resources.

[0079] In the fourth example, and to facilitate any of the preceding examples, a system, device, apparatus, etc., shall include processing circuitry that returns a response including a fault indication indicating that the lookup has failed in the system address decoder, the fault indication indicating at least one of a fault iteration of a memory indirect addressing operation and a fault address.

[0080] In the fifth example, and to facilitate any of the preceding examples, a system, device, apparatus, etc., shall include processing circuitry that: determines that the memory resource is a remote memory resource and sends the request to the remote memory resource via an Ethernet network or a constructed network coupled through an interface, the remote memory resource performing the memory operation to read or write data or to perform a second iteration of the memory indirect addressing operation; or determines that the memory resource is a local memory resource and processes the memory operation to read or write data or to perform a second iteration of the memory indirect addressing operation.

[0081] In the sixth example, and to facilitate any of the preceding examples, a system, device, apparatus, etc., shall include processing circuitry that performs a second iteration of the memory indirect addressing operation, including reading memory at a memory location to determine a fourth address based on a third address, and determining a memory resource based on the fourth address and an offset, the memory resource for which the memory operation is performed against the core.

[0082] In the seventh example, and to facilitate any of the preceding examples, a system, device, apparatus, etc., shall include processing circuitry that receives the request from the core via a construction or network coupled to an interface.

[0083] In the eighth example, and to facilitate any of the preceding examples, a system, device, apparatus, etc., shall include: the memory operation includes reading data to read data from memory or writing data to memory.

[0084] In the ninth example, and to facilitate any of the preceding examples, a system, device, apparatus, etc., shall include: wherein the third address comprises the second address plus the offset.

[0085] In the tenth example, and to facilitate any of the preceding examples, a system, device, apparatus, etc., shall include an interface that includes the processing circuitry and the logic, the interface being one of a host construction interface and a network interface.

[0086] In the eleventh example, and to facilitate any of the preceding examples, a non-transitory computer-readable storage medium includes a plurality of instructions that, when executed, enable processing circuitry to: receive a request from a core, the request being associated with a memory operation to read or write data, and the request including a first address and an offset, the first address being used to identify a memory location; and perform a first iteration of a memory indirect addressing operation, including reading memory at the memory location to determine a second address based on the first address, and determining a memory resource based on the second address and the offset, the memory resource being used to perform the memory operation against the core or to perform a second iteration of the memory indirect addressing operation.

[0087] In the twelfth example, and to facilitate any of the preceding examples, a non-transitory computer-readable storage medium includes a plurality of instructions that, when executed, enable processing circuitry to determine a third address based on a second address and the offset, the third address being associated with the memory resource, wherein the third address includes the second address plus the offset.

[0088] In the thirteenth example, and to facilitate any of the preceding examples, a non-transitory computer-readable storage medium includes a plurality of instructions that, when executed, enable processing circuitry to perform a lookup in a system address decoder using a third address to determine the memory resource from a plurality of memory resources.

[0089] In the fourteenth example, and to facilitate any of the preceding examples, a non-transitory computer-readable storage medium includes a plurality of instructions that, when executed, cause processing circuitry to return a response including a fault indication instructing the system address decoder to perform the lookup for a fault, the fault indication indicating at least one of a fault iteration of a memory indirect addressing operation and a fault address.

[0090] In the fifteenth example, and to facilitate any of the preceding examples, a non-transitory computer-readable storage medium includes a plurality of instructions that, when executed, cause processing circuitry to: determine that the memory resource is a remote memory resource and send the request to the remote memory resource via an Ethernet network or a constructed network coupled through an interface, the remote memory resource to perform the memory operation to read or write data or to perform a second iteration of the memory indirect addressing operation; or determine that the memory resource is a local memory resource and process the memory operation to read or write data or to perform a second iteration of the memory indirect addressing operation.

[0091] In the sixteenth example, and to facilitate any of the preceding examples, a non-transitory computer-readable storage medium includes a plurality of instructions that, when executed, enable processing circuitry to determine a fourth address based on a third address, and to determine a memory resource based on the fourth address and an offset, the memory resource being used to perform the memory operation for the core.

[0092] In the seventeenth example, and to facilitate any of the preceding examples, a non-transitory computer-readable storage medium includes a plurality of instructions that, when executed, enable processing circuitry to perform memory operations, including reading data from memory or writing data to memory.

[0093] In the eighteenth example, and to facilitate any of the preceding examples, a computer-implemented method may include: receiving a request from a core associated with a memory operation to read or write data, the request including a first address and an offset, the first address being used to identify a memory location; and performing a first iteration of a memory indirect addressing operation, including reading memory at the memory location to determine a second address based on the first address, and determining a memory resource based on the second address and the offset, the memory resource being used to perform the memory operation against the core or to perform a second iteration of the memory indirect addressing operation.

[0094] In the nineteenth example, and to facilitate any of the preceding examples, a computer-implemented method may include determining a third address based on a second address and the offset, the third address being associated with the memory resource, wherein the third address comprises the second address plus the offset.

[0095] In the twentieth example, and to facilitate any of the preceding examples, a computer-implemented method may include performing a lookup in a system address decoder using a third address to determine the memory resource from a plurality of memory resources.

[0096] In the twenty-first example, and to facilitate any of the preceding examples, a computer-implemented method may include: returning a response including a fault indication indicating that the lookup has failed in the system address decoder, the fault indication indicating at least one of a fault iteration of a memory indirect addressing operation and a fault address.

[0097] In the twenty-second example, and to facilitate any of the preceding examples, a computer-implemented method may include: determining that the memory resource is a remote memory resource, and sending the request to the remote memory resource via an Ethernet network or a constructed network coupled through an interface, the remote memory resource being to perform the memory operation to read or write data or to perform a second iteration of the memory indirect addressing operation; or determining that the memory resource is a local memory resource, and processing the memory operation to read or write data or to perform a second iteration of the memory indirect addressing operation.

[0098] In the twenty-third example, and to facilitate any of the preceding examples, a computer-implemented method may include a second iteration of performing the memory indirect addressing operation, including reading memory at a memory location to determine a fourth address based on a third address, and determining a memory resource based on the fourth address and an offset, the memory resource for which the memory operation is to be performed against the core.

[0099] In the twenty-fourth example, and to facilitate any of the preceding examples, a computer-implemented method may include performing memory operations, which include reading data to read from memory or writing data to write to memory.

[0100] In the twenty-fifth example, and to facilitate any of the preceding examples, a system, device, apparatus, etc., shall include: components for receiving a request from a core, the request being associated with a memory operation to read or write data, and the request including a first address and an offset, the first address being used to identify a memory location; and components for performing a first iteration of a memory indirect addressing operation, the first iteration of the memory indirect addressing operation including reading memory at the memory location to determine a second address based on the first address, and determining a memory resource based on the second address and the offset, the memory resource being used to perform the memory operation against the core or to perform a second iteration of the memory indirect addressing operation.

[0101] In the twenty-sixth example, and to facilitate any of the preceding examples, a system, device, apparatus, etc., shall include a component for determining a third address based on a second address and the offset, the third address being associated with the memory resource, wherein the third address comprises the second address plus the offset.

[0102] In the twenty-seventh example, and in order to facilitate any of the preceding examples, a system, device, apparatus, etc., shall include a component for performing a lookup in a system address decoder using a third address to determine the memory resource from a plurality of memory resources.

[0103] In the twenty-eighth example, and in order to facilitate any of the preceding examples, a system, device, apparatus, etc., shall include a component for returning a response including a fault indication indicating that the lookup has failed in the system address decoder, the fault indication indicating at least one of a fault iteration of a memory indirect addressing operation and a fault address.

[0104] In the twenty-ninth example, and to facilitate any of the preceding examples, a system, device, apparatus, etc., shall include: components for determining that the memory resource is a remote memory resource and sending the request to the remote memory resource via an Ethernet network or a constructed network coupled through an interface, the remote memory resource to perform the memory operation to read or write data or to perform a second iteration of the memory indirect addressing operation; or components for determining that the memory resource is a local memory resource and processing the memory operation to read or write data or to perform a second iteration of the memory indirect addressing operation.

[0105] Embodiments may be described using the expressions "one embodiment" or "embodiment" and their derivatives. These terms mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. The phrase "in one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, embodiments may be described using the expressions "coupled" and "connected" and their derivatives. These terms are not necessarily intended to be synonyms with each other. For example, the terms "connected" and / or "coupled" may be used to describe embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. However, the term "coupled" may also mean that two or more elements are not in direct contact with each other, but still cooperate or interact with each other.

[0106] It is important to emphasize that an abstract of this disclosure is provided to allow the reader to quickly determine the nature of the technical disclosure. It is asserted that the abstract will not be used to interpret or limit the scope or meaning of the claims. Furthermore, as can be seen in the foregoing detailed description, various features are combined together in a single embodiment for the purpose of organizing this disclosure. The method of this disclosure should not be construed as reflecting an intention that the claimed embodiments require more features than expressly recited in each claim. Rather, as reflected in the following claims, the subject matter of the invention lies in fewer than all features of a single disclosed embodiment. Therefore, the following claims are thus incorporated into the detailed description, wherein each claim is itself a separate embodiment. In the appended claims, the terms "comprising" and "wherein" are used as plain English equivalents of the corresponding terms "including" and "in which," respectively. Furthermore, the terms "first," "second," "third," etc., are used merely as labels and are not intended to impose numerical requirements on their objects.

[0107] The foregoing description includes examples of the disclosed architecture. It is certainly impossible to describe every conceivable combination of components and / or methods, but those skilled in the art will recognize that many other combinations and permutations are possible. Therefore, the novel architecture is intended to cover all such changes, modifications, and variations that fall within the spirit and scope of the appended claims.< / offset> < / addr> < / offset> < / addr> < / offset> < / addr> < / offset> < / addr> < / offset> < / addr> < / offset> < / addr> < / offset> < / addr> < / offset> < / addr>

Claims

1. An apparatus for performing memory indirect addressing operations, comprising: Processing circuitry; as well as The logic includes one or more instructions, which, when executed by the processing circuit, cause the processing circuit to: A request is received from the core, the request being associated with a memory operation to read or write data, and the request including a first address and an offset, the first address being used to identify the memory location; The first iteration of performing a memory indirect addressing operation includes reading memory at the memory location to determine a second address based on a first address, and determining a memory resource based on the second address and the offset, the memory resource being used to perform the memory operation for the core or to perform a second iteration of the memory indirect addressing operation; as well as The third address is determined based on the second address and the offset, and the third address is associated with the memory resource. The second iteration of the memory indirect addressing operation includes reading memory at a memory location to determine a fourth address based on a third address, and determining a memory resource based on the fourth address and an offset, the memory resource for which the memory operation is to be performed against the core.

2. The apparatus of claim 1, wherein the processing circuit performs a lookup in the system address decoder using a third address to determine the memory resource from a plurality of memory resources.

3. The apparatus of claim 2, wherein the processing circuitry returns a response including a fault indication indicating that a fault lookup is performed in the system address decoder, the fault indication indicating at least one of a fault iteration of a memory indirect addressing operation and a fault address.

4. The apparatus according to claim 1, wherein the processing circuit comprises: The memory resource is determined to be a remote memory resource, and the request is sent to the remote memory resource via an Ethernet network or a constructed network coupled through an interface, the remote memory resource to perform the memory operation to read or write data or to perform a second iteration of the memory indirect addressing operation; or A second iteration is performed to determine that the memory resource is a local memory resource and to process the memory operation to read or write data or to perform the memory indirect addressing operation.

5. The apparatus of claim 1, wherein the processing circuitry receives the request from the core via a configuration or network coupled to the interface.

6. The apparatus according to claim 1, wherein, The memory operations include reading data from memory or writing data to memory.

7. The apparatus according to claim 1, wherein, The third address includes the second address plus the offset.

8. The apparatus of claim 1, further comprising an interface, the interface including the processing circuitry and the logic, the interface being one of a host architecture interface and a network interface.

9. A non-transitory computer-readable storage medium comprising a plurality of instructions, which, when executed, cause processing circuitry to: A request is received from the core, the request being associated with a memory operation to read or write data, and the request including a first address and an offset, the first address being used to identify the memory location; The first iteration of performing a memory indirect addressing operation includes reading memory at the memory location to determine a second address based on a first address, and determining a memory resource based on the second address and the offset, the memory resource being used to perform the memory operation for the core or to perform a second iteration of the memory indirect addressing operation; as well as The third address is determined based on the second address and the offset, and the third address is associated with the memory resource. The second iteration of the memory indirect addressing operation includes reading memory at a memory location to determine a fourth address based on a third address, and determining a memory resource based on the fourth address and an offset, the memory resource for which the memory operation is to be performed against the core.

10. The computer-readable storage medium according to claim 9, wherein, The third address includes the second address plus the offset.

11. The computer-readable storage medium of claim 9, comprising a plurality of instructions, which, when executed, enable processing circuitry to perform a lookup in a system address decoder using a third address to determine the memory resource from a plurality of memory resources.

12. The computer-readable storage medium of claim 11, comprising a plurality of instructions, which, when executed, cause processing circuitry to return a response including a fault indication indicating that a fault lookup should be performed in the system address decoder, the fault indication indicating at least one of a fault iteration of a memory indirect addressing operation and a fault address.

13. The computer-readable storage medium of claim 9, comprising a plurality of instructions, which, when executed, cause the processing circuitry to: The memory resource is determined to be a remote memory resource, and the request is sent to the remote memory resource via an Ethernet network or a constructed network coupled through an interface, the remote memory resource to perform the memory operation to read or write data or to perform a second iteration of the memory indirect addressing operation; or A second iteration is performed to determine that the memory resource is a local memory resource and to process the memory operation to read or write data or to perform the memory indirect addressing operation.

14. The computer-readable storage medium according to claim 9, wherein, The memory operations include reading data from memory or writing data to memory.

15. A computer-implemented method for performing memory indirect addressing operations, comprising: A request is received from the core, the request being associated with a memory operation to read or write data, and the request including a first address and an offset, the first address being used to identify the memory location; as well as The first iteration of performing a memory indirect addressing operation includes reading memory at the memory location to determine a second address based on a first address, and determining a memory resource based on the second address and the offset, the memory resource being used to perform the memory operation for the core or to perform a second iteration of the memory indirect addressing operation; as well as The third address is determined based on the second address and the offset, and the third address is associated with the memory resource. The second iteration of the memory indirect addressing operation includes reading memory at a memory location to determine a fourth address based on a third address, and determining a memory resource based on the fourth address and an offset, the memory resource for which the memory operation is to be performed against the core.

16. The computer-implemented method according to claim 15, wherein, The third address includes the second address plus the offset.

17. The computer-implemented method of claim 15, further comprising performing a lookup in a system address decoder using a third address to determine the memory resource from a plurality of memory resources.

18. The computer-implemented method according to claim 17, comprising: The response returns a fault indication indicating that a fault lookup should be performed in the system address decoder, the fault indication indicating at least one of a fault iteration of a memory indirect addressing operation and a fault address.

19. The computer-implemented method according to claim 15, comprising: The memory resource is determined to be a remote memory resource, and the request is sent to the remote memory resource via an Ethernet network or a constructed network coupled through an interface, the remote memory resource to perform the memory operation to read or write data or to perform a second iteration of the memory indirect addressing operation; or A second iteration is performed to determine that the memory resource is a local memory resource and to process the memory operation to read or write data or to perform the memory indirect addressing operation.

20. The computer-implemented method according to claim 15, wherein, The memory operations include reading data from memory or writing data to memory.

Images