A P-type tunneling oxide passivation contact solar cell and its preparation method

Abstract

The invention discloses a P-type tunneling oxide passivation contact solar cell, which belongs to the technical field of crystalline silicon solar cells. The purpose is to solve the problem of poor passivation effect on the back side of solar cells in the prior art. The invention is characterized in that a silicon dioxide layer is first formed on the front side of a silicon wafer, and then an N-type heavily doped polysilicon layer is formed on the silicon dioxide layer, thereby reducing the composite loss of a metal contact area; in addition, a tunneling oxide is combined with a heavily doped silicon film to form a passivation contact structure, replacing the original entire doped back surface area, thereby maintaining a relatively high short-circuit current, increasing the open-circuit voltage, improving the fill factor, and improving the conversion efficiency of the battery.

Description

Technical Field

[0001] The invention belongs to the technical field of crystalline silicon solar cells, and in particular relates to a P-type tunneling oxide passivation contact solar cell and a preparation method thereof. Background Art

[0002] At present, solar cells mainly use crystalline silicon as the base material. Due to periodic damage on the surface of silicon wafers, a large number of dangling bonds will be generated, resulting in a large number of defect energy levels located in the band gap on the surface of the crystal. In addition, dislocations, chemical residues, and surface metal deposition will introduce defect energy levels, making the surface of the silicon wafer a recombination center, resulting in a large surface recombination rate, thereby limiting the conversion efficiency. Back-passivated solar cells are coated with SiN on the front side. x , back coating Al2O3, SiN x In addition, since the front side of the solar cell is the light-absorbing side where sunlight directly enters, the design of the passivation layer must take light absorption into consideration, which greatly limits the research on the front passivation layer.

[0003] The main processes of the existing PERC solar cell are: texturing, phosphorus diffusion, back etching, annealing, back coating Al2O3, back coating SiN x , front side coating SiN x , laser grooving of the back passivation layer, printing of the front and back electrode electric fields, high-temperature sintering, and finally forming a back passivated solar cell. Since an insulating passivation layer is deposited on the back of the battery, it is necessary to selectively etch away part of the passivation layer through laser etching to expose the silicon layer, and then print the back electric field aluminum paste on the laser etched area to form a direct contact with the silicon layer to achieve conductivity. Therefore, in the back laser etched area, since part of the passivation layer is removed, the passivation ability decreases, which directly affects the overall back passivation effect and reduces the conversion efficiency of the battery. Summary of the invention

[0004] The purpose of the present invention is to solve the problem of poor back passivation effect of solar cells in the prior art, and to provide a P-type tunneling oxide passivated contact solar cell with better passivation effect and higher conversion efficiency and a preparation method thereof.

[0005] The technical solution adopted by the present invention is as follows:

[0006] A P-type tunneling oxide passivation contact solar cell comprises a front electrode, an anti-reflection layer 1, an N-type heavily doped silicon layer, a P-type silicon substrate, an Al2O3 passivation layer, an anti-reflection layer 2, and a back electrode. The anti-reflection layer 1, the N-type heavily doped silicon layer, the P-type silicon substrate, the Al2O3 passivation layer, the anti-reflection layer 2, and the back electrode are stacked in sequence, the N-type heavily doped silicon layer is further stacked with an N-type heavily doped polysilicon layer and a SiO2 layer, the SiO2 layer is in contact with the P-type silicon substrate, and the front electrode penetrates the anti-reflection layer 1 and contacts with the N-type heavily doped polysilicon layer.

[0007] Preferably, a P-type heavily doped silicon layer is embedded on the back side of the P-type silicon substrate near the Al2O3 passivation layer, and the back electrode sequentially passes through the second anti-reflection layer and the Al2O3 passivation layer to contact the P-type heavily doped silicon layer.

[0008] Preferably, the thickness of the Al2O3 passivation layer is 3-10 nm, and the anti-reflection layer 1 and the anti-reflection layer 2 are both SiN x Anti-reflection layer, SiN x The thickness of the anti-reflection layer is 100-150 nm.

[0009] Preferably, the thickness of the N-type heavily doped polysilicon layer is 15-300 nm, and the thickness of the SiO2 layer is 0.3-3 nm.

[0010] A method for preparing a P-type tunneling oxide passivation contact solar cell, the preparation of the P-type tunneling oxide passivation contact solar cell comprising the following steps:

[0011] S1, velveting;

[0012] As a preferred method, the damaged layer of the silicon wafer is first removed and then an alkali texturing process is used to form a pyramid texturing surface with a height of 0.5 μm-5 μm;

[0013] S2, forming a P-doped N+ emitter junction on the surface of the silicon wafer:

[0014] Preferably, the silicon wafer after the texturing treatment in step S1 is diffused at high temperature using phosphorus oxychloride (POCl3), the reaction temperature is 750-850°C, and the reaction time is 30-60 minutes, to form a P-doped N+ emitter junction, i.e., an N-type heavily doped silicon layer, on the surface of the silicon wafer, and simultaneously form a phosphosilicate glass (PSG) layer.

[0015] S3, cleaning the surface of the silicon wafer;

[0016] S31, removing the phosphosilicate glass (PSG) layer on the surface of the silicon wafer;

[0017] Preferably, a HF solution is used to remove the phosphosilicate glass (PSG) layer on the surface of the silicon wafer;

[0018] S32, using RCA wet chemical method to clean the surface of silicon wafer;

[0019] S4, forming a silicon dioxide layer on the front side of the silicon wafer, and then forming an N-type heavily doped polysilicon layer on the silicon dioxide layer;

[0020] Preferably, a silicon dioxide layer is formed on the front side of the silicon wafer by using a low pressure chemical vapor deposition (LPCVD) or a plasma enhanced chemical vapor deposition (PECVD) method, and then an N-type heavily doped polysilicon layer is formed on the silicon dioxide layer;

[0021] S5, printing mask;

[0022] Preferably, step S5 adopts screen printing to print the mask slurry rich in boron source on the front side of the silicon wafer according to the designed gate line screen, and adopts infrared or resistance wire heating and drying at a temperature of 110-125°C for 50-130S; after drying, alkali stripping is performed using 1.5-2wt% NaOH or KOH at a temperature of 30-45°C for 40-120S to form a P-type heavily doped silicon layer.

[0023] S6, removing the P-doped N+ junction on the back side of the silicon wafer and polishing the back side;

[0024] Preferably, in step S6, a wet etching process is used to remove the P-doped N+ junction on the back side of the silicon wafer, and the operation is performed in combination with a HNO3 / HF mixed solution.

[0025] S7, annealing;

[0026] S8, forming an aluminum oxide layer (Al2O3 passivation layer) on the back of the silicon wafer, and then forming a silicon nitride layer (anti-reflection layer 2) on the aluminum oxide layer;

[0027] Preferably, in step S8, an aluminum oxide layer (Al2O3 passivation layer) is formed on the back of the silicon wafer by atomic layer deposition (ALD), and then a silicon nitride layer (SiN x Anti-reflection layer 2).

[0028] S9, forming a silicon nitride layer (anti-reflection layer 1) on the front side of the silicon wafer;

[0029] S10, screen printing; specifically, printing metallization paste on the front / back side of the silicon wafer by screen printing, forming ohmic contact after sintering, and manufacturing a P-type tunneling oxide passivation contact solar cell.

[0030] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0031] 1. The P-type tunnel oxide passivated contact (TOPCon) solar cell structure of the present invention is a passivated contact structure formed by a tunnel oxide combined with a heavily doped silicon film, replacing the original full area doped back surface region. Specifically, in the passivated contact structure, a tunnel oxide layer is formed on the surface of a silicon substrate, using silicon oxide (SiO x , x≤2) as the passivation tunneling layer. Silicon oxide has excellent interface passivation effect, which is beneficial to significantly reduce the recombination velocity of the entire silicon wafer surface, and the heavily doped silicon film can be covered on the surface of the tunneling oxide layer through low pressure chemical vapor deposition (LPCVD) or plasma assisted chemical vapor deposition (PECVD). Of course, the silicon substrate and silicon wafer here are Figure 1 Therefore, the TOPCon solar cell structure configured as described above can combine the advantages of the existing heterojunction structure and the traditional polysilicon junction structure, that is, it has high carrier selectivity, high temperature stability, and excellent interface passivation effect, thereby realizing a solar cell with high conversion efficiency and high stability.

[0032] 2. The present invention forms a silicon dioxide layer on the front side of the silicon wafer by low pressure chemical vapor deposition (LPCVD) or plasma enhanced chemical vapor deposition (PECVD), and then forms an N-type heavily doped polysilicon layer on the silicon dioxide layer, thereby reducing the recombination loss in the metal contact area; in addition, atomic layer deposition (ALD) is performed on the back side of the silicon wafer to form an aluminum oxide layer, and then plasma enhanced chemical vapor deposition (PECVD) is performed on the aluminum oxide layer to form a silicon nitride layer, thereby increasing the dangling bonds on the surface of the atomic hydrogen-saturated substrate to provide a large amount of fixed charge field passivation effect, thereby maintaining a high short-circuit current, increasing the open-circuit voltage, improving the fill factor, and improving the battery conversion efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a schematic diagram of the structure of the present invention;

[0034] Markings in the figure: 1-front electrode, 2-anti-reflection layer 1, 3-N-type heavily doped polysilicon layer, 4-SiO2 layer, 5-N-type heavily doped silicon layer, 6-P-type silicon substrate, 7-P-type heavily doped silicon layer, 8-Al2O3 passivation layer, 9-anti-reflection layer 2, 10-back electrode. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not used to limit the present invention.

[0036] A P-type tunneling oxide passivation contact solar cell comprises a front electrode 1, an antireflection layer 2, an N-type heavily doped silicon layer 5, a P-type silicon substrate 6, an Al2O3 passivation layer 8, an antireflection layer 2 9, and a back electrode 10. The antireflection layer 2, the N-type heavily doped silicon layer 5, the P-type silicon substrate 6, the Al2O3 passivation layer 8, the antireflection layer 2 9, and the back electrode 10 are stacked in sequence, the N-type heavily doped silicon layer 5 is further stacked with an N-type heavily doped polysilicon layer 3 and a SiO2 layer 4, the SiO2 layer 4 is in contact with the P-type silicon substrate 6, and the front electrode 1 penetrates the antireflection layer 2 and contacts the N-type heavily doped polysilicon layer 3.

[0037] Among them, a P-type heavily doped silicon layer 7 is embedded on the back of the P-type silicon substrate 6 near the Al2O3 passivation layer 8, and the back electrode 10 passes through the anti-reflection layer 2 9 and the Al2O3 passivation layer 8 in sequence to contact the P-type heavily doped silicon layer 7.

[0038] The thickness of the Al2O3 passivation layer 8 is 3-10 nm, and the anti-reflection layer 1 2 and the anti-reflection layer 2 9 are both SiN x Anti-reflection layer, SiN x The thickness of the anti-reflection layer is 100-150nm; the thickness of the N-type heavily doped polysilicon layer 3 is 15-300nm, and the thickness of the SiO2 layer 4 is 0.3-3nm. Of course, the anti-reflection layer 1 2 and the anti-reflection layer 2 9 are set to SiN x The anti-reflection layer may also be configured to be composed of one or more layers of silicon nitride film, silicon oxide film, silicon oxynitride film.

[0039] The front electrode 1 can be configured as an Ag gate finger electrode, and the back electrode 10 can be configured as an Al electrode. The front electrode 1 and the back electrode 10 can also be configured as a transparent conductive film or a metal composite electrode.

[0040] A method for preparing a P-type tunneling oxide passivation contact solar cell, the preparation of the P-type tunneling oxide passivation contact solar cell comprising the following steps:

[0041] S1, first remove the damaged layer of the silicon wafer and then use alkali texturing process to form a pyramid texture surface with a height of 0.5μm-5μm;

[0042] S2. The silicon wafer treated with texturing in step S1 is diffused at high temperature using phosphorus oxychloride (POCl3). The reaction temperature is 750-850°C and the reaction time is 30-60 minutes. A P-doped N+ emitter junction, i.e., an N-type heavily doped silicon layer, is formed on the surface of the silicon wafer. At the same time, a phosphosilicate glass (PSG) layer is formed.

[0043] S3, cleaning the surface of the silicon wafer;

[0044] S31, removing the phosphosilicate glass (PSG) layer on the surface of the silicon wafer using an HF solution;

[0045] S32, using RCA wet chemical method to clean the surface of silicon wafer;

[0046] S4, forming a silicon dioxide layer on the front side of the silicon wafer by using a low pressure chemical vapor deposition (LPCVD) or a plasma enhanced chemical vapor deposition (PECVD) method, and then forming an N-type heavily doped polysilicon layer on the silicon dioxide layer;

[0047] S5. Print the mask by screen printing, print the mask slurry rich in boron source on the front of the silicon wafer according to the designed grid line screen, and dry it by infrared or resistance wire heating at a temperature of 110-125°C for 50-130S; after drying, perform alkali stripping by using 1.5-2wt% NaOH or KOH at a temperature of 30-45°C for 40-120S to form a P-type heavily doped silicon layer.

[0048] S6. Use a wet etching process with a HNO3 / HF mixed solution to remove the P-doped N+ junction on the back of the silicon wafer and polish the back;

[0049] S7, annealing;

[0050] S8, forming an aluminum oxide layer (Al2O3 passivation layer) on the back of the silicon wafer by atomic layer deposition (ALD), and then forming a silicon nitride layer (anti-reflection layer 2) on the aluminum oxide layer by plasma enhanced chemical vapor deposition (PECVD);

[0051] S9, forming a silicon nitride layer (anti-reflection layer 1) on the front side of the silicon wafer by using a plasma enhanced chemical vapor deposition (PECVD) method;

[0052] S10, printing metallization paste on the front / back side of the silicon wafer by screen printing, forming ohmic contact after sintering, and manufacturing a P-type tunneling oxide passivation contact solar cell.

[0053] Example 1

[0054] A P-type tunneling oxide passivation contact solar cell comprises a front electrode, an anti-reflection layer 1, an N-type heavily doped silicon layer, a P-type silicon substrate, an Al2O3 passivation layer, an anti-reflection layer 2, and a back electrode. The anti-reflection layer 1, the N-type heavily doped silicon layer, the P-type silicon substrate, the Al2O3 passivation layer, the anti-reflection layer 2, and the back electrode are stacked in sequence, the N-type heavily doped silicon layer is further stacked with an N-type heavily doped polysilicon layer and a SiO2 layer, the SiO2 layer is in contact with the P-type silicon substrate, and the front electrode penetrates the anti-reflection layer 1 and contacts with the N-type heavily doped polysilicon layer.

[0055] Among them, a P-type heavily doped silicon layer is embedded on the back of the P-type silicon substrate near the Al2O3 passivation layer, and the back electrode sequentially passes through the second anti-reflection layer, the Al2O3 passivation layer and contacts the P-type heavily doped silicon layer.

[0056] The thickness of the Al2O3 passivation layer is 3-10nm, and the anti-reflection layer 1 and the anti-reflection layer 2 are both SiN x The thickness of the anti-reflection layer is 100-150nm; the thickness of the N-type heavily doped polysilicon layer is 15-300nm, and the thickness of the SiO2 layer is 0.3-3nm.

[0057] The preparation of the above-mentioned P-type tunneling oxide passivated contact solar cell comprises the following steps:

[0058] S1, first remove the damaged layer of the silicon wafer and then use alkali texturing process to form a pyramid texture surface with a height of 0.5μm;

[0059] S2, the silicon wafer after the texturing treatment in step S1 is diffused by phosphorus oxychloride (POCl3) at a high temperature, the reaction temperature is 750°C, the reaction time is 30 minutes, a P-doped N+ emitter junction is formed on the surface of the silicon wafer, that is, an N-type heavily doped silicon layer, and a phosphosilicate glass (PSG) layer is formed at the same time;

[0060] S3, cleaning the surface of the silicon wafer;

[0061] S31, removing the phosphosilicate glass (PSG) layer on the surface of the silicon wafer using an HF solution;

[0062] S32, using RCA wet chemical method to clean the surface of silicon wafer;

[0063] S4, forming a silicon dioxide layer on the front side of the silicon wafer by using a low pressure chemical vapor deposition (LPCVD) or a plasma enhanced chemical vapor deposition (PECVD) method, and then forming an N-type heavily doped polysilicon layer on the silicon dioxide layer;

[0064] S5. Printing mask by screen printing, printing the mask slurry rich in boron source on the front of silicon wafer according to the designed grid line screen, and drying by infrared or resistance wire heating at 110°C for 50 seconds; after drying, alkali stripping is performed by using 1.5wt% NaOH or KOH at 30°C for 40 seconds to form a P-type heavily doped silicon layer;

[0065] S6. Use a wet etching process with a HNO3 / HF mixed solution to remove the P-doped N+ junction on the back of the silicon wafer and polish the back;

[0066] S7, annealing;

[0067] S8, forming an aluminum oxide layer (Al2O3 passivation layer) on the back of the silicon wafer by atomic layer deposition (ALD), and then forming a silicon nitride layer (anti-reflection layer 2) on the aluminum oxide layer by plasma enhanced chemical vapor deposition (PECVD);

[0068] S9, forming a silicon nitride layer (anti-reflection layer 1) on the front side of the silicon wafer by using a plasma enhanced chemical vapor deposition (PECVD) method;

[0069] S10, printing metallization paste on the front / back side of the silicon wafer by screen printing, forming ohmic contact after sintering, and manufacturing a P-type tunneling oxide passivation contact solar cell.

[0070] Example 2

[0071] On the basis of Example 1, the method for preparing a P-type tunneling oxide passivation contact solar cell in this example includes the following steps:

[0072] S1, first remove the damaged layer of the silicon wafer and then use the alkali texturing process to form a 3μm high pyramid texture surface;

[0073] S2, the silicon wafer treated by texturing in step S1 is diffused at high temperature using phosphorus oxychloride (POCl3), the reaction temperature is 800°C, the reaction time is 45 minutes, a P-doped N+ emitter junction is formed on the surface of the silicon wafer, that is, an N-type heavily doped silicon layer, and a phosphosilicate glass (PSG) layer is formed at the same time;

[0074] S3, cleaning the surface of the silicon wafer;

[0075] S31, removing the phosphosilicate glass (PSG) layer on the surface of the silicon wafer using an HF solution;

[0076] S32, using RCA wet chemical method to clean the surface of silicon wafer;

[0077] S4, forming a silicon dioxide layer on the front side of the silicon wafer by using a low pressure chemical vapor deposition (LPCVD) or a plasma enhanced chemical vapor deposition (PECVD) method, and then forming an N-type heavily doped polysilicon layer on the silicon dioxide layer;

[0078] S5. Printing mask by screen printing, printing the mask slurry rich in boron source on the front of silicon wafer according to the designed grid line screen, and drying by infrared or resistance wire heating at a temperature of 115°C for 90 seconds; after drying, alkali stripping is performed by using 1.8wt% NaOH or KOH at a temperature of 38°C for 80 seconds to form a P-type heavily doped silicon layer;

[0079] S6. Use a wet etching process with a HNO3 / HF mixed solution to remove the P-doped N+ junction on the back of the silicon wafer and polish the back;

[0080] S7, annealing;

[0081] S8, forming an aluminum oxide layer (Al2O3 passivation layer) on the back of the silicon wafer by atomic layer deposition (ALD), and then forming a silicon nitride layer (anti-reflection layer 2) on the aluminum oxide layer by plasma enhanced chemical vapor deposition (PECVD);

[0082] S9, forming a silicon nitride layer (anti-reflection layer 1) on the front side of the silicon wafer by using a plasma enhanced chemical vapor deposition (PECVD) method;

[0083] S10, printing metallization paste on the front / back side of the silicon wafer by screen printing, forming ohmic contact after sintering, and manufacturing a P-type tunneling oxide passivation contact solar cell.

[0084] Example 3

[0085] On the basis of Example 1, the method for preparing a P-type tunneling oxide passivation contact solar cell in this example includes the following steps:

[0086] S1, first remove the damaged layer of the silicon wafer and then use the alkali texturing process to form a 5μm high pyramid texture surface;

[0087] S2, using phosphorus oxychloride (POCl3) to diffuse the silicon wafer after the texturing treatment in step S1 at high temperature, the reaction temperature is 850°C, the reaction time is 60 minutes, and a P-doped N+ emitter junction, i.e., an N-type heavily doped silicon layer, is formed on the surface of the silicon wafer, and a phosphosilicate glass (PSG) layer is formed at the same time;

[0088] S3, cleaning the surface of the silicon wafer;

[0089] S31, removing the phosphosilicate glass (PSG) layer on the surface of the silicon wafer using an HF solution;

[0090] S32, using RCA wet chemical method to clean the surface of silicon wafer;

[0091] S4, forming a silicon dioxide layer on the front side of the silicon wafer by using a low pressure chemical vapor deposition (LPCVD) or a plasma enhanced chemical vapor deposition (PECVD) method, and then forming an N-type heavily doped polysilicon layer on the silicon dioxide layer;

[0092] S5. Printing mask by screen printing, printing the mask slurry rich in boron source on the front of silicon wafer according to the designed grid line screen, and drying by infrared or resistance wire heating at a temperature of 125°C for 130 seconds; after drying, alkali stripping is performed by using 2wt% NaOH or KOH at a temperature of 45°C for 120 seconds to form a P-type heavily doped silicon layer;

[0093] S6. Use a wet etching process with a HNO3 / HF mixed solution to remove the P-doped N+ junction on the back of the silicon wafer and polish the back;

[0094] S7, annealing;

[0095] S8, forming an aluminum oxide layer (Al2O3 passivation layer) on the back of the silicon wafer by atomic layer deposition (ALD), and then forming a silicon nitride layer (anti-reflection layer 2) on the aluminum oxide layer by plasma enhanced chemical vapor deposition (PECVD);

[0096] S9, forming a silicon nitride layer (anti-reflection layer 1) on the front side of the silicon wafer by using a plasma enhanced chemical vapor deposition (PECVD) method;

[0097] S10, printing metallization paste on the front / back side of the silicon wafer by screen printing, forming ohmic contact after sintering, and manufacturing a P-type tunneling oxide passivation contact solar cell.

[0098] It should be noted that the specific process methods of each step are not limited in this embodiment, and any process methods that can be implemented fall within the protection scope of the present invention.

[0099] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0100] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A P-type tunnel oxide passivated contact solar cell, characterized in that: The invention comprises a front electrode (1), an anti-reflection layer 1 (2), an N-type heavily doped silicon layer (5), a P-type silicon substrate (6), an Al2O3 passivation layer (8), an anti-reflection layer 2 (9), and a back electrode (10); the anti-reflection layer 1 (2), the N-type heavily doped silicon layer (5), the P-type silicon substrate (6), the Al2O3 passivation layer (8), the anti-reflection layer 2 (9), and the back electrode (10) are stacked in sequence; the N-type heavily doped silicon layer (5) is further stacked with an N-type heavily doped polycrystalline silicon layer (3) and a SiO2 layer (4); the SiO2 layer (4) is arranged in contact with the P-type silicon substrate (6); and the front electrode (1) penetrates the anti-reflection layer 1 (2) and contacts with the N-type heavily doped polycrystalline silicon layer (3); A P-type heavily doped silicon layer (7) is embedded on the back side of the P-type silicon substrate (6) close to the Al2O3 passivation layer (8); a back electrode (10) sequentially passes through the second anti-reflection layer (9) and the Al2O3 passivation layer (8) and contacts the P-type heavily doped silicon layer (7); the thickness of the N-type heavily doped polysilicon layer (3) is 15-300nm, and the thickness of the SiO2 layer (4) is 0.3-3nm.

2. A P-type tunnel oxide passivated contact solar cell according to claim 1, characterized in that: The thickness of the Al2O3 passivation layer (8) is 3-10 nm, and the anti-reflection layer 1 (2) and the anti-reflection layer 2 (9) are both SiN x Anti-reflection layer, SiN x The thickness of the anti-reflection layer is 100-150 nm.

3. A method for preparing a P-type tunneling oxide passivated contact solar cell, characterized in that: The preparation of the P-type tunnel oxide passivated contact solar cell as claimed in claim 1 comprises the following steps: S1, velveting; S2, forming a P-doped N+ emitter junction on the surface of the silicon wafer; S3, cleaning the surface of the silicon wafer; S4, forming a silicon dioxide layer on the front side of the silicon wafer, and then forming an N-type heavily doped polysilicon layer on the silicon dioxide layer; S5, printing mask; S6, removing the P-doped N+ junction on the back side of the silicon wafer and polishing the back side; S7, annealing; S8, forming an aluminum oxide layer on the back of the silicon wafer, and then forming a silicon nitride layer on the aluminum oxide layer; S9, forming a silicon nitride layer on the front side of the silicon wafer; S10, screen printing.

4. The method for preparing a P-type tunnel oxide passivated contact solar cell according to claim 3, characterized in that: Step S2 is specifically as follows: the silicon wafer treated in step S1 is diffused at high temperature using phosphorus oxychloride (POCl3), the reaction temperature is 750-850°C, the reaction time is 30-60 minutes, and a P-doped N+ emitter junction is formed on the surface of the silicon wafer.

5. The method for preparing a P-type tunnel oxide passivated contact solar cell according to claim 3, characterized in that: Step S3 also The following steps are included: S31: removing the phosphosilicate glass (PSG) layer on the surface of the silicon wafer using an HF solution; S32: Clean the silicon wafer surface using RCA wet chemical method.

6. The method for preparing a P-type tunnel oxide passivated contact solar cell according to claim 3, characterized in that: In step S4, a silicon dioxide layer is formed on the front side of the silicon wafer by using a low pressure chemical vapor deposition (LPCVD) or a plasma enhanced chemical vapor deposition (PECVD) method.

7. The method for preparing a P-type tunnel oxide passivated contact solar cell according to claim 3, characterized in that: Step S5 adopts screen printing to print the mask slurry rich in boron source on the back of the silicon wafer according to the designed grid line screen, and adopts infrared or resistance wire heating and drying at a temperature of 110-125°C for 50-130S; after drying, alkali stripping is performed using 1.5-2wt% NaOH or KOH at a temperature of 30-45°C for 40-120S to form a P-type heavily doped silicon layer.

8. The method for preparing a P-type tunnel oxide passivated contact solar cell according to claim 3, characterized in that: In step S8, an aluminum oxide layer is formed on the back of the silicon wafer by atomic layer deposition (ALD), and then a silicon nitride layer is formed on the aluminum oxide layer by plasma enhanced chemical vapor deposition (PECVD).

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