TOPCon solar cell

Abstract

The embodiment of the invention provides a TOPCon solar cell. The TOPCon solar cell comprises a silicon substrate, wherein the silicon substrate comprises a first surface; the first tunneling oxide layer, the first doped polycrystalline silicon layer, the first intrinsic polycrystalline silicon layer and the second doped polycrystalline silicon layer are sequentially stacked on the first surface of the silicon substrate in the first direction; the first tunneling oxide layer, the first doped polycrystalline silicon layer, the first intrinsic polycrystalline silicon layer and the second doped polycrystalline silicon layer jointly form a laminated passivation structure; and the doping concentration of the first doped polycrystalline silicon layer is lower than that of the second doped polycrystalline silicon layer. According to the technical scheme, the first intrinsic polycrystalline silicon layer is free of element doping, the doping elements in the second doped polycrystalline silicon layer are diffused into the first doped polycrystalline silicon layer, the doping elements are prevented from being diffused into the first doped polycrystalline silicon layer, the doping concentration of the doping elements of the first doped polycrystalline silicon layer can be kept low, and the electrical performance of the first doped polycrystalline silicon layer is optimized.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a TOPCon solar cell. Background Art

[0002] As one of the clean energy industries, the solar energy industry is developing rapidly at this stage. Among them, TOPCon batteries / XBC batteries are widely used. Therefore, various battery manufacturers have conducted a lot of research on this process. In order to improve efficiency, various companies have conducted a lot of research on this product process.

[0003] At present, the front passivation method of TOPCon cells is to sequentially prepare a multi-layer passivation layer including a silicon oxynitride layer, a silicon nitride film and a first aluminum oxide layer. However, the passivation effect of the multi-layer passivation layer structure directly applied to the front of the TOPCon cell is not good, and the optical and electrical properties need to be improved.

[0004] It should be noted that the above content is not necessarily prior art, nor is it intended to limit the scope of patent protection of this application. Summary of the invention

[0005] The embodiments of the present application provide a TOPCon solar cell to solve or alleviate one or more of the technical problems mentioned above.

[0006] The embodiment of the present application provides a TOPCon solar cell, comprising: A silicon substrate, the silicon substrate comprising a first surface; A first tunneling oxide layer, a first doped polysilicon layer, a first intrinsic polysilicon layer, and a second doped polysilicon layer are sequentially stacked on the first surface of the silicon substrate and along a first direction; Wherein, the first tunneling oxide layer, the first doped polysilicon layer, the first intrinsic polysilicon layer and the second doped polysilicon layer together constitute a stacked passivation structure; The doping concentration of the first doped polysilicon layer is lower than the doping concentration of the second doped polysilicon layer.

[0007] Optionally, the thickness of the first tunnel oxide layer is 1-3 nm.

[0008] Optionally, the thickness of the first doped polysilicon layer and the first intrinsic polysilicon layer are respectively and independently 5-30 nm.

[0009] Optionally, the second doped polysilicon layer has a thickness of 10-30 nm.

[0010] Optionally, along the first direction, a third doped polysilicon layer is stacked on the second doped polysilicon layer, and the thickness of the third doped polysilicon layer is 20-60 nm; The doping concentration of the first doped polysilicon layer is lower than the doping concentration of the third doped polysilicon layer.

[0011] Optionally, the silicon substrate further includes a second surface arranged opposite to the first surface; Forming a second tunneling oxide layer, a fourth doped polysilicon layer and a second doped silicon nitride layer in sequence on the second surface of the silicon substrate and along a second direction; Wherein, the first direction and the second direction are opposite.

[0012] Optionally, in the second doped polysilicon layer, doping elements of the second doped polysilicon layer include one or more of C, N or O.

[0013] Optionally, when the doping element of the second doped polysilicon layer is C, the element ratio of C to Si is 5-15%.

[0014] Optionally, when the doping element of the second doped polysilicon layer is N, the element ratio of N to Si is 5-15%.

[0015] Optionally, when the doping element of the second doped polysilicon layer is O, the element ratio of O to Si is 5-15%.

[0016] The above technical solution adopted in the embodiment of the present application may have the following advantages: The stacked passivation structure is a multi-layer polysilicon layer passivation structure, which meets the refractive index and passivation effect of the battery. Since the first intrinsic polysilicon layer is not doped with elements, on the one hand, it can reduce the lattice defects and stress caused by high element doping concentration, protect the first tunneling oxide layer, reduce its interface state density, and improve the interface passivation effect; on the other hand, the first intrinsic polysilicon layer can make the doped elements in other passivation layers with high element doping concentrations, such as the second doped polysilicon layer, diffuse into this layer, prevent its doped elements from diffusing into the first doped polysilicon layer, help to keep the doped elements of the first doped polysilicon layer at a low doping concentration, optimize its electrical properties, thereby improving the passivation performance of the stacked passivation structure, and then improving the overall conversion efficiency of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments disclosed in the present application and should not be regarded as limiting the scope of the present application.

[0018] Figure 1 It is a schematic diagram of the structure of the TOPCon solar cell provided in Example 1 of the present application.

[0019] Figure 2 It is a schematic diagram of the structure of the TOPCon solar cell provided in Example 2 of the present application.

[0020] Description of reference numerals: 1. Silicon substrate; 2. First tunneling oxide layer; 3. First doped polysilicon layer; 4. First intrinsic polysilicon layer; 5. Second doped polysilicon layer; 6. Third doped polysilicon layer; 7. Second tunneling oxide layer; 8. Fourth doped polysilicon layer; 9. First aluminum oxide layer; 10. First doped silicon nitride layer; 11. Second doped silicon nitride layer; 12. Front electrode; 13. Third tunneling oxide layer; 14. Fifth doped polysilicon layer; 15. Second intrinsic polysilicon layer; 16. Sixth doped polysilicon layer; 17. Seventh doped polysilicon layer; 18. Second aluminum oxide layer; 19. Third doped silicon nitride layer; 20. Back electrode; A1, first direction; A2, second direction. DETAILED DESCRIPTION

[0021] Embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings. In the accompanying drawings, for clarity, the sizes of layers, regions, elements and their relative sizes may be exaggerated. Wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limitations on the present application. It should be noted that, in the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0022] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present application discloses the existence of the first element, component, region, layer or part.

[0023] In this application, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0024] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein, for example. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0025] In the present application, when it comes to a numerical interval (i.e., a numerical range), unless otherwise specified, the distribution of the optional numerical values ​​in the numerical interval is considered to be continuous, and includes the two numerical endpoints (i.e., the minimum and maximum values) of the numerical interval, and each numerical value between the two numerical endpoints. Unless otherwise specified, when the numerical interval only refers to an integer in the numerical interval, it includes the two endpoint integers of the numerical range, and each integer between the two endpoints, which is equivalent to directly listing each integer. When multiple numerical ranges are provided to describe features or characteristics, these numerical ranges can be merged. In other words, unless otherwise specified, the numerical range disclosed in the present application should be understood to include any and all sub-ranges included therein. The "numerical value" in the numerical interval can be any quantitative value, such as a number, a percentage, a ratio, etc. "Numerical interval" allows for broadly including quantitative intervals such as percentage intervals, ratio intervals, and ratio intervals.

[0026] The following provides an explanation of the terms used in this application.

[0027] Special gas flow rate: the volume of gas flowing per unit time at a certain temperature and pressure.

[0028] Hereinafter, exemplary embodiments according to the present application will be described in more detail with reference to the accompanying drawings. It should be noted that these exemplary embodiments can be implemented in many different forms and should not be construed as being limited to the embodiments described herein.

[0029] The embodiment of the present application provides a TOPCon solar cell, comprising: A silicon substrate 1, wherein the silicon substrate 1 comprises a first surface; A first tunneling oxide layer 2, a first doped polysilicon layer 3, a first intrinsic polysilicon layer 4, and a second doped polysilicon layer 5 are sequentially stacked on a first surface of a silicon substrate 1 and along a first direction A1; The first tunneling oxide layer 2 , the first doped polysilicon layer 3 , the first intrinsic polysilicon layer 4 and the second doped polysilicon layer 5 together constitute a stacked passivation structure; the doping concentration of the first doped polysilicon layer 3 is lower than the doping concentration of the second doped polysilicon layer 5 .

[0030] In this embodiment, the stacked passivation structure is a stacked structure of multiple polysilicon passivation layers, which meets the refractive index and passivation effect of the battery. Since the first intrinsic polysilicon layer 4 is not doped with elements, on the one hand, it can reduce the lattice defects and stress caused by high element doping concentrations, protect the first tunneling oxide layer 2, reduce its interface state density, and improve the interface passivation effect; on the other hand, the first intrinsic polysilicon layer 4 can allow the doped elements in other passivation layers with high element doping concentrations, such as the second doped polysilicon layer 5, to diffuse into this layer, and prevent its doped elements from diffusing into the first doped polysilicon layer 3, which helps to keep the doped elements of the first doped polysilicon layer 3 at a low doping concentration and optimize its electrical properties, thereby improving the passivation performance of the stacked passivation structure and further improving the overall conversion efficiency of the battery.

[0031] Furthermore, the first intrinsic polysilicon layer 4 without element doping can inhibit the grain growth caused by doping in the second doped polysilicon layer 5, reduce the mechanical stress and damage to the passivation layer of the first tunneling oxide layer 2, thereby improving the passivation performance and long-term stability. At the same time, the polysilicon passivation stacked structure can also form a built-in electric field, which helps to separate and collect photogenerated carriers and improve the efficiency of solar cells.

[0032] It should be noted that the first tunneling oxide layer 2, the first doped polysilicon layer 3, the first intrinsic polysilicon layer 4 and the second doped polysilicon layer 5 together constitute a stacked passivation structure which can be arranged on the front or back side of the silicon substrate 1. When the stacked passivation structure is arranged on the back side of the silicon substrate 1, it can improve the overall conversion efficiency of the battery.

[0033] In an optional embodiment, the thickness of the first tunnel oxide layer 2 is 1-3 nm (eg, 1 nm, 2 nm, 3 nm).

[0034] In this embodiment, when the thickness of the first tunneling oxide layer 2 is less than 1 nm, the electron tunneling effect will be insufficient and the surface recombination effect cannot be effectively reduced, thereby affecting the photoelectric conversion efficiency of the battery; when the thickness of the first tunneling oxide layer 2 is higher than 3 nm, the surface reflection will be increased, the utilization rate of light will be reduced, and the performance of the battery will be affected.

[0035] In an optional embodiment, the thickness of the first doped polysilicon layer 3 and the first intrinsic polysilicon layer 4 are respectively and independently 5-30 nm (eg, 5 nm, 15 nm, 30 nm).

[0036] In an optional embodiment, the thickness of the second doped polysilicon layer 5 is 10-30 nm (eg, 10 nm, 20 nm, 30 nm).

[0037] In an optional embodiment, a third doped polysilicon layer 6 is stacked on the second doped polysilicon layer 5 along the first direction, and the thickness of the third doped polysilicon layer 6 is 20~60nm (for example, 20nm, 40nm, 60nm); the doping concentration of the first doped polysilicon layer 3 is lower than the doping concentration of the third doped polysilicon layer 6.

[0038] In this embodiment, by precisely controlling the thickness of each layer, the electrical properties and passivation effect of each polysilicon layer structure can be optimized. Since it is necessary to ensure that the metal slurry cannot burn through, and thus ensure the contact between the metal slurry and the polysilicon layer, the thickness of the third doped polysilicon layer 6 must be at least 20nm; when the thickness of the third doped polysilicon layer 6 is less than 60nm, its H content is low, and the probability of film explosion after annealing is low; and the parasitic absorption of light is weakened, which helps the silicon base to absorb light. In addition, if the thickness of the third doped polysilicon layer 6 is too thick, it will lead to an increase in parasitic absorption and reduce the battery performance. Therefore, the thickness of the third doped polysilicon layer 6 should not exceed 60nm. When the thickness of the third doped polysilicon layer 6 is in the range of 20~60nm, it can prevent the metal slurry from burning through to ensure good contact, and can also avoid the parasitic absorption caused by the excessive thickness of the third doped polysilicon layer 6, thereby optimizing the overall performance of the solar cell. Since the doping concentration of the first doped polysilicon layer 3 is lower than the doping concentration of the third doped polysilicon layer 6, the first intrinsic polysilicon layer 4 can prevent the doping elements of the third doped polysilicon layer 6 from diffusing into the first doped polysilicon layer 3, which helps to keep the doping elements of the first doped polysilicon layer 3 at a low doping concentration.

[0039] In an optional embodiment, it also includes: the silicon substrate 1 also includes a second surface arranged opposite to the first surface; a second tunneling oxide layer 7, a fourth doped polysilicon layer 8 and a second doped silicon nitride layer 11 are sequentially stacked on the second surface of the silicon substrate 1 and along the second direction A2; wherein the first direction A1 and the second direction A2 are opposite.

[0040] In an optional embodiment, in the second doped polysilicon layer 5 , the doping elements of the second doped polysilicon layer 5 include one or more of C, N or O.

[0041] In the second doped polysilicon layer 5, the bond energies of C~H bonds, N~H bonds, and O~H bonds are all higher than those of Si~H bonds, which means that these bonds are stronger in terms of thermal stability and anti-degradation ability. Introducing bonds formed by one or more elements of C, N or O in the second doped polysilicon layer 5 can effectively lock hydrogen atoms and reduce the escape of hydrogen atoms under high temperature or other stress conditions, thereby improving the stability of the polysilicon layer. It should be noted that the presence of hydrogen atoms in the polysilicon layer can passivate interface defects and dangling bonds, thereby improving the passivation effect of the interface. However, under high temperature conditions, hydrogen is easy to escape, resulting in a decrease in the passivation effect and causing a film explosion phenomenon. By introducing C~H bonds, the position of hydrogen atoms can be stabilized and the passivation effect can be maintained. In addition, when the doping element is carbon, the introduction of carbon in the polysilicon layer can also enhance the overall mechanical stability of the material and reduce the film explosion phenomenon caused by stress through the rearrangement of chemical bonds. In addition, carbon doping can also reduce the parasitic absorption of sunlight by the polysilicon layer and improve the photoelectric conversion efficiency of the device.

[0042] In an optional embodiment, during the formation of the first doped polysilicon layer 3, a first mixed gas is introduced into the reaction chamber, and the first mixed gas includes SiH4, H2 and B2H6; during the formation of the first intrinsic polysilicon layer 4, a second mixed gas is introduced into the reaction chamber, and the second mixed gas includes SiH4 and H2; during the formation of the second doped polysilicon layer 5, a third mixed gas is introduced into the reaction chamber, and the third mixed gas includes CH4, SiH4, H2 and B2H6; during the formation of the third doped polysilicon layer 6, a fourth mixed gas is introduced into the reaction chamber, and the fourth mixed gas includes SiH4, H2 and B2H6.

[0043] In this embodiment, all the mixed gases contain SiH4 and H2. After SiH4 is decomposed, silicon atoms are provided for the growth and deposition of the polysilicon layer; H2 is used to remove oxides and other impurities on the surface of the polysilicon layer. H2 can also maintain an inert atmosphere in the reaction chamber during the growth of polysilicon to prevent oxidation and impurity contamination. There is no B2H6 in the second mixed gas, so the prepared first intrinsic polysilicon layer 4 is free of B element doping. The other layers introduce B element into the polysilicon layer through B2H6. The addition of B2H6 can achieve p-type doping, and each polysilicon layer is p-type.

[0044] In an optional embodiment, in the first mixed gas, the ratio of the special gas flow rates of B2H6 and SiH4 is greater than 0 and less than or equal to 0.095; in the third mixed gas, the ratio of the special gas flow rates of B2H6 and SiH4 is greater than or equal to 0.1 and less than or equal to 0.286; in the fourth mixed gas, the ratio of the special gas flow rates of B2H6 and SiH4 is greater than or equal to 0.3.

[0045] In this embodiment, the B element doping concentration in the first doped polysilicon layer 3, the second doped polysilicon layer 5 and the third doped polysilicon layer 6 is adjusted by controlling the special gas flow of B2H6 and SiH4 in the first mixed gas, the third mixed gas and the fourth mixed gas, so that the conductivity and interface characteristics can be optimized and the overall device performance can be improved by controlling the gradient of the doped B concentration in each layer of the first doped polysilicon layer 3, the second doped polysilicon layer 5 and the third doped polysilicon layer 6. It should be noted that the second doped polysilicon layer 5 and the third doped polysilicon layer 6 used in the embodiment of the present application are doped with a high concentration of B element, which can improve the conductivity and help reduce the series resistance, while the first intrinsic polysilicon layer 4 is not doped with B element, which ensures a lower recombination rate and effectively improves the passivation effect.

[0046] In an optional embodiment, the first doped polysilicon layer 3 , the second doped polysilicon layer 5 , and the third doped polysilicon layer 6 are all P-type polysilicon layers.

[0047] In an optional embodiment, the first doped polysilicon layer 3 , the second doped polysilicon layer 5 , and the third doped polysilicon layer 6 are all N-type polysilicon layers.

[0048] In this embodiment, the first doped polysilicon layer 3, the second doped polysilicon layer 5 and the third doped polysilicon layer 6 can be selected as N-type or P-type according to specific device design and application requirements, and each layer works synergistically in the device to improve the overall performance.

[0049] The present application embodiment provides a method for preparing a TOPCon solar cell, and the specific preparation steps are as follows: Step S1: using an N-type single crystal silicon wafer as a silicon substrate, cleaning it with RCA and performing double-sided texturing treatment; Step S2: placing a silicon substrate in a reaction chamber, and forming a first tunneling oxide layer, a first doped polysilicon layer, a first intrinsic polysilicon layer, a second doped polysilicon layer, and a third doped polysilicon layer in sequence on a first surface (front surface) of the silicon substrate and along a first direction; wherein the first tunneling oxide layer, the first doped polysilicon layer, the first intrinsic polysilicon layer, the second doped polysilicon layer, and the third doped polysilicon layer together constitute a preliminary stacked passivation structure, and then placing the preliminary stacked passivation structure in a diffusion furnace for annealing at an annealing temperature of 900° C. for an annealing time of 30 minutes to obtain a stacked passivation structure; in the second doped polysilicon layer, the doping element of the second doped polysilicon layer is one or more of C, N, and O; Step S3: using the PECVD method to sequentially stack a second tunneling oxide layer and a fourth doped polysilicon layer on the second surface (back side) of the silicon substrate along the second direction, and the fourth doped polysilicon layer is subjected to high-temperature annealing; then, a second doped silicon nitride layer is deposited on the fourth doped polysilicon layer; wherein the preparation materials of the first tunneling oxide layer and the second tunneling oxide layer are both silicon dioxide.

[0050] Step S4: depositing a first aluminum oxide layer on the third doped polysilicon layer and performing a high temperature annealing treatment; depositing a first doped silicon nitride layer on the first aluminum oxide layer; Step S5: printing Ag paste on the first doped silicon nitride layer and the second doped silicon nitride layer and sintering to form Ag electrodes to obtain a pre-TOPCon solar cell; Step S6: annealing the pre-TOPCon solar cell at 400° C. for 60 min to obtain a TOPCon solar cell.

[0051] In an optional embodiment, during the high-temperature annealing process of the first aluminum oxide layer, N2O gas is introduced, and the annealing temperature is 350-550°C, and the annealing time is 10-30 minutes.

[0052] In this embodiment, the introduction of N2O gas during the high-temperature annealing of the first aluminum oxide layer can introduce oxygen and nitrogen elements, further oxidize the incompletely oxidized aluminum, and improve the oxidation degree and stability of the first aluminum oxide layer. Nitrogen elements can enter the first aluminum oxide layer to form nitrogen oxides, enhance the passivation effect, increase the stability and mechanical strength of the film, and increase the durability of the film. Therefore, the introduction of N2O gas can further optimize the passivation effect of the first aluminum oxide layer, reduce the interface defect state density, and increase the minority carrier lifetime. High-temperature annealing in an N2O atmosphere can also improve the interface quality between the first aluminum oxide layer and the substrate, and improve the electrical properties of the overall structure.

[0053] In an optional embodiment, during the high-temperature annealing process of the fourth doped polysilicon layer, NH 3 gas is introduced, and the annealing temperature is 250-500° C., and the annealing time is 5-10 min.

[0054] During the high-temperature annealing process of the fourth doped polysilicon layer, NH3 gas is introduced to introduce nitrogen elements and form N~H bonds, which enhance the passivation effect and increase the stability of the film. Nitrogen atoms can enter the fourth doped polysilicon layer to fill vacancies and defects in the silicon lattice. The high bond energy of the N~H bond can effectively "lock" hydrogen atoms, reduce the migration of hydrogen atoms, and reduce the probability of film explosion.

[0055] like Figure 1 As shown, the embodiment of the present application also provides a TOPCon solar cell, which is formed by the preparation method of the TOPCon solar cell of any of the above embodiments, including: on the first surface (front side) of the silicon substrate 1 and in a first direction A1, a first tunneling oxide layer 2, a first doped polysilicon layer 3, a first intrinsic polysilicon layer 4, a second doped polysilicon layer 5, a third doped polysilicon layer 6, a first aluminum oxide layer 9 and a first doped silicon nitride layer 10 are stacked in sequence; on the second surface (back side) of the silicon substrate 1 and in a second direction A2, a second tunneling oxide layer 7, a fourth doped polysilicon layer 8 and a second doped silicon nitride layer 11 are stacked in sequence, the first aluminum oxide layer 9 and the first doped silicon nitride layer 10 are burned through, and the front electrode 12 is penetrated in the third doped polysilicon layer 6; the second doped silicon nitride layer 11 is burned through, and the back electrode 20 is penetrated in the fourth doped polysilicon layer 8.

[0056] The following specific examples further illustrate the present application, but should not be construed as limiting the present application. Without departing from the spirit and substance of the present application, modifications or replacements made to the methods, steps or conditions of the present application are within the scope of the present application.

[0057] [Example 1] like Figure 1 As shown, the specific structure of a TOPCon solar cell is: Silicon substrate 1; A first tunneling oxide layer 2, a first doped polysilicon layer 3, a first intrinsic polysilicon layer 4, a second doped polysilicon layer 5, a third doped polysilicon layer 6, a first aluminum oxide layer 9 and a first doped silicon nitride layer 10 are sequentially stacked on a first surface (front surface) of a silicon substrate 1 and along a first direction A1; A second tunnel oxide layer 7, a fourth doped polysilicon layer 8 and a second doped silicon nitride layer 11 are sequentially stacked on the second surface (back surface) of the silicon substrate 1 and along the second direction A2; And a front electrode 12 and a back electrode 20 located on the front side of the silicon substrate 1 .

[0058] The specific preparation process of a TOPCon solar cell is as follows: Step S1: using an N-type single crystal silicon wafer as a silicon substrate, cleaning it with RCA and performing double-sided texturing treatment; Step S2: placing a silicon substrate in a reaction chamber, passing N2O on the silicon substrate in the reaction chamber to generate a first tunneling oxide layer (2nm), passing a first mixed gas on the first tunneling oxide layer to generate a first doped polysilicon layer (10nm); continuing to pass a second mixed gas on the first doped polysilicon layer to generate a first intrinsic polysilicon layer (10nm); passing a third mixed gas on the first intrinsic polysilicon layer to generate a second doped polysilicon layer (25nm); finally passing a fourth mixed gas on the second doped polysilicon layer to generate a third doped polysilicon layer (30nm); placing the silicon substrate on which the first tunneling oxide layer, the first doped polysilicon layer, the first intrinsic polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer are stacked in sequence in a diffusion furnace at 900°C, and performing high-temperature annealing for 30 minutes to form a stacked passivation structure; Among them, when the doping element in the second doped polysilicon layer is C element (carbon element), the element ratio of C to Si is 10%; the first mixed gas is SiH4, H2 and B2H6, and the ratio of the special gas flow of B2H6 to SiH4 is 0.05; the second mixed gas includes SiH4 and H2; the third mixed gas includes CH4, SiH4, H2 and B2H6, and the ratio of the special gas flow of B2H6 to SiH4 is 0.286; the fourth mixed gas includes SiH4, H2 and B2H6, and the ratio of the special gas flow of B2H6 to SiH4 is 0.3; Step S3: performing RCA cleaning on the surface of the third doped polysilicon layer, depositing a first aluminum oxide layer (8 nm) on the third doped polysilicon layer by ALD method and performing high-temperature annealing treatment; wherein, during the high-temperature annealing treatment of the first aluminum oxide layer, N2O gas is introduced, and the annealing temperature is 460° C., and the annealing time is 25 min; A first doped silicon nitride layer (30 nm) is deposited on the first aluminum oxide layer by using a PECVD method; Step S4: After cleaning and alkali polishing the back side of the silicon substrate to remove the back side coated polysilicon layer, a second tunneling oxide layer (2nm) and a fourth doped polysilicon layer (150nm) are sequentially prepared on the back side of the silicon substrate by a PECVD method, and the fourth doped polysilicon layer is subjected to a high temperature annealing treatment; wherein, during the high temperature annealing treatment of the fourth doped polysilicon layer, NH3 gas is introduced, and the annealing temperature is 300°C and the annealing time is 8min; then, a second doped silicon nitride layer (50nm) is deposited on the fourth doped polysilicon layer; Step S5: burning through the first aluminum oxide layer and the first doped silicon nitride layer, and the front electrode is arranged in the third doped polysilicon layer; burning through the second doped silicon nitride layer, and the back electrode is arranged in the fourth doped polysilicon layer, to obtain a pre-TOPCon solar cell; Step S6: annealing the pre-TOPCon solar cell at 400° C. for 60 min to obtain a TOPCon solar cell.

[0059] [Example 2] like Figure 2 As shown, the specific structure of a TOPCon solar cell is: Silicon substrate 1; A first tunneling oxide layer 2, a first doped polysilicon layer 3, a first intrinsic polysilicon layer 4, a second doped polysilicon layer 5, a third doped polysilicon layer 6, a first aluminum oxide layer 9 and a first doped silicon nitride layer 10 are sequentially stacked on a first surface (front surface) of a silicon substrate 1 and along a first direction A1; A third tunneling oxide layer 13, a fifth doped polysilicon layer 14, a second intrinsic polysilicon layer 15, a sixth doped polysilicon layer 16, a seventh doped polysilicon layer 17, a second aluminum oxide layer 18 and a third doped silicon nitride layer 19 are sequentially stacked on the second surface (back surface) of the silicon substrate 1 and along the second direction A2; And a front electrode 12 and a back electrode 20 located on the front side of the silicon substrate 1 .

[0060] The TOPCon solar cell of Example 2 is prepared by referring to the preparation method of Example 1. The specific preparation process of the TOPCon solar cell of Example 2 is as follows: Step S1: using an N-type single crystal silicon wafer as a silicon substrate, cleaning it with RCA and performing double-sided texturing treatment; Step S2: placing a silicon substrate in a reaction chamber, passing N2O on the silicon substrate in the reaction chamber to generate a first tunneling oxide layer (3nm), passing a first mixed gas on the first tunneling oxide layer to generate a first doped polysilicon layer (30nm); continuing to pass a second mixed gas on the first doped polysilicon layer to generate a first intrinsic polysilicon layer (30nm); passing a third mixed gas on the first intrinsic polysilicon layer to generate a second doped polysilicon layer (30nm); finally, passing a fourth mixed gas on the second doped polysilicon layer to generate a third doped polysilicon layer (60nm); the first tunneling oxide layer, the first doped polysilicon layer, the first intrinsic polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer are stacked in sequence, and after being assembled, they are placed in a diffusion furnace for high-temperature annealing at 900°C for 30 minutes to form a stacked passivation structure; Among them, when the doping element in the second doped polysilicon layer is C element (carbon element), the element ratio of C to Si is 15%, the first mixed gas is SiH4, H2 and B2H6, and the ratio of the special gas flow of B2H6 to SiH4 is 0.05; the second mixed gas includes SiH4 and H2; the third mixed gas includes CH4, SiH4, H2 and B2H6, and the ratio of the special gas flow of B2H6 to SiH4 is 0.286; the fourth mixed gas includes SiH4, H2 and B2H6, and the ratio of the special gas flow of B2H6 to SiH4 is 0.3; Step S3: preparing a third tunneling oxide layer (3 nm) on the back side of the silicon substrate, introducing a fifth mixed gas into the third tunneling oxide layer to generate a fifth doped polysilicon layer (30 nm); continuing to introduce a sixth mixed gas into the fifth doped polysilicon layer to generate a second intrinsic polysilicon layer (30 nm); introducing a seventh mixed gas into the second intrinsic polysilicon layer to generate a sixth doped polysilicon layer (30 nm); finally introducing an eighth mixed gas into the sixth doped polysilicon layer to generate a seventh doped polysilicon layer (60 nm); the fifth doped polysilicon layer, the second intrinsic polysilicon layer, the sixth doped polysilicon layer, and the seventh doped polysilicon layer are stacked in sequence, and after being assembled, they are placed in a diffusion furnace for high-temperature annealing at 900° C. for 30 minutes to form a stacked passivation structure; Among them, when the doping element in the sixth doped polysilicon layer is C element (carbon element), the element ratio of C to Si is 15%; the sixth mixed gas includes SiH4 and H2; the seventh mixed gas includes CH4, SiH4, H2 and PH3, and the ratio of the special gas flow of PH3 to SiH4 is 0.286; the eighth mixed gas includes SiH4, H2 and PH3, and the ratio of the special gas flow of PH3 to SiH4 is 0.3; Step S4: performing RCA cleaning on the front side of the third doped polysilicon layer, and using the ALD method to deposit a first aluminum oxide layer (8 nm) on the third doped polysilicon layer and perform high-temperature annealing treatment; wherein, during the high-temperature annealing treatment of the first aluminum oxide layer, N2O gas is introduced, and the annealing temperature is 460°C, and the annealing time is 25 minutes; then, a first doped silicon nitride layer (30 nm) is deposited on the first aluminum oxide layer by the PECVD method; Step S5: performing RCA cleaning on the back side of the seventh doped polysilicon layer, and using the ALD method to deposit a second aluminum oxide layer (8 nm) on the seventh doped polysilicon layer and perform high-temperature annealing treatment; wherein, during the high-temperature annealing treatment of the second aluminum oxide layer, N2O gas is introduced, and the annealing temperature is 460°C, and the annealing time is 25 minutes; then, a third doped silicon nitride layer (30 nm) is deposited on the second aluminum oxide layer by the PECVD method; Step S6: burning through the first aluminum oxide layer and the first doped silicon nitride layer, and the front electrode is disposed in the third doped polysilicon layer; burning through the second doped silicon nitride layer, and the back electrode is disposed in the fourth doped polysilicon layer, to obtain a pre-TOPCon solar cell; Step S7: annealing the pre-TOPCon solar cell at 450° C. for 90 min to obtain a TOPCon solar cell.

[0061] [Example 3]~[Example 4] The TOPCon solar cells of Examples 3 and 4 were prepared with reference to the preparation method of Example 1, except that, in Example 3, when the doping element in the second doped polysilicon layer is C element (carbon element), the element ratio of C to Si is 5%; the first mixed gas is SiH4, H2 and B2H6, and the ratio of the special gas flow of B2H6 to SiH4 is 0.095; the second mixed gas includes SiH4 and H2; the third mixed gas includes CH4, SiH4, H2 and B2H6, and the ratio of the special gas flow of B2H6 to SiH4 is 0.2; the fourth mixed gas includes SiH4, H2 and B2H6, and the ratio of the special gas flow of B2H6 to SiH4 is 0.4; In Example 4, when the doping element in the second doped polysilicon layer is C element (carbon element), the element ratio of C to Si is 15%; the first mixed gas is SiH4, H2 and B2H6, and the ratio of the special gas flow of B2H6 to SiH4 is 0.03; the second mixed gas includes SiH4 and H2; the third mixed gas includes CH4, SiH4, H2 and B2H6, and the ratio of the special gas flow of B2H6 to SiH4 is 0.1, and the volume ratio of CH4 to SiH4 is 1; the fourth mixed gas includes SiH4, H2 and B2H6, and the ratio of the special gas flow of B2H6 to SiH4 is 0.4.

[0062] In order to more clearly illustrate the technical effects of the embodiments of the present application, the present application also points out the structure and preparation method of the TOPCon solar cell of Comparative Example 1.

[0063] [Comparative Example 1] The TOPCon solar cell of Comparative Example 1 was prepared by referring to the preparation method of Example 1, except that: Step S1: using an N-type single crystal silicon wafer as a silicon substrate, cleaning it with RCA and performing double-sided texturing treatment; Step S2: placing the silicon substrate in PECVD, passing N2O on the front side of the silicon substrate to generate a first tunneling oxide layer (2nm), passing a third mixed gas on the first tunneling oxide layer to generate a second doped polysilicon layer (20nm); finally, passing a fourth mixed gas on the second doped polysilicon layer to generate a third doped polysilicon layer (40nm); the first tunneling oxide layer, the first doped polysilicon layer, the second doped polysilicon layer and the third doped polysilicon layer are stacked in sequence, and after being assembled, they are placed in a diffusion furnace for high-temperature annealing at 900°C for 30 minutes to form a stacked passivation structure; Among them, when the doping element in the second doped polysilicon layer is C element (carbon element), the element ratio of C to Si is 10%, the first mixed gas is SiH4, H2 and B2H6, and the ratio of the special gas flow rate of B2H6 to SiH4 is 0.05; the third mixed gas includes CH4, SiH4, H2 and B2H6, and the ratio of the special gas flow rate of B2H6 to SiH4 is 0.286; the fourth mixed gas includes SiH4, H2 and B2H6, and the ratio of the special gas flow rate of B2H6 to SiH4 is 0.3.

[0064] The following is a performance test of the batteries provided in Examples 1 to 4 of the present application and Comparative Example 1, so as to obtain the open circuit voltage Voc, fill factor FF, short circuit current density Jsc, and photoelectric conversion efficiency PCE of the corresponding battery devices, and the test results are shown in Table 1.

[0065] Table 1 Performance test results of the batteries of Examples 1 to 4 and Comparative Example 1

[0066] It can be seen from Table 1 that compared with Comparative Example 1, the open circuit voltage Voc, fill factor FF, short circuit current density Jsc, and photoelectric conversion efficiency PCE of the TOPCon solar cells of Examples 1 to 4 of the present application are significantly improved, which indicates that the stacked passivation structure of the first tunneling oxide layer, the first doped polysilicon layer, the first intrinsic polysilicon layer, the second doped polysilicon layer, and the third doped polysilicon layer in Examples 1 to 4 of the present application can effectively improve the device efficiency. In addition, the first intrinsic polysilicon layer is element-free, and the first doped polysilicon layer, the second doped polysilicon layer, and the third doped polysilicon layer can optimize the conductivity and interface characteristics by controlling the gradient of the doped B element concentration, thereby effectively improving the passivation effect.

[0067] In summary, the stacked passivation structure is a multi-layer polysilicon passivation layer stacking structure, which meets the refractive index and passivation effect of the battery. Since the first intrinsic polysilicon layer is element-free, on the one hand, it can reduce the lattice defects and stress caused by high element doping concentration, protect the first tunneling oxide layer, reduce its interface state density, and improve the interface passivation effect; on the other hand, the first intrinsic polysilicon layer can make the doped elements in other passivation layers with high element doping concentrations such as the second doped polysilicon layer and the third doped polysilicon layer diffuse into this layer, prevent their doped elements from diffusing into the first doped polysilicon layer, help to keep the doped elements of the first doped polysilicon layer at a low doping concentration, and optimize its electrical properties; in addition, it can also prevent the doped elements in the second doped polysilicon layer from doping and introducing grain enlargement to damage the underlying first tunneling oxide layer, thereby improving the passivation performance of the stacked passivation structure, and then improving the overall conversion efficiency of the battery.

[0068] In addition, the first intrinsic polysilicon layer without element doping can inhibit the grain growth caused by doping in the second doped polysilicon layer and the third doped polysilicon layer, reduce the mechanical stress and damage to the underlying first tunneling oxide passivation layer, thereby improving the passivation performance and long-term stability. At the same time, the multi-layer polysilicon passivation layer superposition structure can also form a built-in electric field, which helps to separate and collect photogenerated carriers and improve the efficiency of solar cells.

[0069] It should be noted that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential", etc. are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. The orientation words "inside" and "outside" refer to the inside and outside relative to the outline of each component itself. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Therefore, the exemplary term "above..." can include both "above..." and "below..." orientations. The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatial relative descriptions used here are interpreted accordingly.

[0070] It should also be noted that "one embodiment", "another embodiment", "embodiment", etc. mentioned in this application refer to the specific features, structures or characteristics described in conjunction with the embodiment included in at least one embodiment generally described in this application. The same expression appearing in multiple places in the specification does not necessarily refer to the same embodiment. Further, when describing a specific feature, structure or characteristic in conjunction with any embodiment, it is claimed that the realization of such feature, structure or characteristic in conjunction with other embodiments also falls within the scope of this application.

[0071] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0072] It should also be noted that the above are only preferred embodiments of the present application, and the patent protection scope of the present application is not limited thereto. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A TOPCon solar cell, characterized in that: include: A silicon substrate (1), wherein the silicon substrate (1) comprises a first surface; A first tunneling oxide layer (2), a first doped polysilicon layer (3), a first intrinsic polysilicon layer (4), and a second doped polysilicon layer (5) are sequentially stacked on a first surface of the silicon substrate (1) and along a first direction; The first tunneling oxide layer (2), the first doped polysilicon layer (3), the first intrinsic polysilicon layer (4) and the second doped polysilicon layer (5) together constitute a stacked passivation structure; The doping concentration of the first doped polysilicon layer (3) is lower than the doping concentration of the second doped polysilicon layer (5).

2. The TOPCon solar cell according to claim 1, characterized in that: The thickness of the first tunnel oxide layer (2) is 1-3 nm.

3. The TOPCon solar cell according to claim 1, characterized in that: The thickness of the first doped polysilicon layer (3) and the first intrinsic polysilicon layer (4) are respectively and independently 5-30 nm.

4. The TOPCon solar cell according to claim 1, characterized in that: The thickness of the second doped polysilicon layer (5) is 10-30 nm.

5. The TOPCon solar cell according to claim 1, characterized in that: A third doped polysilicon layer (6) is stacked on the second doped polysilicon layer (5) along the first direction, and the thickness of the third doped polysilicon layer (6) is 20-60 nm; The doping concentration of the first doped polysilicon layer (3) is lower than the doping concentration of the third doped polysilicon layer (6).

6. The TOPCon solar cell according to claim 1, characterized in that: Also includes: The silicon substrate (1) further comprises a second surface arranged opposite to the first surface; A second tunneling oxide layer (7), a fourth doped polysilicon layer (8) and a second doped silicon nitride layer (11) are sequentially stacked on the second surface of the silicon substrate (1) and along a second direction; The first direction and the second direction are opposite.

7. The TOPCon solar cell according to any one of claims 1 to 6, characterized in that: In the second doped polysilicon layer (5), the doping elements of the second doped polysilicon layer (5) include one or more of C, N or O.

8. The TOPCon solar cell according to claim 7, characterized in that: When the doping element of the second doped polysilicon layer (5) is C, the element ratio of C to Si is 5-15%.

9. The TOPCon solar cell according to claim 7, characterized in that: When the doping element of the second doped polysilicon layer (5) is N, the element ratio of N to Si is 5-15%.

10. The TOPCon solar cell according to claim 7, characterized in that: When the doping element of the second doped polysilicon layer (5) is O, the element ratio of O to Si is 5-15%.

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