A power semiconductor device and a method for manufacturing the same

Abstract

The present invention relates to the field of semiconductor technology, and specifically discloses a power semiconductor device, including a semiconductor substrate, which is divided into a cell area and a terminal protection area, wherein the semiconductor substrate includes a first conductive type substrate and a first conductive type epitaxial layer, and a second conductive type body area is arranged on the surface of the first conductive type epitaxial layer; a first type of groove is arranged in the second conductive type body area located in the cell area, and the bottom of the first type of groove extends into the first conductive type epitaxial layer; at least one second type of groove is arranged in the second conductive type body area located in the terminal protection area near the cell area; the groove depth of the second type of groove is less than the groove depth of the first type of groove, and the groove opening width of the second type of groove is less than the groove opening width of the first type of groove. The present invention also discloses a method for manufacturing a power semiconductor device. The power semiconductor device provided by the present invention improves the withstand voltage reliability of the power semiconductor device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a power semiconductor device and a method for manufacturing the power semiconductor device. Background Art

[0002] Power semiconductor devices usually include an active area for current flow and a terminal protection area for protecting the active area. When the power semiconductor device is working in a reverse blocking state, the terminal protection area can alleviate the strong electric field at the edge of the active area, improve the device's withstand voltage, and reduce the device's leakage current. The structure of the terminal protection area affects the device's withstand voltage on the one hand; on the other hand, it also affects the size of the device's chip area, that is, it affects the integration of cells in the active area.

[0003] like Figure 1 The figure shows the structure of an existing ordinary trench MOSFET. Taking an N-type device as an example, on the cross section of the MOS device, the terminal protection zone of the MOS device includes at least one voltage divider ring of a trench structure, the inner wall of the trench is covered with an insulating oxide layer, and the trench covered with the insulating oxide layer is filled with conductive polysilicon. An insulating dielectric layer is provided at the trench notch and both sides of the notch, and the conductive polysilicon is enclosed in the trench by the insulating dielectric layer, so that the voltage divider trench in the voltage divider ring becomes a floating state.

[0004] When the device is working in the reverse blocking state, the gate and the source are connected to zero potential, and the conductive polysilicon floating in the trench is induced to a high potential. The higher the reverse blocking voltage of the device, the higher the potential induced by the conductive polysilicon floating in the trench closest to the cell region. Since the depletion layer bends upward to the silicon surface along the side wall of the trench closest to the cell region, specifically, the trench side wall is the trench side wall adjacent to the cell region, such as Figure 1 The electric field concentration position marked in the figure is therefore much narrower than the original depletion layer width parallel to the surface of the semiconductor substrate, resulting in an excessively strong electric field formed on the surface of the insulating gate oxide layer on the sidewall of the trench. In addition, the higher the potential induced by the floating conductive polysilicon in the trench closest to the cell area, the stronger the electric field formed. Due to the thin thickness of the insulating gate oxide layer and its limited withstand voltage capability, the withstand voltage reliability of the device will be reduced. Summary of the invention

[0005] The present invention provides a power semiconductor device and a method for manufacturing the power semiconductor device, which solve the problem of voltage resistance reliability of the power semiconductor device existing in the related art.

[0006] As one aspect of the present invention, a power semiconductor device is provided, comprising a semiconductor substrate, wherein the semiconductor substrate is divided into a cell region and a terminal protection region, wherein the cell region is located in a central region of the semiconductor substrate, and the terminal protection region is located in an outer ring of the cell region and is arranged around the cell region, wherein the semiconductor substrate comprises a first conductive type substrate and a first conductive type epitaxial layer located on the first conductive type substrate, and a second conductive type body region is arranged on a surface of the first conductive type epitaxial layer;

[0007] A first type trench is provided in the second conductive type body region located in the cell region, and the bottom of the first type trench extends into the first conductive type epitaxial layer;

[0008] At least one second type trench is arranged in the second conductive type body region of the terminal protection area near the cell region;

[0009] The groove depth of the second type groove is smaller than the groove depth of the first type groove, and the groove opening width of the second type groove is smaller than the groove opening width of the first type groove.

[0010] Furthermore, at least one third type trench is arranged in the second conductive type body region located in the terminal protection area, and the third type trench is arranged around the second type trench;

[0011] The groove depth of the third type groove is not less than the groove depth of the first type groove, and the groove opening width of the third type groove is not less than the groove opening width of the first type groove.

[0012] Furthermore, a gate oxide layer is formed on the inner walls of the first type of trench, the second type of trench and the third type of trench, and conductive polysilicon is arranged in the first type of trench, the second type of trench and the third type of trench. The conductive polysilicon in the first type of trench is connected to the gate potential, and the conductive polysilicon in the second type of trench and the third type of trench is floating.

[0013] Furthermore, three second-type trenches and three third-type trenches are arranged in the second-type conductive type body region located in the terminal protection area.

[0014] Furthermore, at least one terminal groove is arranged in the second conductive type body region located in the terminal protection area, and the terminal groove is arranged around the second type groove;

[0015] The groove depth and groove opening width of the terminal groove are the same as those of the first type of grooves.

[0016] Furthermore, three second-type trenches and four terminal trenches are arranged in the second-type conductive type body region located in the terminal protection area.

[0017] Furthermore, a first conductive type source region is arranged on the surface of the second conductive type body region located in the cell region, an insulating dielectric layer is arranged on the surface of the second conductive type body region located in the cell region and the terminal protection zone, a source metal is arranged on the surface of the insulating dielectric layer located in the cell region, a gate bus metal is arranged on the surface of the insulating dielectric layer located in the terminal protection zone, and the source metal is in contact with the second conductive type body region and the first conductive type source region through through holes on the insulating dielectric layer.

[0018] Furthermore, the power semiconductor device includes an N-type power semiconductor device and a P-type power semiconductor device. When the power semiconductor device is the N-type power semiconductor device, the first conductivity type is N-type and the second conductivity type is P-type. When the power semiconductor device is the P-type semiconductor device, the first conductivity type is P-type and the second conductivity type is N-type.

[0019] As another aspect of the present invention, a method for manufacturing a power semiconductor device is provided, wherein the method for manufacturing a power semiconductor device comprises:

[0020] Providing a first conductive type substrate, and growing a first conductive type epitaxial layer on the first conductive type substrate;

[0021] Selectively etching trenches on the first conductive type epitaxial layer to form first type trenches and second type trenches;

[0022] Thermal growth forms a gate oxide layer;

[0023] Depositing conductive polysilicon on the gate oxide layer, and etching to retain the conductive polysilicon in the first type of trenches and the second type of trenches;

[0024] Implanting second conductivity type impurities and thermally annealing to form a second conductivity type body region;

[0025] Selectively injecting first conductivity type impurities and activating them to form a first conductivity type source region;

[0026] Depositing an insulating dielectric layer, then selectively etching a through hole on the insulating dielectric layer, and injecting second conductive type impurities;

[0027] Metal is deposited and selectively etched to form source metal and gate bus metal.

[0028] Furthermore, the method for manufacturing the power semiconductor device further includes:

[0029] While forming the first type trench and the second type trench, trenches are selectively etched on the first conductive type epitaxial layer to form third type trenches or terminal trenches.

[0030] Through the above-mentioned power semiconductor device and its manufacturing method, by reducing the groove depth and groove opening width of the second type of groove located in the terminal protection area, when the power semiconductor device is in a reverse blocking state, the potential induced on the conductive polysilicon in the terminal groove close to the cell area is reduced, and the formation of an excessively strong electric field on the surface of the insulating gate oxide layer located on the side wall of the groove can be suppressed, thereby improving the voltage resistance reliability of the power semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present invention but do not constitute a limitation of the present invention. In the accompanying drawings:

[0032] Figure 1 It is a schematic diagram of the structure of a power semiconductor device in the prior art.

[0033] Figure 2 It is a schematic structural diagram of an implementation manner of a power semiconductor device of the present invention.

[0034] Figure 3 It is a schematic structural diagram of another embodiment of the power semiconductor device of the present invention.

[0035] Figure 4 This is a schematic structural diagram of growing a first conductivity type epitaxial layer on a first conductivity type substrate provided by the present invention.

[0036] Figure 5 A schematic diagram of the structure for forming the first type of grooves, the second type of grooves and the third type of grooves provided by the present invention.

[0037] Figure 6 A schematic diagram of the structure of forming a gate oxide layer provided by the present invention.

[0038] Figure 7 The present invention provides a schematic diagram of the structure of depositing conductive polysilicon and forming conductive polysilicon in a groove.

[0039] Figure 8 A schematic diagram of the structure of forming a second conductivity type body region and a first conductivity type source region provided by the present invention.

[0040] Fig. 9 A schematic diagram of the structure of forming a through hole in an insulating dielectric layer and injecting second conductive type impurities provided by the present invention. DETAILED DESCRIPTION

[0041] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0042] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work should fall within the scope of protection of the present invention.

[0043] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the present invention described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0044] In this embodiment, a power semiconductor device is provided. Figure 2 and Figure 3 is a schematic diagram of the structure of a power semiconductor device provided according to an embodiment of the present invention, such as Figure 2 and Figure 3 As shown, it includes: a semiconductor substrate, the semiconductor substrate is divided into a cell area 01 and a terminal protection area 02, the cell area 01 is located in the central area of ​​the semiconductor substrate, the terminal protection area 02 is located in the outer ring of the cell area 01 and is arranged around the cell area 01, wherein the semiconductor substrate includes a first conductive type substrate 1 and a first conductive type epitaxial layer 2 located on the first conductive type substrate 1, and a second conductive type body area 3 is arranged on the surface of the first conductive type epitaxial layer 2;

[0045] A first type trench 4 is provided in the second conductive type body region 3 located in the cell region 01, and the bottom of the first type trench 3 extends into the first conductive type epitaxial layer 2;

[0046] At least one second type trench 11 is arranged in the second conductive type body region 3 of the terminal protection region 02 near the cell region 01;

[0047] The groove depth of the second type groove 11 is smaller than the groove depth of the first type groove 4 , and the groove opening width of the second type groove 11 is smaller than the groove opening width of the first type groove 4 .

[0048] Through the above-mentioned power semiconductor device, by reducing the trench depth and trench opening width of the second type of trench located in the terminal protection area, when the power semiconductor device is in a reverse blocking state, the potential induced on the conductive polysilicon in the terminal trench close to the cell area is reduced, and the formation of an excessively strong electric field on the surface of the insulating gate oxide layer located on the side wall of the trench can be suppressed, thereby improving the voltage resistance reliability of the power semiconductor device.

[0049] As a specific implementation of this embodiment, Figure 2 As shown, at least one third type trench 12 is arranged in the second conductive type body region 3 located in the terminal protection zone 02, and the third type trench 12 is arranged around the second type trench 11;

[0050] The groove depth of the third type groove 12 is not less than the groove depth of the first type groove 4 , and the groove opening width of the third type groove 12 is not less than the groove opening width of the first type groove 4 .

[0051] More specifically, a gate oxide layer 6 is formed on the inner walls of the first type of grooves 4, the second type of grooves 11 and the third type of grooves 12, and conductive polysilicon 7 is arranged in the first type of grooves 4, the second type of grooves 11 and the third type of grooves 12. The conductive polysilicon 7 in the first type of grooves 4 is connected to the gate potential, and the conductive polysilicon 7 in the second type of grooves 11 and the third type of grooves 12 are both floating.

[0052] It should be understood that the meaning of “floating setting” here is not connected to any potential, that is, the conductive polysilicon in the second type trench 11 and the third type trench 12 is not connected to any potential.

[0053] Preferably, if Figure 2 As shown, three second-type trenches 11 and three third-type trenches 12 are arranged in the second-type conductive type body region 3 located in the terminal protection area 02 .

[0054] It should be understood that the number of the second type trenches 11 and the third type trenches 12 provided in the second conductive type body region 3 can be set according to requirements and is not limited here. Figure 2 It is for illustrative purposes only.

[0055] As another specific implementation of this embodiment, Figure 3As shown, at least one terminal trench 5 is arranged in the second conductive type body region 3 located in the terminal protection zone 02, and the terminal trench 5 is arranged around the second type trench 11;

[0056] The groove depth and groove opening width of the terminal groove 5 are the same as those of the first type groove 4 .

[0057] It can be understood that adding at least one second-type groove 11 on the side of the original terminal groove 5 close to the cell area 01 is simple to implement.

[0058] Preferably, if Figure 3 As shown, three second-type trenches 11 and four terminal trenches 5 are arranged in the second-type conductive type body region 3 located in the terminal protection area 02 .

[0059] It should be understood that the number of the second type trenches 11 and the terminal trenches 5 provided in the second conductive type body region 3 can be set according to requirements and is not limited here. Figure 3 It is for illustrative purposes only.

[0060] It should be noted that a variety of grooves with different depths can be provided in the terminal protection area 02, as long as the depth of the groove closest to the cell area 01 is less than the depth of the first type of groove 4. The smaller the depth of the groove closest to the cell area 01, the better the effect of reducing the electric field on the surface of the insulating gate oxide layer on the side wall of the groove.

[0061] Specifically, a first conductive type source region 8 is arranged on the surface of the second conductive type body region 3 located in the cell region 01, an insulating dielectric layer 9 is arranged on the surface of the second conductive type body region 3 located in the cell region 01 and the terminal protection region 02, a source metal 10 is arranged on the surface of the insulating dielectric layer 9 located in the cell region 01, and a gate bus metal 13 is arranged on the surface of the insulating dielectric layer 9 located in the terminal protection region 02, and the source metal 10 is in contact with the second conductive type body region 3 and the first conductive type source region 8 through the through holes on the insulating dielectric layer 9.

[0062] Preferably, the power semiconductor device includes an N-type power semiconductor device and a P-type power semiconductor device. When the power semiconductor device is the N-type power semiconductor device, the first conductivity type is N-type and the second conductivity type is P-type. When the power semiconductor device is the P-type semiconductor device, the first conductivity type is P-type and the second conductivity type is N-type.

[0063] It should be noted that the present embodiment is described by taking the power semiconductor device being an N-type power semiconductor device as an example.

[0064] Combine the following Figure 2The structure of the power semiconductor device provided in this embodiment is generally described.

[0065] Take N-type power devices as an example. Figure 2 As shown, it includes a cell area 01 and a terminal protection area 02, the cell area 01 is located in the central area of ​​the device, the terminal protection area 02 surrounds the cell area 01, the cell area 01 includes a plurality of cell units, the cell unit includes a semiconductor substrate, the semiconductor substrate includes an N-type substrate 1 and an N-type epitaxial layer 2 located on the N-type substrate 1, a P-type body area 3 is provided on the surface of the N-type epitaxial layer 2, a first type of groove 4 is provided on the surface of the P-type body area 3, a gate oxide layer 6 and a conductive polysilicon 7 are provided in the first type of groove 4, the bottom of the first type of groove 4 enters the N-type epitaxial layer 2, an N-type source area 8 is provided on the surface of the P-type body area 3, an insulating dielectric layer 9 is covered on the surface of the cell area 01, and a source metal 10 passes through the insulating dielectric The through hole on the dielectric layer 9 contacts the P-type body region 3 and the N-type source region 8. The terminal protection zone 02 includes a semiconductor substrate, which includes an N-type substrate 1 and an N-type epitaxial layer 2 located on the N-type substrate 1. A P-type body region 3 is provided on the surface of the N-type epitaxial layer 2. Three mutually parallel second-type grooves 11 and three mutually parallel third-type grooves 12 are provided in the P-body region 3. Both types of grooves are provided with a gate oxide layer 6 and a conductive polysilicon 7, and both surround the cell region 01. The second-type groove 11 is close to the cell region 01, and the groove depth and the groove opening width are both smaller than the first-type groove 4. The third-type groove 12 is far away from the cell region 01 and surrounds the second-type groove 11, and the groove depth and the groove opening width are both larger than the first-type groove 4.

[0066] The conductive polysilicon 7 in all the trenches in the terminal protection area 02 is floating, and the conductive polysilicon 7 in all the trenches in the cell area 01 is connected to the gate potential.

[0067] As another embodiment of the present invention, a method for manufacturing a power semiconductor device is provided, wherein: Figures 4 to 9 As shown, the method for manufacturing the power semiconductor device includes:

[0068] like Figure 4 As shown, a first conductive type substrate 1 is provided, and a first conductive type epitaxial layer 2 is grown on the first conductive type substrate 1;

[0069] like Figure 5 As shown, trenches are selectively etched on the first conductive type epitaxial layer 2 to form first type trenches 4 and second type trenches 11;

[0070] It should be noted that Figure 5 The embodiment shown also forms a third type of groove 12 as Figure 5In a parallel implementation, the first type groove 4, the second type groove 11 and the terminal groove 5 can also be formed simultaneously.

[0071] like Figure 6 As shown, a gate oxide layer 6 is formed by thermal growth;

[0072] like Figure 7 As shown, a conductive polysilicon 7 is deposited on the gate oxide layer 6, and the conductive polysilicon 7 in the first type trench 4 and the second type trench 11 is etched to remain;

[0073] like Figure 8 As shown, second conductivity type impurities are implanted and thermally annealed to form a second conductivity type body region 3;

[0074] like Figure 8 As shown, first conductivity type impurities are selectively injected and activated to form a first conductivity type source region 8;

[0075] like Fig. 9 As shown, an insulating dielectric layer 9 is deposited, and then through holes are selectively etched on the insulating dielectric layer 9, and second conductive type impurities are injected;

[0076] like Figure 2 As shown, metal is deposited and selectively etched to form source metal 10 and gate bus metal 13.

[0077] The power semiconductor device obtained by the above-mentioned method for manufacturing a power semiconductor device can reduce the groove depth and groove opening width of the second type of groove located in the terminal protection area, and reduce the potential induced on the conductive polysilicon in the terminal groove close to the cell area when the power semiconductor device is in a reverse blocking state, thereby suppressing the formation of an excessively strong electric field on the surface of the insulating gate oxide layer located on the side wall of the groove, thereby improving the withstand voltage reliability of the power semiconductor device. In addition, the method for manufacturing a power semiconductor device provided in this embodiment has the advantages of simple process and easy implementation.

[0078] It should be noted that Figures 4 to 9 The power semiconductor device is an N-type power device as an example for illustration, wherein the first conductivity type is N-type and the second conductivity type is P-type.

[0079] It should be understood that Figures 4 to 9 Only indicates the production Figure 2 The power semiconductor devices shown are targeted at Figure 3 The power semiconductor device shown is fabricated and Figures 4 to 9 The same as shown, the only difference is that when forming the groove, Figure 2 The first type of groove, the second type of groove and the third type of groove are formed at the same time. Figure 3 The first type of trench, the second type of trench and the terminal trench are formed simultaneously.

[0080] The manufacturing method of the power semiconductor device provided in this embodiment is fully compatible with the existing product process and does not require an additional photolithography plate, that is, the voltage resistance reliability problem in the existing technology can be solved without increasing the cost.

[0081] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A power semiconductor device, comprising a semiconductor substrate, wherein the semiconductor substrate is divided into a cell area and a terminal protection area, wherein the cell area is located in the central area of ​​the semiconductor substrate, and the terminal protection area is located in the outer ring of the cell area and surrounds the cell area, characterized in that: The semiconductor substrate comprises a first conductive type substrate and a first conductive type epitaxial layer located on the first conductive type substrate, wherein a second conductive type body region is disposed on a surface of the first conductive type epitaxial layer; A first type trench is provided in the second conductive type body region located in the cell region, and the bottom of the first type trench extends into the first conductive type epitaxial layer; At least one second type trench is arranged in the second conductive type body region of the terminal protection area near the cell region; The groove depth of the second type of groove is smaller than the groove depth of the first type of groove, and the groove opening width of the second type of groove is smaller than the groove opening width of the first type of groove; At least one third type trench is arranged in the second conductive type body region located in the terminal protection area, and the third type trench is arranged around the second type trench; The groove depth of the third type groove is not less than the groove depth of the first type groove, and the groove opening width of the third type groove is not less than the groove opening width of the first type groove.

2. The power semiconductor device according to claim 1, characterized in that: A gate oxide layer is formed on the inner walls of the first type of trench, the second type of trench and the third type of trench. Conductive polysilicon is arranged in the first type of trench, the second type of trench and the third type of trench. The conductive polysilicon in the first type of trench is connected to the gate potential, and the conductive polysilicon in the second type of trench and the third type of trench is floating.

3. The power semiconductor device according to claim 1, characterized in that: Three second-type trenches and three third-type trenches are arranged in the second conductive type body region located in the terminal protection area.

4. The power semiconductor device according to claim 1, characterized in that: At least one terminal groove is arranged in the second conductive type body region located in the terminal protection area, and the terminal groove is arranged around the second type groove; The groove depth and groove opening width of the terminal groove are the same as those of the first type of grooves.

5. The power semiconductor device according to claim 4, characterized in that: Three second-type trenches and four terminal trenches are arranged in the second conductive type body region located in the terminal protection area.

6. The power semiconductor device according to any one of claims 1 to 5, characterized in that: A first conductive type source region is arranged on the surface of the second conductive type body region located in the cell region, an insulating dielectric layer is arranged on the surface of the second conductive type body region located in the cell region and the terminal protection zone, a source metal is arranged on the surface of the insulating dielectric layer located in the cell region, a gate bus metal is arranged on the surface of the insulating dielectric layer located in the terminal protection zone, and the source metal contacts the second conductive type body region and the first conductive type source region through through holes on the insulating dielectric layer.

7. The power semiconductor device according to any one of claims 1 to 5, characterized in that: The power semiconductor device includes an N-type power semiconductor device and a P-type power semiconductor device. When the power semiconductor device is the N-type power semiconductor device, the first conductivity type is N-type and the second conductivity type is P-type. When the power semiconductor device is the P-type power semiconductor device, the first conductivity type is P-type and the second conductivity type is N-type.

8. A method for manufacturing a power semiconductor device, characterized in that: The method for manufacturing the power semiconductor device comprises: Providing a first conductive type substrate, and growing a first conductive type epitaxial layer on the first conductive type substrate; Selectively etching trenches on the first conductive type epitaxial layer to form first type trenches and second type trenches; Thermal growth forms a gate oxide layer; Depositing conductive polysilicon on the gate oxide layer, and etching to retain the conductive polysilicon in the first type of trenches and the second type of trenches; Implanting second conductivity type impurities and thermally annealing to form a second conductivity type body region; Selectively injecting first conductivity type impurities and activating them to form a first conductivity type source region; Depositing an insulating dielectric layer, then selectively etching a through hole on the insulating dielectric layer, and injecting second conductive type impurities; Metal is deposited and selectively etched to form source metal and gate bus metal.

9. The method for manufacturing a power semiconductor device according to claim 8, characterized in that: The method for manufacturing the power semiconductor device further includes: While forming the first type trench and the second type trench, trenches are selectively etched on the first conductive type epitaxial layer to form third type trenches or terminal trenches.

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